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Searched refs:QuadSPI_SOCCR_SOCCFG_MASK (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h282 #define QuadSPI_SOCCR_SOCCFG_MASK (0xFFFFFFFFU) macro
285 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK)
/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h342 #define QuadSPI_SOCCR_SOCCFG_MASK (0xFFFFFFFFU) macro
345 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK)
/hal_nxp-3.6.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h1003 #ifdef QuadSPI_SOCCR_SOCCFG_MASK
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h408 #define QuadSPI_SOCCR_SOCCFG_MASK (0xFFFFFFU) macro
411 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h25332 #define QuadSPI_SOCCR_SOCCFG_MASK (0xFFFFFFFFU) macro
25334 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h25333 #define QuadSPI_SOCCR_SOCCFG_MASK (0xFFFFFFFFU) macro
25335 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK)