Searched refs:QuadSPI_INSTANCE_COUNT (Results 1 – 7 of 7) sorted by relevance
181 QuadSPI_Type * const Qspi_Ip_BaseAddress[QuadSPI_INSTANCE_COUNT] = IP_QuadSPI_BASE_PTRS;183 const uint32 Qspi_Ip_AhbAddress[QuadSPI_INSTANCE_COUNT] = QuadSPI_AHB_PTRS;199 uint8 Qspi_Ip_MemoryPadding[QuadSPI_INSTANCE_COUNT];208 const Qspi_Ip_ControllerConfigType * Qspi_Ip_ControllerConfig[QuadSPI_INSTANCE_COUNT];1050 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_AhbSetup()1205 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_SetLut()1224 DEV_ASSERT_QSPI(Instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_WriteLuts_Privileged()1251 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_SetAhbSeqId_Privileged()1385 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_ControllerInit()1427 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_ControllerDeinit()[all …]
1832 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_Deinit()
78 extern const uint32 Qspi_Ip_AhbAddress[QuadSPI_INSTANCE_COUNT];
139 extern uint8 Qspi_Ip_MemoryPadding[QuadSPI_INSTANCE_COUNT];
126 #define QuadSPI_INSTANCE_COUNT (1) macro
121 #define QuadSPI_INSTANCE_COUNT (1u) macro
163 #define QuadSPI_INSTANCE_COUNT (2u) macro