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Searched refs:QuadSPI_FR_AIBSEF_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h617 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
620 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h594 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
597 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.h116 kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h1011 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
1014 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18886 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
18888 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19859 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
19861 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h18416 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
18418 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h18418 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
18420 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h25565 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
25567 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h25566 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) macro
25568 … (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)