1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef QSPI_IP_TYPES_H 8 #define QSPI_IP_TYPES_H 9 10 /** 11 * @file Qspi_Ip_Types.h 12 * 13 * @addtogroup IPV_QSPI QSPI IPV Driver 14 * @{ 15 */ 16 17 /* implements Qspi_Ip_Types.h_Artifact */ 18 19 #ifdef __cplusplus 20 extern "C"{ 21 #endif 22 23 #include "StandardTypes.h" 24 #include "Qspi_Ip_Features.h" 25 #include "Qspi_Ip_CfgDefines.h" 26 #include "Qspi_Ip_HyperflashTypes.h" 27 28 /*================================================================================================== 29 * SOURCE FILE VERSION INFORMATION 30 ==================================================================================================*/ 31 #define FLS_QSPI_TYPES_VENDOR_ID 43 32 #define FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION 4 33 #define FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION 7 34 #define FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION 0 35 #define FLS_QSPI_TYPES_SW_MAJOR_VERSION 3 36 #define FLS_QSPI_TYPES_SW_MINOR_VERSION 0 37 #define FLS_QSPI_TYPES_SW_PATCH_VERSION 0 38 39 /*================================================================================================== 40 * FILE VERSION CHECKS 41 ==================================================================================================*/ 42 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 43 /* Check if Qspi_Ip_Types header file and StandardTypes.h header file are of the same Autosar version */ 44 #if ((FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \ 45 (FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION) \ 46 ) 47 #error "Autosar Version Numbers of Qspi_Ip_Types.h and StandardTypes.h are different" 48 #endif 49 #endif 50 51 /* Check if current file and Qspi_Ip_Features header file are of the same vendor */ 52 #if (FLS_QSPI_TYPES_VENDOR_ID != QSPI_IP_FEATURES_VENDOR_ID_CFG) 53 #error "Qspi_Ip_Types.h and Qspi_Ip_Features.h have different vendor ids" 54 #endif 55 /* Check if current file and Qspi_Ip_Features header file are of the same Autosar version */ 56 #if ((FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION != QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG) || \ 57 (FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION != QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG) || \ 58 (FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION != QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG) \ 59 ) 60 #error "AutoSar Version Numbers of Qspi_Ip_Types.h and Qspi_Ip_Features.h are different" 61 #endif 62 /* Check if current file and Qspi_Ip_Features header file are of the same Software version */ 63 #if ((FLS_QSPI_TYPES_SW_MAJOR_VERSION != QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG) || \ 64 (FLS_QSPI_TYPES_SW_MINOR_VERSION != QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG) || \ 65 (FLS_QSPI_TYPES_SW_PATCH_VERSION != QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG) \ 66 ) 67 #error "Software Version Numbers of Qspi_Ip_Types.h and Qspi_Ip_Features.h are different" 68 #endif 69 70 /* Check if current file and Qspi_Ip_CfgDefines header file are of the same vendor */ 71 #if (FLS_QSPI_TYPES_VENDOR_ID != QSPI_IP_VENDOR_ID_CFG_DEFINES) 72 #error "Qspi_Ip_Types.h and Qspi_Ip_CfgDefines.h have different vendor ids" 73 #endif 74 /* Check if current file and Qspi_Ip_CfgDefines header file are of the same Autosar version */ 75 #if ((FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION != QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG_DEFINES) || \ 76 (FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION != QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG_DEFINES) || \ 77 (FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION != QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG_DEFINES) \ 78 ) 79 #error "AutoSar Version Numbers of Qspi_Ip_Types.h and Qspi_Ip_CfgDefines.h are different" 80 #endif 81 /* Check if current file and Qspi_Ip_CfgDefines header file are of the same Software version */ 82 #if ((FLS_QSPI_TYPES_SW_MAJOR_VERSION != QSPI_IP_SW_MAJOR_VERSION_CFG_DEFINES) || \ 83 (FLS_QSPI_TYPES_SW_MINOR_VERSION != QSPI_IP_SW_MINOR_VERSION_CFG_DEFINES) || \ 84 (FLS_QSPI_TYPES_SW_PATCH_VERSION != QSPI_IP_SW_PATCH_VERSION_CFG_DEFINES) \ 85 ) 86 #error "Software Version Numbers of Qspi_Ip_Types.h and Qspi_Ip_CfgDefines.h are different" 87 #endif 88 89 /* Check if current file and Qspi_Ip_HyperflashTypes header file are of the same vendor */ 90 #if (FLS_QSPI_TYPES_VENDOR_ID != QSPI_IP_HYPERFLASHTYPES_VENDOR_ID) 91 #error "Qspi_Ip_Types.h and Qspi_Ip_HyperflashTypes.h have different vendor ids" 92 #endif 93 /* Check if current file and Qspi_Ip_HyperflashTypes header file are of the same Autosar version */ 94 #if ((FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION != QSPI_IP_HYPERFLASHTYPES_AR_RELEASE_MAJOR_VERSION) || \ 95 (FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION != QSPI_IP_HYPERFLASHTYPES_AR_RELEASE_MINOR_VERSION) || \ 96 (FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION != QSPI_IP_HYPERFLASHTYPES_AR_RELEASE_REVISION_VERSION) \ 97 ) 98 #error "AutoSar Version Numbers of Qspi_Ip_Types.h and Qspi_Ip_HyperflashTypes.h are different" 99 #endif 100 /* Check if current file and Qspi_Ip_HyperflashTypes header file are of the same Software version */ 101 #if ((FLS_QSPI_TYPES_SW_MAJOR_VERSION != QSPI_IP_HYPERFLASHTYPES_SW_MAJOR_VERSION) || \ 102 (FLS_QSPI_TYPES_SW_MINOR_VERSION != QSPI_IP_HYPERFLASHTYPES_SW_MINOR_VERSION) || \ 103 (FLS_QSPI_TYPES_SW_PATCH_VERSION != QSPI_IP_HYPERFLASHTYPES_SW_PATCH_VERSION) \ 104 ) 105 #error "Software Version Numbers of Qspi_Ip_Types.h and Qspi_Ip_HyperflashTypes.h are different" 106 #endif 107 108 109 /******************************************************************************* 110 * Macros. 111 ******************************************************************************/ 112 #if (CPU_TYPE == CPU_TYPE_64) 113 typedef uint64 Qspi_Ip_UintPtrType; 114 #elif (CPU_TYPE == CPU_TYPE_32) 115 typedef uint32 Qspi_Ip_UintPtrType; 116 #else 117 #error "Unsupported CPU_TYPE" 118 #endif 119 120 /*! Number of erase types that can be supported by a flash device */ 121 #define QSPI_IP_ERASE_TYPES 4U 122 123 /*! @brief Number of AHB buffers in the device */ 124 #define QSPI_IP_AHB_BUFFERS 4 125 126 /*! Invalid index in virtual LUT, used for unsupported features */ 127 #define QSPI_IP_LUT_INVALID (uint16)0xFFFFU 128 /*! End operation for a LUT sequence */ 129 #define QSPI_IP_LUT_SEQ_END (uint16)0x0U 130 /*! Pack the two operations into a LUT register (each operation is a pair of instruction-operand) */ 131 #define QSPI_IP_PACK_LUT_REG(ops0, ops1) ( (uint32)(ops0) + ((uint32)(ops1) << 16U) ) 132 133 134 /******************************************************************************* 135 * Enumerations. 136 ******************************************************************************/ 137 138 /*! @brief qspi return codes 139 */ 140 typedef enum 141 { 142 STATUS_QSPI_IP_SUCCESS = 0x00U, /*!< Successful job */ 143 STATUS_QSPI_IP_ERROR = 0x01U, /*!< IP is performing an operation */ 144 STATUS_QSPI_IP_BUSY = 0x02U, /*!< Error - general code */ 145 STATUS_QSPI_IP_TIMEOUT = 0x03U, /*!< Error - exceeded timeout */ 146 STATUS_QSPI_IP_ERROR_PROGRAM_VERIFY = 0x04U, /*!< Error - selected memory area doesn't contain desired value */ 147 } Qspi_Ip_StatusType; 148 149 150 /*! @brief flash connection to the QSPI module 151 */ 152 typedef enum 153 { 154 QSPI_IP_SIDE_A1 = 0x00U, /*!< Serial flash connected on side A1 */ 155 QSPI_IP_SIDE_A2 = 0x01U, /*!< Serial flash connected on side A2 */ 156 QSPI_IP_SIDE_B1 = 0x02U, /*!< Serial flash connected on side B1 */ 157 QSPI_IP_SIDE_B2 = 0x03U, /*!< Serial flash connected on side B2 */ 158 } Qspi_Ip_ConnectionType; 159 160 161 /*! @brief flash operation type 162 */ 163 typedef enum 164 { 165 QSPI_IP_OP_TYPE_CMD = 0x00U, /*!< Simple command */ 166 QSPI_IP_OP_TYPE_WRITE_REG = 0x01U, /*!< Write value in external flash register */ 167 QSPI_IP_OP_TYPE_RMW_REG = 0x02U, /*!< RMW command on external flash register */ 168 QSPI_IP_OP_TYPE_READ_REG = 0x03U, /*!< Read external flash register until expected value is read */ 169 QSPI_IP_OP_TYPE_QSPI_CFG = 0x04U, /*!< Re-configure QSPI controller */ 170 } Qspi_Ip_OpType; 171 172 /*! @brief Lut commands 173 */ 174 typedef enum 175 { 176 QSPI_IP_LUT_INSTR_STOP = (0U << 10U), /*!< End of sequence */ 177 QSPI_IP_LUT_INSTR_CMD = (1U << 10U), /*!< Command */ 178 QSPI_IP_LUT_INSTR_ADDR = (2U << 10U), /*!< Address */ 179 QSPI_IP_LUT_INSTR_DUMMY = (3U << 10U), /*!< Dummy cycles */ 180 QSPI_IP_LUT_INSTR_MODE = (4U << 10U), /*!< 8-bit mode */ 181 QSPI_IP_LUT_INSTR_MODE2 = (5U << 10U), /*!< 2-bit mode */ 182 QSPI_IP_LUT_INSTR_MODE4 = (6U << 10U), /*!< 4-bit mode */ 183 QSPI_IP_LUT_INSTR_READ = (7U << 10U), /*!< Read data */ 184 QSPI_IP_LUT_INSTR_WRITE = (8U << 10U), /*!< Write data */ 185 QSPI_IP_LUT_INSTR_JMP_ON_CS = (9U << 10U), /*!< Jump on chip select deassert and stop */ 186 QSPI_IP_LUT_INSTR_ADDR_DDR = (10U << 10U), /*!< Address - DDR mode */ 187 QSPI_IP_LUT_INSTR_MODE_DDR = (11U << 10U), /*!< 8-bit mode - DDR mode */ 188 QSPI_IP_LUT_INSTR_MODE2_DDR = (12U << 10U), /*!< 2-bit mode - DDR mode */ 189 QSPI_IP_LUT_INSTR_MODE4_DDR = (13U << 10U), /*!< 4-bit mode - DDR mode */ 190 QSPI_IP_LUT_INSTR_READ_DDR = (14U << 10U), /*!< Read data - DDR mode */ 191 QSPI_IP_LUT_INSTR_WRITE_DDR = (15U << 10U), /*!< Write data - DDR mode */ 192 QSPI_IP_LUT_INSTR_DATA_LEARN = (16U << 10U), /*!< Data learning pattern */ 193 QSPI_IP_LUT_INSTR_CMD_DDR = (17U << 10U), /*!< Command - DDR mode */ 194 QSPI_IP_LUT_INSTR_CADDR = (18U << 10U), /*!< Column address */ 195 QSPI_IP_LUT_INSTR_CADDR_DDR = (19U << 10U), /*!< Column address - DDR mode */ 196 QSPI_IP_LUT_INSTR_JMP_TO_SEQ = (20U << 10U), /*!< Jump on chip select deassert and continue */ 197 } Qspi_Ip_LutCommandsType; 198 199 /*! @brief Lut pad options 200 */ 201 typedef enum 202 { 203 QSPI_IP_LUT_PADS_1 = (0U << 8U), /*!< 1 Pad */ 204 QSPI_IP_LUT_PADS_2 = (1U << 8U), /*!< 2 Pads */ 205 QSPI_IP_LUT_PADS_4 = (2U << 8U), /*!< 4 Pads */ 206 QSPI_IP_LUT_PADS_8 = (3U << 8U), /*!< 8 Pads */ 207 } Qspi_Ip_LutPadsType; 208 209 /*! 210 * @brief Operation in a LUT sequence. 211 * 212 * This type describes one basic operation inside a LUT sequence. Each operation contains: 213 * - instruction (6 bits) 214 * - number of PADs (2 bits) 215 * - operand (8 bits) 216 * Qspi_Ip_LutCommandsType and Qspi_Ip_LutPadsType types should be used to form operations 217 */ 218 typedef uint16 Qspi_Ip_InstrOpType; 219 220 /*! @brief Read mode 221 */ 222 typedef enum 223 { 224 #if (FEATURE_QSPI_INTERNAL_DQS == 1) 225 QSPI_IP_READ_MODE_INTERNAL_DQS = 0U, /*!< Use internally generated strobe signal */ 226 #endif 227 #if (FEATURE_QSPI_LOOPBACK == 1) 228 QSPI_IP_READ_MODE_LOOPBACK = 1U, /*!< Use loopback clock from PAD as strobe signal */ 229 #endif 230 #if (FEATURE_QSPI_LOOPBACK_DQS == 1) 231 QSPI_IP_READ_MODE_LOOPBACK_DQS = 2U, /*!< Use loopback clock from PAD as strobe signal */ 232 #endif 233 QSPI_IP_READ_MODE_EXTERNAL_DQS = 3U, /*!< Use external strobe signal */ 234 } Qspi_Ip_ReadModeType; 235 236 237 /*! @brief Clock phase used for sampling Rx data 238 */ 239 typedef enum 240 { 241 QSPI_IP_DATA_RATE_SDR = 0U, /*!< Single data rate */ 242 QSPI_IP_DATA_RATE_DDR = 1U, /*!< Double data rate */ 243 } Qspi_Ip_DataRateType; 244 245 246 /*! @brief Delay used for sampling Rx data 247 */ 248 typedef enum 249 { 250 QSPI_IP_SAMPLE_DELAY_SAME_DQS = 0U, /*!< Same DQS */ 251 QSPI_IP_SAMPLE_DELAY_HALFCYCLE_EARLY_DQS = 1U, /*!< Half-cycle early DQS */ 252 } Qspi_Ip_SampleDelayType; 253 254 /*! @brief Clock phase used for sampling Rx data 255 */ 256 typedef enum 257 { 258 QSPI_IP_SAMPLE_PHASE_NON_INVERTED = 0U, /*!< Sampling at non-inverted clock */ 259 QSPI_IP_SAMPLE_PHASE_INVERTED = 1U, /*!< Sampling at inverted clock */ 260 } Qspi_Ip_SamplePhaseType; 261 262 /*! @brief Alignment of outgoing data with serial clock 263 */ 264 typedef enum 265 { 266 QSPI_IP_FLASH_DATA_ALIGN_REFCLK = 0U, /*!< Data aligned with the posedge of Internal reference clock of QSPI */ 267 QSPI_IP_FLASH_DATA_ALIGN_2X_REFCLK = 1U, /*!< Data aligned with 2x serial flash half clock */ 268 } Qspi_Ip_FlashDataAlignType; 269 270 /*! @brief DLL configuration modes 271 */ 272 typedef enum 273 { 274 QSPI_IP_DLL_BYPASSED = 0U, /*!< DLL bypass mode */ 275 QSPI_IP_DLL_MANUAL_UPDATE = 1U, /*!< DLL manual update mode */ 276 QSPI_IP_DLL_AUTO_UPDATE = 2U, /*!< DLL auto update mode */ 277 } Qspi_Ip_DllModeType; 278 279 /*! @brief Init callout pointer type 280 */ 281 typedef Qspi_Ip_StatusType (*Qspi_Ip_InitCalloutPtrType)(uint32 instance); 282 283 /*! @brief Reset callout pointer type 284 */ 285 typedef Qspi_Ip_StatusType (*Qspi_Ip_ResetCalloutPtrType)(uint32 instance); 286 287 /*! @brief Error Check callout pointer type 288 */ 289 typedef Qspi_Ip_StatusType (*Qspi_Ip_ErrorCheckCalloutPtrType)(uint32 instance); 290 291 /*! @brief Ecc Check callout pointer type 292 */ 293 typedef Qspi_Ip_StatusType (*Qspi_Ip_EccCheckCalloutPtrType)(uint32 instance, uint32 startAddress, uint32 dataLength); 294 295 296 /******************************************************************************* 297 * Definitions 298 ******************************************************************************/ 299 300 /*! 301 * @brief DLL configuration structure 302 * 303 * This structure contains initialization settings for DLL and slave delay chain 304 */ 305 typedef struct 306 { 307 Qspi_Ip_DllModeType dllMode; /*!< Mode in which DLL is used */ 308 boolean freqEnable; /*!< Selects delay-chain for high frequency of operation */ 309 uint8 referenceCounter; /*!< Select the "n+1" interval of DLL phase detection and reference delay updating interval */ 310 uint8 resolution; /*!< Minimum resolution for DLL phase detector */ 311 uint8 coarseDelay; /*!< Coarse delay DLL slave delay chain */ 312 uint8 fineDelay; /*!< Fine delay DLL slave delay chain */ 313 uint8 tapSelect; /*!< Selects the Nth tap provided by the slave delay-chain */ 314 } Qspi_Ip_DllSettingsType; 315 316 /*! 317 * @brief AHB configuration structure 318 * 319 * This structure is used to provide configuration parameters for AHB access 320 * to the external flash 321 */ 322 typedef struct 323 { 324 uint8 masters[QSPI_IP_AHB_BUFFERS]; /*!< List of AHB masters assigned to each buffer */ 325 uint16 sizes[QSPI_IP_AHB_BUFFERS]; /*!< List of buffer sizes */ 326 boolean allMasters; /*!< Indicates that any master may access the last buffer */ 327 } Qspi_Ip_ControllerAhbConfigType; 328 329 #if defined(FEATURE_QSPI_CHIP_OPTIONS_S32K148) 330 /*! @brief Source of QuadSPI AHB read interface, module and bus interface clock 331 */ 332 typedef enum 333 { 334 QSPI_IP_CLK_SRC_SYS_CLK = 0U, /*!< FIRC_DIV1 is clock source of QuadSPI internal reference clock */ 335 QSPI_IP_CLK_SRC_BUS_CLK = 1U, /*!< PLL_DIV1 is clock source of QuadSPI internal reference clock */ 336 } Qspi_Ip_ClockSourceType; 337 338 /*! @brief Source of QuadSPI internal reference clock 339 */ 340 typedef enum 341 { 342 QSPI_IP_CLK_REF_PLL_DIV1 = 0U, /*!< PLL_DIV1 is clock source of QuadSPI internal reference clock */ 343 QSPI_IP_CLK_REF_FIRC_DIV1 = 1U, /*!< FIRC_DIV1 is clock source of QuadSPI internal reference clock */ 344 } Qspi_Ip_ClockReferenceType; 345 #endif 346 347 348 #if (FEATURE_QSPI_HAS_SFP == 1) 349 350 /** Access control type */ 351 typedef enum 352 { 353 QSPI_IP_SFP_ALL, 354 QSPI_IP_SFP_MDAD, 355 QSPI_IP_SFP_FRAD 356 } Qspi_Ip_Sfp_AccessControlType; 357 358 #if (QSPI_IP_SFP_ENABLE_GLOBAL == STD_ON) 359 360 #if (QSPI_IP_SFP_ENABLE_MDAD == STD_ON) 361 362 typedef enum 363 { 364 QSPI_IP_SFP_RESERVED, 365 QSPI_IP_SFP_UNSECURE, 366 QSPI_IP_SFP_SECURE, 367 QSPI_IP_SFP_BOTH 368 } Qspi_Ip_SfpSaType; 369 370 typedef enum 371 { 372 QSPI_IP_SFP_MASK_AND, 373 QSPI_IP_SFP_MASK_OR 374 } Qspi_Ip_SfpMasktypeType; 375 376 typedef struct 377 { 378 Qspi_Ip_SfpSaType SecureAttribute; 379 Qspi_Ip_SfpMasktypeType MaskType; 380 boolean Valid; 381 uint8 Mask; 382 uint8 DomainId; 383 } Qspi_Ip_SfpTgCfgType; 384 385 #endif /* QSPI_IP_SFP_ENABLE_MDAD */ 386 387 #if (QSPI_IP_SFP_ENABLE_FRAD == STD_ON) 388 389 /** FRADn_WORD3 :: Exclusive access Lock [EAL] */ 390 typedef enum 391 { 392 QSPI_IP_SFP_EAL_DISABLED = 0, 393 QSPI_IP_SFP_EAL_NONE = 2, 394 QSPI_IP_SFP_EAL_OWNER = 3 395 } Qspi_Ip_SfpEalType; 396 397 /** Access Control Policy for write operations */ 398 typedef enum 399 { 400 QSPI_IP_SFP_ACP_NONE = 0, 401 QSPI_IP_SFP_ACP_SECURE = 4, 402 QSPI_IP_SFP_ACP_SECURE_PRIVILEGED = 5, 403 QSPI_IP_SFP_ACP_ALL = 6, 404 QSPI_IP_SFP_ACP_PRIVILEGED = 7 405 } Qspi_Ip_SfpAcpType; 406 407 typedef struct 408 { 409 uint32 StartAddress; 410 uint32 EndAddress; 411 boolean Valid; 412 Qspi_Ip_SfpAcpType Md0Acp; 413 Qspi_Ip_SfpAcpType Md1Acp; 414 Qspi_Ip_SfpEalType ExclusiveAccessLock; 415 uint8 ExclusiveAccessOwner; 416 } Qspi_Ip_SfpFradCfgType; 417 418 #endif /* QSPI_IP_SFP_ENABLE_FRAD */ 419 420 typedef struct 421 { 422 uint32 MasterTimeout; 423 #if (QSPI_IP_SFP_ENABLE_MDAD == STD_ON) 424 Qspi_Ip_SfpTgCfgType Tg[QuadSPI_MDAD_COUNT]; 425 #endif 426 #if (QSPI_IP_SFP_ENABLE_FRAD == STD_ON) 427 Qspi_Ip_SfpFradCfgType Frad[QuadSPI_FRAD_COUNT]; 428 #endif 429 } Qspi_Ip_SfpConfigType; 430 431 #endif /* QSPI_IP_SFP_ENABLE_GLOBAL */ 432 433 #endif /* FEATURE_QSPI_HAS_SFP */ 434 435 436 /*! 437 * @brief Driver configuration structure 438 * 439 * This structure is used to provide configuration parameters for the qspi driver 440 * at initialization time. 441 */ 442 typedef struct 443 { 444 #if defined(FEATURE_QSPI_CHIP_OPTIONS_S32K148) 445 Qspi_Ip_ClockSourceType clockSrc; /*!< AHB read interface, module and bus interface clock */ 446 Qspi_Ip_ClockReferenceType clockRef; /*!< Internal reference clock (async clock domain) */ 447 uint8 clockRefDiv; /*!< Divider value for internal reference clock */ 448 boolean dqsInvertA; /*!< Inverted reference clock selection for DQS Flash A */ 449 boolean dqsInvertB; /*!< Inverted reference clock selection for DQS Flash B */ 450 uint8 dqsDelayA; /*!< Fine delay chain configuration for Flash A */ 451 uint8 dqsDelayB; /*!< Fine delay chain configuration for Flash B */ 452 #endif 453 454 Qspi_Ip_DataRateType dataRate; /*!< Single/double data rate */ 455 uint32 memSizeA1; /*!< Size of serial flash A1 */ 456 uint32 memSizeA2; /*!< Size of serial flash A2 */ 457 uint8 csHoldTime; /*!< CS hold time, expressed in serial clock cycles */ 458 uint8 csSetupTime; /*!< CS setup time, expressed in serial clock cycles */ 459 uint8 columnAddr; /*!< Width of the column address, 0 if not used */ 460 boolean wordAddresable; /*!< True if serial flash is word addressable */ 461 Qspi_Ip_ReadModeType readModeA; /*!< Read mode for incoming data from serial flash A */ 462 Qspi_Ip_SampleDelayType sampleDelay; /*!< Delay (in clock cycles) used for sampling Rx data */ 463 Qspi_Ip_SamplePhaseType samplePhase; /*!< Clock phase used for sampling Rx data */ 464 465 Qspi_Ip_DllSettingsType dllSettingsA; /*!< DLL settings for side A */ 466 467 Qspi_Ip_FlashDataAlignType dataAlign; /*!< Alignment of output data sent to serial flash */ 468 uint8 io2IdleValueA; /*!< (0 / 1) Logic level of IO[2] signal when not used on side A */ 469 uint8 io3IdleValueA; /*!< (0 / 1) Logic level of IO[3] signal when not used on side A */ 470 boolean byteSwap; /*!< Enable byte swap in octal DDR mode */ 471 #if (FEATURE_QSPI_HAS_SFP == 1) 472 #if (QSPI_IP_SFP_ENABLE_GLOBAL == STD_ON) 473 Qspi_Ip_SfpConfigType SfpCfg; 474 #endif 475 #endif 476 Qspi_Ip_ControllerAhbConfigType ahbConfig; /*!< AHB buffers configuration */ 477 } Qspi_Ip_ControllerConfigType; 478 479 /*! 480 * @brief Status register configuration structure 481 * 482 * This structure contains information about the status registers of the external flash 483 */ 484 typedef struct 485 { 486 uint16 statusRegInitReadLut; /*!< Command used to read the status register during initialization */ 487 uint16 statusRegReadLut; /*!< Command used to read the status register */ 488 uint16 statusRegWriteLut; /*!< Command used to write the status register */ 489 uint16 writeEnableSRLut; /*!< Write enable command used before writing to status register */ 490 uint16 writeEnableLut; /*!< Write enable command used before write or erase operations */ 491 uint8 regSize; /*!< Size in bytes of status register */ 492 uint8 busyOffset; /*!< Position of "busy" bit inside status register */ 493 uint8 busyValue; /*!< Value of "busy" bit which indicates that the device is busy; can be 0 or 1 */ 494 uint8 writeEnableOffset; /*!< Position of "write enable" bit inside status register */ 495 uint8 blockProtectionOffset; /*!< Offset of block protection bits inside status register */ 496 uint8 blockProtectionWidth; /*!< Width of block protection bitfield */ 497 uint8 blockProtectionValue; /*!< Value of block protection bitfield, indicate the protected area */ 498 } Qspi_Ip_StatusConfigType; 499 500 501 /*! 502 * @brief Describes one type of erase 503 * 504 * This structure contains information about one type of erase supported by the external flash 505 */ 506 typedef struct 507 { 508 uint16 eraseLut; /*!< Lut index for erase command */ 509 uint8 size; /*!< Size of the erased area: 2 ^ size; e.g. 0x0C means 4 Kbytes */ 510 } Qspi_Ip_EraseVarConfigType; 511 512 513 /*! 514 * @brief Erase capabilities configuration structure 515 * 516 * This structure contains information about the erase capabilities of the external flash 517 */ 518 typedef struct 519 { 520 Qspi_Ip_EraseVarConfigType eraseTypes[QSPI_IP_ERASE_TYPES]; /*!< Erase types supported by the device */ 521 uint16 chipEraseLut; /*!< Lut index for chip erase command */ 522 } Qspi_Ip_EraseConfigType; 523 524 525 /*! 526 * @brief Read Id capabilities configuration structure 527 * 528 * This structure contains information about the read manufacturer/device ID command 529 */ 530 typedef struct 531 { 532 uint16 readIdLut; /*!< Read Id command */ 533 uint8 readIdSize; /*!< Size of data returned by Read Id command */ 534 uint8 readIdExpected[FEATURE_QSPI_FLASH_MDID_SIZE]; /*!< Device ID configured value (Memory density | Memory type | Manufacturer ID) */ 535 } Qspi_Ip_ReadIdConfigType; 536 537 538 /*! 539 * @brief Suspend capabilities configuration structure 540 * 541 * This structure contains information about the Program / Erase Suspend capabilities of the external flash 542 */ 543 typedef struct 544 { 545 uint16 eraseSuspendLut; /*!< Lut index for the erase suspend operation */ 546 uint16 eraseResumeLut; /*!< Lut index for the erase resume operation */ 547 uint16 programSuspendLut; /*!< Lut index for the program suspend operation */ 548 uint16 programResumeLut; /*!< Lut index for the program resume operation */ 549 } Qspi_Ip_SuspendConfigType; 550 551 552 /*! 553 * @brief Soft Reset capabilities configuration structure 554 * 555 * This structure contains information about the Soft Reset capabilities of the external flash 556 */ 557 typedef struct 558 { 559 uint16 resetCmdLut; /*!< First command in reset sequence */ 560 uint8 resetCmdCount; /*!< Number of commands in reset sequence */ 561 } Qspi_Ip_ResetConfigType; 562 563 564 /*! 565 * @brief Last command that was executed by the device flash 566 */ 567 typedef enum 568 { 569 QSPI_IP_LAST_COMMAND_NONE = 0U, /* Command in progress */ 570 QSPI_IP_LAST_COMMAND_WRITE = 1U, /* Erase command */ 571 QSPI_IP_LAST_COMMAND_ERASE = 2U, /* write command */ 572 QSPI_IP_LAST_COMMAND_WRITE_BUFFER_ABORT = 3U, /* Write buffer abort or CRC calculation abort */ 573 QSPI_IP_LAST_COMMAND_WRITE_SUSPEND = 4U, /* Write suspend command */ 574 QSPI_IP_LAST_COMMAND_ERASE_SUSPEND = 5U, /* Erase command */ 575 QSPI_IP_LAST_COMMAND_SECTOR_ERASE_STATUS = 6U, /* Sector erase command */ 576 QSPI_IP_LAST_COMMAND_CRC_SUSPEND = 7U /* CRC suspend command */ 577 } Qspi_Ip_LastCommandType; 578 579 580 /*! 581 * @brief List of LUT sequences. 582 * 583 * List of LUT sequences. Each sequence describes a command to the external flash. Sequences are separated by a 0 operation 584 */ 585 typedef struct 586 { 587 uint16 opCount; /*!< Number of operations in the LUT table */ 588 Qspi_Ip_InstrOpType *lutOps; /*!< List of operations */ 589 } Qspi_Ip_LutConfigType; 590 591 592 /*! 593 * @brief Initialization operation 594 * 595 * This structure describes one initialization operation. 596 */ 597 typedef struct 598 { 599 Qspi_Ip_OpType opType; /*!< Operation type */ 600 uint16 command1Lut; /*!< Index of first command sequence in Lut; for RMW type this is the read command */ 601 uint16 command2Lut; /*!< Index of second command sequence in Lut, only used for RMW type, this is the write command */ 602 uint16 weLut; /*!< Index of write enable sequence in Lut, only used for Write and RMW type */ 603 uint32 addr; /*!< Address, if used in command. */ 604 uint8 size; /*!< Size in bytes of configuration register */ 605 uint8 shift; /*!< Position of configuration field inside the register */ 606 uint8 width; /*!< Width in bits of configuration field. */ 607 uint32 value; /*!< Value to set in the field */ 608 const Qspi_Ip_ControllerConfigType * ctrlCfgPtr; /*!< New controller configuration, valid only for QSPI_IP_OP_TYPE_QSPI_CFG type */ 609 } Qspi_Ip_InitOperationType; 610 611 612 /*! 613 * @brief Initialization sequence 614 * 615 * Describe sequence that will be performed only once during initialization to put the flash in the desired state for operation. 616 * This may include, for example, setting the QE bit, activating 4-byte addressing, activating XPI mode 617 */ 618 typedef struct 619 { 620 uint8 opCount; /*!< Number of operations */ 621 Qspi_Ip_InitOperationType * operations; /*!< List of operations */ 622 } Qspi_Ip_InitConfigType; 623 624 625 /*! 626 * @brief Parameter memory type 627 */ 628 typedef enum 629 { 630 QSPI_IP_HYPER_FLASH = 1U, /*!< Hyperbus devices */ 631 QSPI_IP_SERIAL_FLASH = 0U /*!< Traditional xSPI devices */ 632 } Qspi_Ip_FlashMemoryType; 633 634 635 /*! 636 * @brief Driver configuration structure 637 * 638 * This structure is used to provide configuration parameters for the external flash driver 639 * at initialization time. 640 */ 641 typedef struct 642 { 643 Qspi_Ip_FlashMemoryType memType; /*!< Mmemory device type */ 644 const Qspi_Ip_HyperFlashConfigType * hfConfig; /*!< Hyperflash configuration, NULL if not used */ 645 uint32 memSize; /*!< Memory size (in bytes) */ 646 uint32 pageSize; /*!< Page size (in bytes) */ 647 uint16 readLut; /*!< Command used to read data from flash */ 648 uint16 writeLut; /*!< Command used to write data to flash */ 649 uint16 read0xxLut; /*!< 0-x-x mode read command */ 650 uint16 read0xxLutAHB; /*!< 0-x-x mode AHB read command */ 651 Qspi_Ip_ReadIdConfigType readIdSettings; /*!< Erase settings of the external flash */ 652 Qspi_Ip_EraseConfigType eraseSettings; /*!< Erase settings of the external flash */ 653 Qspi_Ip_StatusConfigType statusConfig; /*!< Status register information */ 654 Qspi_Ip_SuspendConfigType suspendSettings; /*!< Program / Erase Suspend settings */ 655 Qspi_Ip_ResetConfigType resetSettings; /*!< Soft Reset settings, used at runtime */ 656 Qspi_Ip_ResetConfigType initResetSettings; /*!< Soft Reset settings, used for first time reset */ 657 Qspi_Ip_InitConfigType initConfiguration; /*!< Operations for initial flash configuration */ 658 Qspi_Ip_LutConfigType lutSequences; /*!< List of LUT sequences describing flash commands */ 659 Qspi_Ip_InitCalloutPtrType initCallout; /*!< Pointer to init callout */ 660 Qspi_Ip_ResetCalloutPtrType resetCallout; /*!< Pointer to reset callout */ 661 Qspi_Ip_ErrorCheckCalloutPtrType errorCheckCallout; /*!< Pointer to error check callout */ 662 Qspi_Ip_EccCheckCalloutPtrType eccCheckCallout; /*!< Pointer to ecc check callout */ 663 const Qspi_Ip_ControllerConfigType * ctrlAutoCfgPtr; /*!< Initial controller configuration, if needed */ 664 } Qspi_Ip_MemoryConfigType; 665 666 667 /*! 668 * @brief Flash-controller conections configuration structure 669 * 670 * This structure specifies thte connecctions of each flash device to QSPI controllers 671 * at initialization time. 672 */ 673 typedef struct 674 { 675 uint32 qspiInstance; /*!< QSPI Instance where this device is connected */ 676 Qspi_Ip_ConnectionType connectionType; /*!< Device connection to QSPI module */ 677 uint8 memAlignment; /*!< Memory alignment required by the external flash */ 678 } Qspi_Ip_MemoryConnectionType; 679 680 681 #ifdef __cplusplus 682 } 683 #endif 684 685 /** @} */ 686 687 #endif /* QSPI_IP_TYPES_H */ 688
