Home
last modified time | relevance | path

Searched refs:PWRCTRL (Results 1 – 25 of 30) sorted by relevance

12

/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/puf/
Dfsl_puf.c84 base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); in puf_powerOn()
85 base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); in puf_powerOn()
86 base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); in puf_powerOn()
95 base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; in puf_powerOn()
96 while (0U == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) in puf_powerOn()
116 …base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /*… in PUF_PowerCycle()
119 base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ in PUF_PowerCycle()
120 base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK); /* enable RAM CK */ in PUF_PowerCycle()
121 …base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLAR… in PUF_PowerCycle()
128 base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | in PUF_PowerCycle()
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h7358 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h10945 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h12251 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h12251 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h15953 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h15953 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core0.h16551 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
DLPC55S66_cm33_core1.h16551 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h16551 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
DLPC55S69_cm33_core0.h16551 __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h17935 __IO uint32_t PWRCTRL; /**< PUF Power Control, offset: 0x108 */ member
DMIMXRT685S_cm33.h25921 __IO uint32_t PWRCTRL; /**< PUF Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h25921 __IO uint32_t PWRCTRL; /**< PUF Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h29610 __IO uint32_t PWRCTRL; /**< PUF Power Control, offset: 0x108 */ member
DMIMXRT595S_cm33.h36868 __IO uint32_t PWRCTRL; /**< PUF Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h35241 __IO uint32_t PWRCTRL; /**< PUF Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h36867 __IO uint32_t PWRCTRL; /**< PUF Power Control, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h63090 __IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */ member
DMIMXRT1165_cm4.h64023 __IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h74274 __IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h67933 __IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */ member
DMIMXRT1166_cm7.h67000 __IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h74274 __IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h78181 __IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */ member

12