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Searched refs:PUF_IDXBLK_L_DP_IDX5_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h16605 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
16609 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h16605 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
16609 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core0.h17203 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
17207 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
DLPC55S66_cm33_core1.h17203 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
17207 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h17203 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
17207 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
DLPC55S69_cm33_core0.h17203 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
17207 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h18593 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
18597 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
DMIMXRT685S_cm33.h26579 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
26583 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h26579 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
26583 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h30315 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
30322 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
DMIMXRT595S_cm33.h37573 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
37580 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h35946 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
35953 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h37572 #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) macro
37579 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)