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Searched refs:PUF_IDXBLK_H_DP_IDX9_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h16466 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
16470 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h16466 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
16470 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core0.h17064 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
17068 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
DLPC55S66_cm33_core1.h17064 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
17068 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h17064 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
17068 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
DLPC55S69_cm33_core0.h17064 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
17068 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h18446 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
18450 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
DMIMXRT685S_cm33.h26432 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
26436 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h26432 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
26436 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h30110 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
30117 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
DMIMXRT595S_cm33.h37368 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
37375 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h35741 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
35748 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h37367 #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) macro
37374 … (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)