Searched refs:PLL_PLLODIV_DIV_MASK (Results 1 – 3 of 3) sorted by relevance
211 #define PLL_PLLODIV_DIV_MASK (0xF0000U) macro214 … (((uint32_t)(((uint32_t)(x)) << PLL_PLLODIV_DIV_SHIFT)) & PLL_PLLODIV_DIV_MASK)
247 RegValue &= ~PLL_PLLODIV_DIV_MASK; in Clock_Ip_SetPllPll0divDeDivOutput()
1851 …Frequency /= (((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLL_PHI0_Frequency()1858 …Frequency /= (((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLL_PHI1_Frequency()1866 …Frequency /= (((IP_PLL_AUX->PLLODIV[0U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLLAUX_PHI0_Frequency()1875 …Frequency /= (((IP_PLL_AUX->PLLODIV[1U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLLAUX_PHI1_Frequency()1884 …Frequency /= (((IP_PLL_AUX->PLLODIV[2U] & PLL_PLLODIV_DIV_MASK) >> PLL_PLLODIV_DIV_SHIFT) + 1U); … in Clock_Ip_Get_PLLAUX_PHI2_Frequency()
