PLL0_SSCG_MD_FRACT_P (reference) in projects: hal_nxp-3.6.0

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Searched refs:PLL0_SSCG_MD_FRACT_P (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5506/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5502CPXXXX/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5504/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5504CPXXXX/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5506CPXXXX/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5502/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S04/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S06/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5528/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S16/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5516/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5526/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5514/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S26/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5512/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S28/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S66/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S14/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S69/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5534/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S36/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5536/drivers/
D	fsl_clock.c	`50 #define PLL0_SSCG_MD_FRACT_P 0U macro 52 #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) 55 #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_F…`

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