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Searched refs:NULL_PTR (Results 1 – 25 of 85) sorted by relevance

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/hal_nxp-3.6.0/s32/drivers/s32k3/Adc/src/
DAdc_Sar_Ip.c415 ADC_Type * AdcBasePtr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
417 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
420 volatile uint32 * STAW0RAddr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
423 volatile uint32 * STAW1RAddr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
426 volatile uint32 * STAW1ARAddr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
427 volatile uint32 * STAW1BRAddr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
430 volatile uint32 * STAW2RAddr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
433 volatile uint32 * STAW4RAddr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
434 volatile uint32 * STAW5RAddr = NULL_PTR; in Adc_Sar_ConfigSelftestThreshold()
524 ADC_Type * AdcBasePtr = NULL_PTR; in Adc_Sar_EnableSelftestThreshold()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip_HwAccess.h118 ADC_Type * AdcBasePtr = NULL_PTR; in Adc_Sar_Powerup()
120 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR; in Adc_Sar_Powerup()
145 ADC_Type * AdcBasePtr = NULL_PTR; in Adc_Sar_Powerdown()
147 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR; in Adc_Sar_Powerdown()
192 ADC_Type * AdcBasePtr = NULL_PTR; in Adc_Sar_WriteThresholds()
194 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR; in Adc_Sar_WriteThresholds()
197 volatile uint32 * THRHLR0Addr = NULL_PTR; in Adc_Sar_WriteThresholds()
198 volatile uint32 * THRHLR1Addr = NULL_PTR; in Adc_Sar_WriteThresholds()
199 volatile uint32 * THRHLR2Addr = NULL_PTR; in Adc_Sar_WriteThresholds()
200 volatile uint32 * THRHLR3Addr = NULL_PTR; in Adc_Sar_WriteThresholds()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/Platform/src/
DMru_Ip_Irq.c374 if(NULL_PTR != State) in ISR()
398 if(NULL_PTR != State) in ISR()
425 if(NULL_PTR != State) in ISR()
449 if(NULL_PTR != State) in ISR()
476 if(NULL_PTR != State) in ISR()
500 if(NULL_PTR != State) in ISR()
527 if(NULL_PTR != State) in ISR()
551 if(NULL_PTR != State) in ISR()
578 if(NULL_PTR != State) in ISR()
602 if(NULL_PTR != State) in ISR()
[all …]
DMru_Ip.c170 DevAssert(NULL_PTR != HWUnitConfigPtr); in Mru_Ip_Init_Privileged()
175 DevAssert(NULL_PTR == State); in Mru_Ip_Init_Privileged()
183 if(NULL_PTR != HWUnitConfigPtr->ChannelCfg[CfgIndex].MBLinkReceiveChCfg) in Mru_Ip_Init_Privileged()
204 DevAssert(NULL_PTR != TransmitChCfgPtr); in Mru_Ip_Transmit_Privileged()
205 DevAssert(NULL_PTR != TxBufferPtr); in Mru_Ip_Transmit_Privileged()
238 const Mru_Ip_ChannelCfgType * ChannelConfig = NULL_PTR; in Mru_Ip_ReadMailbox_Privileged()
245 DevAssert(NULL_PTR != ReceiveChCfgPtr); in Mru_Ip_ReadMailbox_Privileged()
246 DevAssert(NULL_PTR != RxBufferPtr); in Mru_Ip_ReadMailbox_Privileged()
271 if(NULL_PTR != ReceiveChCfgPtr->ReceiveNotification) in Mru_Ip_ReadMailbox_Privileged()
300 const Mru_Ip_ChannelCfgType * ChannelConfig = NULL_PTR; in Mru_Ip_GetMailboxStatus_Privileged()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Specific.c339 if (Config != NULL_PTR) in DisableSafeClock()
533 const Clock_Ip_IrcoscConfigType *ReturnValue = NULL_PTR; in getFircConfig()
535 if (Clock_Ip_apConfig != NULL_PTR) in getFircConfig()
548 if (ReturnValue == NULL_PTR) in getFircConfig()
567 const Clock_Ip_XoscConfigType *ReturnValue = NULL_PTR; in getSoscConfig()
569 if (Clock_Ip_apConfig != NULL_PTR) in getSoscConfig()
582 if (ReturnValue == NULL_PTR) in getSoscConfig()
600 const Clock_Ip_PllConfigType *ReturnValue = NULL_PTR; in getSpllConfig()
602 if (Clock_Ip_apConfig != NULL_PTR) in getSpllConfig()
615 if (ReturnValue == NULL_PTR) in getSpllConfig()
[all …]
DClock_Ip_Selector.c224 if (NULL_PTR != Config) in Clock_Ip_ResetScgRunSel()
238 if (NULL_PTR != Config) in Clock_Ip_SetScgRunSel()
255 if (NULL_PTR != Config) in Clock_Ip_SetScgVlprSel()
272 if (NULL_PTR != Config) in Clock_Ip_ResetScgHsrunSel()
285 if (NULL_PTR != Config) in Clock_Ip_SetScgHsrunSel()
301 if (NULL_PTR != Config) in Clock_Ip_ResetSimRtcSel()
314 if (NULL_PTR != Config) in Clock_Ip_SetSimRtcSel()
330 if (NULL_PTR != Config) in Clock_Ip_ResetSimLpoSel()
343 if (NULL_PTR != Config) in Clock_Ip_SetSimLpoSel()
359 if (NULL_PTR != Config) in Clock_Ip_ResetScgClkoutSel()
[all …]
DClock_Ip_Divider.c236 if (NULL_PTR != Config) in Clock_Ip_SetScgAsyncDiv1()
252 if (NULL_PTR != Config) in Clock_Ip_SetScgAsyncDiv2()
268 if (NULL_PTR != Config) in Clock_Ip_SetScgRunDivcore()
284 if (NULL_PTR != Config) in Clock_Ip_SetScgRunDivbus()
300 if (NULL_PTR != Config) in Clock_Ip_SetScgRunDivslow()
316 if (NULL_PTR != Config) in Clock_Ip_SetScgVlprDivcore()
332 if (NULL_PTR != Config) in Clock_Ip_SetScgVlprDivbus()
348 if (NULL_PTR != Config) in Clock_Ip_SetScgVlprDivslow()
364 if (NULL_PTR != Config) in Clock_Ip_SetScgHsrunDivcore()
380 if (NULL_PTR != Config) in Clock_Ip_SetScgHsrunDivbus()
[all …]
DClock_Ip.c563 Clock_Ip_axCmuCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR, 0U); in Clock_Ip_CallEmptyCallbacks()
566 Clock_Ip_axDividerCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
568 Clock_Ip_axDividerTriggerCallbacks[CLOCK_IP_NO_CALLBACK].Configure(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
570 Clock_Ip_axExtOscCallbacks[CLOCK_IP_NO_CALLBACK].Reset(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
572 Clock_Ip_axFracDivCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
575 Clock_Ip_axGateCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
578 Clock_Ip_axIntOscCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
580 Clock_Ip_axPllCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
583 Clock_Ip_axSelectorCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
585 Clock_Ip_axPcfsCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR, 0U); in Clock_Ip_CallEmptyCallbacks()
[all …]
DClock_Ip_IntOsc.c191 if (NULL_PTR != Config) in Clock_Ip_SetFircDivSelHSEb()
261 if (NULL_PTR != Config) in Clock_Ip_SetSirc()
274 if (NULL_PTR != Config) in Clock_Ip_EnableSirc()
300 if (NULL_PTR != Config) in Clock_Ip_SetSircVlp()
313 if (NULL_PTR != Config) in Clock_Ip_EnableSircVlp()
339 if (NULL_PTR != Config) in Clock_Ip_SetSircStop()
352 if (NULL_PTR != Config) in Clock_Ip_EnableSircStop()
408 if (NULL_PTR != Config) in Clock_Ip_SetFirc()
421 if (NULL_PTR != Config) in Clock_Ip_EnableFirc()
459 if (NULL_PTR == Config) in Clock_Ip_SetSirc_TrustedCall()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c272 LINFLEXD_UART_IP_DEV_ASSERT(UartState != NULL_PTR); in Linflexd_Uart_Ip_SetBaudrate()
348 LINFLEXD_UART_IP_DEV_ASSERT(ConfiguredBaudRate != NULL_PTR); in Linflexd_Uart_Ip_GetBaudrate()
354 LINFLEXD_UART_IP_DEV_ASSERT(UartStatePtr != NULL_PTR); in Linflexd_Uart_Ip_GetBaudrate()
380 LINFLEXD_UART_IP_DEV_ASSERT(NULL_PTR == Linflexd_Uart_Ip_apStateStructuresArray[Instance]); in Linflexd_Uart_Ip_Init()
381 LINFLEXD_UART_IP_DEV_ASSERT(UserConfig != NULL_PTR); in Linflexd_Uart_Ip_Init()
486 Linflexd_Uart_Ip_apStateStructuresArray[Instance] = NULL_PTR; in Linflexd_Uart_Ip_Deinit()
505 LINFLEXD_UART_IP_DEV_ASSERT(TxBuff != NULL_PTR); in Linflexd_Uart_Ip_SetTxBuffer()
512 LINFLEXD_UART_IP_DEV_ASSERT(UartState != NULL_PTR); in Linflexd_Uart_Ip_SetTxBuffer()
531 LINFLEXD_UART_IP_DEV_ASSERT(RxBuff != NULL_PTR); in Linflexd_Uart_Ip_SetRxBuffer()
538 LINFLEXD_UART_IP_DEV_ASSERT(UartState != NULL_PTR); in Linflexd_Uart_Ip_SetRxBuffer()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Data.c2648 NULL_PTR,
2649 NULL_PTR,
2650 NULL_PTR,
2651 NULL_PTR,
2679 NULL_PTR,
2680 NULL_PTR,
2681 NULL_PTR,
2682 NULL_PTR,
2683 NULL_PTR,
2684 NULL_PTR,
[all …]
DClock_Ip.c557 Clock_Ip_axCmuCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR, 0U); in Clock_Ip_CallEmptyCallbacks()
560 Clock_Ip_axDividerCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
562 Clock_Ip_axDividerTriggerCallbacks[CLOCK_IP_NO_CALLBACK].Configure(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
564 Clock_Ip_axExtOscCallbacks[CLOCK_IP_NO_CALLBACK].Reset(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
566 Clock_Ip_axFracDivCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
569 Clock_Ip_axGateCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
572 Clock_Ip_axIntOscCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
574 Clock_Ip_axPllCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
577 Clock_Ip_axSelectorCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
579 Clock_Ip_axPcfsCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR, 0U); in Clock_Ip_CallEmptyCallbacks()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/Eth_NETC/src/
DNetc_Eth_Ip.c497 config->stateStructure->SIGeneralConfig = NULL_PTR; in Netc_Eth_Ip_InitStateStructure()
498 config->stateStructure->generalConfig = NULL_PTR; in Netc_Eth_Ip_InitStateStructure()
502 config->stateStructure->PcieAerErrorReportingCallback = NULL_PTR; in Netc_Eth_Ip_InitStateStructure()
610 … Netc_Eth_Ip_RxTimestampInfoBuff[ctrlIndex][u8RxBDIdx][DataBuffIndex].ReceivedDataPtr = NULL_PTR; in Netc_Eth_Ip_InitRxBD()
686 ((*config->siConfig).siMsgMruMailboxAddr != NULL_PTR)) in Netc_Eth_Ip_EnableIrq()
693 if ((*config->siConfig).siMsgMruMailboxAddr != NULL_PTR) in Netc_Eth_Ip_EnableIrq()
845 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]); in Netc_Eth_Ip_AddMACFilterEntry()
882 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[CtrlIndex]); in Netc_Eth_Ip_DeleteMACFilterEntry()
1282 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]); in Netc_Eth_Ip_AddVLANFilterTableEntry()
1314 DevAssert(NULL_PTR != Netc_Eth_Ip_apxState[ctrlIndex]); in Netc_Eth_Ip_QueryVLANFilterTableEntry()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Dio/src/
DSiul2_Dio_Ip.c178 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_WritePin()
206 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_WritePins()
222 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_GetPinsOutput()
242 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_SetPins()
260 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_ClearPins()
276 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_TogglePins()
292 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_ReadPins()
311 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_ReadPin()
/hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip.c217 Gmac_Ip_StateType *Gmac_apxState[FEATURE_GMAC_NUM_INSTANCES] = {NULL_PTR};
742 …TxRingConfig[i].RingDesc[j].Des0 = (TxRingConfig[i].Buffer != NULL_PTR)? (uint32)(&TxRingConfig[i… in Gmac_Ip_InitTxBD()
802 if (RxRingConfig[i].Buffer != NULL_PTR) in Gmac_Ip_InitRxBD()
1093 GMAC_DEV_ASSERT(Config != NULL_PTR); in Gmac_Ip_Init()
1094 GMAC_DEV_ASSERT(Config->Gmac_pCtrlState != NULL_PTR); in Gmac_Ip_Init()
1095 GMAC_DEV_ASSERT(Config->Gmac_pCtrlConfig != NULL_PTR); in Gmac_Ip_Init()
1096 GMAC_DEV_ASSERT(Config->Gmac_paCtrlRxRingConfig != NULL_PTR); in Gmac_Ip_Init()
1097 GMAC_DEV_ASSERT(Config->Gmac_paCtrlTxRingConfig != NULL_PTR); in Gmac_Ip_Init()
1098 GMAC_DEV_ASSERT(Config->Gmac_pau8CtrlPhysAddr != NULL_PTR); in Gmac_Ip_Init()
1107 GMAC_DEV_ASSERT(Config->Gmac_paCtrlRxRingConfig[i].RingDesc != NULL_PTR); in Gmac_Ip_Init()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/src/
DOsIf_Timer_System.c281 if ((CoreId >= OSIF_MAX_COREIDX_SUPPORTED) || (NULL_PTR == OsIf_apxPredefinedConfig[CoreId])) in OsIf_Timer_System_Init()
283 if (NULL_PTR == OsIf_apxPredefinedConfig[CoreId]) in OsIf_Timer_System_Init()
335 else if ((CoreId >= OSIF_MAX_COREIDX_SUPPORTED) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_GetCounter()
337 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_GetCounter()
389 else if ((CoreId >= OSIF_MAX_COREIDX_SUPPORTED) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_GetElapsed()
391 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_GetElapsed()
444 else if ((CoreId >= OSIF_MAX_COREIDX_SUPPORTED) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_SetTimerFrequency()
446 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_SetTimerFrequency()
493 else if ((CoreId >= OSIF_MAX_COREIDX_SUPPORTED) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_MicrosToTicks()
495 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/src/
DOsIf_Timer_System.c299 if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxPredefinedConfig[CoreId])) in OsIf_Timer_System_Init()
301 if (NULL_PTR == OsIf_apxPredefinedConfig[CoreId]) in OsIf_Timer_System_Init()
358 else if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_GetCounter()
360 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_GetCounter()
419 else if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_GetElapsed()
421 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_GetElapsed()
473 else if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_SetTimerFrequency()
475 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_SetTimerFrequency()
523 else if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_MicrosToTicks()
525 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/src/
DOsIf_Timer_System.c299 if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxPredefinedConfig[CoreId])) in OsIf_Timer_System_Init()
301 if (NULL_PTR == OsIf_apxPredefinedConfig[CoreId]) in OsIf_Timer_System_Init()
358 else if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_GetCounter()
360 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_GetCounter()
419 else if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_GetElapsed()
421 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_GetElapsed()
473 else if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_SetTimerFrequency()
475 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_SetTimerFrequency()
523 else if ((OSIF_MAX_COREIDX_SUPPORTED <= CoreId) || (NULL_PTR == OsIf_apxInternalCfg[CoreId])) in OsIf_Timer_System_MicrosToTicks()
525 else if (NULL_PTR == OsIf_apxInternalCfg[CoreId]) in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.6.0/s32/drivers/s32k3/Fls/src/
DQspi_Ip.c353 …status = Qspi_Ip_RunReadCommand(instance, statusConfig->statusRegReadLut, 0U, data, NULL_PTR, stat… in Qspi_Ip_UpdateStatusReg()
394 …status = Qspi_Ip_RunReadCommand(instance, statusConfig->statusRegReadLut, 0U, data, NULL_PTR, stat… in Qspi_Ip_CheckStatusReg()
527 … status = Qspi_Ip_RunReadCommand(instance, VirtualLut, 0U, data, NULL_PTR, statusConfig->regSize); in Qspi_Ip_CheckMemoryStatus()
645 …unReadCommand(instance, operation->command1Lut, operation->addr, value, NULL_PTR, operation->size); in Qspi_Ip_InitRMWReg()
693 …unReadCommand(instance, operation->command1Lut, operation->addr, value, NULL_PTR, operation->size); in Qspi_Ip_InitReadReg()
1052 DEV_ASSERT_QSPI(data != NULL_PTR); in Qspi_Ip_RunWriteCommand()
1247 … if ((STATUS_QSPI_IP_SUCCESS == status) && (state->configuration->ctrlAutoCfgPtr != NULL_PTR)) in Qspi_Ip_Reset()
1259 if (NULL_PTR != state->configuration->resetCallout) in Qspi_Ip_Reset()
1300 …if ((state->lastCommand != QSPI_IP_LAST_COMMAND_NONE) && (NULL_PTR != state->configuration->errorC… in Qspi_Ip_GetMemoryStatus()
1365 DEV_ASSERT_QSPI(data != NULL_PTR); in Qspi_Ip_Read()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip.c557 Clock_Ip_axCmuCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR, 0U); in Clock_Ip_CallEmptyCallbacks()
560 Clock_Ip_axDividerCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
562 Clock_Ip_axDividerTriggerCallbacks[CLOCK_IP_NO_CALLBACK].Configure(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
564 Clock_Ip_axExtOscCallbacks[CLOCK_IP_NO_CALLBACK].Reset(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
566 Clock_Ip_axFracDivCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
569 Clock_Ip_axGateCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
572 Clock_Ip_axIntOscCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
574 Clock_Ip_axPllCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
577 Clock_Ip_axSelectorCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR); in Clock_Ip_CallEmptyCallbacks()
579 Clock_Ip_axPcfsCallbacks[CLOCK_IP_NO_CALLBACK].Set(NULL_PTR, 0U); in Clock_Ip_CallEmptyCallbacks()
[all …]
DClock_Ip_ExtOsc.c159 if (NULL_PTR != Config) in Clock_Ip_ResetFxoscOsconBypEocvGmSel()
177 if (NULL_PTR != Config) in Clock_Ip_SetFxoscOsconBypEocvGmSel()
221 if (NULL_PTR != Config) in Clock_Ip_CompleteFxoscOsconBypEocvGmSel()
280 if (NULL_PTR != Config) in Clock_Ip_EnableFxoscOsconBypEocvGmSel()
302 if (NULL_PTR != Config) in Clock_Ip_ResetSxoscOsconEocv()
320 if (NULL_PTR != Config) in Clock_Ip_SetSxoscOsconEocv()
351 if (NULL_PTR != Config) in Clock_Ip_CompleteSxoscOsconEocv()
/hal_nxp-3.6.0/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c481 if(NULL_PTR == State->TxBuffer) in Spi_Ip_TxDmaTcdSGConfig()
577 if(NULL_PTR == State->RxBuffer) in Spi_Ip_RxDmaTcdSGConfig()
764 if(NULL_PTR == State->TxBuffer) in Spi_Ip_DmaConfig()
811 if(NULL_PTR == State->RxBuffer) in Spi_Ip_DmaConfig()
987 if(NULL_PTR != State->RxBuffer) in Spi_Ip_ReadRxFifo()
1027 if(NULL_PTR != State->TxBuffer) in Spi_Ip_WriteTxFifo()
1119 if (NULL_PTR != State->Callback) in Spi_Ip_ChannelFinished()
1245 if(NULL_PTR != State) in Spi_Ip_IrqDmaHandler()
1292 if (State->Callback != NULL_PTR) in Spi_Ip_IrqDmaHandler()
1342 DevAssert(PhyUnitConfigPtr != NULL_PTR); in Spi_Ip_Init()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/Dio/src/
DSiul2_Dio_Ip.c269 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_WritePin()
300 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_WritePins()
326 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_GetPinsOutput()
358 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_SetPins()
388 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_ClearPins()
416 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_TogglePins()
442 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_ReadPins()
474 SIUL2_DIO_IP_DEV_ASSERT(NULL_PTR != base); in Siul2_Dio_Ip_ReadPin()
/hal_nxp-3.6.0/s32/soc/s32k344/src/
DClock_Ip_Cfg.c2310 (NULL_PTR), /* Register data if register value optimization is enabled */
2331 (NULL_PTR), /* fracDivs configurations */
2334 (NULL_PTR), /* pcfs configurations */
2343 (NULL_PTR), /* Register data if register value optimization is enabled */
2358 (NULL_PTR), /* Ircosc configurations */
2359 (NULL_PTR), /* Xosc configurations */
2360 (NULL_PTR), /* Pll configurations */
2363 (NULL_PTR), /* dividerTriggers configurations */
2364 (NULL_PTR), /* fracDivs configurations */
2367 (NULL_PTR), /* pcfs configurations */
/hal_nxp-3.6.0/s32/drivers/s32ze/EthSwt_NETC/src/
DNetc_EthSwt_Ip.c1359 DevAssert(MacAddr != NULL_PTR);
1385 DevAssert(MacAddr != NULL_PTR);
1429 DevAssert(MacAddr != NULL_PTR);
1430 DevAssert(PortIdx != NULL_PTR);
1544 DevAssert(MatchedEntries != NULL_PTR);
1545 DevAssert(FdbTableEntry != NULL_PTR);
1559 …status = Netc_EthSwt_Ip_FillInFdbTableReqDataBuff(ActionsData, &KeyeData[0U], NULL_PTR, NETC_ETHSW…
1644 DevAssert(MatchedEntries != NULL_PTR);
1645 DevAssert(FdbTableEntry != NULL_PTR);
1657 …status = Netc_EthSwt_Ip_FillInFdbTableReqDataBuff(ActionsData, &KeyeData[0U], NULL_PTR, NETC_ETHSW…
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