1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_PRIV.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_NETC_PRIV 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_PRIV_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_PRIV_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_PRIV Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_PRIV_Peripheral_Access_Layer NETC_PRIV Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_PRIV - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[256]; 74 __IO uint32_t NETCRR; /**< NETC reset register, offset: 0x100 */ 75 __I uint32_t NETCSR; /**< NETC status register, offset: 0x104 */ 76 uint8_t RESERVED_1[248]; 77 __IO uint32_t IEICR0; /**< Integrity Error Injection Config Register 0, offset: 0x200 */ 78 __IO uint32_t IEICR1; /**< Integrity Error Injection Config Register 1, offset: 0x204 */ 79 __IO uint32_t MEICR; /**< Memory Error Injection Config Register, offset: 0x208 */ 80 uint8_t RESERVED_2[244]; 81 __IO uint32_t NETCWDTR; /**< NETC watch dog timer register, offset: 0x300 */ 82 uint8_t RESERVED_3[2812]; 83 __IO uint32_t CMECR; /**< Correctable memory error configuration register, offset: 0xE00 */ 84 __IO uint32_t CMESR; /**< Correctable memory error status register, offset: 0xE04 */ 85 uint8_t RESERVED_4[4]; 86 __I uint32_t CMECTR; /**< Correctable memory error count register, offset: 0xE0C */ 87 uint8_t RESERVED_5[32]; 88 __IO uint32_t UNMECR; /**< Uncorrectable non-fatal memory error configuration register, offset: 0xE30 */ 89 __IO uint32_t UNMESR0; /**< Uncorrectable non-fatal memory error status register 0, offset: 0xE34 */ 90 __I uint32_t UNMESR1; /**< Uncorrectable non-fatal memory error status register 1, offset: 0xE38 */ 91 __I uint32_t UNMECTR; /**< Uncorrectable non-fatal memory error count register, offset: 0xE3C */ 92 __IO uint32_t UFMECR; /**< Uncorrectable fatal memory error configuration register, offset: 0xE40 */ 93 __IO uint32_t UFMESR0; /**< Uncorrectable fatal memory error status register 0, offset: 0xE44 */ 94 __I uint32_t UFMESR1; /**< Uncorrectable fatal memory error status register 1, offset: 0xE48 */ 95 uint8_t RESERVED_6[4]; 96 __IO uint32_t UNIECR; /**< Uncorrectable non-fatal integrity error configuration register, offset: 0xE50 */ 97 __IO uint32_t UNIESR; /**< Uncorrectable non-fatal integrity error status register, offset: 0xE54 */ 98 uint8_t RESERVED_7[4]; 99 __I uint32_t UNIECTR; /**< Uncorrectable non-fatal integrity error count register, offset: 0xE5C */ 100 __IO uint32_t UFIECR; /**< Uncorrectable fatal integrity error configuration register, offset: 0xE60 */ 101 __IO uint32_t UFIESR; /**< Uncorrectable fatal integrity error status register, offset: 0xE64 */ 102 } NETC_PRIV_Type, *NETC_PRIV_MemMapPtr; 103 104 /** Number of instances of the NETC_PRIV module. */ 105 #define NETC_PRIV_INSTANCE_COUNT (1u) 106 107 /* NETC_PRIV - Peripheral instance base addresses */ 108 /** Peripheral NETC__NETC_PRIV base address */ 109 #define IP_NETC__NETC_PRIV_BASE (0x74900000u) 110 /** Peripheral NETC__NETC_PRIV base pointer */ 111 #define IP_NETC__NETC_PRIV ((NETC_PRIV_Type *)IP_NETC__NETC_PRIV_BASE) 112 /** Array initializer of NETC_PRIV peripheral base addresses */ 113 #define IP_NETC_PRIV_BASE_ADDRS { IP_NETC__NETC_PRIV_BASE } 114 /** Array initializer of NETC_PRIV peripheral base pointers */ 115 #define IP_NETC_PRIV_BASE_PTRS { IP_NETC__NETC_PRIV } 116 117 /* ---------------------------------------------------------------------------- 118 -- NETC_PRIV Register Masks 119 ---------------------------------------------------------------------------- */ 120 121 /*! 122 * @addtogroup NETC_PRIV_Register_Masks NETC_PRIV Register Masks 123 * @{ 124 */ 125 126 /*! @name NETCRR - NETC reset register */ 127 /*! @{ */ 128 129 #define NETC_PRIV_NETCRR_SR_MASK (0x1U) 130 #define NETC_PRIV_NETCRR_SR_SHIFT (0U) 131 #define NETC_PRIV_NETCRR_SR_WIDTH (1U) 132 #define NETC_PRIV_NETCRR_SR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCRR_SR_SHIFT)) & NETC_PRIV_NETCRR_SR_MASK) 133 134 #define NETC_PRIV_NETCRR_LOCK_MASK (0x2U) 135 #define NETC_PRIV_NETCRR_LOCK_SHIFT (1U) 136 #define NETC_PRIV_NETCRR_LOCK_WIDTH (1U) 137 #define NETC_PRIV_NETCRR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCRR_LOCK_SHIFT)) & NETC_PRIV_NETCRR_LOCK_MASK) 138 /*! @} */ 139 140 /*! @name NETCSR - NETC status register */ 141 /*! @{ */ 142 143 #define NETC_PRIV_NETCSR_ERROR_MASK (0x1U) 144 #define NETC_PRIV_NETCSR_ERROR_SHIFT (0U) 145 #define NETC_PRIV_NETCSR_ERROR_WIDTH (1U) 146 #define NETC_PRIV_NETCSR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCSR_ERROR_SHIFT)) & NETC_PRIV_NETCSR_ERROR_MASK) 147 148 #define NETC_PRIV_NETCSR_STATE_MASK (0x2U) 149 #define NETC_PRIV_NETCSR_STATE_SHIFT (1U) 150 #define NETC_PRIV_NETCSR_STATE_WIDTH (1U) 151 #define NETC_PRIV_NETCSR_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCSR_STATE_SHIFT)) & NETC_PRIV_NETCSR_STATE_MASK) 152 /*! @} */ 153 154 /*! @name IEICR0 - Integrity Error Injection Config Register 0 */ 155 /*! @{ */ 156 157 #define NETC_PRIV_IEICR0_LINK_SLICE_ID_MASK (0xFU) 158 #define NETC_PRIV_IEICR0_LINK_SLICE_ID_SHIFT (0U) 159 #define NETC_PRIV_IEICR0_LINK_SLICE_ID_WIDTH (4U) 160 #define NETC_PRIV_IEICR0_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_IEICR0_LINK_SLICE_ID_SHIFT)) & NETC_PRIV_IEICR0_LINK_SLICE_ID_MASK) 161 162 #define NETC_PRIV_IEICR0_BLOCK_ID_MASK (0xF0U) 163 #define NETC_PRIV_IEICR0_BLOCK_ID_SHIFT (4U) 164 #define NETC_PRIV_IEICR0_BLOCK_ID_WIDTH (4U) 165 #define NETC_PRIV_IEICR0_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_IEICR0_BLOCK_ID_SHIFT)) & NETC_PRIV_IEICR0_BLOCK_ID_MASK) 166 167 #define NETC_PRIV_IEICR0_SM_ID_MASK (0x3F00U) 168 #define NETC_PRIV_IEICR0_SM_ID_SHIFT (8U) 169 #define NETC_PRIV_IEICR0_SM_ID_WIDTH (6U) 170 #define NETC_PRIV_IEICR0_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_IEICR0_SM_ID_SHIFT)) & NETC_PRIV_IEICR0_SM_ID_MASK) 171 172 #define NETC_PRIV_IEICR0_ENGINE_ID_MASK (0x10000U) 173 #define NETC_PRIV_IEICR0_ENGINE_ID_SHIFT (16U) 174 #define NETC_PRIV_IEICR0_ENGINE_ID_WIDTH (1U) 175 #define NETC_PRIV_IEICR0_ENGINE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_IEICR0_ENGINE_ID_SHIFT)) & NETC_PRIV_IEICR0_ENGINE_ID_MASK) 176 177 #define NETC_PRIV_IEICR0_ARM_MASK (0x400000U) 178 #define NETC_PRIV_IEICR0_ARM_SHIFT (22U) 179 #define NETC_PRIV_IEICR0_ARM_WIDTH (1U) 180 #define NETC_PRIV_IEICR0_ARM(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_IEICR0_ARM_SHIFT)) & NETC_PRIV_IEICR0_ARM_MASK) 181 182 #define NETC_PRIV_IEICR0_EN_MASK (0xFF000000U) 183 #define NETC_PRIV_IEICR0_EN_SHIFT (24U) 184 #define NETC_PRIV_IEICR0_EN_WIDTH (8U) 185 #define NETC_PRIV_IEICR0_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_IEICR0_EN_SHIFT)) & NETC_PRIV_IEICR0_EN_MASK) 186 /*! @} */ 187 188 /*! @name IEICR1 - Integrity Error Injection Config Register 1 */ 189 /*! @{ */ 190 191 #define NETC_PRIV_IEICR1_ENGINE_EN0_MASK (0x1U) 192 #define NETC_PRIV_IEICR1_ENGINE_EN0_SHIFT (0U) 193 #define NETC_PRIV_IEICR1_ENGINE_EN0_WIDTH (1U) 194 #define NETC_PRIV_IEICR1_ENGINE_EN0(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_IEICR1_ENGINE_EN0_SHIFT)) & NETC_PRIV_IEICR1_ENGINE_EN0_MASK) 195 196 #define NETC_PRIV_IEICR1_ENGINE_EN1_MASK (0x2U) 197 #define NETC_PRIV_IEICR1_ENGINE_EN1_SHIFT (1U) 198 #define NETC_PRIV_IEICR1_ENGINE_EN1_WIDTH (1U) 199 #define NETC_PRIV_IEICR1_ENGINE_EN1(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_IEICR1_ENGINE_EN1_SHIFT)) & NETC_PRIV_IEICR1_ENGINE_EN1_MASK) 200 /*! @} */ 201 202 /*! @name MEICR - Memory Error Injection Config Register */ 203 /*! @{ */ 204 205 #define NETC_PRIV_MEICR_MEM_ID_MASK (0x1FU) 206 #define NETC_PRIV_MEICR_MEM_ID_SHIFT (0U) 207 #define NETC_PRIV_MEICR_MEM_ID_WIDTH (5U) 208 #define NETC_PRIV_MEICR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_MEM_ID_SHIFT)) & NETC_PRIV_MEICR_MEM_ID_MASK) 209 210 #define NETC_PRIV_MEICR_ARM_MASK (0xC00000U) 211 #define NETC_PRIV_MEICR_ARM_SHIFT (22U) 212 #define NETC_PRIV_MEICR_ARM_WIDTH (2U) 213 #define NETC_PRIV_MEICR_ARM(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_ARM_SHIFT)) & NETC_PRIV_MEICR_ARM_MASK) 214 215 #define NETC_PRIV_MEICR_EN_MASK (0xFF000000U) 216 #define NETC_PRIV_MEICR_EN_SHIFT (24U) 217 #define NETC_PRIV_MEICR_EN_WIDTH (8U) 218 #define NETC_PRIV_MEICR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_MEICR_EN_SHIFT)) & NETC_PRIV_MEICR_EN_MASK) 219 /*! @} */ 220 221 /*! @name NETCWDTR - NETC watch dog timer register */ 222 /*! @{ */ 223 224 #define NETC_PRIV_NETCWDTR_MCED_MASK (0x1U) 225 #define NETC_PRIV_NETCWDTR_MCED_SHIFT (0U) 226 #define NETC_PRIV_NETCWDTR_MCED_WIDTH (1U) 227 #define NETC_PRIV_NETCWDTR_MCED(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCWDTR_MCED_SHIFT)) & NETC_PRIV_NETCWDTR_MCED_MASK) 228 229 #define NETC_PRIV_NETCWDTR_MCPD_MASK (0x2U) 230 #define NETC_PRIV_NETCWDTR_MCPD_SHIFT (1U) 231 #define NETC_PRIV_NETCWDTR_MCPD_WIDTH (1U) 232 #define NETC_PRIV_NETCWDTR_MCPD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCWDTR_MCPD_SHIFT)) & NETC_PRIV_NETCWDTR_MCPD_MASK) 233 234 #define NETC_PRIV_NETCWDTR_PCED_MASK (0x4U) 235 #define NETC_PRIV_NETCWDTR_PCED_SHIFT (2U) 236 #define NETC_PRIV_NETCWDTR_PCED_WIDTH (1U) 237 #define NETC_PRIV_NETCWDTR_PCED(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCWDTR_PCED_SHIFT)) & NETC_PRIV_NETCWDTR_PCED_MASK) 238 239 #define NETC_PRIV_NETCWDTR_HTAD_MASK (0x8U) 240 #define NETC_PRIV_NETCWDTR_HTAD_SHIFT (3U) 241 #define NETC_PRIV_NETCWDTR_HTAD_WIDTH (1U) 242 #define NETC_PRIV_NETCWDTR_HTAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_NETCWDTR_HTAD_SHIFT)) & NETC_PRIV_NETCWDTR_HTAD_MASK) 243 /*! @} */ 244 245 /*! @name CMECR - Correctable memory error configuration register */ 246 /*! @{ */ 247 248 #define NETC_PRIV_CMECR_THRESHOLD_MASK (0xFFU) 249 #define NETC_PRIV_CMECR_THRESHOLD_SHIFT (0U) 250 #define NETC_PRIV_CMECR_THRESHOLD_WIDTH (8U) 251 #define NETC_PRIV_CMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMECR_THRESHOLD_SHIFT)) & NETC_PRIV_CMECR_THRESHOLD_MASK) 252 /*! @} */ 253 254 /*! @name CMESR - Correctable memory error status register */ 255 /*! @{ */ 256 257 #define NETC_PRIV_CMESR_MEM_ID_MASK (0x1F0000U) 258 #define NETC_PRIV_CMESR_MEM_ID_SHIFT (16U) 259 #define NETC_PRIV_CMESR_MEM_ID_WIDTH (5U) 260 #define NETC_PRIV_CMESR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMESR_MEM_ID_SHIFT)) & NETC_PRIV_CMESR_MEM_ID_MASK) 261 262 #define NETC_PRIV_CMESR_SBEE_MASK (0x80000000U) 263 #define NETC_PRIV_CMESR_SBEE_SHIFT (31U) 264 #define NETC_PRIV_CMESR_SBEE_WIDTH (1U) 265 #define NETC_PRIV_CMESR_SBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMESR_SBEE_SHIFT)) & NETC_PRIV_CMESR_SBEE_MASK) 266 /*! @} */ 267 268 /*! @name CMECTR - Correctable memory error count register */ 269 /*! @{ */ 270 271 #define NETC_PRIV_CMECTR_COUNT_MASK (0xFFU) 272 #define NETC_PRIV_CMECTR_COUNT_SHIFT (0U) 273 #define NETC_PRIV_CMECTR_COUNT_WIDTH (8U) 274 #define NETC_PRIV_CMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_CMECTR_COUNT_SHIFT)) & NETC_PRIV_CMECTR_COUNT_MASK) 275 /*! @} */ 276 277 /*! @name UNMECR - Uncorrectable non-fatal memory error configuration register */ 278 /*! @{ */ 279 280 #define NETC_PRIV_UNMECR_THRESHOLD_MASK (0xFFU) 281 #define NETC_PRIV_UNMECR_THRESHOLD_SHIFT (0U) 282 #define NETC_PRIV_UNMECR_THRESHOLD_WIDTH (8U) 283 #define NETC_PRIV_UNMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECR_THRESHOLD_SHIFT)) & NETC_PRIV_UNMECR_THRESHOLD_MASK) 284 285 #define NETC_PRIV_UNMECR_RD_MASK (0x80000000U) 286 #define NETC_PRIV_UNMECR_RD_SHIFT (31U) 287 #define NETC_PRIV_UNMECR_RD_WIDTH (1U) 288 #define NETC_PRIV_UNMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECR_RD_SHIFT)) & NETC_PRIV_UNMECR_RD_MASK) 289 /*! @} */ 290 291 /*! @name UNMESR0 - Uncorrectable non-fatal memory error status register 0 */ 292 /*! @{ */ 293 294 #define NETC_PRIV_UNMESR0_SYNDROME_MASK (0x7FFU) 295 #define NETC_PRIV_UNMESR0_SYNDROME_SHIFT (0U) 296 #define NETC_PRIV_UNMESR0_SYNDROME_WIDTH (11U) 297 #define NETC_PRIV_UNMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_SYNDROME_SHIFT)) & NETC_PRIV_UNMESR0_SYNDROME_MASK) 298 299 #define NETC_PRIV_UNMESR0_MEM_ID_MASK (0x1F0000U) 300 #define NETC_PRIV_UNMESR0_MEM_ID_SHIFT (16U) 301 #define NETC_PRIV_UNMESR0_MEM_ID_WIDTH (5U) 302 #define NETC_PRIV_UNMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_MEM_ID_SHIFT)) & NETC_PRIV_UNMESR0_MEM_ID_MASK) 303 304 #define NETC_PRIV_UNMESR0_MBEE_MASK (0x80000000U) 305 #define NETC_PRIV_UNMESR0_MBEE_SHIFT (31U) 306 #define NETC_PRIV_UNMESR0_MBEE_WIDTH (1U) 307 #define NETC_PRIV_UNMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR0_MBEE_SHIFT)) & NETC_PRIV_UNMESR0_MBEE_MASK) 308 /*! @} */ 309 310 /*! @name UNMESR1 - Uncorrectable non-fatal memory error status register 1 */ 311 /*! @{ */ 312 313 #define NETC_PRIV_UNMESR1_ADDR_MASK (0xFFFFFFFFU) 314 #define NETC_PRIV_UNMESR1_ADDR_SHIFT (0U) 315 #define NETC_PRIV_UNMESR1_ADDR_WIDTH (32U) 316 #define NETC_PRIV_UNMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMESR1_ADDR_SHIFT)) & NETC_PRIV_UNMESR1_ADDR_MASK) 317 /*! @} */ 318 319 /*! @name UNMECTR - Uncorrectable non-fatal memory error count register */ 320 /*! @{ */ 321 322 #define NETC_PRIV_UNMECTR_COUNT_MASK (0xFFU) 323 #define NETC_PRIV_UNMECTR_COUNT_SHIFT (0U) 324 #define NETC_PRIV_UNMECTR_COUNT_WIDTH (8U) 325 #define NETC_PRIV_UNMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNMECTR_COUNT_SHIFT)) & NETC_PRIV_UNMECTR_COUNT_MASK) 326 /*! @} */ 327 328 /*! @name UFMECR - Uncorrectable fatal memory error configuration register */ 329 /*! @{ */ 330 331 #define NETC_PRIV_UFMECR_RD_MASK (0x80000000U) 332 #define NETC_PRIV_UFMECR_RD_SHIFT (31U) 333 #define NETC_PRIV_UFMECR_RD_WIDTH (1U) 334 #define NETC_PRIV_UFMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMECR_RD_SHIFT)) & NETC_PRIV_UFMECR_RD_MASK) 335 /*! @} */ 336 337 /*! @name UFMESR0 - Uncorrectable fatal memory error status register 0 */ 338 /*! @{ */ 339 340 #define NETC_PRIV_UFMESR0_SYNDROME_MASK (0x7FFU) 341 #define NETC_PRIV_UFMESR0_SYNDROME_SHIFT (0U) 342 #define NETC_PRIV_UFMESR0_SYNDROME_WIDTH (11U) 343 #define NETC_PRIV_UFMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_SYNDROME_SHIFT)) & NETC_PRIV_UFMESR0_SYNDROME_MASK) 344 345 #define NETC_PRIV_UFMESR0_MEM_ID_MASK (0x1F0000U) 346 #define NETC_PRIV_UFMESR0_MEM_ID_SHIFT (16U) 347 #define NETC_PRIV_UFMESR0_MEM_ID_WIDTH (5U) 348 #define NETC_PRIV_UFMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_MEM_ID_SHIFT)) & NETC_PRIV_UFMESR0_MEM_ID_MASK) 349 350 #define NETC_PRIV_UFMESR0_M_MASK (0x40000000U) 351 #define NETC_PRIV_UFMESR0_M_SHIFT (30U) 352 #define NETC_PRIV_UFMESR0_M_WIDTH (1U) 353 #define NETC_PRIV_UFMESR0_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_M_SHIFT)) & NETC_PRIV_UFMESR0_M_MASK) 354 355 #define NETC_PRIV_UFMESR0_MBEE_MASK (0x80000000U) 356 #define NETC_PRIV_UFMESR0_MBEE_SHIFT (31U) 357 #define NETC_PRIV_UFMESR0_MBEE_WIDTH (1U) 358 #define NETC_PRIV_UFMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR0_MBEE_SHIFT)) & NETC_PRIV_UFMESR0_MBEE_MASK) 359 /*! @} */ 360 361 /*! @name UFMESR1 - Uncorrectable fatal memory error status register 1 */ 362 /*! @{ */ 363 364 #define NETC_PRIV_UFMESR1_ADDR_MASK (0xFFFFFFFFU) 365 #define NETC_PRIV_UFMESR1_ADDR_SHIFT (0U) 366 #define NETC_PRIV_UFMESR1_ADDR_WIDTH (32U) 367 #define NETC_PRIV_UFMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFMESR1_ADDR_SHIFT)) & NETC_PRIV_UFMESR1_ADDR_MASK) 368 /*! @} */ 369 370 /*! @name UNIECR - Uncorrectable non-fatal integrity error configuration register */ 371 /*! @{ */ 372 373 #define NETC_PRIV_UNIECR_THRESHOLD_MASK (0xFFU) 374 #define NETC_PRIV_UNIECR_THRESHOLD_SHIFT (0U) 375 #define NETC_PRIV_UNIECR_THRESHOLD_WIDTH (8U) 376 #define NETC_PRIV_UNIECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNIECR_THRESHOLD_SHIFT)) & NETC_PRIV_UNIECR_THRESHOLD_MASK) 377 378 #define NETC_PRIV_UNIECR_RD_MASK (0x80000000U) 379 #define NETC_PRIV_UNIECR_RD_SHIFT (31U) 380 #define NETC_PRIV_UNIECR_RD_WIDTH (1U) 381 #define NETC_PRIV_UNIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNIECR_RD_SHIFT)) & NETC_PRIV_UNIECR_RD_MASK) 382 /*! @} */ 383 384 /*! @name UNIESR - Uncorrectable non-fatal integrity error status register */ 385 /*! @{ */ 386 387 #define NETC_PRIV_UNIESR_LINK_SLICE_ID_MASK (0xFU) 388 #define NETC_PRIV_UNIESR_LINK_SLICE_ID_SHIFT (0U) 389 #define NETC_PRIV_UNIESR_LINK_SLICE_ID_WIDTH (4U) 390 #define NETC_PRIV_UNIESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNIESR_LINK_SLICE_ID_SHIFT)) & NETC_PRIV_UNIESR_LINK_SLICE_ID_MASK) 391 392 #define NETC_PRIV_UNIESR_BLOCK_ID_MASK (0xF0U) 393 #define NETC_PRIV_UNIESR_BLOCK_ID_SHIFT (4U) 394 #define NETC_PRIV_UNIESR_BLOCK_ID_WIDTH (4U) 395 #define NETC_PRIV_UNIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNIESR_BLOCK_ID_SHIFT)) & NETC_PRIV_UNIESR_BLOCK_ID_MASK) 396 397 #define NETC_PRIV_UNIESR_SM_ID_MASK (0x3F00U) 398 #define NETC_PRIV_UNIESR_SM_ID_SHIFT (8U) 399 #define NETC_PRIV_UNIESR_SM_ID_WIDTH (6U) 400 #define NETC_PRIV_UNIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNIESR_SM_ID_SHIFT)) & NETC_PRIV_UNIESR_SM_ID_MASK) 401 402 #define NETC_PRIV_UNIESR_ENGINE_ID_MASK (0x10000U) 403 #define NETC_PRIV_UNIESR_ENGINE_ID_SHIFT (16U) 404 #define NETC_PRIV_UNIESR_ENGINE_ID_WIDTH (1U) 405 #define NETC_PRIV_UNIESR_ENGINE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNIESR_ENGINE_ID_SHIFT)) & NETC_PRIV_UNIESR_ENGINE_ID_MASK) 406 407 #define NETC_PRIV_UNIESR_INTERR_MASK (0x80000000U) 408 #define NETC_PRIV_UNIESR_INTERR_SHIFT (31U) 409 #define NETC_PRIV_UNIESR_INTERR_WIDTH (1U) 410 #define NETC_PRIV_UNIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNIESR_INTERR_SHIFT)) & NETC_PRIV_UNIESR_INTERR_MASK) 411 /*! @} */ 412 413 /*! @name UNIECTR - Uncorrectable non-fatal integrity error count register */ 414 /*! @{ */ 415 416 #define NETC_PRIV_UNIECTR_COUNT_MASK (0xFFU) 417 #define NETC_PRIV_UNIECTR_COUNT_SHIFT (0U) 418 #define NETC_PRIV_UNIECTR_COUNT_WIDTH (8U) 419 #define NETC_PRIV_UNIECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UNIECTR_COUNT_SHIFT)) & NETC_PRIV_UNIECTR_COUNT_MASK) 420 /*! @} */ 421 422 /*! @name UFIECR - Uncorrectable fatal integrity error configuration register */ 423 /*! @{ */ 424 425 #define NETC_PRIV_UFIECR_RD_MASK (0x80000000U) 426 #define NETC_PRIV_UFIECR_RD_SHIFT (31U) 427 #define NETC_PRIV_UFIECR_RD_WIDTH (1U) 428 #define NETC_PRIV_UFIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFIECR_RD_SHIFT)) & NETC_PRIV_UFIECR_RD_MASK) 429 /*! @} */ 430 431 /*! @name UFIESR - Uncorrectable fatal integrity error status register */ 432 /*! @{ */ 433 434 #define NETC_PRIV_UFIESR_LINK_SLICE_ID_MASK (0xFU) 435 #define NETC_PRIV_UFIESR_LINK_SLICE_ID_SHIFT (0U) 436 #define NETC_PRIV_UFIESR_LINK_SLICE_ID_WIDTH (4U) 437 #define NETC_PRIV_UFIESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFIESR_LINK_SLICE_ID_SHIFT)) & NETC_PRIV_UFIESR_LINK_SLICE_ID_MASK) 438 439 #define NETC_PRIV_UFIESR_BLOCK_ID_MASK (0xF0U) 440 #define NETC_PRIV_UFIESR_BLOCK_ID_SHIFT (4U) 441 #define NETC_PRIV_UFIESR_BLOCK_ID_WIDTH (4U) 442 #define NETC_PRIV_UFIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFIESR_BLOCK_ID_SHIFT)) & NETC_PRIV_UFIESR_BLOCK_ID_MASK) 443 444 #define NETC_PRIV_UFIESR_SM_ID_MASK (0x3F00U) 445 #define NETC_PRIV_UFIESR_SM_ID_SHIFT (8U) 446 #define NETC_PRIV_UFIESR_SM_ID_WIDTH (6U) 447 #define NETC_PRIV_UFIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFIESR_SM_ID_SHIFT)) & NETC_PRIV_UFIESR_SM_ID_MASK) 448 449 #define NETC_PRIV_UFIESR_ENGINE_ID_MASK (0x10000U) 450 #define NETC_PRIV_UFIESR_ENGINE_ID_SHIFT (16U) 451 #define NETC_PRIV_UFIESR_ENGINE_ID_WIDTH (1U) 452 #define NETC_PRIV_UFIESR_ENGINE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFIESR_ENGINE_ID_SHIFT)) & NETC_PRIV_UFIESR_ENGINE_ID_MASK) 453 454 #define NETC_PRIV_UFIESR_M_MASK (0x40000000U) 455 #define NETC_PRIV_UFIESR_M_SHIFT (30U) 456 #define NETC_PRIV_UFIESR_M_WIDTH (1U) 457 #define NETC_PRIV_UFIESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFIESR_M_SHIFT)) & NETC_PRIV_UFIESR_M_MASK) 458 459 #define NETC_PRIV_UFIESR_INTERR_MASK (0x80000000U) 460 #define NETC_PRIV_UFIESR_INTERR_SHIFT (31U) 461 #define NETC_PRIV_UFIESR_INTERR_WIDTH (1U) 462 #define NETC_PRIV_UFIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_PRIV_UFIESR_INTERR_SHIFT)) & NETC_PRIV_UFIESR_INTERR_MASK) 463 /*! @} */ 464 465 /*! 466 * @} 467 */ /* end of group NETC_PRIV_Register_Masks */ 468 469 /*! 470 * @} 471 */ /* end of group NETC_PRIV_Peripheral_Access_Layer */ 472 473 #endif /* #if !defined(S32Z2_NETC_PRIV_H_) */ 474
