1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_IERB.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_NETC_IERB 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_IERB_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_IERB_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_IERB Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_IERB_Peripheral_Access_Layer NETC_IERB Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_IERB - Size of Registers Arrays */ 72 #define NETC_IERB_HTA_NUM_COUNT 1u 73 #define NETC_IERB_ARRAY_NUM_RC_COUNT 1u 74 #define NETC_IERB_EMDIO_PF_BOOT_LOAD_COUNT 2u 75 #define NETC_IERB_NUM_TMR_ARRAY_TMR_PF_BOOT_LOAD_COUNT 2u 76 #define NETC_IERB_NUM_TMR_ARRAY_COUNT 1u 77 #define NETC_IERB_CFG_SW_INST_SW_PF_BOOT_LOAD_COUNT 2u 78 #define NETC_IERB_CFG_SW_INST_COUNT 1u 79 #define NETC_IERB_CFG_ENETC_INST_ENETC_PF_BOOT_LOAD_COUNT 2u 80 #define NETC_IERB_CFG_ENETC_INST_COUNT 1u 81 #define NETC_IERB_CFG_VSI_INST_VSI_PF_BOOT_LOAD_COUNT 2u 82 #define NETC_IERB_CFG_VSI_INST_COUNT 7u 83 84 /** NETC_IERB - Register Layout Typedef */ 85 typedef struct { 86 __I uint32_t CAPR0; /**< Capability register 0, offset: 0x0 */ 87 __I uint32_t CAPR1; /**< Capability register 1, offset: 0x4 */ 88 __I uint32_t CAPR2; /**< Capability register 2, offset: 0x8 */ 89 __I uint32_t CAPR3; /**< Capability register 3, offset: 0xC */ 90 uint8_t RESERVED_0[16]; 91 __I uint32_t CMCAPR; /**< Common memory capability register, offset: 0x20 */ 92 uint8_t RESERVED_1[12]; 93 __I uint32_t IPFTMCAPR; /**< Ingress port filter ternary memory capability register, offset: 0x30 */ 94 uint8_t RESERVED_2[16]; 95 __I uint32_t TGSMCAPR; /**< Time gate scheduling memory capability register, offset: 0x44 */ 96 uint8_t RESERVED_3[56]; 97 __IO uint32_t SMDTR; /**< Shared memory depletion threshold register, offset: 0x80 */ 98 __IO uint32_t ERSMBAR; /**< ENETC receive shared memory buffer allotment register, offset: 0x84 */ 99 uint8_t RESERVED_4[56]; 100 struct { /* offset: 0xC0, array step: 0x8 */ 101 __IO uint32_t HTAHPCR; /**< HTA 0 HP configuration register, array offset: 0xC0, array step: 0x8 */ 102 __IO uint32_t HTALPCR; /**< HTA 0 LP configuration register, array offset: 0xC4, array step: 0x8 */ 103 } HTA_NUM[NETC_IERB_HTA_NUM_COUNT]; 104 uint8_t RESERVED_5[56]; 105 __IO uint32_t HBTMAR; /**< Hash bucket table memory allocation register, offset: 0x100 */ 106 __IO uint32_t HBTCR; /**< Hash bucket table configuration register, offset: 0x104 */ 107 __I uint32_t GHTEMCAPR; /**< Guaranteed hash table entry memory capability register, offset: 0x108 */ 108 uint8_t RESERVED_6[100]; 109 __IO uint32_t NETCFLRCR; /**< NETC FLR configuration register, offset: 0x170 */ 110 uint8_t RESERVED_7[4]; 111 __IO uint32_t NETCCLKFR; /**< NETC clock period fractional register, offset: 0x178 */ 112 __IO uint32_t NETCCLKCR; /**< NETC clock configuration register, offset: 0x17C */ 113 __IO uint32_t SBCR; /**< System bus configuration register, offset: 0x180 */ 114 __IO uint32_t SBOTCR; /**< System bus outstanding transaction control register, offset: 0x184 */ 115 uint8_t RESERVED_8[8]; 116 __IO uint32_t SGLTTR; /**< Stream gating lag time for refresh register, offset: 0x190 */ 117 uint8_t RESERVED_9[108]; 118 struct { /* offset: 0x200, array step: 0x10 */ 119 __I uint32_t RBCR; /**< Root complex 0 binding configuration register, array offset: 0x200, array step: 0x10 */ 120 uint8_t RESERVED_0[4]; 121 __IO uint32_t RCMSICAR; /**< Root complex 0 MSI-X cache attribute register, array offset: 0x208, array step: 0x10 */ 122 __IO uint32_t RCMSIAMQR; /**< Root complex 0 MSI access management qualifier register, array offset: 0x20C, array step: 0x10 */ 123 } ARRAY_NUM_RC[NETC_IERB_ARRAY_NUM_RC_COUNT]; 124 uint8_t RESERVED_10[240]; 125 __I uint32_t EMDIOBCR; /**< EMDIO binding configuration register, offset: 0x300 */ 126 uint8_t RESERVED_11[16]; 127 __I uint32_t EMDIOMCR; /**< EMDIO MSI-X configuration register, offset: 0x314 */ 128 uint8_t RESERVED_12[8]; 129 __IO uint32_t EMDIO_CFH_DIDVID; /**< EMDIO config header device ID and vendor ID register, offset: 0x320 */ 130 __IO uint32_t EMDIO_CFH_SIDSVID; /**< EMDIO config header subsystem ID and subsystem vendor ID register, offset: 0x324 */ 131 uint8_t RESERVED_13[32]; 132 __IO uint32_t EMDIOBLPR[NETC_IERB_EMDIO_PF_BOOT_LOAD_COUNT]; /**< EMDIO boot loader parameter register 0..EMDIO boot loader parameter register 1, array offset: 0x348, array step: 0x4 */ 133 __IO uint32_t EMDIO_CFG; /**< EMDIO configuration register, offset: 0x350 */ 134 uint8_t RESERVED_14[172]; 135 struct { /* offset: 0x400, array step: 0x50 */ 136 __I uint32_t TBCR; /**< Timer 0 binding configuration register, array offset: 0x400, array step: 0x50 */ 137 uint8_t RESERVED_0[16]; 138 __IO uint32_t TMCR; /**< Timer 0 MSI-X configuration register, array offset: 0x414, array step: 0x50 */ 139 uint8_t RESERVED_1[8]; 140 __IO uint32_t T_CFH_DIDVID; /**< Timer 0 config header device ID and vendor ID register, array offset: 0x420, array step: 0x50 */ 141 __IO uint32_t T_CFH_SIDSVID; /**< Timer 0 config header subsystem ID and subsystem vendor ID register, array offset: 0x424, array step: 0x50 */ 142 uint8_t RESERVED_2[32]; 143 __IO uint32_t TBLPR[NETC_IERB_NUM_TMR_ARRAY_TMR_PF_BOOT_LOAD_COUNT]; /**< Timer 0 boot loader parameter register 0..Timer 0 boot loader parameter register 1, array offset: 0x448, array step: index*0x50, index2*0x4 */ 144 } NUM_TMR_ARRAY[NETC_IERB_NUM_TMR_ARRAY_COUNT]; 145 uint8_t RESERVED_15[2992]; 146 __I uint32_t L0CAPR; /**< Link 0 capability register, offset: 0x1000 */ 147 __I uint32_t L0MCAPR; /**< Link 0 MAC capability register, offset: 0x1004 */ 148 __I uint32_t L0IOCAPR; /**< Link 0 I/O capability register, offset: 0x1008 */ 149 uint8_t RESERVED_16[4]; 150 __IO uint32_t L0BCR; /**< Link 0 binding configuration register, offset: 0x1010 */ 151 __IO uint32_t L0TXBCCTR; /**< Link 0 transmit byte credit comfort threshold register, offset: 0x1014 */ 152 uint8_t RESERVED_17[8]; 153 __IO uint32_t L0E0MAR0; /**< Link 0 end 0 MAC address register 0, offset: 0x1020 */ 154 __IO uint32_t L0E0MAR1; /**< Link 0 end 0 MAC address register 1, offset: 0x1024 */ 155 uint8_t RESERVED_18[24]; 156 __I uint32_t L1CAPR; /**< Link 1 capability register, offset: 0x1040 */ 157 __I uint32_t L1MCAPR; /**< Link 1 MAC capability register, offset: 0x1044 */ 158 __I uint32_t L1IOCAPR; /**< Link 1 I/O capability register, offset: 0x1048 */ 159 uint8_t RESERVED_19[4]; 160 __IO uint32_t L1BCR; /**< Link 1 binding configuration register, offset: 0x1050 */ 161 __IO uint32_t L1TXBCCTR; /**< Link 1 transmit byte credit comfort threshold register, offset: 0x1054 */ 162 uint8_t RESERVED_20[8]; 163 __IO uint32_t L1E0MAR0; /**< Link 1 end 0 MAC address register 0, offset: 0x1060 */ 164 __IO uint32_t L1E0MAR1; /**< Link 1 end 0 MAC address register 1, offset: 0x1064 */ 165 uint8_t RESERVED_21[24]; 166 __I uint32_t L2CAPR; /**< Link 2 capability register, offset: 0x1080 */ 167 __I uint32_t L2MCAPR; /**< Link 2 MAC capability register, offset: 0x1084 */ 168 uint8_t RESERVED_22[8]; 169 __I uint32_t L2BCR; /**< Link 2 binding configuration register, offset: 0x1090 */ 170 __IO uint32_t L2TXBCCTR; /**< Link 2 transmit byte credit comfort threshold register, offset: 0x1094 */ 171 uint8_t RESERVED_23[8]; 172 __IO uint32_t L2E0MAR0; /**< Link 2 end 0 MAC address register 0, offset: 0x10A0 */ 173 __IO uint32_t L2E0MAR1; /**< Link 2 end 0 MAC address register 1, offset: 0x10A4 */ 174 __IO uint32_t L2E1MAR0; /**< Link 2 end 1 MAC address register 0, offset: 0x10A8 */ 175 __IO uint32_t L2E1MAR1; /**< Link 2 end 1 MAC address register 1, offset: 0x10AC */ 176 uint8_t RESERVED_24[3920]; 177 struct { /* offset: 0x2000, array step: 0x21C */ 178 __I uint32_t SBCR; /**< Switch 0 binding configuration register, array offset: 0x2000, array step: 0x21C */ 179 uint8_t RESERVED_0[16]; 180 __IO uint32_t SMCR; /**< Switch 0 MSI-X configuration register, array offset: 0x2014, array step: 0x21C */ 181 uint8_t RESERVED_1[8]; 182 __IO uint32_t S_CFH_DIDVID; /**< Switch 0 config header device ID and vendor ID register, array offset: 0x2020, array step: 0x21C */ 183 __IO uint32_t S_CFH_SIDSVID; /**< Switch 0 config header subsystem ID and subsystem vendor ID register, array offset: 0x2024, array step: 0x21C */ 184 uint8_t RESERVED_2[16]; 185 __IO uint32_t SCCAR; /**< Switch 0 command cache attribute register, array offset: 0x2038, array step: 0x21C */ 186 uint8_t RESERVED_3[4]; 187 __IO uint32_t SAMQR; /**< Switch 0 access management qualifier register, array offset: 0x2040, array step: 0x21C */ 188 uint8_t RESERVED_4[4]; 189 __IO uint32_t SBLPR[NETC_IERB_CFG_SW_INST_SW_PF_BOOT_LOAD_COUNT]; /**< Switch 0 boot loader parameter register 0..Switch 0 boot loader parameter register 1, array offset: 0x2048, array step: index*0x21C, index2*0x4 */ 190 uint8_t RESERVED_5[16]; 191 __IO uint32_t SSMBAR; /**< Switch 0 shared memory buffer allotment register, array offset: 0x2060, array step: 0x21C */ 192 uint8_t RESERVED_6[28]; 193 __IO uint32_t SHTMAR; /**< Switch 0 hash table memory allotment register, array offset: 0x2080, array step: 0x21C */ 194 __IO uint32_t SITMAR; /**< Switch 0 index table memory allocation register, array offset: 0x2084, array step: 0x21C */ 195 __IO uint32_t SIPFTMAR; /**< Switch 0 ingress port filter table memory allocation register, array offset: 0x2088, array step: 0x21C */ 196 uint8_t RESERVED_7[20]; 197 __IO uint32_t SRPITMAR; /**< Switch 0 rate policer index table memory allocation register, array offset: 0x20A0, array step: 0x21C */ 198 __IO uint32_t SISCITMAR; /**< Switch 0 ingress stream counter index table memory allocation register, array offset: 0x20A4, array step: 0x21C */ 199 __IO uint32_t SISITMAR; /**< Switch 0 ingress stream index table memory allocation register, array offset: 0x20A8, array step: 0x21C */ 200 __IO uint32_t SISQGITMAR; /**< Switch 0 ingress sequence generation index table memory allocation register, array offset: 0x20AC, array step: 0x21C */ 201 uint8_t RESERVED_8[4]; 202 __IO uint32_t SSGIITMAR; /**< Switch 0 stream gate instance index table memory allocation register, array offset: 0x20B4, array step: 0x21C */ 203 __IO uint32_t SSGCLITMAR; /**< Switch 0 stream gate control list index table memory allocation register, array offset: 0x20B8, array step: 0x21C */ 204 __IO uint32_t SFMITMAR; /**< Switch 0 frame modification index table memory allocation register, array offset: 0x20BC, array step: 0x21C */ 205 __IO uint32_t SFMDITMAR; /**< Switch 0 frame modification data index table memory allocation register, array offset: 0x20C0, array step: 0x21C */ 206 uint8_t RESERVED_9[44]; 207 __IO uint32_t STGSTAR; /**< Switch 0 time gate scheduling table allocation register, array offset: 0x20F0, array step: 0x21C */ 208 __IO uint32_t STGSLR; /**< Switch 0 time gate scheduling lookahead register, array offset: 0x20F4, array step: 0x21C */ 209 uint8_t RESERVED_10[268]; 210 __I uint32_t SMPCR; /**< Switch 0 management port configuration register, array offset: 0x2204, array step: 0x21C */ 211 uint8_t RESERVED_11[8]; 212 __IO uint32_t SVFHTDECR0; /**< Switch 0 VLAN Filter (hash) table default entry configuration registers 0, array offset: 0x2210, array step: 0x21C */ 213 __IO uint32_t SVFHTDECR1; /**< Switch 0 VLAN filter hash table default entry configuration registers 1, array offset: 0x2214, array step: 0x21C */ 214 __IO uint32_t SVFHTDECR2; /**< Switch 0 VLAN filter hash table default entry configuration registers 2, array offset: 0x2218, array step: 0x21C */ 215 } CFG_SW_INST[NETC_IERB_CFG_SW_INST_COUNT]; 216 uint8_t RESERVED_25[3556]; 217 struct { /* offset: 0x3000, array step: 0xF8 */ 218 __I uint32_t EBCR0; /**< ENETC 0 binding configuration register 0, array offset: 0x3000, array step: 0xF8 */ 219 __I uint32_t EBCR1; /**< ENETC 0 binding configuration register 1, array offset: 0x3004, array step: 0xF8 */ 220 __I uint32_t EBCR2; /**< ENETC 0 binding configuration register 2, array offset: 0x3008, array step: 0xF8 */ 221 uint8_t RESERVED_0[4]; 222 __I uint32_t EVBCR; /**< ENETC 0 VSI binding configuration register, array offset: 0x3010, array step: 0xF8 */ 223 __IO uint32_t EMCR; /**< ENETC 0 MSI-X configuration register, array offset: 0x3014, array step: 0xF8 */ 224 uint8_t RESERVED_1[8]; 225 __IO uint32_t E_CFH_DIDVID; /**< ENETC 0 config header device ID and vendor ID register, array offset: 0x3020, array step: 0xF8 */ 226 __IO uint32_t E_CFH_SIDSVID; /**< ENETC 0 config header subsystem ID and subsystem vendor ID register, array offset: 0x3024, array step: 0xF8 */ 227 __IO uint32_t E_CFC_VFDID; /**< ENETC 0 config capability VF device ID register, array offset: 0x3028, array step: 0xF8 */ 228 uint8_t RESERVED_2[4]; 229 __IO uint32_t EBCAR; /**< ENETC 0 buffer cache attribute register 0, array offset: 0x3030, array step: 0xF8 */ 230 __IO uint32_t EMCAR; /**< ENETC 0 message cache attribute register, array offset: 0x3034, array step: 0xF8 */ 231 __IO uint32_t ECAR; /**< ENETC 0 command cache attribute register, array offset: 0x3038, array step: 0xF8 */ 232 uint8_t RESERVED_3[4]; 233 __IO uint32_t EAMQR; /**< ENETC 0 access management qualifier register, array offset: 0x3040, array step: 0xF8 */ 234 uint8_t RESERVED_4[4]; 235 __IO uint32_t EBLPR[NETC_IERB_CFG_ENETC_INST_ENETC_PF_BOOT_LOAD_COUNT]; /**< ENETC 0 boot loader parameter register 0..ENETC 0 boot loader parameter register 1, array offset: 0x3048, array step: index*0xF8, index2*0x4 */ 236 __IO uint32_t ERXMBER; /**< ENETC 0 receive memory buffer entitlement register, array offset: 0x3050, array step: 0xF8 */ 237 __IO uint32_t ERXMBLR; /**< ENETC 0 receive memory buffer limit register, array offset: 0x3054, array step: 0xF8 */ 238 uint8_t RESERVED_5[24]; 239 __IO uint32_t ETXHPTBCR; /**< ENETC 0 transmit high priority tier byte credit register, array offset: 0x3070, array step: 0xF8 */ 240 __IO uint32_t ETXLPTBCR; /**< ENETC 0 transmit low priority tier byte credit register, array offset: 0x3074, array step: 0xF8 */ 241 uint8_t RESERVED_6[8]; 242 __IO uint32_t EHTMAR; /**< ENETC 0 hash table memory allotment register, array offset: 0x3080, array step: 0xF8 */ 243 __IO uint32_t EITMAR; /**< ENETC 0 index table memory allocation register, array offset: 0x3084, array step: 0xF8 */ 244 __IO uint32_t EIPFTMAR; /**< ENETC 0 ingress port filter table memory allocation register, array offset: 0x3088, array step: 0xF8 */ 245 uint8_t RESERVED_7[4]; 246 __I uint32_t ERTMAR; /**< ENETC 0 RFS ternary memory allocation register, array offset: 0x3090, array step: 0xF8 */ 247 uint8_t RESERVED_8[12]; 248 __IO uint32_t ERPITMAR; /**< ENETC 0 rate policer index table memory allocation register, array offset: 0x30A0, array step: 0xF8 */ 249 __IO uint32_t EISCITMAR; /**< ENETC 0 ingress stream counter index table memory allocation register, array offset: 0x30A4, array step: 0xF8 */ 250 __IO uint32_t EISITMAR; /**< ENETC 0 ingress stream index table memory allocation register, array offset: 0x30A8, array step: 0xF8 */ 251 uint8_t RESERVED_9[8]; 252 __IO uint32_t ESGIITMAR; /**< ENETC 0 stream gate instance index table memory allocation register, array offset: 0x30B4, array step: 0xF8 */ 253 __IO uint32_t ESGCLITMAR; /**< ENETC 0 stream gate control list index table memory allocation register, array offset: 0x30B8, array step: 0xF8 */ 254 uint8_t RESERVED_10[52]; 255 __IO uint32_t ETGSTAR; /**< ENETC 0 time gate scheduling table allocation register, array offset: 0x30F0, array step: 0xF8 */ 256 __IO uint32_t ETGSLR; /**< ENETC 0 time gate scheduling lookahead register, array offset: 0x30F4, array step: 0xF8 */ 257 } CFG_ENETC_INST[NETC_IERB_CFG_ENETC_INST_COUNT]; 258 uint8_t RESERVED_26[3848]; 259 struct { /* offset: 0x4000, array step: 0x40 */ 260 __IO uint32_t VAMQR; /**< VSI 0 access management qualifier register..VSI 6 access management qualifier register, array offset: 0x4000, array step: 0x40 */ 261 uint8_t RESERVED_0[4]; 262 __IO uint32_t VBLPR[NETC_IERB_CFG_VSI_INST_VSI_PF_BOOT_LOAD_COUNT]; /**< VSI 0 boot loader parameter register 0..VSI 6 boot loader parameter register 1, array offset: 0x4008, array step: index*0x40, index2*0x4 */ 263 __IO uint32_t VPMAR0; /**< VSI 0 primary MAC address register 0..VSI 6 primary MAC address register 0, array offset: 0x4010, array step: 0x40 */ 264 __IO uint32_t VPMAR1; /**< VSI 0 primary MAC address register 1..VSI 6 primary MAC address register 1, array offset: 0x4014, array step: 0x40 */ 265 uint8_t RESERVED_1[40]; 266 } CFG_VSI_INST[NETC_IERB_CFG_VSI_INST_COUNT]; 267 } NETC_IERB_Type, *NETC_IERB_MemMapPtr; 268 269 /** Number of instances of the NETC_IERB module. */ 270 #define NETC_IERB_INSTANCE_COUNT (1u) 271 272 /* NETC_IERB - Peripheral instance base addresses */ 273 /** Peripheral NETC__NETC_IERB base address */ 274 #define IP_NETC__NETC_IERB_BASE (0x74800000u) 275 /** Peripheral NETC__NETC_IERB base pointer */ 276 #define IP_NETC__NETC_IERB ((NETC_IERB_Type *)IP_NETC__NETC_IERB_BASE) 277 /** Array initializer of NETC_IERB peripheral base addresses */ 278 #define IP_NETC_IERB_BASE_ADDRS { IP_NETC__NETC_IERB_BASE } 279 /** Array initializer of NETC_IERB peripheral base pointers */ 280 #define IP_NETC_IERB_BASE_PTRS { IP_NETC__NETC_IERB } 281 282 /* ---------------------------------------------------------------------------- 283 -- NETC_IERB Register Masks 284 ---------------------------------------------------------------------------- */ 285 286 /*! 287 * @addtogroup NETC_IERB_Register_Masks NETC_IERB Register Masks 288 * @{ 289 */ 290 291 /*! @name CAPR0 - Capability register 0 */ 292 /*! @{ */ 293 294 #define NETC_IERB_CAPR0_NUM_RC_MASK (0xFU) 295 #define NETC_IERB_CAPR0_NUM_RC_SHIFT (0U) 296 #define NETC_IERB_CAPR0_NUM_RC_WIDTH (4U) 297 #define NETC_IERB_CAPR0_NUM_RC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_RC_SHIFT)) & NETC_IERB_CAPR0_NUM_RC_MASK) 298 299 #define NETC_IERB_CAPR0_NUM_EMDIO_MASK (0x10U) 300 #define NETC_IERB_CAPR0_NUM_EMDIO_SHIFT (4U) 301 #define NETC_IERB_CAPR0_NUM_EMDIO_WIDTH (1U) 302 #define NETC_IERB_CAPR0_NUM_EMDIO(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_EMDIO_SHIFT)) & NETC_IERB_CAPR0_NUM_EMDIO_MASK) 303 304 #define NETC_IERB_CAPR0_NUM_TMR_MASK (0xC0U) 305 #define NETC_IERB_CAPR0_NUM_TMR_SHIFT (6U) 306 #define NETC_IERB_CAPR0_NUM_TMR_WIDTH (2U) 307 #define NETC_IERB_CAPR0_NUM_TMR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_TMR_SHIFT)) & NETC_IERB_CAPR0_NUM_TMR_MASK) 308 309 #define NETC_IERB_CAPR0_NUM_LINKS_MASK (0x1F00U) 310 #define NETC_IERB_CAPR0_NUM_LINKS_SHIFT (8U) 311 #define NETC_IERB_CAPR0_NUM_LINKS_WIDTH (5U) 312 #define NETC_IERB_CAPR0_NUM_LINKS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_LINKS_SHIFT)) & NETC_IERB_CAPR0_NUM_LINKS_MASK) 313 314 #define NETC_IERB_CAPR0_NUM_SW_MASK (0x30000U) 315 #define NETC_IERB_CAPR0_NUM_SW_SHIFT (16U) 316 #define NETC_IERB_CAPR0_NUM_SW_WIDTH (2U) 317 #define NETC_IERB_CAPR0_NUM_SW(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_SW_SHIFT)) & NETC_IERB_CAPR0_NUM_SW_MASK) 318 319 #define NETC_IERB_CAPR0_NUM_ENETC_MASK (0xF80000U) 320 #define NETC_IERB_CAPR0_NUM_ENETC_SHIFT (19U) 321 #define NETC_IERB_CAPR0_NUM_ENETC_WIDTH (5U) 322 #define NETC_IERB_CAPR0_NUM_ENETC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_ENETC_SHIFT)) & NETC_IERB_CAPR0_NUM_ENETC_MASK) 323 324 #define NETC_IERB_CAPR0_NUM_VSI_MASK (0x7F000000U) 325 #define NETC_IERB_CAPR0_NUM_VSI_SHIFT (24U) 326 #define NETC_IERB_CAPR0_NUM_VSI_WIDTH (7U) 327 #define NETC_IERB_CAPR0_NUM_VSI(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR0_NUM_VSI_SHIFT)) & NETC_IERB_CAPR0_NUM_VSI_MASK) 328 /*! @} */ 329 330 /*! @name CAPR1 - Capability register 1 */ 331 /*! @{ */ 332 333 #define NETC_IERB_CAPR1_NUM_RX_BDR_MASK (0x3FFU) 334 #define NETC_IERB_CAPR1_NUM_RX_BDR_SHIFT (0U) 335 #define NETC_IERB_CAPR1_NUM_RX_BDR_WIDTH (10U) 336 #define NETC_IERB_CAPR1_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR1_NUM_RX_BDR_SHIFT)) & NETC_IERB_CAPR1_NUM_RX_BDR_MASK) 337 338 #define NETC_IERB_CAPR1_NUM_TX_BDR_MASK (0x3FF0000U) 339 #define NETC_IERB_CAPR1_NUM_TX_BDR_SHIFT (16U) 340 #define NETC_IERB_CAPR1_NUM_TX_BDR_WIDTH (10U) 341 #define NETC_IERB_CAPR1_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR1_NUM_TX_BDR_SHIFT)) & NETC_IERB_CAPR1_NUM_TX_BDR_MASK) 342 /*! @} */ 343 344 /*! @name CAPR2 - Capability register 2 */ 345 /*! @{ */ 346 347 #define NETC_IERB_CAPR2_NUM_MSIX_MASK (0x7FFU) 348 #define NETC_IERB_CAPR2_NUM_MSIX_SHIFT (0U) 349 #define NETC_IERB_CAPR2_NUM_MSIX_WIDTH (11U) 350 #define NETC_IERB_CAPR2_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR2_NUM_MSIX_SHIFT)) & NETC_IERB_CAPR2_NUM_MSIX_MASK) 351 /*! @} */ 352 353 /*! @name CAPR3 - Capability register 3 */ 354 /*! @{ */ 355 356 #define NETC_IERB_CAPR3_NUM_MAC_AFTE_MASK (0xFFFU) 357 #define NETC_IERB_CAPR3_NUM_MAC_AFTE_SHIFT (0U) 358 #define NETC_IERB_CAPR3_NUM_MAC_AFTE_WIDTH (12U) 359 #define NETC_IERB_CAPR3_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR3_NUM_MAC_AFTE_SHIFT)) & NETC_IERB_CAPR3_NUM_MAC_AFTE_MASK) 360 361 #define NETC_IERB_CAPR3_NUM_VLAN_FTE_MASK (0xFFF0000U) 362 #define NETC_IERB_CAPR3_NUM_VLAN_FTE_SHIFT (16U) 363 #define NETC_IERB_CAPR3_NUM_VLAN_FTE_WIDTH (12U) 364 #define NETC_IERB_CAPR3_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CAPR3_NUM_VLAN_FTE_SHIFT)) & NETC_IERB_CAPR3_NUM_VLAN_FTE_MASK) 365 /*! @} */ 366 367 /*! @name CMCAPR - Common memory capability register */ 368 /*! @{ */ 369 370 #define NETC_IERB_CMCAPR_NUM_WORDS_MASK (0xFFFFFFU) 371 #define NETC_IERB_CMCAPR_NUM_WORDS_SHIFT (0U) 372 #define NETC_IERB_CMCAPR_NUM_WORDS_WIDTH (24U) 373 #define NETC_IERB_CMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_CMCAPR_NUM_WORDS_MASK) 374 375 #define NETC_IERB_CMCAPR_WORD_SIZE_MASK (0x30000000U) 376 #define NETC_IERB_CMCAPR_WORD_SIZE_SHIFT (28U) 377 #define NETC_IERB_CMCAPR_WORD_SIZE_WIDTH (2U) 378 #define NETC_IERB_CMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_CMCAPR_WORD_SIZE_SHIFT)) & NETC_IERB_CMCAPR_WORD_SIZE_MASK) 379 /*! @} */ 380 381 /*! @name IPFTMCAPR - Ingress port filter ternary memory capability register */ 382 /*! @{ */ 383 384 #define NETC_IERB_IPFTMCAPR_NUM_WORDS_MASK (0xFFFFU) 385 #define NETC_IERB_IPFTMCAPR_NUM_WORDS_SHIFT (0U) 386 #define NETC_IERB_IPFTMCAPR_NUM_WORDS_WIDTH (16U) 387 #define NETC_IERB_IPFTMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_IPFTMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_IPFTMCAPR_NUM_WORDS_MASK) 388 389 #define NETC_IERB_IPFTMCAPR_WORD_SIZE_MASK (0x30000000U) 390 #define NETC_IERB_IPFTMCAPR_WORD_SIZE_SHIFT (28U) 391 #define NETC_IERB_IPFTMCAPR_WORD_SIZE_WIDTH (2U) 392 #define NETC_IERB_IPFTMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_IPFTMCAPR_WORD_SIZE_SHIFT)) & NETC_IERB_IPFTMCAPR_WORD_SIZE_MASK) 393 /*! @} */ 394 395 /*! @name TGSMCAPR - Time gate scheduling memory capability register */ 396 /*! @{ */ 397 398 #define NETC_IERB_TGSMCAPR_NUM_WORDS_MASK (0xFFFFU) 399 #define NETC_IERB_TGSMCAPR_NUM_WORDS_SHIFT (0U) 400 #define NETC_IERB_TGSMCAPR_NUM_WORDS_WIDTH (16U) 401 #define NETC_IERB_TGSMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TGSMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_TGSMCAPR_NUM_WORDS_MASK) 402 /*! @} */ 403 404 /*! @name SMDTR - Shared memory depletion threshold register */ 405 /*! @{ */ 406 407 #define NETC_IERB_SMDTR_THRESH_MASK (0xFFFFFFU) 408 #define NETC_IERB_SMDTR_THRESH_SHIFT (0U) 409 #define NETC_IERB_SMDTR_THRESH_WIDTH (24U) 410 #define NETC_IERB_SMDTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SMDTR_THRESH_SHIFT)) & NETC_IERB_SMDTR_THRESH_MASK) 411 /*! @} */ 412 413 /*! @name ERSMBAR - ENETC receive shared memory buffer allotment register */ 414 /*! @{ */ 415 416 #define NETC_IERB_ERSMBAR_THRESH_MASK (0xFFFFFFU) 417 #define NETC_IERB_ERSMBAR_THRESH_SHIFT (0U) 418 #define NETC_IERB_ERSMBAR_THRESH_WIDTH (24U) 419 #define NETC_IERB_ERSMBAR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERSMBAR_THRESH_SHIFT)) & NETC_IERB_ERSMBAR_THRESH_MASK) 420 /*! @} */ 421 422 /*! @name HTAHPCR - HTA 0 HP configuration register */ 423 /*! @{ */ 424 425 #define NETC_IERB_HTAHPCR_BLIMIT_MASK (0xFFFFU) 426 #define NETC_IERB_HTAHPCR_BLIMIT_SHIFT (0U) 427 #define NETC_IERB_HTAHPCR_BLIMIT_WIDTH (16U) 428 #define NETC_IERB_HTAHPCR_BLIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTAHPCR_BLIMIT_SHIFT)) & NETC_IERB_HTAHPCR_BLIMIT_MASK) 429 430 #define NETC_IERB_HTAHPCR_FLIMIT_MASK (0xFF000000U) 431 #define NETC_IERB_HTAHPCR_FLIMIT_SHIFT (24U) 432 #define NETC_IERB_HTAHPCR_FLIMIT_WIDTH (8U) 433 #define NETC_IERB_HTAHPCR_FLIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTAHPCR_FLIMIT_SHIFT)) & NETC_IERB_HTAHPCR_FLIMIT_MASK) 434 /*! @} */ 435 436 /*! @name HTALPCR - HTA 0 LP configuration register */ 437 /*! @{ */ 438 439 #define NETC_IERB_HTALPCR_BLIMIT_MASK (0xFFFFU) 440 #define NETC_IERB_HTALPCR_BLIMIT_SHIFT (0U) 441 #define NETC_IERB_HTALPCR_BLIMIT_WIDTH (16U) 442 #define NETC_IERB_HTALPCR_BLIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTALPCR_BLIMIT_SHIFT)) & NETC_IERB_HTALPCR_BLIMIT_MASK) 443 444 #define NETC_IERB_HTALPCR_FLIMIT_MASK (0xFF000000U) 445 #define NETC_IERB_HTALPCR_FLIMIT_SHIFT (24U) 446 #define NETC_IERB_HTALPCR_FLIMIT_WIDTH (8U) 447 #define NETC_IERB_HTALPCR_FLIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HTALPCR_FLIMIT_SHIFT)) & NETC_IERB_HTALPCR_FLIMIT_MASK) 448 /*! @} */ 449 450 /*! @name HBTMAR - Hash bucket table memory allocation register */ 451 /*! @{ */ 452 453 #define NETC_IERB_HBTMAR_NUM_WORDS_MASK (0x3FFFU) 454 #define NETC_IERB_HBTMAR_NUM_WORDS_SHIFT (0U) 455 #define NETC_IERB_HBTMAR_NUM_WORDS_WIDTH (14U) 456 #define NETC_IERB_HBTMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_NUM_WORDS_SHIFT)) & NETC_IERB_HBTMAR_NUM_WORDS_MASK) 457 458 #define NETC_IERB_HBTMAR_MIN_WORDS_MASK (0xFF0000U) 459 #define NETC_IERB_HBTMAR_MIN_WORDS_SHIFT (16U) 460 #define NETC_IERB_HBTMAR_MIN_WORDS_WIDTH (8U) 461 #define NETC_IERB_HBTMAR_MIN_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_MIN_WORDS_SHIFT)) & NETC_IERB_HBTMAR_MIN_WORDS_MASK) 462 463 #define NETC_IERB_HBTMAR_NEPW_MASK (0x7000000U) 464 #define NETC_IERB_HBTMAR_NEPW_SHIFT (24U) 465 #define NETC_IERB_HBTMAR_NEPW_WIDTH (3U) 466 #define NETC_IERB_HBTMAR_NEPW(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_NEPW_SHIFT)) & NETC_IERB_HBTMAR_NEPW_MASK) 467 468 #define NETC_IERB_HBTMAR_MLOC_MASK (0xC0000000U) 469 #define NETC_IERB_HBTMAR_MLOC_SHIFT (30U) 470 #define NETC_IERB_HBTMAR_MLOC_WIDTH (2U) 471 #define NETC_IERB_HBTMAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTMAR_MLOC_SHIFT)) & NETC_IERB_HBTMAR_MLOC_MASK) 472 /*! @} */ 473 474 /*! @name HBTCR - Hash bucket table configuration register */ 475 /*! @{ */ 476 477 #define NETC_IERB_HBTCR_MAX_COL_MASK (0x7U) 478 #define NETC_IERB_HBTCR_MAX_COL_SHIFT (0U) 479 #define NETC_IERB_HBTCR_MAX_COL_WIDTH (3U) 480 #define NETC_IERB_HBTCR_MAX_COL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTCR_MAX_COL_SHIFT)) & NETC_IERB_HBTCR_MAX_COL_MASK) 481 482 #define NETC_IERB_HBTCR_MAX_VISITS_MASK (0xF0U) 483 #define NETC_IERB_HBTCR_MAX_VISITS_SHIFT (4U) 484 #define NETC_IERB_HBTCR_MAX_VISITS_WIDTH (4U) 485 #define NETC_IERB_HBTCR_MAX_VISITS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_HBTCR_MAX_VISITS_SHIFT)) & NETC_IERB_HBTCR_MAX_VISITS_MASK) 486 /*! @} */ 487 488 /*! @name GHTEMCAPR - Guaranteed hash table entry memory capability register */ 489 /*! @{ */ 490 491 #define NETC_IERB_GHTEMCAPR_NUM_WORDS_MASK (0x1FFU) 492 #define NETC_IERB_GHTEMCAPR_NUM_WORDS_SHIFT (0U) 493 #define NETC_IERB_GHTEMCAPR_NUM_WORDS_WIDTH (9U) 494 #define NETC_IERB_GHTEMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_GHTEMCAPR_NUM_WORDS_SHIFT)) & NETC_IERB_GHTEMCAPR_NUM_WORDS_MASK) 495 496 #define NETC_IERB_GHTEMCAPR_MLOC_MASK (0xC0000000U) 497 #define NETC_IERB_GHTEMCAPR_MLOC_SHIFT (30U) 498 #define NETC_IERB_GHTEMCAPR_MLOC_WIDTH (2U) 499 #define NETC_IERB_GHTEMCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_GHTEMCAPR_MLOC_SHIFT)) & NETC_IERB_GHTEMCAPR_MLOC_MASK) 500 /*! @} */ 501 502 /*! @name NETCFLRCR - NETC FLR configuration register */ 503 /*! @{ */ 504 505 #define NETC_IERB_NETCFLRCR_VALUE_MASK (0x1FFU) 506 #define NETC_IERB_NETCFLRCR_VALUE_SHIFT (0U) 507 #define NETC_IERB_NETCFLRCR_VALUE_WIDTH (9U) 508 #define NETC_IERB_NETCFLRCR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCFLRCR_VALUE_SHIFT)) & NETC_IERB_NETCFLRCR_VALUE_MASK) 509 510 #define NETC_IERB_NETCFLRCR_SCALE_MASK (0xE00U) 511 #define NETC_IERB_NETCFLRCR_SCALE_SHIFT (9U) 512 #define NETC_IERB_NETCFLRCR_SCALE_WIDTH (3U) 513 #define NETC_IERB_NETCFLRCR_SCALE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCFLRCR_SCALE_SHIFT)) & NETC_IERB_NETCFLRCR_SCALE_MASK) 514 /*! @} */ 515 516 /*! @name NETCCLKFR - NETC clock period fractional register */ 517 /*! @{ */ 518 519 #define NETC_IERB_NETCCLKFR_FRAC_MASK (0xFFFFFFFFU) 520 #define NETC_IERB_NETCCLKFR_FRAC_SHIFT (0U) 521 #define NETC_IERB_NETCCLKFR_FRAC_WIDTH (32U) 522 #define NETC_IERB_NETCCLKFR_FRAC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKFR_FRAC_SHIFT)) & NETC_IERB_NETCCLKFR_FRAC_MASK) 523 /*! @} */ 524 525 /*! @name NETCCLKCR - NETC clock configuration register */ 526 /*! @{ */ 527 528 #define NETC_IERB_NETCCLKCR_FREQ_MASK (0x7FFU) 529 #define NETC_IERB_NETCCLKCR_FREQ_SHIFT (0U) 530 #define NETC_IERB_NETCCLKCR_FREQ_WIDTH (11U) 531 #define NETC_IERB_NETCCLKCR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKCR_FREQ_SHIFT)) & NETC_IERB_NETCCLKCR_FREQ_MASK) 532 533 #define NETC_IERB_NETCCLKCR_PERIOD_MASK (0x3FF0000U) 534 #define NETC_IERB_NETCCLKCR_PERIOD_SHIFT (16U) 535 #define NETC_IERB_NETCCLKCR_PERIOD_WIDTH (10U) 536 #define NETC_IERB_NETCCLKCR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_NETCCLKCR_PERIOD_SHIFT)) & NETC_IERB_NETCCLKCR_PERIOD_MASK) 537 /*! @} */ 538 539 /*! @name SBCR - System bus configuration register */ 540 /*! @{ */ 541 542 #define NETC_IERB_SBCR_WBS_MASK (0x3U) 543 #define NETC_IERB_SBCR_WBS_SHIFT (0U) 544 #define NETC_IERB_SBCR_WBS_WIDTH (2U) 545 #define NETC_IERB_SBCR_WBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_WBS_SHIFT)) & NETC_IERB_SBCR_WBS_MASK) 546 547 #define NETC_IERB_SBCR_RBS_MASK (0xCU) 548 #define NETC_IERB_SBCR_RBS_SHIFT (2U) 549 #define NETC_IERB_SBCR_RBS_WIDTH (2U) 550 #define NETC_IERB_SBCR_RBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_RBS_SHIFT)) & NETC_IERB_SBCR_RBS_MASK) 551 /*! @} */ 552 553 /*! @name SBOTCR - System bus outstanding transaction control register */ 554 /*! @{ */ 555 556 #define NETC_IERB_SBOTCR_OT_LIMIT_MASK (0xFFFFFFFFU) 557 #define NETC_IERB_SBOTCR_OT_LIMIT_SHIFT (0U) 558 #define NETC_IERB_SBOTCR_OT_LIMIT_WIDTH (32U) 559 #define NETC_IERB_SBOTCR_OT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBOTCR_OT_LIMIT_SHIFT)) & NETC_IERB_SBOTCR_OT_LIMIT_MASK) 560 /*! @} */ 561 562 /*! @name SGLTTR - Stream gating lag time for refresh register */ 563 /*! @{ */ 564 565 #define NETC_IERB_SGLTTR_LAG_TIME_MASK (0x1FU) 566 #define NETC_IERB_SGLTTR_LAG_TIME_SHIFT (0U) 567 #define NETC_IERB_SGLTTR_LAG_TIME_WIDTH (5U) 568 #define NETC_IERB_SGLTTR_LAG_TIME(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SGLTTR_LAG_TIME_SHIFT)) & NETC_IERB_SGLTTR_LAG_TIME_MASK) 569 /*! @} */ 570 571 /*! @name RBCR - Root complex 0 binding configuration register */ 572 /*! @{ */ 573 574 #define NETC_IERB_RBCR_TYPE_MASK (0x1U) 575 #define NETC_IERB_RBCR_TYPE_SHIFT (0U) 576 #define NETC_IERB_RBCR_TYPE_WIDTH (1U) 577 #define NETC_IERB_RBCR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RBCR_TYPE_SHIFT)) & NETC_IERB_RBCR_TYPE_MASK) 578 579 #define NETC_IERB_RBCR_PORT_MASK (0xF0U) 580 #define NETC_IERB_RBCR_PORT_SHIFT (4U) 581 #define NETC_IERB_RBCR_PORT_WIDTH (4U) 582 #define NETC_IERB_RBCR_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RBCR_PORT_SHIFT)) & NETC_IERB_RBCR_PORT_MASK) 583 /*! @} */ 584 585 /*! @name RCMSICAR - Root complex 0 MSI-X cache attribute register */ 586 /*! @{ */ 587 588 #define NETC_IERB_RCMSICAR_MSI_WRCACHE_MASK (0xFU) 589 #define NETC_IERB_RCMSICAR_MSI_WRCACHE_SHIFT (0U) 590 #define NETC_IERB_RCMSICAR_MSI_WRCACHE_WIDTH (4U) 591 #define NETC_IERB_RCMSICAR_MSI_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRCACHE_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRCACHE_MASK) 592 593 #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN_MASK (0x30U) 594 #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN_SHIFT (4U) 595 #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN_WIDTH (2U) 596 #define NETC_IERB_RCMSICAR_MSI_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRDOMAIN_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRDOMAIN_MASK) 597 598 #define NETC_IERB_RCMSICAR_MSI_WRSNP_MASK (0x40U) 599 #define NETC_IERB_RCMSICAR_MSI_WRSNP_SHIFT (6U) 600 #define NETC_IERB_RCMSICAR_MSI_WRSNP_WIDTH (1U) 601 #define NETC_IERB_RCMSICAR_MSI_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSICAR_MSI_WRSNP_SHIFT)) & NETC_IERB_RCMSICAR_MSI_WRSNP_MASK) 602 /*! @} */ 603 604 /*! @name RCMSIAMQR - Root complex 0 MSI access management qualifier register */ 605 /*! @{ */ 606 607 #define NETC_IERB_RCMSIAMQR_AWQOS_MASK (0xF00000U) 608 #define NETC_IERB_RCMSIAMQR_AWQOS_SHIFT (20U) 609 #define NETC_IERB_RCMSIAMQR_AWQOS_WIDTH (4U) 610 #define NETC_IERB_RCMSIAMQR_AWQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSIAMQR_AWQOS_SHIFT)) & NETC_IERB_RCMSIAMQR_AWQOS_MASK) 611 612 #define NETC_IERB_RCMSIAMQR_BMT_MASK (0x80000000U) 613 #define NETC_IERB_RCMSIAMQR_BMT_SHIFT (31U) 614 #define NETC_IERB_RCMSIAMQR_BMT_WIDTH (1U) 615 #define NETC_IERB_RCMSIAMQR_BMT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_RCMSIAMQR_BMT_SHIFT)) & NETC_IERB_RCMSIAMQR_BMT_MASK) 616 /*! @} */ 617 618 /*! @name EMDIOBCR - EMDIO binding configuration register */ 619 /*! @{ */ 620 621 #define NETC_IERB_EMDIOBCR_RC_INST_MASK (0xFU) 622 #define NETC_IERB_EMDIOBCR_RC_INST_SHIFT (0U) 623 #define NETC_IERB_EMDIOBCR_RC_INST_WIDTH (4U) 624 #define NETC_IERB_EMDIOBCR_RC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBCR_RC_INST_SHIFT)) & NETC_IERB_EMDIOBCR_RC_INST_MASK) 625 626 #define NETC_IERB_EMDIOBCR_FN_MASK (0xF00U) 627 #define NETC_IERB_EMDIOBCR_FN_SHIFT (8U) 628 #define NETC_IERB_EMDIOBCR_FN_WIDTH (4U) 629 #define NETC_IERB_EMDIOBCR_FN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBCR_FN_SHIFT)) & NETC_IERB_EMDIOBCR_FN_MASK) 630 631 #define NETC_IERB_EMDIOBCR_VALID_MASK (0x80000000U) 632 #define NETC_IERB_EMDIOBCR_VALID_SHIFT (31U) 633 #define NETC_IERB_EMDIOBCR_VALID_WIDTH (1U) 634 #define NETC_IERB_EMDIOBCR_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBCR_VALID_SHIFT)) & NETC_IERB_EMDIOBCR_VALID_MASK) 635 /*! @} */ 636 637 /*! @name EMDIOMCR - EMDIO MSI-X configuration register */ 638 /*! @{ */ 639 640 #define NETC_IERB_EMDIOMCR_NUM_MSIX_MASK (0x1U) 641 #define NETC_IERB_EMDIOMCR_NUM_MSIX_SHIFT (0U) 642 #define NETC_IERB_EMDIOMCR_NUM_MSIX_WIDTH (1U) 643 #define NETC_IERB_EMDIOMCR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOMCR_NUM_MSIX_SHIFT)) & NETC_IERB_EMDIOMCR_NUM_MSIX_MASK) 644 /*! @} */ 645 646 /*! @name EMDIO_CFH_DIDVID - EMDIO config header device ID and vendor ID register */ 647 /*! @{ */ 648 649 #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) 650 #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_SHIFT (0U) 651 #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_WIDTH (16U) 652 #define NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_DIDVID_VENDOR_ID_MASK) 653 654 #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) 655 #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_SHIFT (16U) 656 #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_WIDTH (16U) 657 #define NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_DIDVID_DEVICE_ID_MASK) 658 /*! @} */ 659 660 /*! @name EMDIO_CFH_SIDSVID - EMDIO config header subsystem ID and subsystem vendor ID register */ 661 /*! @{ */ 662 663 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) 664 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) 665 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_WIDTH (16U) 666 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) 667 668 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) 669 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) 670 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_WIDTH (16U) 671 #define NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_EMDIO_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) 672 /*! @} */ 673 674 /*! @name EMDIOBLPR - EMDIO boot loader parameter register 0..EMDIO boot loader parameter register 1 */ 675 /*! @{ */ 676 677 #define NETC_IERB_EMDIOBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) 678 #define NETC_IERB_EMDIOBLPR_PARAM_VAL_SHIFT (0U) 679 #define NETC_IERB_EMDIOBLPR_PARAM_VAL_WIDTH (32U) 680 #define NETC_IERB_EMDIOBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIOBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_EMDIOBLPR_PARAM_VAL_MASK) 681 /*! @} */ 682 683 /*! @name EMDIO_CFG - EMDIO configuration register */ 684 /*! @{ */ 685 686 #define NETC_IERB_EMDIO_CFG_MDIO_MODE_MASK (0x10U) 687 #define NETC_IERB_EMDIO_CFG_MDIO_MODE_SHIFT (4U) 688 #define NETC_IERB_EMDIO_CFG_MDIO_MODE_WIDTH (1U) 689 #define NETC_IERB_EMDIO_CFG_MDIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFG_MDIO_MODE_SHIFT)) & NETC_IERB_EMDIO_CFG_MDIO_MODE_MASK) 690 691 #define NETC_IERB_EMDIO_CFG_MDC_MODE_MASK (0x20U) 692 #define NETC_IERB_EMDIO_CFG_MDC_MODE_SHIFT (5U) 693 #define NETC_IERB_EMDIO_CFG_MDC_MODE_WIDTH (1U) 694 #define NETC_IERB_EMDIO_CFG_MDC_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMDIO_CFG_MDC_MODE_SHIFT)) & NETC_IERB_EMDIO_CFG_MDC_MODE_MASK) 695 /*! @} */ 696 697 /*! @name TBCR - Timer 0 binding configuration register */ 698 /*! @{ */ 699 700 #define NETC_IERB_TBCR_RC_INST_MASK (0xFU) 701 #define NETC_IERB_TBCR_RC_INST_SHIFT (0U) 702 #define NETC_IERB_TBCR_RC_INST_WIDTH (4U) 703 #define NETC_IERB_TBCR_RC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBCR_RC_INST_SHIFT)) & NETC_IERB_TBCR_RC_INST_MASK) 704 705 #define NETC_IERB_TBCR_FN_MASK (0xF00U) 706 #define NETC_IERB_TBCR_FN_SHIFT (8U) 707 #define NETC_IERB_TBCR_FN_WIDTH (4U) 708 #define NETC_IERB_TBCR_FN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBCR_FN_SHIFT)) & NETC_IERB_TBCR_FN_MASK) 709 710 #define NETC_IERB_TBCR_VALID_MASK (0x80000000U) 711 #define NETC_IERB_TBCR_VALID_SHIFT (31U) 712 #define NETC_IERB_TBCR_VALID_WIDTH (1U) 713 #define NETC_IERB_TBCR_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBCR_VALID_SHIFT)) & NETC_IERB_TBCR_VALID_MASK) 714 /*! @} */ 715 716 /*! @name TMCR - Timer 0 MSI-X configuration register */ 717 /*! @{ */ 718 719 #define NETC_IERB_TMCR_NUM_MSIX_MASK (0x1U) 720 #define NETC_IERB_TMCR_NUM_MSIX_SHIFT (0U) 721 #define NETC_IERB_TMCR_NUM_MSIX_WIDTH (1U) 722 #define NETC_IERB_TMCR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TMCR_NUM_MSIX_SHIFT)) & NETC_IERB_TMCR_NUM_MSIX_MASK) 723 /*! @} */ 724 725 /*! @name T_CFH_DIDVID - Timer 0 config header device ID and vendor ID register */ 726 /*! @{ */ 727 728 #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) 729 #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID_SHIFT (0U) 730 #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID_WIDTH (16U) 731 #define NETC_IERB_T_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_T_CFH_DIDVID_VENDOR_ID_MASK) 732 733 #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) 734 #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID_SHIFT (16U) 735 #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID_WIDTH (16U) 736 #define NETC_IERB_T_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_T_CFH_DIDVID_DEVICE_ID_MASK) 737 /*! @} */ 738 739 /*! @name T_CFH_SIDSVID - Timer 0 config header subsystem ID and subsystem vendor ID register */ 740 /*! @{ */ 741 742 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) 743 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) 744 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_WIDTH (16U) 745 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) 746 747 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) 748 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) 749 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_WIDTH (16U) 750 #define NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_T_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) 751 /*! @} */ 752 753 /*! @name TBLPR - Timer 0 boot loader parameter register 0..Timer 0 boot loader parameter register 1 */ 754 /*! @{ */ 755 756 #define NETC_IERB_TBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) 757 #define NETC_IERB_TBLPR_PARAM_VAL_SHIFT (0U) 758 #define NETC_IERB_TBLPR_PARAM_VAL_WIDTH (32U) 759 #define NETC_IERB_TBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_TBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_TBLPR_PARAM_VAL_MASK) 760 /*! @} */ 761 762 /*! @name L0CAPR - Link 0 capability register */ 763 /*! @{ */ 764 765 #define NETC_IERB_L0CAPR_LINK_TYPE_MASK (0x10U) 766 #define NETC_IERB_L0CAPR_LINK_TYPE_SHIFT (4U) 767 #define NETC_IERB_L0CAPR_LINK_TYPE_WIDTH (1U) 768 #define NETC_IERB_L0CAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L0CAPR_LINK_TYPE_MASK) 769 770 #define NETC_IERB_L0CAPR_NUM_TC_MASK (0xF000U) 771 #define NETC_IERB_L0CAPR_NUM_TC_SHIFT (12U) 772 #define NETC_IERB_L0CAPR_NUM_TC_WIDTH (4U) 773 #define NETC_IERB_L0CAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_NUM_TC_SHIFT)) & NETC_IERB_L0CAPR_NUM_TC_MASK) 774 775 #define NETC_IERB_L0CAPR_NUM_Q_MASK (0xF0000U) 776 #define NETC_IERB_L0CAPR_NUM_Q_SHIFT (16U) 777 #define NETC_IERB_L0CAPR_NUM_Q_WIDTH (4U) 778 #define NETC_IERB_L0CAPR_NUM_Q(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_NUM_Q_SHIFT)) & NETC_IERB_L0CAPR_NUM_Q_MASK) 779 780 #define NETC_IERB_L0CAPR_NUM_CG_MASK (0xF000000U) 781 #define NETC_IERB_L0CAPR_NUM_CG_SHIFT (24U) 782 #define NETC_IERB_L0CAPR_NUM_CG_WIDTH (4U) 783 #define NETC_IERB_L0CAPR_NUM_CG(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_NUM_CG_SHIFT)) & NETC_IERB_L0CAPR_NUM_CG_MASK) 784 785 #define NETC_IERB_L0CAPR_TGS_MASK (0x10000000U) 786 #define NETC_IERB_L0CAPR_TGS_SHIFT (28U) 787 #define NETC_IERB_L0CAPR_TGS_WIDTH (1U) 788 #define NETC_IERB_L0CAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_TGS_SHIFT)) & NETC_IERB_L0CAPR_TGS_MASK) 789 790 #define NETC_IERB_L0CAPR_CBS_MASK (0x20000000U) 791 #define NETC_IERB_L0CAPR_CBS_SHIFT (29U) 792 #define NETC_IERB_L0CAPR_CBS_WIDTH (1U) 793 #define NETC_IERB_L0CAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0CAPR_CBS_SHIFT)) & NETC_IERB_L0CAPR_CBS_MASK) 794 /*! @} */ 795 796 /*! @name L0MCAPR - Link 0 MAC capability register */ 797 /*! @{ */ 798 799 #define NETC_IERB_L0MCAPR_MAC_VAR_MASK (0x7U) 800 #define NETC_IERB_L0MCAPR_MAC_VAR_SHIFT (0U) 801 #define NETC_IERB_L0MCAPR_MAC_VAR_WIDTH (3U) 802 #define NETC_IERB_L0MCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L0MCAPR_MAC_VAR_MASK) 803 804 #define NETC_IERB_L0MCAPR_EFPAD_MASK (0x30U) 805 #define NETC_IERB_L0MCAPR_EFPAD_SHIFT (4U) 806 #define NETC_IERB_L0MCAPR_EFPAD_WIDTH (2U) 807 #define NETC_IERB_L0MCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_EFPAD_SHIFT)) & NETC_IERB_L0MCAPR_EFPAD_MASK) 808 809 #define NETC_IERB_L0MCAPR_HD_MASK (0x100U) 810 #define NETC_IERB_L0MCAPR_HD_SHIFT (8U) 811 #define NETC_IERB_L0MCAPR_HD_WIDTH (1U) 812 #define NETC_IERB_L0MCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_HD_SHIFT)) & NETC_IERB_L0MCAPR_HD_MASK) 813 814 #define NETC_IERB_L0MCAPR_FP_MASK (0x600U) 815 #define NETC_IERB_L0MCAPR_FP_SHIFT (9U) 816 #define NETC_IERB_L0MCAPR_FP_WIDTH (2U) 817 #define NETC_IERB_L0MCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_FP_SHIFT)) & NETC_IERB_L0MCAPR_FP_MASK) 818 819 #define NETC_IERB_L0MCAPR_MII_PROT_MASK (0xF000000U) 820 #define NETC_IERB_L0MCAPR_MII_PROT_SHIFT (24U) 821 #define NETC_IERB_L0MCAPR_MII_PROT_WIDTH (4U) 822 #define NETC_IERB_L0MCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L0MCAPR_MII_PROT_MASK) 823 /*! @} */ 824 825 /*! @name L0IOCAPR - Link 0 I/O capability register */ 826 /*! @{ */ 827 828 #define NETC_IERB_L0IOCAPR_PCS_PROT_MASK (0xFFFFU) 829 #define NETC_IERB_L0IOCAPR_PCS_PROT_SHIFT (0U) 830 #define NETC_IERB_L0IOCAPR_PCS_PROT_WIDTH (16U) 831 #define NETC_IERB_L0IOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L0IOCAPR_PCS_PROT_MASK) 832 833 #define NETC_IERB_L0IOCAPR_IO_VAR_MASK (0xF000000U) 834 #define NETC_IERB_L0IOCAPR_IO_VAR_SHIFT (24U) 835 #define NETC_IERB_L0IOCAPR_IO_VAR_WIDTH (4U) 836 #define NETC_IERB_L0IOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L0IOCAPR_IO_VAR_MASK) 837 838 #define NETC_IERB_L0IOCAPR_EMDIO_MASK (0x10000000U) 839 #define NETC_IERB_L0IOCAPR_EMDIO_SHIFT (28U) 840 #define NETC_IERB_L0IOCAPR_EMDIO_WIDTH (1U) 841 #define NETC_IERB_L0IOCAPR_EMDIO(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_EMDIO_SHIFT)) & NETC_IERB_L0IOCAPR_EMDIO_MASK) 842 843 #define NETC_IERB_L0IOCAPR_REVMII_RATE_MASK (0x40000000U) 844 #define NETC_IERB_L0IOCAPR_REVMII_RATE_SHIFT (30U) 845 #define NETC_IERB_L0IOCAPR_REVMII_RATE_WIDTH (1U) 846 #define NETC_IERB_L0IOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L0IOCAPR_REVMII_RATE_MASK) 847 848 #define NETC_IERB_L0IOCAPR_REVMII_MASK (0x80000000U) 849 #define NETC_IERB_L0IOCAPR_REVMII_SHIFT (31U) 850 #define NETC_IERB_L0IOCAPR_REVMII_WIDTH (1U) 851 #define NETC_IERB_L0IOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0IOCAPR_REVMII_SHIFT)) & NETC_IERB_L0IOCAPR_REVMII_MASK) 852 /*! @} */ 853 854 /*! @name L0BCR - Link 0 binding configuration register */ 855 /*! @{ */ 856 857 #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST_MASK (0x1FU) 858 #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST_SHIFT (0U) 859 #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST_WIDTH (5U) 860 #define NETC_IERB_L0BCR_SW_PORT_ENETC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L0BCR_SW_PORT_ENETC_INST_MASK) 861 862 #define NETC_IERB_L0BCR_NETC_FUNC_MASK (0x40U) 863 #define NETC_IERB_L0BCR_NETC_FUNC_SHIFT (6U) 864 #define NETC_IERB_L0BCR_NETC_FUNC_WIDTH (1U) 865 #define NETC_IERB_L0BCR_NETC_FUNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L0BCR_NETC_FUNC_MASK) 866 867 #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_MASK (0x1F00U) 868 #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_SHIFT (8U) 869 #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_WIDTH (5U) 870 #define NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L0BCR_MDIO_PHYAD_PRTAD_MASK) 871 872 #define NETC_IERB_L0BCR_SPL_SW_PORT_MASK (0x1F0000U) 873 #define NETC_IERB_L0BCR_SPL_SW_PORT_SHIFT (16U) 874 #define NETC_IERB_L0BCR_SPL_SW_PORT_WIDTH (5U) 875 #define NETC_IERB_L0BCR_SPL_SW_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L0BCR_SPL_SW_PORT_MASK) 876 /*! @} */ 877 878 /*! @name L0TXBCCTR - Link 0 transmit byte credit comfort threshold register */ 879 /*! @{ */ 880 881 #define NETC_IERB_L0TXBCCTR_THRESH_MASK (0xFFFFU) 882 #define NETC_IERB_L0TXBCCTR_THRESH_SHIFT (0U) 883 #define NETC_IERB_L0TXBCCTR_THRESH_WIDTH (16U) 884 #define NETC_IERB_L0TXBCCTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L0TXBCCTR_THRESH_MASK) 885 /*! @} */ 886 887 /*! @name L0E0MAR0 - Link 0 end 0 MAC address register 0 */ 888 /*! @{ */ 889 890 #define NETC_IERB_L0E0MAR0_MAC_ADDR_MASK (0xFFFFFFFFU) 891 #define NETC_IERB_L0E0MAR0_MAC_ADDR_SHIFT (0U) 892 #define NETC_IERB_L0E0MAR0_MAC_ADDR_WIDTH (32U) 893 #define NETC_IERB_L0E0MAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L0E0MAR0_MAC_ADDR_MASK) 894 /*! @} */ 895 896 /*! @name L0E0MAR1 - Link 0 end 0 MAC address register 1 */ 897 /*! @{ */ 898 899 #define NETC_IERB_L0E0MAR1_MAC_ADDR_MASK (0xFFFFU) 900 #define NETC_IERB_L0E0MAR1_MAC_ADDR_SHIFT (0U) 901 #define NETC_IERB_L0E0MAR1_MAC_ADDR_WIDTH (16U) 902 #define NETC_IERB_L0E0MAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L0E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L0E0MAR1_MAC_ADDR_MASK) 903 /*! @} */ 904 905 /*! @name L1CAPR - Link 1 capability register */ 906 /*! @{ */ 907 908 #define NETC_IERB_L1CAPR_LINK_TYPE_MASK (0x10U) 909 #define NETC_IERB_L1CAPR_LINK_TYPE_SHIFT (4U) 910 #define NETC_IERB_L1CAPR_LINK_TYPE_WIDTH (1U) 911 #define NETC_IERB_L1CAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L1CAPR_LINK_TYPE_MASK) 912 913 #define NETC_IERB_L1CAPR_NUM_TC_MASK (0xF000U) 914 #define NETC_IERB_L1CAPR_NUM_TC_SHIFT (12U) 915 #define NETC_IERB_L1CAPR_NUM_TC_WIDTH (4U) 916 #define NETC_IERB_L1CAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_NUM_TC_SHIFT)) & NETC_IERB_L1CAPR_NUM_TC_MASK) 917 918 #define NETC_IERB_L1CAPR_NUM_Q_MASK (0xF0000U) 919 #define NETC_IERB_L1CAPR_NUM_Q_SHIFT (16U) 920 #define NETC_IERB_L1CAPR_NUM_Q_WIDTH (4U) 921 #define NETC_IERB_L1CAPR_NUM_Q(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_NUM_Q_SHIFT)) & NETC_IERB_L1CAPR_NUM_Q_MASK) 922 923 #define NETC_IERB_L1CAPR_NUM_CG_MASK (0xF000000U) 924 #define NETC_IERB_L1CAPR_NUM_CG_SHIFT (24U) 925 #define NETC_IERB_L1CAPR_NUM_CG_WIDTH (4U) 926 #define NETC_IERB_L1CAPR_NUM_CG(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_NUM_CG_SHIFT)) & NETC_IERB_L1CAPR_NUM_CG_MASK) 927 928 #define NETC_IERB_L1CAPR_TGS_MASK (0x10000000U) 929 #define NETC_IERB_L1CAPR_TGS_SHIFT (28U) 930 #define NETC_IERB_L1CAPR_TGS_WIDTH (1U) 931 #define NETC_IERB_L1CAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_TGS_SHIFT)) & NETC_IERB_L1CAPR_TGS_MASK) 932 933 #define NETC_IERB_L1CAPR_CBS_MASK (0x20000000U) 934 #define NETC_IERB_L1CAPR_CBS_SHIFT (29U) 935 #define NETC_IERB_L1CAPR_CBS_WIDTH (1U) 936 #define NETC_IERB_L1CAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1CAPR_CBS_SHIFT)) & NETC_IERB_L1CAPR_CBS_MASK) 937 /*! @} */ 938 939 /*! @name L1MCAPR - Link 1 MAC capability register */ 940 /*! @{ */ 941 942 #define NETC_IERB_L1MCAPR_MAC_VAR_MASK (0x7U) 943 #define NETC_IERB_L1MCAPR_MAC_VAR_SHIFT (0U) 944 #define NETC_IERB_L1MCAPR_MAC_VAR_WIDTH (3U) 945 #define NETC_IERB_L1MCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L1MCAPR_MAC_VAR_MASK) 946 947 #define NETC_IERB_L1MCAPR_EFPAD_MASK (0x30U) 948 #define NETC_IERB_L1MCAPR_EFPAD_SHIFT (4U) 949 #define NETC_IERB_L1MCAPR_EFPAD_WIDTH (2U) 950 #define NETC_IERB_L1MCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_EFPAD_SHIFT)) & NETC_IERB_L1MCAPR_EFPAD_MASK) 951 952 #define NETC_IERB_L1MCAPR_HD_MASK (0x100U) 953 #define NETC_IERB_L1MCAPR_HD_SHIFT (8U) 954 #define NETC_IERB_L1MCAPR_HD_WIDTH (1U) 955 #define NETC_IERB_L1MCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_HD_SHIFT)) & NETC_IERB_L1MCAPR_HD_MASK) 956 957 #define NETC_IERB_L1MCAPR_FP_MASK (0x600U) 958 #define NETC_IERB_L1MCAPR_FP_SHIFT (9U) 959 #define NETC_IERB_L1MCAPR_FP_WIDTH (2U) 960 #define NETC_IERB_L1MCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_FP_SHIFT)) & NETC_IERB_L1MCAPR_FP_MASK) 961 962 #define NETC_IERB_L1MCAPR_MII_PROT_MASK (0xF000000U) 963 #define NETC_IERB_L1MCAPR_MII_PROT_SHIFT (24U) 964 #define NETC_IERB_L1MCAPR_MII_PROT_WIDTH (4U) 965 #define NETC_IERB_L1MCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L1MCAPR_MII_PROT_MASK) 966 /*! @} */ 967 968 /*! @name L1IOCAPR - Link 1 I/O capability register */ 969 /*! @{ */ 970 971 #define NETC_IERB_L1IOCAPR_PCS_PROT_MASK (0xFFFFU) 972 #define NETC_IERB_L1IOCAPR_PCS_PROT_SHIFT (0U) 973 #define NETC_IERB_L1IOCAPR_PCS_PROT_WIDTH (16U) 974 #define NETC_IERB_L1IOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_PCS_PROT_SHIFT)) & NETC_IERB_L1IOCAPR_PCS_PROT_MASK) 975 976 #define NETC_IERB_L1IOCAPR_IO_VAR_MASK (0xF000000U) 977 #define NETC_IERB_L1IOCAPR_IO_VAR_SHIFT (24U) 978 #define NETC_IERB_L1IOCAPR_IO_VAR_WIDTH (4U) 979 #define NETC_IERB_L1IOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_IO_VAR_SHIFT)) & NETC_IERB_L1IOCAPR_IO_VAR_MASK) 980 981 #define NETC_IERB_L1IOCAPR_EMDIO_MASK (0x10000000U) 982 #define NETC_IERB_L1IOCAPR_EMDIO_SHIFT (28U) 983 #define NETC_IERB_L1IOCAPR_EMDIO_WIDTH (1U) 984 #define NETC_IERB_L1IOCAPR_EMDIO(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_EMDIO_SHIFT)) & NETC_IERB_L1IOCAPR_EMDIO_MASK) 985 986 #define NETC_IERB_L1IOCAPR_REVMII_RATE_MASK (0x40000000U) 987 #define NETC_IERB_L1IOCAPR_REVMII_RATE_SHIFT (30U) 988 #define NETC_IERB_L1IOCAPR_REVMII_RATE_WIDTH (1U) 989 #define NETC_IERB_L1IOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_REVMII_RATE_SHIFT)) & NETC_IERB_L1IOCAPR_REVMII_RATE_MASK) 990 991 #define NETC_IERB_L1IOCAPR_REVMII_MASK (0x80000000U) 992 #define NETC_IERB_L1IOCAPR_REVMII_SHIFT (31U) 993 #define NETC_IERB_L1IOCAPR_REVMII_WIDTH (1U) 994 #define NETC_IERB_L1IOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1IOCAPR_REVMII_SHIFT)) & NETC_IERB_L1IOCAPR_REVMII_MASK) 995 /*! @} */ 996 997 /*! @name L1BCR - Link 1 binding configuration register */ 998 /*! @{ */ 999 1000 #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST_MASK (0x1FU) 1001 #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST_SHIFT (0U) 1002 #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST_WIDTH (5U) 1003 #define NETC_IERB_L1BCR_SW_PORT_ENETC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L1BCR_SW_PORT_ENETC_INST_MASK) 1004 1005 #define NETC_IERB_L1BCR_NETC_FUNC_MASK (0x40U) 1006 #define NETC_IERB_L1BCR_NETC_FUNC_SHIFT (6U) 1007 #define NETC_IERB_L1BCR_NETC_FUNC_WIDTH (1U) 1008 #define NETC_IERB_L1BCR_NETC_FUNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L1BCR_NETC_FUNC_MASK) 1009 1010 #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_MASK (0x1F00U) 1011 #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_SHIFT (8U) 1012 #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_WIDTH (5U) 1013 #define NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_SHIFT)) & NETC_IERB_L1BCR_MDIO_PHYAD_PRTAD_MASK) 1014 1015 #define NETC_IERB_L1BCR_SPL_SW_PORT_MASK (0x1F0000U) 1016 #define NETC_IERB_L1BCR_SPL_SW_PORT_SHIFT (16U) 1017 #define NETC_IERB_L1BCR_SPL_SW_PORT_WIDTH (5U) 1018 #define NETC_IERB_L1BCR_SPL_SW_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L1BCR_SPL_SW_PORT_MASK) 1019 /*! @} */ 1020 1021 /*! @name L1TXBCCTR - Link 1 transmit byte credit comfort threshold register */ 1022 /*! @{ */ 1023 1024 #define NETC_IERB_L1TXBCCTR_THRESH_MASK (0xFFFFU) 1025 #define NETC_IERB_L1TXBCCTR_THRESH_SHIFT (0U) 1026 #define NETC_IERB_L1TXBCCTR_THRESH_WIDTH (16U) 1027 #define NETC_IERB_L1TXBCCTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L1TXBCCTR_THRESH_MASK) 1028 /*! @} */ 1029 1030 /*! @name L1E0MAR0 - Link 1 end 0 MAC address register 0 */ 1031 /*! @{ */ 1032 1033 #define NETC_IERB_L1E0MAR0_MAC_ADDR_MASK (0xFFFFFFFFU) 1034 #define NETC_IERB_L1E0MAR0_MAC_ADDR_SHIFT (0U) 1035 #define NETC_IERB_L1E0MAR0_MAC_ADDR_WIDTH (32U) 1036 #define NETC_IERB_L1E0MAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L1E0MAR0_MAC_ADDR_MASK) 1037 /*! @} */ 1038 1039 /*! @name L1E0MAR1 - Link 1 end 0 MAC address register 1 */ 1040 /*! @{ */ 1041 1042 #define NETC_IERB_L1E0MAR1_MAC_ADDR_MASK (0xFFFFU) 1043 #define NETC_IERB_L1E0MAR1_MAC_ADDR_SHIFT (0U) 1044 #define NETC_IERB_L1E0MAR1_MAC_ADDR_WIDTH (16U) 1045 #define NETC_IERB_L1E0MAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L1E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L1E0MAR1_MAC_ADDR_MASK) 1046 /*! @} */ 1047 1048 /*! @name L2CAPR - Link 2 capability register */ 1049 /*! @{ */ 1050 1051 #define NETC_IERB_L2CAPR_LINK_TYPE_MASK (0x10U) 1052 #define NETC_IERB_L2CAPR_LINK_TYPE_SHIFT (4U) 1053 #define NETC_IERB_L2CAPR_LINK_TYPE_WIDTH (1U) 1054 #define NETC_IERB_L2CAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_LINK_TYPE_SHIFT)) & NETC_IERB_L2CAPR_LINK_TYPE_MASK) 1055 1056 #define NETC_IERB_L2CAPR_NUM_TC_MASK (0xF000U) 1057 #define NETC_IERB_L2CAPR_NUM_TC_SHIFT (12U) 1058 #define NETC_IERB_L2CAPR_NUM_TC_WIDTH (4U) 1059 #define NETC_IERB_L2CAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_NUM_TC_SHIFT)) & NETC_IERB_L2CAPR_NUM_TC_MASK) 1060 1061 #define NETC_IERB_L2CAPR_NUM_Q_MASK (0xF0000U) 1062 #define NETC_IERB_L2CAPR_NUM_Q_SHIFT (16U) 1063 #define NETC_IERB_L2CAPR_NUM_Q_WIDTH (4U) 1064 #define NETC_IERB_L2CAPR_NUM_Q(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_NUM_Q_SHIFT)) & NETC_IERB_L2CAPR_NUM_Q_MASK) 1065 1066 #define NETC_IERB_L2CAPR_NUM_CG_MASK (0xF000000U) 1067 #define NETC_IERB_L2CAPR_NUM_CG_SHIFT (24U) 1068 #define NETC_IERB_L2CAPR_NUM_CG_WIDTH (4U) 1069 #define NETC_IERB_L2CAPR_NUM_CG(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_NUM_CG_SHIFT)) & NETC_IERB_L2CAPR_NUM_CG_MASK) 1070 1071 #define NETC_IERB_L2CAPR_TGS_MASK (0x10000000U) 1072 #define NETC_IERB_L2CAPR_TGS_SHIFT (28U) 1073 #define NETC_IERB_L2CAPR_TGS_WIDTH (1U) 1074 #define NETC_IERB_L2CAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_TGS_SHIFT)) & NETC_IERB_L2CAPR_TGS_MASK) 1075 1076 #define NETC_IERB_L2CAPR_CBS_MASK (0x20000000U) 1077 #define NETC_IERB_L2CAPR_CBS_SHIFT (29U) 1078 #define NETC_IERB_L2CAPR_CBS_WIDTH (1U) 1079 #define NETC_IERB_L2CAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2CAPR_CBS_SHIFT)) & NETC_IERB_L2CAPR_CBS_MASK) 1080 /*! @} */ 1081 1082 /*! @name L2MCAPR - Link 2 MAC capability register */ 1083 /*! @{ */ 1084 1085 #define NETC_IERB_L2MCAPR_MAC_VAR_MASK (0x7U) 1086 #define NETC_IERB_L2MCAPR_MAC_VAR_SHIFT (0U) 1087 #define NETC_IERB_L2MCAPR_MAC_VAR_WIDTH (3U) 1088 #define NETC_IERB_L2MCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_MAC_VAR_SHIFT)) & NETC_IERB_L2MCAPR_MAC_VAR_MASK) 1089 1090 #define NETC_IERB_L2MCAPR_EFPAD_MASK (0x30U) 1091 #define NETC_IERB_L2MCAPR_EFPAD_SHIFT (4U) 1092 #define NETC_IERB_L2MCAPR_EFPAD_WIDTH (2U) 1093 #define NETC_IERB_L2MCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_EFPAD_SHIFT)) & NETC_IERB_L2MCAPR_EFPAD_MASK) 1094 1095 #define NETC_IERB_L2MCAPR_HD_MASK (0x100U) 1096 #define NETC_IERB_L2MCAPR_HD_SHIFT (8U) 1097 #define NETC_IERB_L2MCAPR_HD_WIDTH (1U) 1098 #define NETC_IERB_L2MCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_HD_SHIFT)) & NETC_IERB_L2MCAPR_HD_MASK) 1099 1100 #define NETC_IERB_L2MCAPR_FP_MASK (0x600U) 1101 #define NETC_IERB_L2MCAPR_FP_SHIFT (9U) 1102 #define NETC_IERB_L2MCAPR_FP_WIDTH (2U) 1103 #define NETC_IERB_L2MCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_FP_SHIFT)) & NETC_IERB_L2MCAPR_FP_MASK) 1104 1105 #define NETC_IERB_L2MCAPR_MII_PROT_MASK (0xF000000U) 1106 #define NETC_IERB_L2MCAPR_MII_PROT_SHIFT (24U) 1107 #define NETC_IERB_L2MCAPR_MII_PROT_WIDTH (4U) 1108 #define NETC_IERB_L2MCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2MCAPR_MII_PROT_SHIFT)) & NETC_IERB_L2MCAPR_MII_PROT_MASK) 1109 /*! @} */ 1110 1111 /*! @name L2BCR - Link 2 binding configuration register */ 1112 /*! @{ */ 1113 1114 #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST_MASK (0x1FU) 1115 #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST_SHIFT (0U) 1116 #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST_WIDTH (5U) 1117 #define NETC_IERB_L2BCR_SW_PORT_ENETC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_SW_PORT_ENETC_INST_SHIFT)) & NETC_IERB_L2BCR_SW_PORT_ENETC_INST_MASK) 1118 1119 #define NETC_IERB_L2BCR_NETC_FUNC_MASK (0x40U) 1120 #define NETC_IERB_L2BCR_NETC_FUNC_SHIFT (6U) 1121 #define NETC_IERB_L2BCR_NETC_FUNC_WIDTH (1U) 1122 #define NETC_IERB_L2BCR_NETC_FUNC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_NETC_FUNC_SHIFT)) & NETC_IERB_L2BCR_NETC_FUNC_MASK) 1123 1124 #define NETC_IERB_L2BCR_SPL_SW_PORT_MASK (0x1F0000U) 1125 #define NETC_IERB_L2BCR_SPL_SW_PORT_SHIFT (16U) 1126 #define NETC_IERB_L2BCR_SPL_SW_PORT_WIDTH (5U) 1127 #define NETC_IERB_L2BCR_SPL_SW_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2BCR_SPL_SW_PORT_SHIFT)) & NETC_IERB_L2BCR_SPL_SW_PORT_MASK) 1128 /*! @} */ 1129 1130 /*! @name L2TXBCCTR - Link 2 transmit byte credit comfort threshold register */ 1131 /*! @{ */ 1132 1133 #define NETC_IERB_L2TXBCCTR_THRESH_MASK (0xFFFFU) 1134 #define NETC_IERB_L2TXBCCTR_THRESH_SHIFT (0U) 1135 #define NETC_IERB_L2TXBCCTR_THRESH_WIDTH (16U) 1136 #define NETC_IERB_L2TXBCCTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2TXBCCTR_THRESH_SHIFT)) & NETC_IERB_L2TXBCCTR_THRESH_MASK) 1137 /*! @} */ 1138 1139 /*! @name L2E0MAR0 - Link 2 end 0 MAC address register 0 */ 1140 /*! @{ */ 1141 1142 #define NETC_IERB_L2E0MAR0_MAC_ADDR_MASK (0xFFFFFFFFU) 1143 #define NETC_IERB_L2E0MAR0_MAC_ADDR_SHIFT (0U) 1144 #define NETC_IERB_L2E0MAR0_MAC_ADDR_WIDTH (32U) 1145 #define NETC_IERB_L2E0MAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2E0MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L2E0MAR0_MAC_ADDR_MASK) 1146 /*! @} */ 1147 1148 /*! @name L2E0MAR1 - Link 2 end 0 MAC address register 1 */ 1149 /*! @{ */ 1150 1151 #define NETC_IERB_L2E0MAR1_MAC_ADDR_MASK (0xFFFFU) 1152 #define NETC_IERB_L2E0MAR1_MAC_ADDR_SHIFT (0U) 1153 #define NETC_IERB_L2E0MAR1_MAC_ADDR_WIDTH (16U) 1154 #define NETC_IERB_L2E0MAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2E0MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L2E0MAR1_MAC_ADDR_MASK) 1155 /*! @} */ 1156 1157 /*! @name L2E1MAR0 - Link 2 end 1 MAC address register 0 */ 1158 /*! @{ */ 1159 1160 #define NETC_IERB_L2E1MAR0_MAC_ADDR_MASK (0xFFFFFFFFU) 1161 #define NETC_IERB_L2E1MAR0_MAC_ADDR_SHIFT (0U) 1162 #define NETC_IERB_L2E1MAR0_MAC_ADDR_WIDTH (32U) 1163 #define NETC_IERB_L2E1MAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2E1MAR0_MAC_ADDR_SHIFT)) & NETC_IERB_L2E1MAR0_MAC_ADDR_MASK) 1164 /*! @} */ 1165 1166 /*! @name L2E1MAR1 - Link 2 end 1 MAC address register 1 */ 1167 /*! @{ */ 1168 1169 #define NETC_IERB_L2E1MAR1_MAC_ADDR_MASK (0xFFFFU) 1170 #define NETC_IERB_L2E1MAR1_MAC_ADDR_SHIFT (0U) 1171 #define NETC_IERB_L2E1MAR1_MAC_ADDR_WIDTH (16U) 1172 #define NETC_IERB_L2E1MAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_L2E1MAR1_MAC_ADDR_SHIFT)) & NETC_IERB_L2E1MAR1_MAC_ADDR_MASK) 1173 /*! @} */ 1174 1175 /*! @name SBCR - Switch 0 binding configuration register */ 1176 /*! @{ */ 1177 1178 #define NETC_IERB_SBCR_RC_INST_MASK (0xFU) 1179 #define NETC_IERB_SBCR_RC_INST_SHIFT (0U) 1180 #define NETC_IERB_SBCR_RC_INST_WIDTH (4U) 1181 #define NETC_IERB_SBCR_RC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_RC_INST_SHIFT)) & NETC_IERB_SBCR_RC_INST_MASK) 1182 1183 #define NETC_IERB_SBCR_FN_MASK (0xF00U) 1184 #define NETC_IERB_SBCR_FN_SHIFT (8U) 1185 #define NETC_IERB_SBCR_FN_WIDTH (4U) 1186 #define NETC_IERB_SBCR_FN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_FN_SHIFT)) & NETC_IERB_SBCR_FN_MASK) 1187 1188 #define NETC_IERB_SBCR_VALID_MASK (0x80000000U) 1189 #define NETC_IERB_SBCR_VALID_SHIFT (31U) 1190 #define NETC_IERB_SBCR_VALID_WIDTH (1U) 1191 #define NETC_IERB_SBCR_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBCR_VALID_SHIFT)) & NETC_IERB_SBCR_VALID_MASK) 1192 /*! @} */ 1193 1194 /*! @name SMCR - Switch 0 MSI-X configuration register */ 1195 /*! @{ */ 1196 1197 #define NETC_IERB_SMCR_NUM_MSIX_MASK (0xFU) 1198 #define NETC_IERB_SMCR_NUM_MSIX_SHIFT (0U) 1199 #define NETC_IERB_SMCR_NUM_MSIX_WIDTH (4U) 1200 #define NETC_IERB_SMCR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SMCR_NUM_MSIX_SHIFT)) & NETC_IERB_SMCR_NUM_MSIX_MASK) 1201 /*! @} */ 1202 1203 /*! @name S_CFH_DIDVID - Switch 0 config header device ID and vendor ID register */ 1204 /*! @{ */ 1205 1206 #define NETC_IERB_S_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) 1207 #define NETC_IERB_S_CFH_DIDVID_VENDOR_ID_SHIFT (0U) 1208 #define NETC_IERB_S_CFH_DIDVID_VENDOR_ID_WIDTH (16U) 1209 #define NETC_IERB_S_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_S_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_S_CFH_DIDVID_VENDOR_ID_MASK) 1210 1211 #define NETC_IERB_S_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) 1212 #define NETC_IERB_S_CFH_DIDVID_DEVICE_ID_SHIFT (16U) 1213 #define NETC_IERB_S_CFH_DIDVID_DEVICE_ID_WIDTH (16U) 1214 #define NETC_IERB_S_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_S_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_S_CFH_DIDVID_DEVICE_ID_MASK) 1215 /*! @} */ 1216 1217 /*! @name S_CFH_SIDSVID - Switch 0 config header subsystem ID and subsystem vendor ID register */ 1218 /*! @{ */ 1219 1220 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) 1221 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) 1222 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_WIDTH (16U) 1223 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) 1224 1225 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) 1226 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) 1227 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_WIDTH (16U) 1228 #define NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_S_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) 1229 /*! @} */ 1230 1231 /*! @name SCCAR - Switch 0 command cache attribute register */ 1232 /*! @{ */ 1233 1234 #define NETC_IERB_SCCAR_CBD_WRCACHE_MASK (0xFU) 1235 #define NETC_IERB_SCCAR_CBD_WRCACHE_SHIFT (0U) 1236 #define NETC_IERB_SCCAR_CBD_WRCACHE_WIDTH (4U) 1237 #define NETC_IERB_SCCAR_CBD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_WRCACHE_SHIFT)) & NETC_IERB_SCCAR_CBD_WRCACHE_MASK) 1238 1239 #define NETC_IERB_SCCAR_CBD_WRDOMAIN_MASK (0x30U) 1240 #define NETC_IERB_SCCAR_CBD_WRDOMAIN_SHIFT (4U) 1241 #define NETC_IERB_SCCAR_CBD_WRDOMAIN_WIDTH (2U) 1242 #define NETC_IERB_SCCAR_CBD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_WRDOMAIN_SHIFT)) & NETC_IERB_SCCAR_CBD_WRDOMAIN_MASK) 1243 1244 #define NETC_IERB_SCCAR_CBD_WRSNP_MASK (0x40U) 1245 #define NETC_IERB_SCCAR_CBD_WRSNP_SHIFT (6U) 1246 #define NETC_IERB_SCCAR_CBD_WRSNP_WIDTH (1U) 1247 #define NETC_IERB_SCCAR_CBD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_WRSNP_SHIFT)) & NETC_IERB_SCCAR_CBD_WRSNP_MASK) 1248 1249 #define NETC_IERB_SCCAR_CWRCACHE_MASK (0xF00U) 1250 #define NETC_IERB_SCCAR_CWRCACHE_SHIFT (8U) 1251 #define NETC_IERB_SCCAR_CWRCACHE_WIDTH (4U) 1252 #define NETC_IERB_SCCAR_CWRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CWRCACHE_SHIFT)) & NETC_IERB_SCCAR_CWRCACHE_MASK) 1253 1254 #define NETC_IERB_SCCAR_CWRDOMAIN_MASK (0x3000U) 1255 #define NETC_IERB_SCCAR_CWRDOMAIN_SHIFT (12U) 1256 #define NETC_IERB_SCCAR_CWRDOMAIN_WIDTH (2U) 1257 #define NETC_IERB_SCCAR_CWRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CWRDOMAIN_SHIFT)) & NETC_IERB_SCCAR_CWRDOMAIN_MASK) 1258 1259 #define NETC_IERB_SCCAR_CWRSNP_MASK (0x4000U) 1260 #define NETC_IERB_SCCAR_CWRSNP_SHIFT (14U) 1261 #define NETC_IERB_SCCAR_CWRSNP_WIDTH (1U) 1262 #define NETC_IERB_SCCAR_CWRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CWRSNP_SHIFT)) & NETC_IERB_SCCAR_CWRSNP_MASK) 1263 1264 #define NETC_IERB_SCCAR_CBD_RDCACHE_MASK (0xF0000U) 1265 #define NETC_IERB_SCCAR_CBD_RDCACHE_SHIFT (16U) 1266 #define NETC_IERB_SCCAR_CBD_RDCACHE_WIDTH (4U) 1267 #define NETC_IERB_SCCAR_CBD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_RDCACHE_SHIFT)) & NETC_IERB_SCCAR_CBD_RDCACHE_MASK) 1268 1269 #define NETC_IERB_SCCAR_CBD_RDDOMAIN_MASK (0x300000U) 1270 #define NETC_IERB_SCCAR_CBD_RDDOMAIN_SHIFT (20U) 1271 #define NETC_IERB_SCCAR_CBD_RDDOMAIN_WIDTH (2U) 1272 #define NETC_IERB_SCCAR_CBD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_RDDOMAIN_SHIFT)) & NETC_IERB_SCCAR_CBD_RDDOMAIN_MASK) 1273 1274 #define NETC_IERB_SCCAR_CBD_RDSNP_MASK (0x400000U) 1275 #define NETC_IERB_SCCAR_CBD_RDSNP_SHIFT (22U) 1276 #define NETC_IERB_SCCAR_CBD_RDSNP_WIDTH (1U) 1277 #define NETC_IERB_SCCAR_CBD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CBD_RDSNP_SHIFT)) & NETC_IERB_SCCAR_CBD_RDSNP_MASK) 1278 1279 #define NETC_IERB_SCCAR_CRDCACHE_MASK (0xF000000U) 1280 #define NETC_IERB_SCCAR_CRDCACHE_SHIFT (24U) 1281 #define NETC_IERB_SCCAR_CRDCACHE_WIDTH (4U) 1282 #define NETC_IERB_SCCAR_CRDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CRDCACHE_SHIFT)) & NETC_IERB_SCCAR_CRDCACHE_MASK) 1283 1284 #define NETC_IERB_SCCAR_CRDDOMAIN_MASK (0x30000000U) 1285 #define NETC_IERB_SCCAR_CRDDOMAIN_SHIFT (28U) 1286 #define NETC_IERB_SCCAR_CRDDOMAIN_WIDTH (2U) 1287 #define NETC_IERB_SCCAR_CRDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CRDDOMAIN_SHIFT)) & NETC_IERB_SCCAR_CRDDOMAIN_MASK) 1288 1289 #define NETC_IERB_SCCAR_CRDSNP_MASK (0x40000000U) 1290 #define NETC_IERB_SCCAR_CRDSNP_SHIFT (30U) 1291 #define NETC_IERB_SCCAR_CRDSNP_WIDTH (1U) 1292 #define NETC_IERB_SCCAR_CRDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SCCAR_CRDSNP_SHIFT)) & NETC_IERB_SCCAR_CRDSNP_MASK) 1293 /*! @} */ 1294 1295 /*! @name SAMQR - Switch 0 access management qualifier register */ 1296 /*! @{ */ 1297 1298 #define NETC_IERB_SAMQR_ARQOS_MASK (0xF0000U) 1299 #define NETC_IERB_SAMQR_ARQOS_SHIFT (16U) 1300 #define NETC_IERB_SAMQR_ARQOS_WIDTH (4U) 1301 #define NETC_IERB_SAMQR_ARQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SAMQR_ARQOS_SHIFT)) & NETC_IERB_SAMQR_ARQOS_MASK) 1302 1303 #define NETC_IERB_SAMQR_AWQOS_MASK (0xF00000U) 1304 #define NETC_IERB_SAMQR_AWQOS_SHIFT (20U) 1305 #define NETC_IERB_SAMQR_AWQOS_WIDTH (4U) 1306 #define NETC_IERB_SAMQR_AWQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SAMQR_AWQOS_SHIFT)) & NETC_IERB_SAMQR_AWQOS_MASK) 1307 1308 #define NETC_IERB_SAMQR_BMT_MASK (0x80000000U) 1309 #define NETC_IERB_SAMQR_BMT_SHIFT (31U) 1310 #define NETC_IERB_SAMQR_BMT_WIDTH (1U) 1311 #define NETC_IERB_SAMQR_BMT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SAMQR_BMT_SHIFT)) & NETC_IERB_SAMQR_BMT_MASK) 1312 /*! @} */ 1313 1314 /*! @name SBLPR - Switch 0 boot loader parameter register 0..Switch 0 boot loader parameter register 1 */ 1315 /*! @{ */ 1316 1317 #define NETC_IERB_SBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) 1318 #define NETC_IERB_SBLPR_PARAM_VAL_SHIFT (0U) 1319 #define NETC_IERB_SBLPR_PARAM_VAL_WIDTH (32U) 1320 #define NETC_IERB_SBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_SBLPR_PARAM_VAL_MASK) 1321 /*! @} */ 1322 1323 /*! @name SSMBAR - Switch 0 shared memory buffer allotment register */ 1324 /*! @{ */ 1325 1326 #define NETC_IERB_SSMBAR_ALLOC_MASK (0xFFFFFFU) 1327 #define NETC_IERB_SSMBAR_ALLOC_SHIFT (0U) 1328 #define NETC_IERB_SSMBAR_ALLOC_WIDTH (24U) 1329 #define NETC_IERB_SSMBAR_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SSMBAR_ALLOC_SHIFT)) & NETC_IERB_SSMBAR_ALLOC_MASK) 1330 1331 #define NETC_IERB_SSMBAR_MLOC_MASK (0xC0000000U) 1332 #define NETC_IERB_SSMBAR_MLOC_SHIFT (30U) 1333 #define NETC_IERB_SSMBAR_MLOC_WIDTH (2U) 1334 #define NETC_IERB_SSMBAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SSMBAR_MLOC_SHIFT)) & NETC_IERB_SSMBAR_MLOC_MASK) 1335 /*! @} */ 1336 1337 /*! @name SHTMAR - Switch 0 hash table memory allotment register */ 1338 /*! @{ */ 1339 1340 #define NETC_IERB_SHTMAR_NUM_WORDS_MASK (0xFFFFU) 1341 #define NETC_IERB_SHTMAR_NUM_WORDS_SHIFT (0U) 1342 #define NETC_IERB_SHTMAR_NUM_WORDS_WIDTH (16U) 1343 #define NETC_IERB_SHTMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SHTMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SHTMAR_NUM_WORDS_MASK) 1344 1345 #define NETC_IERB_SHTMAR_MLOC_MASK (0xC0000000U) 1346 #define NETC_IERB_SHTMAR_MLOC_SHIFT (30U) 1347 #define NETC_IERB_SHTMAR_MLOC_WIDTH (2U) 1348 #define NETC_IERB_SHTMAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SHTMAR_MLOC_SHIFT)) & NETC_IERB_SHTMAR_MLOC_MASK) 1349 /*! @} */ 1350 1351 /*! @name SITMAR - Switch 0 index table memory allocation register */ 1352 /*! @{ */ 1353 1354 #define NETC_IERB_SITMAR_NUM_WORDS_MASK (0xFFFFU) 1355 #define NETC_IERB_SITMAR_NUM_WORDS_SHIFT (0U) 1356 #define NETC_IERB_SITMAR_NUM_WORDS_WIDTH (16U) 1357 #define NETC_IERB_SITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SITMAR_NUM_WORDS_MASK) 1358 1359 #define NETC_IERB_SITMAR_MLOC_MASK (0xC0000000U) 1360 #define NETC_IERB_SITMAR_MLOC_SHIFT (30U) 1361 #define NETC_IERB_SITMAR_MLOC_WIDTH (2U) 1362 #define NETC_IERB_SITMAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SITMAR_MLOC_SHIFT)) & NETC_IERB_SITMAR_MLOC_MASK) 1363 /*! @} */ 1364 1365 /*! @name SIPFTMAR - Switch 0 ingress port filter table memory allocation register */ 1366 /*! @{ */ 1367 1368 #define NETC_IERB_SIPFTMAR_ALLOC_MASK (0xFFFFU) 1369 #define NETC_IERB_SIPFTMAR_ALLOC_SHIFT (0U) 1370 #define NETC_IERB_SIPFTMAR_ALLOC_WIDTH (16U) 1371 #define NETC_IERB_SIPFTMAR_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SIPFTMAR_ALLOC_SHIFT)) & NETC_IERB_SIPFTMAR_ALLOC_MASK) 1372 /*! @} */ 1373 1374 /*! @name SRPITMAR - Switch 0 rate policer index table memory allocation register */ 1375 /*! @{ */ 1376 1377 #define NETC_IERB_SRPITMAR_NUM_WORDS_MASK (0xFFFFU) 1378 #define NETC_IERB_SRPITMAR_NUM_WORDS_SHIFT (0U) 1379 #define NETC_IERB_SRPITMAR_NUM_WORDS_WIDTH (16U) 1380 #define NETC_IERB_SRPITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SRPITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SRPITMAR_NUM_WORDS_MASK) 1381 /*! @} */ 1382 1383 /*! @name SISCITMAR - Switch 0 ingress stream counter index table memory allocation register */ 1384 /*! @{ */ 1385 1386 #define NETC_IERB_SISCITMAR_NUM_WORDS_MASK (0xFFFFU) 1387 #define NETC_IERB_SISCITMAR_NUM_WORDS_SHIFT (0U) 1388 #define NETC_IERB_SISCITMAR_NUM_WORDS_WIDTH (16U) 1389 #define NETC_IERB_SISCITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SISCITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SISCITMAR_NUM_WORDS_MASK) 1390 /*! @} */ 1391 1392 /*! @name SISITMAR - Switch 0 ingress stream index table memory allocation register */ 1393 /*! @{ */ 1394 1395 #define NETC_IERB_SISITMAR_NUM_WORDS_MASK (0xFFFFU) 1396 #define NETC_IERB_SISITMAR_NUM_WORDS_SHIFT (0U) 1397 #define NETC_IERB_SISITMAR_NUM_WORDS_WIDTH (16U) 1398 #define NETC_IERB_SISITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SISITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SISITMAR_NUM_WORDS_MASK) 1399 /*! @} */ 1400 1401 /*! @name SISQGITMAR - Switch 0 ingress sequence generation index table memory allocation register */ 1402 /*! @{ */ 1403 1404 #define NETC_IERB_SISQGITMAR_NUM_WORDS_MASK (0x1FFFU) 1405 #define NETC_IERB_SISQGITMAR_NUM_WORDS_SHIFT (0U) 1406 #define NETC_IERB_SISQGITMAR_NUM_WORDS_WIDTH (13U) 1407 #define NETC_IERB_SISQGITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SISQGITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SISQGITMAR_NUM_WORDS_MASK) 1408 /*! @} */ 1409 1410 /*! @name SSGIITMAR - Switch 0 stream gate instance index table memory allocation register */ 1411 /*! @{ */ 1412 1413 #define NETC_IERB_SSGIITMAR_NUM_WORDS_MASK (0xFFFFU) 1414 #define NETC_IERB_SSGIITMAR_NUM_WORDS_SHIFT (0U) 1415 #define NETC_IERB_SSGIITMAR_NUM_WORDS_WIDTH (16U) 1416 #define NETC_IERB_SSGIITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SSGIITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SSGIITMAR_NUM_WORDS_MASK) 1417 /*! @} */ 1418 1419 /*! @name SSGCLITMAR - Switch 0 stream gate control list index table memory allocation register */ 1420 /*! @{ */ 1421 1422 #define NETC_IERB_SSGCLITMAR_NUM_WORDS_MASK (0xFFFFU) 1423 #define NETC_IERB_SSGCLITMAR_NUM_WORDS_SHIFT (0U) 1424 #define NETC_IERB_SSGCLITMAR_NUM_WORDS_WIDTH (16U) 1425 #define NETC_IERB_SSGCLITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SSGCLITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SSGCLITMAR_NUM_WORDS_MASK) 1426 /*! @} */ 1427 1428 /*! @name SFMITMAR - Switch 0 frame modification index table memory allocation register */ 1429 /*! @{ */ 1430 1431 #define NETC_IERB_SFMITMAR_NUM_WORDS_MASK (0x1FFFU) 1432 #define NETC_IERB_SFMITMAR_NUM_WORDS_SHIFT (0U) 1433 #define NETC_IERB_SFMITMAR_NUM_WORDS_WIDTH (13U) 1434 #define NETC_IERB_SFMITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SFMITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SFMITMAR_NUM_WORDS_MASK) 1435 /*! @} */ 1436 1437 /*! @name SFMDITMAR - Switch 0 frame modification data index table memory allocation register */ 1438 /*! @{ */ 1439 1440 #define NETC_IERB_SFMDITMAR_NUM_WORDS_MASK (0xFFFFU) 1441 #define NETC_IERB_SFMDITMAR_NUM_WORDS_SHIFT (0U) 1442 #define NETC_IERB_SFMDITMAR_NUM_WORDS_WIDTH (16U) 1443 #define NETC_IERB_SFMDITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SFMDITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_SFMDITMAR_NUM_WORDS_MASK) 1444 /*! @} */ 1445 1446 /*! @name STGSTAR - Switch 0 time gate scheduling table allocation register */ 1447 /*! @{ */ 1448 1449 #define NETC_IERB_STGSTAR_NUM_WORDS_MASK (0xFFFU) 1450 #define NETC_IERB_STGSTAR_NUM_WORDS_SHIFT (0U) 1451 #define NETC_IERB_STGSTAR_NUM_WORDS_WIDTH (12U) 1452 #define NETC_IERB_STGSTAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_STGSTAR_NUM_WORDS_SHIFT)) & NETC_IERB_STGSTAR_NUM_WORDS_MASK) 1453 /*! @} */ 1454 1455 /*! @name STGSLR - Switch 0 time gate scheduling lookahead register */ 1456 /*! @{ */ 1457 1458 #define NETC_IERB_STGSLR_MIN_LOOKAHEAD_MASK (0xFFFFFU) 1459 #define NETC_IERB_STGSLR_MIN_LOOKAHEAD_SHIFT (0U) 1460 #define NETC_IERB_STGSLR_MIN_LOOKAHEAD_WIDTH (20U) 1461 #define NETC_IERB_STGSLR_MIN_LOOKAHEAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_STGSLR_MIN_LOOKAHEAD_SHIFT)) & NETC_IERB_STGSLR_MIN_LOOKAHEAD_MASK) 1462 /*! @} */ 1463 1464 /*! @name SMPCR - Switch 0 management port configuration register */ 1465 /*! @{ */ 1466 1467 #define NETC_IERB_SMPCR_PORT_MASK (0x1FU) 1468 #define NETC_IERB_SMPCR_PORT_SHIFT (0U) 1469 #define NETC_IERB_SMPCR_PORT_WIDTH (5U) 1470 #define NETC_IERB_SMPCR_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SMPCR_PORT_SHIFT)) & NETC_IERB_SMPCR_PORT_MASK) 1471 /*! @} */ 1472 1473 /*! @name SVFHTDECR0 - Switch 0 VLAN Filter (hash) table default entry configuration registers 0 */ 1474 /*! @{ */ 1475 1476 #define NETC_IERB_SVFHTDECR0_PORT0_MASK (0x1U) 1477 #define NETC_IERB_SVFHTDECR0_PORT0_SHIFT (0U) 1478 #define NETC_IERB_SVFHTDECR0_PORT0_WIDTH (1U) 1479 #define NETC_IERB_SVFHTDECR0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_PORT0_SHIFT)) & NETC_IERB_SVFHTDECR0_PORT0_MASK) 1480 1481 #define NETC_IERB_SVFHTDECR0_PORT1_MASK (0x2U) 1482 #define NETC_IERB_SVFHTDECR0_PORT1_SHIFT (1U) 1483 #define NETC_IERB_SVFHTDECR0_PORT1_WIDTH (1U) 1484 #define NETC_IERB_SVFHTDECR0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_PORT1_SHIFT)) & NETC_IERB_SVFHTDECR0_PORT1_MASK) 1485 1486 #define NETC_IERB_SVFHTDECR0_PORT2_MASK (0x4U) 1487 #define NETC_IERB_SVFHTDECR0_PORT2_SHIFT (2U) 1488 #define NETC_IERB_SVFHTDECR0_PORT2_WIDTH (1U) 1489 #define NETC_IERB_SVFHTDECR0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_PORT2_SHIFT)) & NETC_IERB_SVFHTDECR0_PORT2_MASK) 1490 1491 #define NETC_IERB_SVFHTDECR0_STG_ID_MASK (0xF000000U) 1492 #define NETC_IERB_SVFHTDECR0_STG_ID_SHIFT (24U) 1493 #define NETC_IERB_SVFHTDECR0_STG_ID_WIDTH (4U) 1494 #define NETC_IERB_SVFHTDECR0_STG_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_STG_ID_SHIFT)) & NETC_IERB_SVFHTDECR0_STG_ID_MASK) 1495 1496 #define NETC_IERB_SVFHTDECR0_IPMFE_MASK (0x20000000U) 1497 #define NETC_IERB_SVFHTDECR0_IPMFE_SHIFT (29U) 1498 #define NETC_IERB_SVFHTDECR0_IPMFE_WIDTH (1U) 1499 #define NETC_IERB_SVFHTDECR0_IPMFE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_IPMFE_SHIFT)) & NETC_IERB_SVFHTDECR0_IPMFE_MASK) 1500 1501 #define NETC_IERB_SVFHTDECR0_IPMFLE_MASK (0x40000000U) 1502 #define NETC_IERB_SVFHTDECR0_IPMFLE_SHIFT (30U) 1503 #define NETC_IERB_SVFHTDECR0_IPMFLE_WIDTH (1U) 1504 #define NETC_IERB_SVFHTDECR0_IPMFLE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR0_IPMFLE_SHIFT)) & NETC_IERB_SVFHTDECR0_IPMFLE_MASK) 1505 /*! @} */ 1506 1507 /*! @name SVFHTDECR1 - Switch 0 VLAN filter hash table default entry configuration registers 1 */ 1508 /*! @{ */ 1509 1510 #define NETC_IERB_SVFHTDECR1_FID_MASK (0xFFFU) 1511 #define NETC_IERB_SVFHTDECR1_FID_SHIFT (0U) 1512 #define NETC_IERB_SVFHTDECR1_FID_WIDTH (12U) 1513 #define NETC_IERB_SVFHTDECR1_FID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR1_FID_SHIFT)) & NETC_IERB_SVFHTDECR1_FID_MASK) 1514 1515 #define NETC_IERB_SVFHTDECR1_VL_MODE_MASK (0x1000U) 1516 #define NETC_IERB_SVFHTDECR1_VL_MODE_SHIFT (12U) 1517 #define NETC_IERB_SVFHTDECR1_VL_MODE_WIDTH (1U) 1518 #define NETC_IERB_SVFHTDECR1_VL_MODE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR1_VL_MODE_SHIFT)) & NETC_IERB_SVFHTDECR1_VL_MODE_MASK) 1519 1520 #define NETC_IERB_SVFHTDECR1_BASE_ETEID_MASK (0xFFFF0000U) 1521 #define NETC_IERB_SVFHTDECR1_BASE_ETEID_SHIFT (16U) 1522 #define NETC_IERB_SVFHTDECR1_BASE_ETEID_WIDTH (16U) 1523 #define NETC_IERB_SVFHTDECR1_BASE_ETEID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR1_BASE_ETEID_SHIFT)) & NETC_IERB_SVFHTDECR1_BASE_ETEID_MASK) 1524 /*! @} */ 1525 1526 /*! @name SVFHTDECR2 - Switch 0 VLAN filter hash table default entry configuration registers 2 */ 1527 /*! @{ */ 1528 1529 #define NETC_IERB_SVFHTDECR2_ES_PORT0_MASK (0x1U) 1530 #define NETC_IERB_SVFHTDECR2_ES_PORT0_SHIFT (0U) 1531 #define NETC_IERB_SVFHTDECR2_ES_PORT0_WIDTH (1U) 1532 #define NETC_IERB_SVFHTDECR2_ES_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_ES_PORT0_SHIFT)) & NETC_IERB_SVFHTDECR2_ES_PORT0_MASK) 1533 1534 #define NETC_IERB_SVFHTDECR2_ES_PORT1_MASK (0x2U) 1535 #define NETC_IERB_SVFHTDECR2_ES_PORT1_SHIFT (1U) 1536 #define NETC_IERB_SVFHTDECR2_ES_PORT1_WIDTH (1U) 1537 #define NETC_IERB_SVFHTDECR2_ES_PORT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_ES_PORT1_SHIFT)) & NETC_IERB_SVFHTDECR2_ES_PORT1_MASK) 1538 1539 #define NETC_IERB_SVFHTDECR2_ES_PORT2_MASK (0x4U) 1540 #define NETC_IERB_SVFHTDECR2_ES_PORT2_SHIFT (2U) 1541 #define NETC_IERB_SVFHTDECR2_ES_PORT2_WIDTH (1U) 1542 #define NETC_IERB_SVFHTDECR2_ES_PORT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_ES_PORT2_SHIFT)) & NETC_IERB_SVFHTDECR2_ES_PORT2_MASK) 1543 1544 #define NETC_IERB_SVFHTDECR2_MLO_MASK (0x7000000U) 1545 #define NETC_IERB_SVFHTDECR2_MLO_SHIFT (24U) 1546 #define NETC_IERB_SVFHTDECR2_MLO_WIDTH (3U) 1547 #define NETC_IERB_SVFHTDECR2_MLO(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_MLO_SHIFT)) & NETC_IERB_SVFHTDECR2_MLO_MASK) 1548 1549 #define NETC_IERB_SVFHTDECR2_MFO_MASK (0x18000000U) 1550 #define NETC_IERB_SVFHTDECR2_MFO_SHIFT (27U) 1551 #define NETC_IERB_SVFHTDECR2_MFO_WIDTH (2U) 1552 #define NETC_IERB_SVFHTDECR2_MFO(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_SVFHTDECR2_MFO_SHIFT)) & NETC_IERB_SVFHTDECR2_MFO_MASK) 1553 /*! @} */ 1554 1555 /*! @name EBCR0 - ENETC 0 binding configuration register 0 */ 1556 /*! @{ */ 1557 1558 #define NETC_IERB_EBCR0_RC_INST_MASK (0xFU) 1559 #define NETC_IERB_EBCR0_RC_INST_SHIFT (0U) 1560 #define NETC_IERB_EBCR0_RC_INST_WIDTH (4U) 1561 #define NETC_IERB_EBCR0_RC_INST(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR0_RC_INST_SHIFT)) & NETC_IERB_EBCR0_RC_INST_MASK) 1562 1563 #define NETC_IERB_EBCR0_FN_MASK (0xF00U) 1564 #define NETC_IERB_EBCR0_FN_SHIFT (8U) 1565 #define NETC_IERB_EBCR0_FN_WIDTH (4U) 1566 #define NETC_IERB_EBCR0_FN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR0_FN_SHIFT)) & NETC_IERB_EBCR0_FN_MASK) 1567 1568 #define NETC_IERB_EBCR0_VALID_MASK (0x80000000U) 1569 #define NETC_IERB_EBCR0_VALID_SHIFT (31U) 1570 #define NETC_IERB_EBCR0_VALID_WIDTH (1U) 1571 #define NETC_IERB_EBCR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR0_VALID_SHIFT)) & NETC_IERB_EBCR0_VALID_MASK) 1572 /*! @} */ 1573 1574 /*! @name EBCR1 - ENETC 0 binding configuration register 1 */ 1575 /*! @{ */ 1576 1577 #define NETC_IERB_EBCR1_NUM_RX_BDR_MASK (0x3FFU) 1578 #define NETC_IERB_EBCR1_NUM_RX_BDR_SHIFT (0U) 1579 #define NETC_IERB_EBCR1_NUM_RX_BDR_WIDTH (10U) 1580 #define NETC_IERB_EBCR1_NUM_RX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR1_NUM_RX_BDR_SHIFT)) & NETC_IERB_EBCR1_NUM_RX_BDR_MASK) 1581 1582 #define NETC_IERB_EBCR1_NUM_TX_BDR_MASK (0x3FF0000U) 1583 #define NETC_IERB_EBCR1_NUM_TX_BDR_SHIFT (16U) 1584 #define NETC_IERB_EBCR1_NUM_TX_BDR_WIDTH (10U) 1585 #define NETC_IERB_EBCR1_NUM_TX_BDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR1_NUM_TX_BDR_SHIFT)) & NETC_IERB_EBCR1_NUM_TX_BDR_MASK) 1586 /*! @} */ 1587 1588 /*! @name EBCR2 - ENETC 0 binding configuration register 2 */ 1589 /*! @{ */ 1590 1591 #define NETC_IERB_EBCR2_NUM_MAC_AFTE_MASK (0xFFFU) 1592 #define NETC_IERB_EBCR2_NUM_MAC_AFTE_SHIFT (0U) 1593 #define NETC_IERB_EBCR2_NUM_MAC_AFTE_WIDTH (12U) 1594 #define NETC_IERB_EBCR2_NUM_MAC_AFTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR2_NUM_MAC_AFTE_SHIFT)) & NETC_IERB_EBCR2_NUM_MAC_AFTE_MASK) 1595 1596 #define NETC_IERB_EBCR2_NUM_VLAN_FTE_MASK (0xFFF0000U) 1597 #define NETC_IERB_EBCR2_NUM_VLAN_FTE_SHIFT (16U) 1598 #define NETC_IERB_EBCR2_NUM_VLAN_FTE_WIDTH (12U) 1599 #define NETC_IERB_EBCR2_NUM_VLAN_FTE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCR2_NUM_VLAN_FTE_SHIFT)) & NETC_IERB_EBCR2_NUM_VLAN_FTE_MASK) 1600 /*! @} */ 1601 1602 /*! @name EVBCR - ENETC 0 VSI binding configuration register */ 1603 /*! @{ */ 1604 1605 #define NETC_IERB_EVBCR_NUM_VSI_MASK (0xFU) 1606 #define NETC_IERB_EVBCR_NUM_VSI_SHIFT (0U) 1607 #define NETC_IERB_EVBCR_NUM_VSI_WIDTH (4U) 1608 #define NETC_IERB_EVBCR_NUM_VSI(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EVBCR_NUM_VSI_SHIFT)) & NETC_IERB_EVBCR_NUM_VSI_MASK) 1609 /*! @} */ 1610 1611 /*! @name EMCR - ENETC 0 MSI-X configuration register */ 1612 /*! @{ */ 1613 1614 #define NETC_IERB_EMCR_NUM_MSIX_MASK (0x7FFU) 1615 #define NETC_IERB_EMCR_NUM_MSIX_SHIFT (0U) 1616 #define NETC_IERB_EMCR_NUM_MSIX_WIDTH (11U) 1617 #define NETC_IERB_EMCR_NUM_MSIX(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCR_NUM_MSIX_SHIFT)) & NETC_IERB_EMCR_NUM_MSIX_MASK) 1618 /*! @} */ 1619 1620 /*! @name E_CFH_DIDVID - ENETC 0 config header device ID and vendor ID register */ 1621 /*! @{ */ 1622 1623 #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID_MASK (0xFFFFU) 1624 #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID_SHIFT (0U) 1625 #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID_WIDTH (16U) 1626 #define NETC_IERB_E_CFH_DIDVID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_DIDVID_VENDOR_ID_SHIFT)) & NETC_IERB_E_CFH_DIDVID_VENDOR_ID_MASK) 1627 1628 #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID_MASK (0xFFFF0000U) 1629 #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID_SHIFT (16U) 1630 #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID_WIDTH (16U) 1631 #define NETC_IERB_E_CFH_DIDVID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_DIDVID_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFH_DIDVID_DEVICE_ID_MASK) 1632 /*! @} */ 1633 1634 /*! @name E_CFH_SIDSVID - ENETC 0 config header subsystem ID and subsystem vendor ID register */ 1635 /*! @{ */ 1636 1637 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) 1638 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) 1639 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_WIDTH (16U) 1640 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_SHIFT)) & NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_VENDOR_ID_MASK) 1641 1642 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK (0xFFFF0000U) 1643 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT (16U) 1644 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_WIDTH (16U) 1645 #define NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFH_SIDSVID_SUBSYSTEM_DEVICE_ID_MASK) 1646 /*! @} */ 1647 1648 /*! @name E_CFC_VFDID - ENETC 0 config capability VF device ID register */ 1649 /*! @{ */ 1650 1651 #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_MASK (0xFFFF0000U) 1652 #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_SHIFT (16U) 1653 #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_WIDTH (16U) 1654 #define NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_SHIFT)) & NETC_IERB_E_CFC_VFDID_VF_DEVICE_ID_MASK) 1655 /*! @} */ 1656 1657 /*! @name EBCAR - ENETC 0 buffer cache attribute register 0 */ 1658 /*! @{ */ 1659 1660 #define NETC_IERB_EBCAR_BD_WRCACHE_MASK (0xFU) 1661 #define NETC_IERB_EBCAR_BD_WRCACHE_SHIFT (0U) 1662 #define NETC_IERB_EBCAR_BD_WRCACHE_WIDTH (4U) 1663 #define NETC_IERB_EBCAR_BD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRCACHE_SHIFT)) & NETC_IERB_EBCAR_BD_WRCACHE_MASK) 1664 1665 #define NETC_IERB_EBCAR_BD_WRDOMAIN_MASK (0x30U) 1666 #define NETC_IERB_EBCAR_BD_WRDOMAIN_SHIFT (4U) 1667 #define NETC_IERB_EBCAR_BD_WRDOMAIN_WIDTH (2U) 1668 #define NETC_IERB_EBCAR_BD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRDOMAIN_SHIFT)) & NETC_IERB_EBCAR_BD_WRDOMAIN_MASK) 1669 1670 #define NETC_IERB_EBCAR_BD_WRSNP_MASK (0x40U) 1671 #define NETC_IERB_EBCAR_BD_WRSNP_SHIFT (6U) 1672 #define NETC_IERB_EBCAR_BD_WRSNP_WIDTH (1U) 1673 #define NETC_IERB_EBCAR_BD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_WRSNP_SHIFT)) & NETC_IERB_EBCAR_BD_WRSNP_MASK) 1674 1675 #define NETC_IERB_EBCAR_WRCACHE_MASK (0xF00U) 1676 #define NETC_IERB_EBCAR_WRCACHE_SHIFT (8U) 1677 #define NETC_IERB_EBCAR_WRCACHE_WIDTH (4U) 1678 #define NETC_IERB_EBCAR_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRCACHE_SHIFT)) & NETC_IERB_EBCAR_WRCACHE_MASK) 1679 1680 #define NETC_IERB_EBCAR_WRDOMAIN_MASK (0x3000U) 1681 #define NETC_IERB_EBCAR_WRDOMAIN_SHIFT (12U) 1682 #define NETC_IERB_EBCAR_WRDOMAIN_WIDTH (2U) 1683 #define NETC_IERB_EBCAR_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRDOMAIN_SHIFT)) & NETC_IERB_EBCAR_WRDOMAIN_MASK) 1684 1685 #define NETC_IERB_EBCAR_WRSNP_MASK (0x4000U) 1686 #define NETC_IERB_EBCAR_WRSNP_SHIFT (14U) 1687 #define NETC_IERB_EBCAR_WRSNP_WIDTH (1U) 1688 #define NETC_IERB_EBCAR_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_WRSNP_SHIFT)) & NETC_IERB_EBCAR_WRSNP_MASK) 1689 1690 #define NETC_IERB_EBCAR_BD_RDCACHE_MASK (0xF0000U) 1691 #define NETC_IERB_EBCAR_BD_RDCACHE_SHIFT (16U) 1692 #define NETC_IERB_EBCAR_BD_RDCACHE_WIDTH (4U) 1693 #define NETC_IERB_EBCAR_BD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDCACHE_SHIFT)) & NETC_IERB_EBCAR_BD_RDCACHE_MASK) 1694 1695 #define NETC_IERB_EBCAR_BD_RDDOMAIN_MASK (0x300000U) 1696 #define NETC_IERB_EBCAR_BD_RDDOMAIN_SHIFT (20U) 1697 #define NETC_IERB_EBCAR_BD_RDDOMAIN_WIDTH (2U) 1698 #define NETC_IERB_EBCAR_BD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDDOMAIN_SHIFT)) & NETC_IERB_EBCAR_BD_RDDOMAIN_MASK) 1699 1700 #define NETC_IERB_EBCAR_BD_RDSNP_MASK (0x400000U) 1701 #define NETC_IERB_EBCAR_BD_RDSNP_SHIFT (22U) 1702 #define NETC_IERB_EBCAR_BD_RDSNP_WIDTH (1U) 1703 #define NETC_IERB_EBCAR_BD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_BD_RDSNP_SHIFT)) & NETC_IERB_EBCAR_BD_RDSNP_MASK) 1704 1705 #define NETC_IERB_EBCAR_RDCACHE_MASK (0xF000000U) 1706 #define NETC_IERB_EBCAR_RDCACHE_SHIFT (24U) 1707 #define NETC_IERB_EBCAR_RDCACHE_WIDTH (4U) 1708 #define NETC_IERB_EBCAR_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDCACHE_SHIFT)) & NETC_IERB_EBCAR_RDCACHE_MASK) 1709 1710 #define NETC_IERB_EBCAR_RDDOMAIN_MASK (0x30000000U) 1711 #define NETC_IERB_EBCAR_RDDOMAIN_SHIFT (28U) 1712 #define NETC_IERB_EBCAR_RDDOMAIN_WIDTH (2U) 1713 #define NETC_IERB_EBCAR_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDDOMAIN_SHIFT)) & NETC_IERB_EBCAR_RDDOMAIN_MASK) 1714 1715 #define NETC_IERB_EBCAR_RDSNP_MASK (0x40000000U) 1716 #define NETC_IERB_EBCAR_RDSNP_SHIFT (30U) 1717 #define NETC_IERB_EBCAR_RDSNP_WIDTH (1U) 1718 #define NETC_IERB_EBCAR_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBCAR_RDSNP_SHIFT)) & NETC_IERB_EBCAR_RDSNP_MASK) 1719 /*! @} */ 1720 1721 /*! @name EMCAR - ENETC 0 message cache attribute register */ 1722 /*! @{ */ 1723 1724 #define NETC_IERB_EMCAR_MSG_WRCACHE_MASK (0xFU) 1725 #define NETC_IERB_EMCAR_MSG_WRCACHE_SHIFT (0U) 1726 #define NETC_IERB_EMCAR_MSG_WRCACHE_WIDTH (4U) 1727 #define NETC_IERB_EMCAR_MSG_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRCACHE_SHIFT)) & NETC_IERB_EMCAR_MSG_WRCACHE_MASK) 1728 1729 #define NETC_IERB_EMCAR_MSG_WRDOMAIN_MASK (0x30U) 1730 #define NETC_IERB_EMCAR_MSG_WRDOMAIN_SHIFT (4U) 1731 #define NETC_IERB_EMCAR_MSG_WRDOMAIN_WIDTH (2U) 1732 #define NETC_IERB_EMCAR_MSG_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRDOMAIN_SHIFT)) & NETC_IERB_EMCAR_MSG_WRDOMAIN_MASK) 1733 1734 #define NETC_IERB_EMCAR_MSG_WRSNP_MASK (0x40U) 1735 #define NETC_IERB_EMCAR_MSG_WRSNP_SHIFT (6U) 1736 #define NETC_IERB_EMCAR_MSG_WRSNP_WIDTH (1U) 1737 #define NETC_IERB_EMCAR_MSG_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_WRSNP_SHIFT)) & NETC_IERB_EMCAR_MSG_WRSNP_MASK) 1738 1739 #define NETC_IERB_EMCAR_MSG_RDCACHE_MASK (0xF0000U) 1740 #define NETC_IERB_EMCAR_MSG_RDCACHE_SHIFT (16U) 1741 #define NETC_IERB_EMCAR_MSG_RDCACHE_WIDTH (4U) 1742 #define NETC_IERB_EMCAR_MSG_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDCACHE_SHIFT)) & NETC_IERB_EMCAR_MSG_RDCACHE_MASK) 1743 1744 #define NETC_IERB_EMCAR_MSG_RDDOMAIN_MASK (0x300000U) 1745 #define NETC_IERB_EMCAR_MSG_RDDOMAIN_SHIFT (20U) 1746 #define NETC_IERB_EMCAR_MSG_RDDOMAIN_WIDTH (2U) 1747 #define NETC_IERB_EMCAR_MSG_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDDOMAIN_SHIFT)) & NETC_IERB_EMCAR_MSG_RDDOMAIN_MASK) 1748 1749 #define NETC_IERB_EMCAR_MSG_RDSNP_MASK (0x400000U) 1750 #define NETC_IERB_EMCAR_MSG_RDSNP_SHIFT (22U) 1751 #define NETC_IERB_EMCAR_MSG_RDSNP_WIDTH (1U) 1752 #define NETC_IERB_EMCAR_MSG_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EMCAR_MSG_RDSNP_SHIFT)) & NETC_IERB_EMCAR_MSG_RDSNP_MASK) 1753 /*! @} */ 1754 1755 /*! @name ECAR - ENETC 0 command cache attribute register */ 1756 /*! @{ */ 1757 1758 #define NETC_IERB_ECAR_CBD_WRCACHE_MASK (0xFU) 1759 #define NETC_IERB_ECAR_CBD_WRCACHE_SHIFT (0U) 1760 #define NETC_IERB_ECAR_CBD_WRCACHE_WIDTH (4U) 1761 #define NETC_IERB_ECAR_CBD_WRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRCACHE_SHIFT)) & NETC_IERB_ECAR_CBD_WRCACHE_MASK) 1762 1763 #define NETC_IERB_ECAR_CBD_WRDOMAIN_MASK (0x30U) 1764 #define NETC_IERB_ECAR_CBD_WRDOMAIN_SHIFT (4U) 1765 #define NETC_IERB_ECAR_CBD_WRDOMAIN_WIDTH (2U) 1766 #define NETC_IERB_ECAR_CBD_WRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRDOMAIN_SHIFT)) & NETC_IERB_ECAR_CBD_WRDOMAIN_MASK) 1767 1768 #define NETC_IERB_ECAR_CBD_WRSNP_MASK (0x40U) 1769 #define NETC_IERB_ECAR_CBD_WRSNP_SHIFT (6U) 1770 #define NETC_IERB_ECAR_CBD_WRSNP_WIDTH (1U) 1771 #define NETC_IERB_ECAR_CBD_WRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_WRSNP_SHIFT)) & NETC_IERB_ECAR_CBD_WRSNP_MASK) 1772 1773 #define NETC_IERB_ECAR_CWRCACHE_MASK (0xF00U) 1774 #define NETC_IERB_ECAR_CWRCACHE_SHIFT (8U) 1775 #define NETC_IERB_ECAR_CWRCACHE_WIDTH (4U) 1776 #define NETC_IERB_ECAR_CWRCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRCACHE_SHIFT)) & NETC_IERB_ECAR_CWRCACHE_MASK) 1777 1778 #define NETC_IERB_ECAR_CWRDOMAIN_MASK (0x3000U) 1779 #define NETC_IERB_ECAR_CWRDOMAIN_SHIFT (12U) 1780 #define NETC_IERB_ECAR_CWRDOMAIN_WIDTH (2U) 1781 #define NETC_IERB_ECAR_CWRDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRDOMAIN_SHIFT)) & NETC_IERB_ECAR_CWRDOMAIN_MASK) 1782 1783 #define NETC_IERB_ECAR_CWRSNP_MASK (0x4000U) 1784 #define NETC_IERB_ECAR_CWRSNP_SHIFT (14U) 1785 #define NETC_IERB_ECAR_CWRSNP_WIDTH (1U) 1786 #define NETC_IERB_ECAR_CWRSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CWRSNP_SHIFT)) & NETC_IERB_ECAR_CWRSNP_MASK) 1787 1788 #define NETC_IERB_ECAR_CBD_RDCACHE_MASK (0xF0000U) 1789 #define NETC_IERB_ECAR_CBD_RDCACHE_SHIFT (16U) 1790 #define NETC_IERB_ECAR_CBD_RDCACHE_WIDTH (4U) 1791 #define NETC_IERB_ECAR_CBD_RDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDCACHE_SHIFT)) & NETC_IERB_ECAR_CBD_RDCACHE_MASK) 1792 1793 #define NETC_IERB_ECAR_CBD_RDDOMAIN_MASK (0x300000U) 1794 #define NETC_IERB_ECAR_CBD_RDDOMAIN_SHIFT (20U) 1795 #define NETC_IERB_ECAR_CBD_RDDOMAIN_WIDTH (2U) 1796 #define NETC_IERB_ECAR_CBD_RDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDDOMAIN_SHIFT)) & NETC_IERB_ECAR_CBD_RDDOMAIN_MASK) 1797 1798 #define NETC_IERB_ECAR_CBD_RDSNP_MASK (0x400000U) 1799 #define NETC_IERB_ECAR_CBD_RDSNP_SHIFT (22U) 1800 #define NETC_IERB_ECAR_CBD_RDSNP_WIDTH (1U) 1801 #define NETC_IERB_ECAR_CBD_RDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CBD_RDSNP_SHIFT)) & NETC_IERB_ECAR_CBD_RDSNP_MASK) 1802 1803 #define NETC_IERB_ECAR_CRDCACHE_MASK (0xF000000U) 1804 #define NETC_IERB_ECAR_CRDCACHE_SHIFT (24U) 1805 #define NETC_IERB_ECAR_CRDCACHE_WIDTH (4U) 1806 #define NETC_IERB_ECAR_CRDCACHE(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDCACHE_SHIFT)) & NETC_IERB_ECAR_CRDCACHE_MASK) 1807 1808 #define NETC_IERB_ECAR_CRDDOMAIN_MASK (0x30000000U) 1809 #define NETC_IERB_ECAR_CRDDOMAIN_SHIFT (28U) 1810 #define NETC_IERB_ECAR_CRDDOMAIN_WIDTH (2U) 1811 #define NETC_IERB_ECAR_CRDDOMAIN(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDDOMAIN_SHIFT)) & NETC_IERB_ECAR_CRDDOMAIN_MASK) 1812 1813 #define NETC_IERB_ECAR_CRDSNP_MASK (0x40000000U) 1814 #define NETC_IERB_ECAR_CRDSNP_SHIFT (30U) 1815 #define NETC_IERB_ECAR_CRDSNP_WIDTH (1U) 1816 #define NETC_IERB_ECAR_CRDSNP(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ECAR_CRDSNP_SHIFT)) & NETC_IERB_ECAR_CRDSNP_MASK) 1817 /*! @} */ 1818 1819 /*! @name EAMQR - ENETC 0 access management qualifier register */ 1820 /*! @{ */ 1821 1822 #define NETC_IERB_EAMQR_ARQOS_MASK (0xF0000U) 1823 #define NETC_IERB_EAMQR_ARQOS_SHIFT (16U) 1824 #define NETC_IERB_EAMQR_ARQOS_WIDTH (4U) 1825 #define NETC_IERB_EAMQR_ARQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EAMQR_ARQOS_SHIFT)) & NETC_IERB_EAMQR_ARQOS_MASK) 1826 1827 #define NETC_IERB_EAMQR_AWQOS_MASK (0xF00000U) 1828 #define NETC_IERB_EAMQR_AWQOS_SHIFT (20U) 1829 #define NETC_IERB_EAMQR_AWQOS_WIDTH (4U) 1830 #define NETC_IERB_EAMQR_AWQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EAMQR_AWQOS_SHIFT)) & NETC_IERB_EAMQR_AWQOS_MASK) 1831 1832 #define NETC_IERB_EAMQR_BMT_MASK (0x80000000U) 1833 #define NETC_IERB_EAMQR_BMT_SHIFT (31U) 1834 #define NETC_IERB_EAMQR_BMT_WIDTH (1U) 1835 #define NETC_IERB_EAMQR_BMT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EAMQR_BMT_SHIFT)) & NETC_IERB_EAMQR_BMT_MASK) 1836 /*! @} */ 1837 1838 /*! @name EBLPR - ENETC 0 boot loader parameter register 0..ENETC 0 boot loader parameter register 1 */ 1839 /*! @{ */ 1840 1841 #define NETC_IERB_EBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) 1842 #define NETC_IERB_EBLPR_PARAM_VAL_SHIFT (0U) 1843 #define NETC_IERB_EBLPR_PARAM_VAL_WIDTH (32U) 1844 #define NETC_IERB_EBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_EBLPR_PARAM_VAL_MASK) 1845 /*! @} */ 1846 1847 /*! @name ERXMBER - ENETC 0 receive memory buffer entitlement register */ 1848 /*! @{ */ 1849 1850 #define NETC_IERB_ERXMBER_AMOUNT_MASK (0xFFFFFFU) 1851 #define NETC_IERB_ERXMBER_AMOUNT_SHIFT (0U) 1852 #define NETC_IERB_ERXMBER_AMOUNT_WIDTH (24U) 1853 #define NETC_IERB_ERXMBER_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERXMBER_AMOUNT_SHIFT)) & NETC_IERB_ERXMBER_AMOUNT_MASK) 1854 /*! @} */ 1855 1856 /*! @name ERXMBLR - ENETC 0 receive memory buffer limit register */ 1857 /*! @{ */ 1858 1859 #define NETC_IERB_ERXMBLR_LIMIT_MASK (0xFFFFFFU) 1860 #define NETC_IERB_ERXMBLR_LIMIT_SHIFT (0U) 1861 #define NETC_IERB_ERXMBLR_LIMIT_WIDTH (24U) 1862 #define NETC_IERB_ERXMBLR_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERXMBLR_LIMIT_SHIFT)) & NETC_IERB_ERXMBLR_LIMIT_MASK) 1863 /*! @} */ 1864 1865 /*! @name ETXHPTBCR - ENETC 0 transmit high priority tier byte credit register */ 1866 /*! @{ */ 1867 1868 #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT_MASK (0xFFFFU) 1869 #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT_SHIFT (0U) 1870 #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT_WIDTH (16U) 1871 #define NETC_IERB_ETXHPTBCR_BYTE_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETXHPTBCR_BYTE_CREDIT_SHIFT)) & NETC_IERB_ETXHPTBCR_BYTE_CREDIT_MASK) 1872 /*! @} */ 1873 1874 /*! @name ETXLPTBCR - ENETC 0 transmit low priority tier byte credit register */ 1875 /*! @{ */ 1876 1877 #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT_MASK (0xFFFFU) 1878 #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT_SHIFT (0U) 1879 #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT_WIDTH (16U) 1880 #define NETC_IERB_ETXLPTBCR_BYTE_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETXLPTBCR_BYTE_CREDIT_SHIFT)) & NETC_IERB_ETXLPTBCR_BYTE_CREDIT_MASK) 1881 /*! @} */ 1882 1883 /*! @name EHTMAR - ENETC 0 hash table memory allotment register */ 1884 /*! @{ */ 1885 1886 #define NETC_IERB_EHTMAR_NUM_WORDS_MASK (0xFFFFU) 1887 #define NETC_IERB_EHTMAR_NUM_WORDS_SHIFT (0U) 1888 #define NETC_IERB_EHTMAR_NUM_WORDS_WIDTH (16U) 1889 #define NETC_IERB_EHTMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EHTMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EHTMAR_NUM_WORDS_MASK) 1890 1891 #define NETC_IERB_EHTMAR_MLOC_MASK (0xC0000000U) 1892 #define NETC_IERB_EHTMAR_MLOC_SHIFT (30U) 1893 #define NETC_IERB_EHTMAR_MLOC_WIDTH (2U) 1894 #define NETC_IERB_EHTMAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EHTMAR_MLOC_SHIFT)) & NETC_IERB_EHTMAR_MLOC_MASK) 1895 /*! @} */ 1896 1897 /*! @name EITMAR - ENETC 0 index table memory allocation register */ 1898 /*! @{ */ 1899 1900 #define NETC_IERB_EITMAR_NUM_WORDS_MASK (0xFFFFU) 1901 #define NETC_IERB_EITMAR_NUM_WORDS_SHIFT (0U) 1902 #define NETC_IERB_EITMAR_NUM_WORDS_WIDTH (16U) 1903 #define NETC_IERB_EITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EITMAR_NUM_WORDS_MASK) 1904 1905 #define NETC_IERB_EITMAR_MLOC_MASK (0xC0000000U) 1906 #define NETC_IERB_EITMAR_MLOC_SHIFT (30U) 1907 #define NETC_IERB_EITMAR_MLOC_WIDTH (2U) 1908 #define NETC_IERB_EITMAR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EITMAR_MLOC_SHIFT)) & NETC_IERB_EITMAR_MLOC_MASK) 1909 /*! @} */ 1910 1911 /*! @name EIPFTMAR - ENETC 0 ingress port filter table memory allocation register */ 1912 /*! @{ */ 1913 1914 #define NETC_IERB_EIPFTMAR_ALLOC_MASK (0xFFFFU) 1915 #define NETC_IERB_EIPFTMAR_ALLOC_SHIFT (0U) 1916 #define NETC_IERB_EIPFTMAR_ALLOC_WIDTH (16U) 1917 #define NETC_IERB_EIPFTMAR_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EIPFTMAR_ALLOC_SHIFT)) & NETC_IERB_EIPFTMAR_ALLOC_MASK) 1918 /*! @} */ 1919 1920 /*! @name ERTMAR - ENETC 0 RFS ternary memory allocation register */ 1921 /*! @{ */ 1922 1923 #define NETC_IERB_ERTMAR_ALLOC_MASK (0xFFFFU) 1924 #define NETC_IERB_ERTMAR_ALLOC_SHIFT (0U) 1925 #define NETC_IERB_ERTMAR_ALLOC_WIDTH (16U) 1926 #define NETC_IERB_ERTMAR_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERTMAR_ALLOC_SHIFT)) & NETC_IERB_ERTMAR_ALLOC_MASK) 1927 /*! @} */ 1928 1929 /*! @name ERPITMAR - ENETC 0 rate policer index table memory allocation register */ 1930 /*! @{ */ 1931 1932 #define NETC_IERB_ERPITMAR_NUM_WORDS_MASK (0xFFFFU) 1933 #define NETC_IERB_ERPITMAR_NUM_WORDS_SHIFT (0U) 1934 #define NETC_IERB_ERPITMAR_NUM_WORDS_WIDTH (16U) 1935 #define NETC_IERB_ERPITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ERPITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ERPITMAR_NUM_WORDS_MASK) 1936 /*! @} */ 1937 1938 /*! @name EISCITMAR - ENETC 0 ingress stream counter index table memory allocation register */ 1939 /*! @{ */ 1940 1941 #define NETC_IERB_EISCITMAR_NUM_WORDS_MASK (0xFFFFU) 1942 #define NETC_IERB_EISCITMAR_NUM_WORDS_SHIFT (0U) 1943 #define NETC_IERB_EISCITMAR_NUM_WORDS_WIDTH (16U) 1944 #define NETC_IERB_EISCITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EISCITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EISCITMAR_NUM_WORDS_MASK) 1945 /*! @} */ 1946 1947 /*! @name EISITMAR - ENETC 0 ingress stream index table memory allocation register */ 1948 /*! @{ */ 1949 1950 #define NETC_IERB_EISITMAR_NUM_WORDS_MASK (0xFFFFU) 1951 #define NETC_IERB_EISITMAR_NUM_WORDS_SHIFT (0U) 1952 #define NETC_IERB_EISITMAR_NUM_WORDS_WIDTH (16U) 1953 #define NETC_IERB_EISITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_EISITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_EISITMAR_NUM_WORDS_MASK) 1954 /*! @} */ 1955 1956 /*! @name ESGIITMAR - ENETC 0 stream gate instance index table memory allocation register */ 1957 /*! @{ */ 1958 1959 #define NETC_IERB_ESGIITMAR_NUM_WORDS_MASK (0xFFFFU) 1960 #define NETC_IERB_ESGIITMAR_NUM_WORDS_SHIFT (0U) 1961 #define NETC_IERB_ESGIITMAR_NUM_WORDS_WIDTH (16U) 1962 #define NETC_IERB_ESGIITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ESGIITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ESGIITMAR_NUM_WORDS_MASK) 1963 /*! @} */ 1964 1965 /*! @name ESGCLITMAR - ENETC 0 stream gate control list index table memory allocation register */ 1966 /*! @{ */ 1967 1968 #define NETC_IERB_ESGCLITMAR_NUM_WORDS_MASK (0xFFFFU) 1969 #define NETC_IERB_ESGCLITMAR_NUM_WORDS_SHIFT (0U) 1970 #define NETC_IERB_ESGCLITMAR_NUM_WORDS_WIDTH (16U) 1971 #define NETC_IERB_ESGCLITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ESGCLITMAR_NUM_WORDS_SHIFT)) & NETC_IERB_ESGCLITMAR_NUM_WORDS_MASK) 1972 /*! @} */ 1973 1974 /*! @name ETGSTAR - ENETC 0 time gate scheduling table allocation register */ 1975 /*! @{ */ 1976 1977 #define NETC_IERB_ETGSTAR_NUM_WORDS_MASK (0xFFFU) 1978 #define NETC_IERB_ETGSTAR_NUM_WORDS_SHIFT (0U) 1979 #define NETC_IERB_ETGSTAR_NUM_WORDS_WIDTH (12U) 1980 #define NETC_IERB_ETGSTAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSTAR_NUM_WORDS_SHIFT)) & NETC_IERB_ETGSTAR_NUM_WORDS_MASK) 1981 /*! @} */ 1982 1983 /*! @name ETGSLR - ENETC 0 time gate scheduling lookahead register */ 1984 /*! @{ */ 1985 1986 #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD_MASK (0xFFFFFU) 1987 #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD_SHIFT (0U) 1988 #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD_WIDTH (20U) 1989 #define NETC_IERB_ETGSLR_MIN_LOOKAHEAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSLR_MIN_LOOKAHEAD_SHIFT)) & NETC_IERB_ETGSLR_MIN_LOOKAHEAD_MASK) 1990 1991 #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_MASK (0x80000000U) 1992 #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_SHIFT (31U) 1993 #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_WIDTH (1U) 1994 #define NETC_IERB_ETGSLR_ZERO_LOOKAHEAD(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_SHIFT)) & NETC_IERB_ETGSLR_ZERO_LOOKAHEAD_MASK) 1995 /*! @} */ 1996 1997 /*! @name VAMQR - VSI 0 access management qualifier register..VSI 6 access management qualifier register */ 1998 /*! @{ */ 1999 2000 #define NETC_IERB_VAMQR_ARQOS_MASK (0xF0000U) 2001 #define NETC_IERB_VAMQR_ARQOS_SHIFT (16U) 2002 #define NETC_IERB_VAMQR_ARQOS_WIDTH (4U) 2003 #define NETC_IERB_VAMQR_ARQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VAMQR_ARQOS_SHIFT)) & NETC_IERB_VAMQR_ARQOS_MASK) 2004 2005 #define NETC_IERB_VAMQR_AWQOS_MASK (0xF00000U) 2006 #define NETC_IERB_VAMQR_AWQOS_SHIFT (20U) 2007 #define NETC_IERB_VAMQR_AWQOS_WIDTH (4U) 2008 #define NETC_IERB_VAMQR_AWQOS(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VAMQR_AWQOS_SHIFT)) & NETC_IERB_VAMQR_AWQOS_MASK) 2009 2010 #define NETC_IERB_VAMQR_BMT_MASK (0x80000000U) 2011 #define NETC_IERB_VAMQR_BMT_SHIFT (31U) 2012 #define NETC_IERB_VAMQR_BMT_WIDTH (1U) 2013 #define NETC_IERB_VAMQR_BMT(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VAMQR_BMT_SHIFT)) & NETC_IERB_VAMQR_BMT_MASK) 2014 /*! @} */ 2015 2016 /*! @name VBLPR - VSI 0 boot loader parameter register 0..VSI 6 boot loader parameter register 1 */ 2017 /*! @{ */ 2018 2019 #define NETC_IERB_VBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) 2020 #define NETC_IERB_VBLPR_PARAM_VAL_SHIFT (0U) 2021 #define NETC_IERB_VBLPR_PARAM_VAL_WIDTH (32U) 2022 #define NETC_IERB_VBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VBLPR_PARAM_VAL_SHIFT)) & NETC_IERB_VBLPR_PARAM_VAL_MASK) 2023 /*! @} */ 2024 2025 /*! @name VPMAR0 - VSI 0 primary MAC address register 0..VSI 6 primary MAC address register 0 */ 2026 /*! @{ */ 2027 2028 #define NETC_IERB_VPMAR0_MAC_ADDR_MASK (0xFFFFFFFFU) 2029 #define NETC_IERB_VPMAR0_MAC_ADDR_SHIFT (0U) 2030 #define NETC_IERB_VPMAR0_MAC_ADDR_WIDTH (32U) 2031 #define NETC_IERB_VPMAR0_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VPMAR0_MAC_ADDR_SHIFT)) & NETC_IERB_VPMAR0_MAC_ADDR_MASK) 2032 /*! @} */ 2033 2034 /*! @name VPMAR1 - VSI 0 primary MAC address register 1..VSI 6 primary MAC address register 1 */ 2035 /*! @{ */ 2036 2037 #define NETC_IERB_VPMAR1_MAC_ADDR_MASK (0xFFFFU) 2038 #define NETC_IERB_VPMAR1_MAC_ADDR_SHIFT (0U) 2039 #define NETC_IERB_VPMAR1_MAC_ADDR_WIDTH (16U) 2040 #define NETC_IERB_VPMAR1_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_IERB_VPMAR1_MAC_ADDR_SHIFT)) & NETC_IERB_VPMAR1_MAC_ADDR_MASK) 2041 /*! @} */ 2042 2043 /*! 2044 * @} 2045 */ /* end of group NETC_IERB_Register_Masks */ 2046 2047 /*! 2048 * @} 2049 */ /* end of group NETC_IERB_Peripheral_Access_Layer */ 2050 2051 #endif /* #if !defined(S32Z2_NETC_IERB_H_) */ 2052
