1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2023 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_NETC_F3_GLOBAL.h
10  * @version 2.1
11  * @date 2023-07-20
12  * @brief Peripheral Access Layer for S32Z2_NETC_F3_GLOBAL
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_NETC_F3_GLOBAL_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_NETC_F3_GLOBAL_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- NETC_F3_GLOBAL Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup NETC_F3_GLOBAL_Peripheral_Access_Layer NETC_F3_GLOBAL Peripheral Access Layer
68  * @{
69  */
70 
71 /** NETC_F3_GLOBAL - Size of Registers Arrays */
72 #define NETC_F3_GLOBAL_PCE_SL_COUNT               1u
73 #define NETC_F3_GLOBAL_HTA_LOOP_COUNT             1u
74 #define NETC_F3_GLOBAL_ARRAY_NUM_RC_COUNT         1u
75 #define NETC_F3_GLOBAL_G_BOOT_COUNT               2u
76 
77 /** NETC_F3_GLOBAL - Register Layout Typedef */
78 typedef struct {
79   __I  uint32_t SMCAPR;                            /**< Shared memory capability register, offset: 0x0 */
80   __I  uint32_t SMDTR;                             /**< Shared memory depletion threshold register, offset: 0x4 */
81   __I  uint32_t SMACR;                             /**< Shared memory available count register, offset: 0x8 */
82   uint8_t RESERVED_0[4];
83   __I  uint32_t SMCLWMR;                           /**< Shared memory count low watermark register, offset: 0x10 */
84   __I  uint32_t SMBUCR;                            /**< Shared memory buffer unassigned count register, offset: 0x14 */
85   __I  uint32_t SMBUCHWMR;                         /**< Shared memory buffer unassigned count high watermark register, offset: 0x18 */
86   __I  uint32_t SMLCR;                             /**< Shared memory loss count register, offset: 0x1C */
87   __I  uint32_t HBTCAPR;                           /**< Hash bucket table capability register, offset: 0x20 */
88   __I  uint32_t HBTOR0;                            /**< Hash bucket table operational register 0, offset: 0x24 */
89   uint8_t RESERVED_1[4];
90   __I  uint32_t HBTOR2;                            /**< Hash bucket table operational register 2, offset: 0x2C */
91   uint8_t RESERVED_2[16];
92   __I  uint32_t SMERBCAPR;                         /**< Shared memory ENETC receive buffer capability register, offset: 0x40 */
93   __I  uint32_t SMERBOR0;                          /**< Shared memory ENETC receive buffer operational register 0, offset: 0x44 */
94   __I  uint32_t SMERBOR1;                          /**< Shared memory ENETC receive buffer operational 1, offset: 0x48 */
95   uint8_t RESERVED_3[180];
96   struct {                                         /* offset: 0x100, array step: 0x8 */
97     __I  uint32_t PCEOR;                             /**< PCE 0 operational register, array offset: 0x100, array step: 0x8 */
98     __I  uint32_t RFEOR;                             /**< Replication Forwarding Engine 0 operational register, array offset: 0x104, array step: 0x8 */
99   } PCE_SL[NETC_F3_GLOBAL_PCE_SL_COUNT];
100   uint8_t RESERVED_4[92];
101   __I  uint32_t NETCCLKR;                          /**< NETC clock register, offset: 0x164 */
102   uint8_t RESERVED_5[152];
103   struct {                                         /* offset: 0x200, array step: 0x28 */
104     __I  uint32_t HTACAPR;                           /**< HTA 0 capability register, array offset: 0x200, array step: 0x28 */
105     __I  uint32_t HTARFCOR;                          /**< HTA 0 receive frame count operational register, array offset: 0x204, array step: 0x28 */
106     __I  uint32_t HTAHPBCOR;                         /**< HTA 0 high priority byte count operational register, array offset: 0x208, array step: 0x28 */
107     __I  uint32_t HTALPBCOR;                         /**< HTA 0 low priority byte count operational register, array offset: 0x20C, array step: 0x28 */
108     uint8_t RESERVED_0[20];
109     __I  uint32_t HTATFCOR;                          /**< HTA 0 transmit frame count operational register, array offset: 0x224, array step: 0x28 */
110   } HTA_LOOP[NETC_F3_GLOBAL_HTA_LOOP_COUNT];
111   uint8_t RESERVED_6[216];
112   struct {                                         /* offset: 0x300, array step: 0x10 */
113     __IO uint32_t RCSBRLAR;                          /**< Root complex 0 system bus read latency average register, array offset: 0x300, array step: 0x10 */
114     __I  uint32_t RCSBRLHWMR;                        /**< Root complex 0 system bus read latency high watermark register, array offset: 0x304, array step: 0x10 */
115     __IO uint32_t RCSBWLAR;                          /**< Root complex 0 system bus write latency average register, array offset: 0x308, array step: 0x10 */
116     __I  uint32_t RCSBWLHWMR;                        /**< Root complex 0 system bus write latency high watermark register, array offset: 0x30C, array step: 0x10 */
117   } ARRAY_NUM_RC[NETC_F3_GLOBAL_ARRAY_NUM_RC_COUNT];
118   uint8_t RESERVED_7[2280];
119   __I  uint32_t IPBRR0;                            /**< IP block revision register 0, offset: 0xBF8 */
120   __I  uint32_t IPBRR1;                            /**< IP block revision register 1, offset: 0xBFC */
121   uint8_t RESERVED_8[256];
122   __I  uint32_t FBLPR[NETC_F3_GLOBAL_G_BOOT_COUNT]; /**< Function boot loader parameter register 0..Function boot loader parameter register 1, array offset: 0xD00, array step: 0x4 */
123 } NETC_F3_GLOBAL_Type, *NETC_F3_GLOBAL_MemMapPtr;
124 
125 /** Number of instances of the NETC_F3_GLOBAL module. */
126 #define NETC_F3_GLOBAL_INSTANCE_COUNT            (1u)
127 
128 /* NETC_F3_GLOBAL - Peripheral instance base addresses */
129 /** Peripheral NETC__ENETC0_GLOBAL base address */
130 #define IP_NETC__ENETC0_GLOBAL_BASE              (0x74B20000u)
131 /** Peripheral NETC__ENETC0_GLOBAL base pointer */
132 #define IP_NETC__ENETC0_GLOBAL                   ((NETC_F3_GLOBAL_Type *)IP_NETC__ENETC0_GLOBAL_BASE)
133 /** Array initializer of NETC_F3_GLOBAL peripheral base addresses */
134 #define IP_NETC_F3_GLOBAL_BASE_ADDRS             { IP_NETC__ENETC0_GLOBAL_BASE }
135 /** Array initializer of NETC_F3_GLOBAL peripheral base pointers */
136 #define IP_NETC_F3_GLOBAL_BASE_PTRS              { IP_NETC__ENETC0_GLOBAL }
137 
138 /* ----------------------------------------------------------------------------
139    -- NETC_F3_GLOBAL Register Masks
140    ---------------------------------------------------------------------------- */
141 
142 /*!
143  * @addtogroup NETC_F3_GLOBAL_Register_Masks NETC_F3_GLOBAL Register Masks
144  * @{
145  */
146 
147 /*! @name SMCAPR - Shared memory capability register */
148 /*! @{ */
149 
150 #define NETC_F3_GLOBAL_SMCAPR_NUM_WORDS_MASK     (0xFFFFFFU)
151 #define NETC_F3_GLOBAL_SMCAPR_NUM_WORDS_SHIFT    (0U)
152 #define NETC_F3_GLOBAL_SMCAPR_NUM_WORDS_WIDTH    (24U)
153 #define NETC_F3_GLOBAL_SMCAPR_NUM_WORDS(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMCAPR_NUM_WORDS_SHIFT)) & NETC_F3_GLOBAL_SMCAPR_NUM_WORDS_MASK)
154 /*! @} */
155 
156 /*! @name SMDTR - Shared memory depletion threshold register */
157 /*! @{ */
158 
159 #define NETC_F3_GLOBAL_SMDTR_THRESH_MASK         (0xFFFFFFU)
160 #define NETC_F3_GLOBAL_SMDTR_THRESH_SHIFT        (0U)
161 #define NETC_F3_GLOBAL_SMDTR_THRESH_WIDTH        (24U)
162 #define NETC_F3_GLOBAL_SMDTR_THRESH(x)           (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMDTR_THRESH_SHIFT)) & NETC_F3_GLOBAL_SMDTR_THRESH_MASK)
163 /*! @} */
164 
165 /*! @name SMACR - Shared memory available count register */
166 /*! @{ */
167 
168 #define NETC_F3_GLOBAL_SMACR_COUNT_MASK          (0xFFFFFFU)
169 #define NETC_F3_GLOBAL_SMACR_COUNT_SHIFT         (0U)
170 #define NETC_F3_GLOBAL_SMACR_COUNT_WIDTH         (24U)
171 #define NETC_F3_GLOBAL_SMACR_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMACR_COUNT_SHIFT)) & NETC_F3_GLOBAL_SMACR_COUNT_MASK)
172 /*! @} */
173 
174 /*! @name SMCLWMR - Shared memory count low watermark register */
175 /*! @{ */
176 
177 #define NETC_F3_GLOBAL_SMCLWMR_WATERMARK_MASK    (0xFFFFFFU)
178 #define NETC_F3_GLOBAL_SMCLWMR_WATERMARK_SHIFT   (0U)
179 #define NETC_F3_GLOBAL_SMCLWMR_WATERMARK_WIDTH   (24U)
180 #define NETC_F3_GLOBAL_SMCLWMR_WATERMARK(x)      (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMCLWMR_WATERMARK_SHIFT)) & NETC_F3_GLOBAL_SMCLWMR_WATERMARK_MASK)
181 /*! @} */
182 
183 /*! @name SMBUCR - Shared memory buffer unassigned count register */
184 /*! @{ */
185 
186 #define NETC_F3_GLOBAL_SMBUCR_COUNT_MASK         (0xFFFFFFU)
187 #define NETC_F3_GLOBAL_SMBUCR_COUNT_SHIFT        (0U)
188 #define NETC_F3_GLOBAL_SMBUCR_COUNT_WIDTH        (24U)
189 #define NETC_F3_GLOBAL_SMBUCR_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMBUCR_COUNT_SHIFT)) & NETC_F3_GLOBAL_SMBUCR_COUNT_MASK)
190 /*! @} */
191 
192 /*! @name SMBUCHWMR - Shared memory buffer unassigned count high watermark register */
193 /*! @{ */
194 
195 #define NETC_F3_GLOBAL_SMBUCHWMR_WATERMARK_MASK  (0xFFFFFFU)
196 #define NETC_F3_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT (0U)
197 #define NETC_F3_GLOBAL_SMBUCHWMR_WATERMARK_WIDTH (24U)
198 #define NETC_F3_GLOBAL_SMBUCHWMR_WATERMARK(x)    (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT)) & NETC_F3_GLOBAL_SMBUCHWMR_WATERMARK_MASK)
199 /*! @} */
200 
201 /*! @name SMLCR - Shared memory loss count register */
202 /*! @{ */
203 
204 #define NETC_F3_GLOBAL_SMLCR_COUNT_MASK          (0xFFFFFFU)
205 #define NETC_F3_GLOBAL_SMLCR_COUNT_SHIFT         (0U)
206 #define NETC_F3_GLOBAL_SMLCR_COUNT_WIDTH         (24U)
207 #define NETC_F3_GLOBAL_SMLCR_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMLCR_COUNT_SHIFT)) & NETC_F3_GLOBAL_SMLCR_COUNT_MASK)
208 
209 #define NETC_F3_GLOBAL_SMLCR_IFLC_MASK           (0x40000000U)
210 #define NETC_F3_GLOBAL_SMLCR_IFLC_SHIFT          (30U)
211 #define NETC_F3_GLOBAL_SMLCR_IFLC_WIDTH          (1U)
212 #define NETC_F3_GLOBAL_SMLCR_IFLC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMLCR_IFLC_SHIFT)) & NETC_F3_GLOBAL_SMLCR_IFLC_MASK)
213 
214 #define NETC_F3_GLOBAL_SMLCR_IFDC_MASK           (0x80000000U)
215 #define NETC_F3_GLOBAL_SMLCR_IFDC_SHIFT          (31U)
216 #define NETC_F3_GLOBAL_SMLCR_IFDC_WIDTH          (1U)
217 #define NETC_F3_GLOBAL_SMLCR_IFDC(x)             (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMLCR_IFDC_SHIFT)) & NETC_F3_GLOBAL_SMLCR_IFDC_MASK)
218 /*! @} */
219 
220 /*! @name HBTCAPR - Hash bucket table capability register */
221 /*! @{ */
222 
223 #define NETC_F3_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK  (0xFFFFU)
224 #define NETC_F3_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT (0U)
225 #define NETC_F3_GLOBAL_HBTCAPR_NUM_ENTRIES_WIDTH (16U)
226 #define NETC_F3_GLOBAL_HBTCAPR_NUM_ENTRIES(x)    (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT)) & NETC_F3_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK)
227 
228 #define NETC_F3_GLOBAL_HBTCAPR_MAX_COL_MASK      (0x7000000U)
229 #define NETC_F3_GLOBAL_HBTCAPR_MAX_COL_SHIFT     (24U)
230 #define NETC_F3_GLOBAL_HBTCAPR_MAX_COL_WIDTH     (3U)
231 #define NETC_F3_GLOBAL_HBTCAPR_MAX_COL(x)        (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HBTCAPR_MAX_COL_SHIFT)) & NETC_F3_GLOBAL_HBTCAPR_MAX_COL_MASK)
232 
233 #define NETC_F3_GLOBAL_HBTCAPR_MAX_VISITS_MASK   (0xF0000000U)
234 #define NETC_F3_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT  (28U)
235 #define NETC_F3_GLOBAL_HBTCAPR_MAX_VISITS_WIDTH  (4U)
236 #define NETC_F3_GLOBAL_HBTCAPR_MAX_VISITS(x)     (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT)) & NETC_F3_GLOBAL_HBTCAPR_MAX_VISITS_MASK)
237 /*! @} */
238 
239 /*! @name HBTOR0 - Hash bucket table operational register 0 */
240 /*! @{ */
241 
242 #define NETC_F3_GLOBAL_HBTOR0_NUM_ENTRIES_MASK   (0xFFFFU)
243 #define NETC_F3_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT  (0U)
244 #define NETC_F3_GLOBAL_HBTOR0_NUM_ENTRIES_WIDTH  (16U)
245 #define NETC_F3_GLOBAL_HBTOR0_NUM_ENTRIES(x)     (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT)) & NETC_F3_GLOBAL_HBTOR0_NUM_ENTRIES_MASK)
246 
247 #define NETC_F3_GLOBAL_HBTOR0_HWM_ENTRIES_MASK   (0xFFFF0000U)
248 #define NETC_F3_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT  (16U)
249 #define NETC_F3_GLOBAL_HBTOR0_HWM_ENTRIES_WIDTH  (16U)
250 #define NETC_F3_GLOBAL_HBTOR0_HWM_ENTRIES(x)     (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT)) & NETC_F3_GLOBAL_HBTOR0_HWM_ENTRIES_MASK)
251 /*! @} */
252 
253 /*! @name HBTOR2 - Hash bucket table operational register 2 */
254 /*! @{ */
255 
256 #define NETC_F3_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK (0xFFU)
257 #define NETC_F3_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT (0U)
258 #define NETC_F3_GLOBAL_HBTOR2_RUN_AVG_FRACT_WIDTH (8U)
259 #define NETC_F3_GLOBAL_HBTOR2_RUN_AVG_FRACT(x)   (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT)) & NETC_F3_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK)
260 
261 #define NETC_F3_GLOBAL_HBTOR2_RUN_AVG_INT_MASK   (0xFF00U)
262 #define NETC_F3_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT  (8U)
263 #define NETC_F3_GLOBAL_HBTOR2_RUN_AVG_INT_WIDTH  (8U)
264 #define NETC_F3_GLOBAL_HBTOR2_RUN_AVG_INT(x)     (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT)) & NETC_F3_GLOBAL_HBTOR2_RUN_AVG_INT_MASK)
265 
266 #define NETC_F3_GLOBAL_HBTOR2_HWM_COL_MASK       (0xF0000U)
267 #define NETC_F3_GLOBAL_HBTOR2_HWM_COL_SHIFT      (16U)
268 #define NETC_F3_GLOBAL_HBTOR2_HWM_COL_WIDTH      (4U)
269 #define NETC_F3_GLOBAL_HBTOR2_HWM_COL(x)         (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HBTOR2_HWM_COL_SHIFT)) & NETC_F3_GLOBAL_HBTOR2_HWM_COL_MASK)
270 /*! @} */
271 
272 /*! @name SMERBCAPR - Shared memory ENETC receive buffer capability register */
273 /*! @{ */
274 
275 #define NETC_F3_GLOBAL_SMERBCAPR_THRESH_MASK     (0xFFFFFFU)
276 #define NETC_F3_GLOBAL_SMERBCAPR_THRESH_SHIFT    (0U)
277 #define NETC_F3_GLOBAL_SMERBCAPR_THRESH_WIDTH    (24U)
278 #define NETC_F3_GLOBAL_SMERBCAPR_THRESH(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMERBCAPR_THRESH_SHIFT)) & NETC_F3_GLOBAL_SMERBCAPR_THRESH_MASK)
279 
280 #define NETC_F3_GLOBAL_SMERBCAPR_WORD_SIZE_MASK  (0x30000000U)
281 #define NETC_F3_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT (28U)
282 #define NETC_F3_GLOBAL_SMERBCAPR_WORD_SIZE_WIDTH (2U)
283 #define NETC_F3_GLOBAL_SMERBCAPR_WORD_SIZE(x)    (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT)) & NETC_F3_GLOBAL_SMERBCAPR_WORD_SIZE_MASK)
284 
285 #define NETC_F3_GLOBAL_SMERBCAPR_MLOC_MASK       (0xC0000000U)
286 #define NETC_F3_GLOBAL_SMERBCAPR_MLOC_SHIFT      (30U)
287 #define NETC_F3_GLOBAL_SMERBCAPR_MLOC_WIDTH      (2U)
288 #define NETC_F3_GLOBAL_SMERBCAPR_MLOC(x)         (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMERBCAPR_MLOC_SHIFT)) & NETC_F3_GLOBAL_SMERBCAPR_MLOC_MASK)
289 /*! @} */
290 
291 /*! @name SMERBOR0 - Shared memory ENETC receive buffer operational register 0 */
292 /*! @{ */
293 
294 #define NETC_F3_GLOBAL_SMERBOR0_AMOUNT_MASK      (0xFFFFFFU)
295 #define NETC_F3_GLOBAL_SMERBOR0_AMOUNT_SHIFT     (0U)
296 #define NETC_F3_GLOBAL_SMERBOR0_AMOUNT_WIDTH     (24U)
297 #define NETC_F3_GLOBAL_SMERBOR0_AMOUNT(x)        (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMERBOR0_AMOUNT_SHIFT)) & NETC_F3_GLOBAL_SMERBOR0_AMOUNT_MASK)
298 /*! @} */
299 
300 /*! @name SMERBOR1 - Shared memory ENETC receive buffer operational 1 */
301 /*! @{ */
302 
303 #define NETC_F3_GLOBAL_SMERBOR1_WATERMARK_MASK   (0xFFFFFFU)
304 #define NETC_F3_GLOBAL_SMERBOR1_WATERMARK_SHIFT  (0U)
305 #define NETC_F3_GLOBAL_SMERBOR1_WATERMARK_WIDTH  (24U)
306 #define NETC_F3_GLOBAL_SMERBOR1_WATERMARK(x)     (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_SMERBOR1_WATERMARK_SHIFT)) & NETC_F3_GLOBAL_SMERBOR1_WATERMARK_MASK)
307 /*! @} */
308 
309 /*! @name PCEOR - PCE 0 operational register */
310 /*! @{ */
311 
312 #define NETC_F3_GLOBAL_PCEOR_NUM_FRAMES_MASK     (0x3FU)
313 #define NETC_F3_GLOBAL_PCEOR_NUM_FRAMES_SHIFT    (0U)
314 #define NETC_F3_GLOBAL_PCEOR_NUM_FRAMES_WIDTH    (6U)
315 #define NETC_F3_GLOBAL_PCEOR_NUM_FRAMES(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_PCEOR_NUM_FRAMES_SHIFT)) & NETC_F3_GLOBAL_PCEOR_NUM_FRAMES_MASK)
316 
317 #define NETC_F3_GLOBAL_PCEOR_HWM_FRAMES_MASK     (0x3F00U)
318 #define NETC_F3_GLOBAL_PCEOR_HWM_FRAMES_SHIFT    (8U)
319 #define NETC_F3_GLOBAL_PCEOR_HWM_FRAMES_WIDTH    (6U)
320 #define NETC_F3_GLOBAL_PCEOR_HWM_FRAMES(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_PCEOR_HWM_FRAMES_SHIFT)) & NETC_F3_GLOBAL_PCEOR_HWM_FRAMES_MASK)
321 
322 #define NETC_F3_GLOBAL_PCEOR_MAX_FRAMES_MASK     (0x3F0000U)
323 #define NETC_F3_GLOBAL_PCEOR_MAX_FRAMES_SHIFT    (16U)
324 #define NETC_F3_GLOBAL_PCEOR_MAX_FRAMES_WIDTH    (6U)
325 #define NETC_F3_GLOBAL_PCEOR_MAX_FRAMES(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_PCEOR_MAX_FRAMES_SHIFT)) & NETC_F3_GLOBAL_PCEOR_MAX_FRAMES_MASK)
326 /*! @} */
327 
328 /*! @name RFEOR - Replication Forwarding Engine 0 operational register */
329 /*! @{ */
330 
331 #define NETC_F3_GLOBAL_RFEOR_NUM_FRAMES_MASK     (0x3FU)
332 #define NETC_F3_GLOBAL_RFEOR_NUM_FRAMES_SHIFT    (0U)
333 #define NETC_F3_GLOBAL_RFEOR_NUM_FRAMES_WIDTH    (6U)
334 #define NETC_F3_GLOBAL_RFEOR_NUM_FRAMES(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RFEOR_NUM_FRAMES_SHIFT)) & NETC_F3_GLOBAL_RFEOR_NUM_FRAMES_MASK)
335 
336 #define NETC_F3_GLOBAL_RFEOR_HWM_FRAMES_MASK     (0x3F00U)
337 #define NETC_F3_GLOBAL_RFEOR_HWM_FRAMES_SHIFT    (8U)
338 #define NETC_F3_GLOBAL_RFEOR_HWM_FRAMES_WIDTH    (6U)
339 #define NETC_F3_GLOBAL_RFEOR_HWM_FRAMES(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RFEOR_HWM_FRAMES_SHIFT)) & NETC_F3_GLOBAL_RFEOR_HWM_FRAMES_MASK)
340 
341 #define NETC_F3_GLOBAL_RFEOR_MAX_FRAMES_MASK     (0x3F0000U)
342 #define NETC_F3_GLOBAL_RFEOR_MAX_FRAMES_SHIFT    (16U)
343 #define NETC_F3_GLOBAL_RFEOR_MAX_FRAMES_WIDTH    (6U)
344 #define NETC_F3_GLOBAL_RFEOR_MAX_FRAMES(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RFEOR_MAX_FRAMES_SHIFT)) & NETC_F3_GLOBAL_RFEOR_MAX_FRAMES_MASK)
345 /*! @} */
346 
347 /*! @name NETCCLKR - NETC clock register */
348 /*! @{ */
349 
350 #define NETC_F3_GLOBAL_NETCCLKR_FREQ_MASK        (0x7FFU)
351 #define NETC_F3_GLOBAL_NETCCLKR_FREQ_SHIFT       (0U)
352 #define NETC_F3_GLOBAL_NETCCLKR_FREQ_WIDTH       (11U)
353 #define NETC_F3_GLOBAL_NETCCLKR_FREQ(x)          (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_NETCCLKR_FREQ_SHIFT)) & NETC_F3_GLOBAL_NETCCLKR_FREQ_MASK)
354 /*! @} */
355 
356 /*! @name HTACAPR - HTA 0 capability register */
357 /*! @{ */
358 
359 #define NETC_F3_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK (0xFFU)
360 #define NETC_F3_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT (0U)
361 #define NETC_F3_GLOBAL_HTACAPR_MAX_RX_FRAMES_WIDTH (8U)
362 #define NETC_F3_GLOBAL_HTACAPR_MAX_RX_FRAMES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT)) & NETC_F3_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK)
363 
364 #define NETC_F3_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK (0xFF00U)
365 #define NETC_F3_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT (8U)
366 #define NETC_F3_GLOBAL_HTACAPR_MAX_TX_FRAMES_WIDTH (8U)
367 #define NETC_F3_GLOBAL_HTACAPR_MAX_TX_FRAMES(x)  (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT)) & NETC_F3_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK)
368 /*! @} */
369 
370 /*! @name HTARFCOR - HTA 0 receive frame count operational register */
371 /*! @{ */
372 
373 #define NETC_F3_GLOBAL_HTARFCOR_HP_COUNT_MASK    (0xFFU)
374 #define NETC_F3_GLOBAL_HTARFCOR_HP_COUNT_SHIFT   (0U)
375 #define NETC_F3_GLOBAL_HTARFCOR_HP_COUNT_WIDTH   (8U)
376 #define NETC_F3_GLOBAL_HTARFCOR_HP_COUNT(x)      (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTARFCOR_HP_COUNT_SHIFT)) & NETC_F3_GLOBAL_HTARFCOR_HP_COUNT_MASK)
377 
378 #define NETC_F3_GLOBAL_HTARFCOR_HP_HWM_MASK      (0xFF00U)
379 #define NETC_F3_GLOBAL_HTARFCOR_HP_HWM_SHIFT     (8U)
380 #define NETC_F3_GLOBAL_HTARFCOR_HP_HWM_WIDTH     (8U)
381 #define NETC_F3_GLOBAL_HTARFCOR_HP_HWM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTARFCOR_HP_HWM_SHIFT)) & NETC_F3_GLOBAL_HTARFCOR_HP_HWM_MASK)
382 
383 #define NETC_F3_GLOBAL_HTARFCOR_LP_COUNT_MASK    (0xFF0000U)
384 #define NETC_F3_GLOBAL_HTARFCOR_LP_COUNT_SHIFT   (16U)
385 #define NETC_F3_GLOBAL_HTARFCOR_LP_COUNT_WIDTH   (8U)
386 #define NETC_F3_GLOBAL_HTARFCOR_LP_COUNT(x)      (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTARFCOR_LP_COUNT_SHIFT)) & NETC_F3_GLOBAL_HTARFCOR_LP_COUNT_MASK)
387 
388 #define NETC_F3_GLOBAL_HTARFCOR_LP_HWM_MASK      (0xFF000000U)
389 #define NETC_F3_GLOBAL_HTARFCOR_LP_HWM_SHIFT     (24U)
390 #define NETC_F3_GLOBAL_HTARFCOR_LP_HWM_WIDTH     (8U)
391 #define NETC_F3_GLOBAL_HTARFCOR_LP_HWM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTARFCOR_LP_HWM_SHIFT)) & NETC_F3_GLOBAL_HTARFCOR_LP_HWM_MASK)
392 /*! @} */
393 
394 /*! @name HTAHPBCOR - HTA 0 high priority byte count operational register */
395 /*! @{ */
396 
397 #define NETC_F3_GLOBAL_HTAHPBCOR_HP_COUNT_MASK   (0xFFFFU)
398 #define NETC_F3_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT  (0U)
399 #define NETC_F3_GLOBAL_HTAHPBCOR_HP_COUNT_WIDTH  (16U)
400 #define NETC_F3_GLOBAL_HTAHPBCOR_HP_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT)) & NETC_F3_GLOBAL_HTAHPBCOR_HP_COUNT_MASK)
401 
402 #define NETC_F3_GLOBAL_HTAHPBCOR_HWM_MASK        (0xFFFF0000U)
403 #define NETC_F3_GLOBAL_HTAHPBCOR_HWM_SHIFT       (16U)
404 #define NETC_F3_GLOBAL_HTAHPBCOR_HWM_WIDTH       (16U)
405 #define NETC_F3_GLOBAL_HTAHPBCOR_HWM(x)          (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTAHPBCOR_HWM_SHIFT)) & NETC_F3_GLOBAL_HTAHPBCOR_HWM_MASK)
406 /*! @} */
407 
408 /*! @name HTALPBCOR - HTA 0 low priority byte count operational register */
409 /*! @{ */
410 
411 #define NETC_F3_GLOBAL_HTALPBCOR_LP_COUNT_MASK   (0xFFFFU)
412 #define NETC_F3_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT  (0U)
413 #define NETC_F3_GLOBAL_HTALPBCOR_LP_COUNT_WIDTH  (16U)
414 #define NETC_F3_GLOBAL_HTALPBCOR_LP_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT)) & NETC_F3_GLOBAL_HTALPBCOR_LP_COUNT_MASK)
415 
416 #define NETC_F3_GLOBAL_HTALPBCOR_HWM_MASK        (0xFFFF0000U)
417 #define NETC_F3_GLOBAL_HTALPBCOR_HWM_SHIFT       (16U)
418 #define NETC_F3_GLOBAL_HTALPBCOR_HWM_WIDTH       (16U)
419 #define NETC_F3_GLOBAL_HTALPBCOR_HWM(x)          (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTALPBCOR_HWM_SHIFT)) & NETC_F3_GLOBAL_HTALPBCOR_HWM_MASK)
420 /*! @} */
421 
422 /*! @name HTATFCOR - HTA 0 transmit frame count operational register */
423 /*! @{ */
424 
425 #define NETC_F3_GLOBAL_HTATFCOR_HP_COUNT_MASK    (0xFFU)
426 #define NETC_F3_GLOBAL_HTATFCOR_HP_COUNT_SHIFT   (0U)
427 #define NETC_F3_GLOBAL_HTATFCOR_HP_COUNT_WIDTH   (8U)
428 #define NETC_F3_GLOBAL_HTATFCOR_HP_COUNT(x)      (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTATFCOR_HP_COUNT_SHIFT)) & NETC_F3_GLOBAL_HTATFCOR_HP_COUNT_MASK)
429 
430 #define NETC_F3_GLOBAL_HTATFCOR_HP_HWM_MASK      (0xFF00U)
431 #define NETC_F3_GLOBAL_HTATFCOR_HP_HWM_SHIFT     (8U)
432 #define NETC_F3_GLOBAL_HTATFCOR_HP_HWM_WIDTH     (8U)
433 #define NETC_F3_GLOBAL_HTATFCOR_HP_HWM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTATFCOR_HP_HWM_SHIFT)) & NETC_F3_GLOBAL_HTATFCOR_HP_HWM_MASK)
434 
435 #define NETC_F3_GLOBAL_HTATFCOR_LP_COUNT_MASK    (0xFF0000U)
436 #define NETC_F3_GLOBAL_HTATFCOR_LP_COUNT_SHIFT   (16U)
437 #define NETC_F3_GLOBAL_HTATFCOR_LP_COUNT_WIDTH   (8U)
438 #define NETC_F3_GLOBAL_HTATFCOR_LP_COUNT(x)      (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTATFCOR_LP_COUNT_SHIFT)) & NETC_F3_GLOBAL_HTATFCOR_LP_COUNT_MASK)
439 
440 #define NETC_F3_GLOBAL_HTATFCOR_LP_HWM_MASK      (0xFF000000U)
441 #define NETC_F3_GLOBAL_HTATFCOR_LP_HWM_SHIFT     (24U)
442 #define NETC_F3_GLOBAL_HTATFCOR_LP_HWM_WIDTH     (8U)
443 #define NETC_F3_GLOBAL_HTATFCOR_LP_HWM(x)        (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_HTATFCOR_LP_HWM_SHIFT)) & NETC_F3_GLOBAL_HTATFCOR_LP_HWM_MASK)
444 /*! @} */
445 
446 /*! @name RCSBRLAR - Root complex 0 system bus read latency average register */
447 /*! @{ */
448 
449 #define NETC_F3_GLOBAL_RCSBRLAR_FRACT_MASK       (0xFFU)
450 #define NETC_F3_GLOBAL_RCSBRLAR_FRACT_SHIFT      (0U)
451 #define NETC_F3_GLOBAL_RCSBRLAR_FRACT_WIDTH      (8U)
452 #define NETC_F3_GLOBAL_RCSBRLAR_FRACT(x)         (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RCSBRLAR_FRACT_SHIFT)) & NETC_F3_GLOBAL_RCSBRLAR_FRACT_MASK)
453 
454 #define NETC_F3_GLOBAL_RCSBRLAR_INT_MASK         (0xFFF00U)
455 #define NETC_F3_GLOBAL_RCSBRLAR_INT_SHIFT        (8U)
456 #define NETC_F3_GLOBAL_RCSBRLAR_INT_WIDTH        (12U)
457 #define NETC_F3_GLOBAL_RCSBRLAR_INT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RCSBRLAR_INT_SHIFT)) & NETC_F3_GLOBAL_RCSBRLAR_INT_MASK)
458 /*! @} */
459 
460 /*! @name RCSBRLHWMR - Root complex 0 system bus read latency high watermark register */
461 /*! @{ */
462 
463 #define NETC_F3_GLOBAL_RCSBRLHWMR_FRACT_MASK     (0xFFU)
464 #define NETC_F3_GLOBAL_RCSBRLHWMR_FRACT_SHIFT    (0U)
465 #define NETC_F3_GLOBAL_RCSBRLHWMR_FRACT_WIDTH    (8U)
466 #define NETC_F3_GLOBAL_RCSBRLHWMR_FRACT(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RCSBRLHWMR_FRACT_SHIFT)) & NETC_F3_GLOBAL_RCSBRLHWMR_FRACT_MASK)
467 
468 #define NETC_F3_GLOBAL_RCSBRLHWMR_INT_MASK       (0xFFF00U)
469 #define NETC_F3_GLOBAL_RCSBRLHWMR_INT_SHIFT      (8U)
470 #define NETC_F3_GLOBAL_RCSBRLHWMR_INT_WIDTH      (12U)
471 #define NETC_F3_GLOBAL_RCSBRLHWMR_INT(x)         (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RCSBRLHWMR_INT_SHIFT)) & NETC_F3_GLOBAL_RCSBRLHWMR_INT_MASK)
472 /*! @} */
473 
474 /*! @name RCSBWLAR - Root complex 0 system bus write latency average register */
475 /*! @{ */
476 
477 #define NETC_F3_GLOBAL_RCSBWLAR_FRACT_MASK       (0xFFU)
478 #define NETC_F3_GLOBAL_RCSBWLAR_FRACT_SHIFT      (0U)
479 #define NETC_F3_GLOBAL_RCSBWLAR_FRACT_WIDTH      (8U)
480 #define NETC_F3_GLOBAL_RCSBWLAR_FRACT(x)         (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RCSBWLAR_FRACT_SHIFT)) & NETC_F3_GLOBAL_RCSBWLAR_FRACT_MASK)
481 
482 #define NETC_F3_GLOBAL_RCSBWLAR_INT_MASK         (0xFFF00U)
483 #define NETC_F3_GLOBAL_RCSBWLAR_INT_SHIFT        (8U)
484 #define NETC_F3_GLOBAL_RCSBWLAR_INT_WIDTH        (12U)
485 #define NETC_F3_GLOBAL_RCSBWLAR_INT(x)           (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RCSBWLAR_INT_SHIFT)) & NETC_F3_GLOBAL_RCSBWLAR_INT_MASK)
486 /*! @} */
487 
488 /*! @name RCSBWLHWMR - Root complex 0 system bus write latency high watermark register */
489 /*! @{ */
490 
491 #define NETC_F3_GLOBAL_RCSBWLHWMR_FRACT_MASK     (0xFFU)
492 #define NETC_F3_GLOBAL_RCSBWLHWMR_FRACT_SHIFT    (0U)
493 #define NETC_F3_GLOBAL_RCSBWLHWMR_FRACT_WIDTH    (8U)
494 #define NETC_F3_GLOBAL_RCSBWLHWMR_FRACT(x)       (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RCSBWLHWMR_FRACT_SHIFT)) & NETC_F3_GLOBAL_RCSBWLHWMR_FRACT_MASK)
495 
496 #define NETC_F3_GLOBAL_RCSBWLHWMR_INT_MASK       (0xFFF00U)
497 #define NETC_F3_GLOBAL_RCSBWLHWMR_INT_SHIFT      (8U)
498 #define NETC_F3_GLOBAL_RCSBWLHWMR_INT_WIDTH      (12U)
499 #define NETC_F3_GLOBAL_RCSBWLHWMR_INT(x)         (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_RCSBWLHWMR_INT_SHIFT)) & NETC_F3_GLOBAL_RCSBWLHWMR_INT_MASK)
500 /*! @} */
501 
502 /*! @name IPBRR0 - IP block revision register 0 */
503 /*! @{ */
504 
505 #define NETC_F3_GLOBAL_IPBRR0_IP_MN_MASK         (0xFFU)
506 #define NETC_F3_GLOBAL_IPBRR0_IP_MN_SHIFT        (0U)
507 #define NETC_F3_GLOBAL_IPBRR0_IP_MN_WIDTH        (8U)
508 #define NETC_F3_GLOBAL_IPBRR0_IP_MN(x)           (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_IPBRR0_IP_MN_SHIFT)) & NETC_F3_GLOBAL_IPBRR0_IP_MN_MASK)
509 
510 #define NETC_F3_GLOBAL_IPBRR0_IP_MJ_MASK         (0xFF00U)
511 #define NETC_F3_GLOBAL_IPBRR0_IP_MJ_SHIFT        (8U)
512 #define NETC_F3_GLOBAL_IPBRR0_IP_MJ_WIDTH        (8U)
513 #define NETC_F3_GLOBAL_IPBRR0_IP_MJ(x)           (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_IPBRR0_IP_MJ_SHIFT)) & NETC_F3_GLOBAL_IPBRR0_IP_MJ_MASK)
514 
515 #define NETC_F3_GLOBAL_IPBRR0_IP_ID_MASK         (0xFFFF0000U)
516 #define NETC_F3_GLOBAL_IPBRR0_IP_ID_SHIFT        (16U)
517 #define NETC_F3_GLOBAL_IPBRR0_IP_ID_WIDTH        (16U)
518 #define NETC_F3_GLOBAL_IPBRR0_IP_ID(x)           (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_IPBRR0_IP_ID_SHIFT)) & NETC_F3_GLOBAL_IPBRR0_IP_ID_MASK)
519 /*! @} */
520 
521 /*! @name IPBRR1 - IP block revision register 1 */
522 /*! @{ */
523 
524 #define NETC_F3_GLOBAL_IPBRR1_IP_CFG_MASK        (0xFFU)
525 #define NETC_F3_GLOBAL_IPBRR1_IP_CFG_SHIFT       (0U)
526 #define NETC_F3_GLOBAL_IPBRR1_IP_CFG_WIDTH       (8U)
527 #define NETC_F3_GLOBAL_IPBRR1_IP_CFG(x)          (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_IPBRR1_IP_CFG_SHIFT)) & NETC_F3_GLOBAL_IPBRR1_IP_CFG_MASK)
528 
529 #define NETC_F3_GLOBAL_IPBRR1_IP_MNT_MASK        (0xFF00U)
530 #define NETC_F3_GLOBAL_IPBRR1_IP_MNT_SHIFT       (8U)
531 #define NETC_F3_GLOBAL_IPBRR1_IP_MNT_WIDTH       (8U)
532 #define NETC_F3_GLOBAL_IPBRR1_IP_MNT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_IPBRR1_IP_MNT_SHIFT)) & NETC_F3_GLOBAL_IPBRR1_IP_MNT_MASK)
533 
534 #define NETC_F3_GLOBAL_IPBRR1_IP_INT_MASK        (0xFF0000U)
535 #define NETC_F3_GLOBAL_IPBRR1_IP_INT_SHIFT       (16U)
536 #define NETC_F3_GLOBAL_IPBRR1_IP_INT_WIDTH       (8U)
537 #define NETC_F3_GLOBAL_IPBRR1_IP_INT(x)          (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_IPBRR1_IP_INT_SHIFT)) & NETC_F3_GLOBAL_IPBRR1_IP_INT_MASK)
538 /*! @} */
539 
540 /*! @name FBLPR - Function boot loader parameter register 0..Function boot loader parameter register 1 */
541 /*! @{ */
542 
543 #define NETC_F3_GLOBAL_FBLPR_PARAM_VAL_MASK      (0xFFFFFFFFU)
544 #define NETC_F3_GLOBAL_FBLPR_PARAM_VAL_SHIFT     (0U)
545 #define NETC_F3_GLOBAL_FBLPR_PARAM_VAL_WIDTH     (32U)
546 #define NETC_F3_GLOBAL_FBLPR_PARAM_VAL(x)        (((uint32_t)(((uint32_t)(x)) << NETC_F3_GLOBAL_FBLPR_PARAM_VAL_SHIFT)) & NETC_F3_GLOBAL_FBLPR_PARAM_VAL_MASK)
547 /*! @} */
548 
549 /*!
550  * @}
551  */ /* end of group NETC_F3_GLOBAL_Register_Masks */
552 
553 /*!
554  * @}
555  */ /* end of group NETC_F3_GLOBAL_Peripheral_Access_Layer */
556 
557 #endif  /* #if !defined(S32Z2_NETC_F3_GLOBAL_H_) */
558