1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F3_COMMON.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_NETC_F3_COMMON 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F3_COMMON_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F3_COMMON_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F3_COMMON Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F3_COMMON_Peripheral_Access_Layer NETC_F3_COMMON Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F3_COMMON - Size of Registers Arrays */ 72 #define NETC_F3_COMMON_NUM_PROFILE_COUNT 1u 73 74 /** NETC_F3_COMMON - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[4096]; 77 __I uint32_t IPCAPR; /**< Ingress port capability register, offset: 0x1000 */ 78 __I uint32_t EPCAPR; /**< Egress port capability register, offset: 0x1004 */ 79 uint8_t RESERVED_1[8]; 80 __I uint32_t OSR; /**< Operational state register, offset: 0x1010 */ 81 uint8_t RESERVED_2[44]; 82 __IO uint32_t CMECR; /**< Correctable memory error configuration register, offset: 0x1040 */ 83 __IO uint32_t CMESR; /**< Correctable memory error status register, offset: 0x1044 */ 84 uint8_t RESERVED_3[4]; 85 __I uint32_t CMECTR; /**< Correctable memory error count register, offset: 0x104C */ 86 uint8_t RESERVED_4[16]; 87 __IO uint32_t UNMACECR; /**< Uncorrectable non-fatal MAC error configuration register, offset: 0x1060 */ 88 __I uint32_t UNMACESR; /**< Uncorrectable non-fatal MAC error status register, offset: 0x1064 */ 89 uint8_t RESERVED_5[40]; 90 __IO uint32_t UNMECR; /**< Uncorrectable non-fatal memory error configuration register, offset: 0x1090 */ 91 __IO uint32_t UNMESR0; /**< Uncorrectable non-fatal memory error status register 0, offset: 0x1094 */ 92 __I uint32_t UNMESR1; /**< Uncorrectable non-fatal memory error status register 1, offset: 0x1098 */ 93 __I uint32_t UNMECTR; /**< Uncorrectable non-fatal memory error count register, offset: 0x109C */ 94 __IO uint32_t UFMECR; /**< Uncorrectable fatal memory error configuration register, offset: 0x10A0 */ 95 __IO uint32_t UFMESR0; /**< Uncorrectable fatal memory error status register 0, offset: 0x10A4 */ 96 __I uint32_t UFMESR1; /**< Uncorrectable fatal memory error status register 1, offset: 0x10A8 */ 97 uint8_t RESERVED_6[4]; 98 __IO uint32_t UNIECR; /**< Uncorrectable non-fatal integrity error configuration register, offset: 0x10B0 */ 99 __IO uint32_t UNIESR; /**< Uncorrectable non-fatal integrity error status register, offset: 0x10B4 */ 100 uint8_t RESERVED_7[4]; 101 __I uint32_t UNIECTR; /**< Uncorrectable non-fatal integrity error count register, offset: 0x10BC */ 102 __IO uint32_t UFIECR; /**< Uncorrectable fatal integrity error configuration register, offset: 0x10C0 */ 103 __IO uint32_t UFIESR; /**< Uncorrectable fatal integrity error status register, offset: 0x10C4 */ 104 uint8_t RESERVED_8[312]; 105 __IO uint32_t CVLANR1; /**< Custom VLAN Ethertype register 1, offset: 0x1200 */ 106 __IO uint32_t CVLANR2; /**< Custom VLAN Ethertype register 2, offset: 0x1204 */ 107 uint8_t RESERVED_9[24]; 108 __IO uint32_t DOSL2CR; /**< DoS L2 configuration register, offset: 0x1220 */ 109 uint8_t RESERVED_10[220]; 110 struct { /* offset: 0x1300, array step: 0xC */ 111 __IO uint32_t VLANIPVMPR0; /**< VLAN to IPV mapping profile 0 register 0, array offset: 0x1300, array step: 0xC */ 112 __IO uint32_t VLANIPVMPR1; /**< VLAN to IPV mapping profile 0 register 1, array offset: 0x1304, array step: 0xC */ 113 __IO uint32_t VLANDRMPR; /**< VLAN to DR mapping profile 0 register, array offset: 0x1308, array step: 0xC */ 114 } NUM_PROFILE[NETC_F3_COMMON_NUM_PROFILE_COUNT]; 115 uint8_t RESERVED_11[820]; 116 __I uint32_t IPFCAPR; /**< Ingress port filter capability register, offset: 0x1640 */ 117 __I uint32_t IPFTCAPR; /**< Ingress port filter table capability register, offset: 0x1644 */ 118 __I uint32_t IPFTMOR; /**< Ingress port filter table memory operational register, offset: 0x1648 */ 119 uint8_t RESERVED_12[436]; 120 __I uint32_t ITMCAPR; /**< Index table memory capability register, offset: 0x1800 */ 121 uint8_t RESERVED_13[12]; 122 __I uint32_t RPCAPR; /**< Rate policer capability register, offset: 0x1810 */ 123 __I uint32_t RPITCAPR; /**< Rate policer index table capability register, offset: 0x1814 */ 124 __IO uint32_t RPITMAR; /**< Rate policer index table memory allocation register, offset: 0x1818 */ 125 __I uint32_t RPITOR; /**< Rate policer index table operational register, offset: 0x181C */ 126 uint8_t RESERVED_14[4]; 127 __I uint32_t ISCITCAPR; /**< Ingress stream counter index table capability register, offset: 0x1824 */ 128 __IO uint32_t ISCITMAR; /**< Ingress stream counter index table memory allocation register, offset: 0x1828 */ 129 __I uint32_t ISCITOR; /**< Ingress stream counter index table operational register, offset: 0x182C */ 130 __I uint32_t ISCAPR; /**< Ingress stream capability register, offset: 0x1830 */ 131 __I uint32_t ISITCAPR; /**< Ingress stream index table capability register, offset: 0x1834 */ 132 __IO uint32_t ISITMAR; /**< Ingress stream index table memory allocation register, offset: 0x1838 */ 133 __I uint32_t ISITOR; /**< Ingress stream index table operational register, offset: 0x183C */ 134 uint8_t RESERVED_15[32]; 135 __I uint32_t SGCAPR; /**< Stream gate capability register, offset: 0x1860 */ 136 __I uint32_t SGIITCAPR; /**< Stream gate instance index table capability register, offset: 0x1864 */ 137 __IO uint32_t SGIITMAR; /**< Stream gate instance index table memory allocation register, offset: 0x1868 */ 138 __I uint32_t SGIITOR; /**< Stream gate instance index table operational register, offset: 0x186C */ 139 uint8_t RESERVED_16[4]; 140 __I uint32_t SGCLITCAPR; /**< Stream gate control list index table capability register, offset: 0x1874 */ 141 __IO uint32_t SGCLITMAR; /**< Stream gate control list index table memory allocation register, offset: 0x1878 */ 142 __I uint32_t SGCLTMOR; /**< Stream gate control list table memory operational register, offset: 0x187C */ 143 uint8_t RESERVED_17[84]; 144 __I uint32_t TGSTCAPR; /**< Time gate scheduling table capability register, offset: 0x18D4 */ 145 uint8_t RESERVED_18[4]; 146 __I uint32_t TGSTMOR; /**< Time gate scheduling table memory operation register, offset: 0x18DC */ 147 uint8_t RESERVED_19[32]; 148 __I uint32_t HTMCAPR; /**< Hash table memory capability register, offset: 0x1900 */ 149 __I uint32_t HTMOR; /**< Hash table memory operational register, offset: 0x1904 */ 150 uint8_t RESERVED_20[8]; 151 __I uint32_t ISIDCAPR; /**< Ingress stream identification capability register, offset: 0x1910 */ 152 __I uint32_t ISIDHTCAPR; /**< Ingress stream identification hash table capability register, offset: 0x1914 */ 153 uint8_t RESERVED_21[8]; 154 __I uint32_t ISIDKC0OR; /**< Ingress stream identification key construction 0 operational register, offset: 0x1920 */ 155 __IO uint32_t ISIDKC0CR0; /**< Ingress stream identification key construction 0 configuration register 0, offset: 0x1924 */ 156 uint8_t RESERVED_22[8]; 157 __IO uint32_t ISIDKC0PF0CR; /**< Ingress stream identification key construction 0 payload field 0 configuration register, offset: 0x1930 */ 158 __IO uint32_t ISIDKC0PF1CR; /**< Ingress stream identification key construction 0 payload field 1 configuration register, offset: 0x1934 */ 159 __IO uint32_t ISIDKC0PF2CR; /**< Ingress stream identification key construction 0 payload field 2 configuration register, offset: 0x1938 */ 160 __IO uint32_t ISIDKC0PF3CR; /**< Ingress stream identification key construction 0 payload field 3 configuration register, offset: 0x193C */ 161 __I uint32_t ISIDKC1OR; /**< Ingress stream identification key construction 1 operational register, offset: 0x1940 */ 162 __IO uint32_t ISIDKC1CR0; /**< Ingress stream identification key construction 1 configuration register 0, offset: 0x1944 */ 163 uint8_t RESERVED_23[8]; 164 __IO uint32_t ISIDKC1PF0CR; /**< Ingress stream identification key construction 1 payload field 0 configuration register, offset: 0x1950 */ 165 __IO uint32_t ISIDKC1PF1CR; /**< Ingress stream identification key construction 1 payload field 1 configuration register, offset: 0x1954 */ 166 __IO uint32_t ISIDKC1PF2CR; /**< Ingress stream identification key construction 1 payload field 2 configuration register, offset: 0x1958 */ 167 __IO uint32_t ISIDKC1PF3CR; /**< Ingress stream identification key construction 1 payload field 3 configuration register, offset: 0x195C */ 168 uint8_t RESERVED_24[160]; 169 __I uint32_t ISFHTCAPR; /**< Ingress stream filter hash table capability register, offset: 0x1A00 */ 170 __I uint32_t ISFHTOR; /**< Ingress stream filter hash table operational register, offset: 0x1A04 */ 171 } NETC_F3_COMMON_Type, *NETC_F3_COMMON_MemMapPtr; 172 173 /** Number of instances of the NETC_F3_COMMON module. */ 174 #define NETC_F3_COMMON_INSTANCE_COUNT (1u) 175 176 /* NETC_F3_COMMON - Peripheral instance base addresses */ 177 /** Peripheral NETC__ENETC0_COMMON base address */ 178 #define IP_NETC__ENETC0_COMMON_BASE (0x74B10000u) 179 /** Peripheral NETC__ENETC0_COMMON base pointer */ 180 #define IP_NETC__ENETC0_COMMON ((NETC_F3_COMMON_Type *)IP_NETC__ENETC0_COMMON_BASE) 181 /** Array initializer of NETC_F3_COMMON peripheral base addresses */ 182 #define IP_NETC_F3_COMMON_BASE_ADDRS { IP_NETC__ENETC0_COMMON_BASE } 183 /** Array initializer of NETC_F3_COMMON peripheral base pointers */ 184 #define IP_NETC_F3_COMMON_BASE_PTRS { IP_NETC__ENETC0_COMMON } 185 186 /* ---------------------------------------------------------------------------- 187 -- NETC_F3_COMMON Register Masks 188 ---------------------------------------------------------------------------- */ 189 190 /*! 191 * @addtogroup NETC_F3_COMMON_Register_Masks NETC_F3_COMMON Register Masks 192 * @{ 193 */ 194 195 /*! @name IPCAPR - Ingress port capability register */ 196 /*! @{ */ 197 198 #define NETC_F3_COMMON_IPCAPR_RP_MASK (0x1U) 199 #define NETC_F3_COMMON_IPCAPR_RP_SHIFT (0U) 200 #define NETC_F3_COMMON_IPCAPR_RP_WIDTH (1U) 201 #define NETC_F3_COMMON_IPCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPCAPR_RP_SHIFT)) & NETC_F3_COMMON_IPCAPR_RP_MASK) 202 203 #define NETC_F3_COMMON_IPCAPR_IPFLT_MASK (0x2U) 204 #define NETC_F3_COMMON_IPCAPR_IPFLT_SHIFT (1U) 205 #define NETC_F3_COMMON_IPCAPR_IPFLT_WIDTH (1U) 206 #define NETC_F3_COMMON_IPCAPR_IPFLT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPCAPR_IPFLT_SHIFT)) & NETC_F3_COMMON_IPCAPR_IPFLT_MASK) 207 208 #define NETC_F3_COMMON_IPCAPR_ISID_MASK (0x4U) 209 #define NETC_F3_COMMON_IPCAPR_ISID_SHIFT (2U) 210 #define NETC_F3_COMMON_IPCAPR_ISID_WIDTH (1U) 211 #define NETC_F3_COMMON_IPCAPR_ISID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPCAPR_ISID_SHIFT)) & NETC_F3_COMMON_IPCAPR_ISID_MASK) 212 213 #define NETC_F3_COMMON_IPCAPR_SDU_MASK (0x1F00U) 214 #define NETC_F3_COMMON_IPCAPR_SDU_SHIFT (8U) 215 #define NETC_F3_COMMON_IPCAPR_SDU_WIDTH (5U) 216 #define NETC_F3_COMMON_IPCAPR_SDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPCAPR_SDU_SHIFT)) & NETC_F3_COMMON_IPCAPR_SDU_MASK) 217 218 #define NETC_F3_COMMON_IPCAPR_NUM_VQMP_MASK (0xF0000U) 219 #define NETC_F3_COMMON_IPCAPR_NUM_VQMP_SHIFT (16U) 220 #define NETC_F3_COMMON_IPCAPR_NUM_VQMP_WIDTH (4U) 221 #define NETC_F3_COMMON_IPCAPR_NUM_VQMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPCAPR_NUM_VQMP_SHIFT)) & NETC_F3_COMMON_IPCAPR_NUM_VQMP_MASK) 222 /*! @} */ 223 224 /*! @name EPCAPR - Egress port capability register */ 225 /*! @{ */ 226 227 #define NETC_F3_COMMON_EPCAPR_SDU_MASK (0x1F00U) 228 #define NETC_F3_COMMON_EPCAPR_SDU_SHIFT (8U) 229 #define NETC_F3_COMMON_EPCAPR_SDU_WIDTH (5U) 230 #define NETC_F3_COMMON_EPCAPR_SDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_EPCAPR_SDU_SHIFT)) & NETC_F3_COMMON_EPCAPR_SDU_MASK) 231 232 #define NETC_F3_COMMON_EPCAPR_NUM_QVMP_MASK (0xF0000U) 233 #define NETC_F3_COMMON_EPCAPR_NUM_QVMP_SHIFT (16U) 234 #define NETC_F3_COMMON_EPCAPR_NUM_QVMP_WIDTH (4U) 235 #define NETC_F3_COMMON_EPCAPR_NUM_QVMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_EPCAPR_NUM_QVMP_SHIFT)) & NETC_F3_COMMON_EPCAPR_NUM_QVMP_MASK) 236 /*! @} */ 237 238 /*! @name OSR - Operational state register */ 239 /*! @{ */ 240 241 #define NETC_F3_COMMON_OSR_STATE_MASK (0x1U) 242 #define NETC_F3_COMMON_OSR_STATE_SHIFT (0U) 243 #define NETC_F3_COMMON_OSR_STATE_WIDTH (1U) 244 #define NETC_F3_COMMON_OSR_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_OSR_STATE_SHIFT)) & NETC_F3_COMMON_OSR_STATE_MASK) 245 246 #define NETC_F3_COMMON_OSR_ITM_STATE_MASK (0x2U) 247 #define NETC_F3_COMMON_OSR_ITM_STATE_SHIFT (1U) 248 #define NETC_F3_COMMON_OSR_ITM_STATE_WIDTH (1U) 249 #define NETC_F3_COMMON_OSR_ITM_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_OSR_ITM_STATE_SHIFT)) & NETC_F3_COMMON_OSR_ITM_STATE_MASK) 250 /*! @} */ 251 252 /*! @name CMECR - Correctable memory error configuration register */ 253 /*! @{ */ 254 255 #define NETC_F3_COMMON_CMECR_THRESHOLD_MASK (0xFFU) 256 #define NETC_F3_COMMON_CMECR_THRESHOLD_SHIFT (0U) 257 #define NETC_F3_COMMON_CMECR_THRESHOLD_WIDTH (8U) 258 #define NETC_F3_COMMON_CMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_CMECR_THRESHOLD_SHIFT)) & NETC_F3_COMMON_CMECR_THRESHOLD_MASK) 259 /*! @} */ 260 261 /*! @name CMESR - Correctable memory error status register */ 262 /*! @{ */ 263 264 #define NETC_F3_COMMON_CMESR_MEM_ID_MASK (0x1F0000U) 265 #define NETC_F3_COMMON_CMESR_MEM_ID_SHIFT (16U) 266 #define NETC_F3_COMMON_CMESR_MEM_ID_WIDTH (5U) 267 #define NETC_F3_COMMON_CMESR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_CMESR_MEM_ID_SHIFT)) & NETC_F3_COMMON_CMESR_MEM_ID_MASK) 268 269 #define NETC_F3_COMMON_CMESR_SBEE_MASK (0x80000000U) 270 #define NETC_F3_COMMON_CMESR_SBEE_SHIFT (31U) 271 #define NETC_F3_COMMON_CMESR_SBEE_WIDTH (1U) 272 #define NETC_F3_COMMON_CMESR_SBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_CMESR_SBEE_SHIFT)) & NETC_F3_COMMON_CMESR_SBEE_MASK) 273 /*! @} */ 274 275 /*! @name CMECTR - Correctable memory error count register */ 276 /*! @{ */ 277 278 #define NETC_F3_COMMON_CMECTR_COUNT_MASK (0xFFU) 279 #define NETC_F3_COMMON_CMECTR_COUNT_SHIFT (0U) 280 #define NETC_F3_COMMON_CMECTR_COUNT_WIDTH (8U) 281 #define NETC_F3_COMMON_CMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_CMECTR_COUNT_SHIFT)) & NETC_F3_COMMON_CMECTR_COUNT_MASK) 282 /*! @} */ 283 284 /*! @name UNMACECR - Uncorrectable non-fatal MAC error configuration register */ 285 /*! @{ */ 286 287 #define NETC_F3_COMMON_UNMACECR_PORT0_MASK (0x1U) 288 #define NETC_F3_COMMON_UNMACECR_PORT0_SHIFT (0U) 289 #define NETC_F3_COMMON_UNMACECR_PORT0_WIDTH (1U) 290 #define NETC_F3_COMMON_UNMACECR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMACECR_PORT0_SHIFT)) & NETC_F3_COMMON_UNMACECR_PORT0_MASK) 291 /*! @} */ 292 293 /*! @name UNMACESR - Uncorrectable non-fatal MAC error status register */ 294 /*! @{ */ 295 296 #define NETC_F3_COMMON_UNMACESR_PORT0_MASK (0x1U) 297 #define NETC_F3_COMMON_UNMACESR_PORT0_SHIFT (0U) 298 #define NETC_F3_COMMON_UNMACESR_PORT0_WIDTH (1U) 299 #define NETC_F3_COMMON_UNMACESR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMACESR_PORT0_SHIFT)) & NETC_F3_COMMON_UNMACESR_PORT0_MASK) 300 /*! @} */ 301 302 /*! @name UNMECR - Uncorrectable non-fatal memory error configuration register */ 303 /*! @{ */ 304 305 #define NETC_F3_COMMON_UNMECR_THRESHOLD_MASK (0xFFU) 306 #define NETC_F3_COMMON_UNMECR_THRESHOLD_SHIFT (0U) 307 #define NETC_F3_COMMON_UNMECR_THRESHOLD_WIDTH (8U) 308 #define NETC_F3_COMMON_UNMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMECR_THRESHOLD_SHIFT)) & NETC_F3_COMMON_UNMECR_THRESHOLD_MASK) 309 310 #define NETC_F3_COMMON_UNMECR_RD_MASK (0x80000000U) 311 #define NETC_F3_COMMON_UNMECR_RD_SHIFT (31U) 312 #define NETC_F3_COMMON_UNMECR_RD_WIDTH (1U) 313 #define NETC_F3_COMMON_UNMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMECR_RD_SHIFT)) & NETC_F3_COMMON_UNMECR_RD_MASK) 314 /*! @} */ 315 316 /*! @name UNMESR0 - Uncorrectable non-fatal memory error status register 0 */ 317 /*! @{ */ 318 319 #define NETC_F3_COMMON_UNMESR0_SYNDROME_MASK (0x7FFU) 320 #define NETC_F3_COMMON_UNMESR0_SYNDROME_SHIFT (0U) 321 #define NETC_F3_COMMON_UNMESR0_SYNDROME_WIDTH (11U) 322 #define NETC_F3_COMMON_UNMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMESR0_SYNDROME_SHIFT)) & NETC_F3_COMMON_UNMESR0_SYNDROME_MASK) 323 324 #define NETC_F3_COMMON_UNMESR0_MEM_ID_MASK (0x1F0000U) 325 #define NETC_F3_COMMON_UNMESR0_MEM_ID_SHIFT (16U) 326 #define NETC_F3_COMMON_UNMESR0_MEM_ID_WIDTH (5U) 327 #define NETC_F3_COMMON_UNMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMESR0_MEM_ID_SHIFT)) & NETC_F3_COMMON_UNMESR0_MEM_ID_MASK) 328 329 #define NETC_F3_COMMON_UNMESR0_MBEE_MASK (0x80000000U) 330 #define NETC_F3_COMMON_UNMESR0_MBEE_SHIFT (31U) 331 #define NETC_F3_COMMON_UNMESR0_MBEE_WIDTH (1U) 332 #define NETC_F3_COMMON_UNMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMESR0_MBEE_SHIFT)) & NETC_F3_COMMON_UNMESR0_MBEE_MASK) 333 /*! @} */ 334 335 /*! @name UNMESR1 - Uncorrectable non-fatal memory error status register 1 */ 336 /*! @{ */ 337 338 #define NETC_F3_COMMON_UNMESR1_ADDR_MASK (0xFFFFFFFFU) 339 #define NETC_F3_COMMON_UNMESR1_ADDR_SHIFT (0U) 340 #define NETC_F3_COMMON_UNMESR1_ADDR_WIDTH (32U) 341 #define NETC_F3_COMMON_UNMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMESR1_ADDR_SHIFT)) & NETC_F3_COMMON_UNMESR1_ADDR_MASK) 342 /*! @} */ 343 344 /*! @name UNMECTR - Uncorrectable non-fatal memory error count register */ 345 /*! @{ */ 346 347 #define NETC_F3_COMMON_UNMECTR_COUNT_MASK (0xFFU) 348 #define NETC_F3_COMMON_UNMECTR_COUNT_SHIFT (0U) 349 #define NETC_F3_COMMON_UNMECTR_COUNT_WIDTH (8U) 350 #define NETC_F3_COMMON_UNMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNMECTR_COUNT_SHIFT)) & NETC_F3_COMMON_UNMECTR_COUNT_MASK) 351 /*! @} */ 352 353 /*! @name UFMECR - Uncorrectable fatal memory error configuration register */ 354 /*! @{ */ 355 356 #define NETC_F3_COMMON_UFMECR_RD_MASK (0x80000000U) 357 #define NETC_F3_COMMON_UFMECR_RD_SHIFT (31U) 358 #define NETC_F3_COMMON_UFMECR_RD_WIDTH (1U) 359 #define NETC_F3_COMMON_UFMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFMECR_RD_SHIFT)) & NETC_F3_COMMON_UFMECR_RD_MASK) 360 /*! @} */ 361 362 /*! @name UFMESR0 - Uncorrectable fatal memory error status register 0 */ 363 /*! @{ */ 364 365 #define NETC_F3_COMMON_UFMESR0_SYNDROME_MASK (0x7FFU) 366 #define NETC_F3_COMMON_UFMESR0_SYNDROME_SHIFT (0U) 367 #define NETC_F3_COMMON_UFMESR0_SYNDROME_WIDTH (11U) 368 #define NETC_F3_COMMON_UFMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFMESR0_SYNDROME_SHIFT)) & NETC_F3_COMMON_UFMESR0_SYNDROME_MASK) 369 370 #define NETC_F3_COMMON_UFMESR0_MEM_ID_MASK (0x1F0000U) 371 #define NETC_F3_COMMON_UFMESR0_MEM_ID_SHIFT (16U) 372 #define NETC_F3_COMMON_UFMESR0_MEM_ID_WIDTH (5U) 373 #define NETC_F3_COMMON_UFMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFMESR0_MEM_ID_SHIFT)) & NETC_F3_COMMON_UFMESR0_MEM_ID_MASK) 374 375 #define NETC_F3_COMMON_UFMESR0_M_MASK (0x40000000U) 376 #define NETC_F3_COMMON_UFMESR0_M_SHIFT (30U) 377 #define NETC_F3_COMMON_UFMESR0_M_WIDTH (1U) 378 #define NETC_F3_COMMON_UFMESR0_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFMESR0_M_SHIFT)) & NETC_F3_COMMON_UFMESR0_M_MASK) 379 380 #define NETC_F3_COMMON_UFMESR0_MBEE_MASK (0x80000000U) 381 #define NETC_F3_COMMON_UFMESR0_MBEE_SHIFT (31U) 382 #define NETC_F3_COMMON_UFMESR0_MBEE_WIDTH (1U) 383 #define NETC_F3_COMMON_UFMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFMESR0_MBEE_SHIFT)) & NETC_F3_COMMON_UFMESR0_MBEE_MASK) 384 /*! @} */ 385 386 /*! @name UFMESR1 - Uncorrectable fatal memory error status register 1 */ 387 /*! @{ */ 388 389 #define NETC_F3_COMMON_UFMESR1_ADDR_MASK (0xFFFFFFFFU) 390 #define NETC_F3_COMMON_UFMESR1_ADDR_SHIFT (0U) 391 #define NETC_F3_COMMON_UFMESR1_ADDR_WIDTH (32U) 392 #define NETC_F3_COMMON_UFMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFMESR1_ADDR_SHIFT)) & NETC_F3_COMMON_UFMESR1_ADDR_MASK) 393 /*! @} */ 394 395 /*! @name UNIECR - Uncorrectable non-fatal integrity error configuration register */ 396 /*! @{ */ 397 398 #define NETC_F3_COMMON_UNIECR_THRESHOLD_MASK (0xFFU) 399 #define NETC_F3_COMMON_UNIECR_THRESHOLD_SHIFT (0U) 400 #define NETC_F3_COMMON_UNIECR_THRESHOLD_WIDTH (8U) 401 #define NETC_F3_COMMON_UNIECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNIECR_THRESHOLD_SHIFT)) & NETC_F3_COMMON_UNIECR_THRESHOLD_MASK) 402 403 #define NETC_F3_COMMON_UNIECR_RD_MASK (0x80000000U) 404 #define NETC_F3_COMMON_UNIECR_RD_SHIFT (31U) 405 #define NETC_F3_COMMON_UNIECR_RD_WIDTH (1U) 406 #define NETC_F3_COMMON_UNIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNIECR_RD_SHIFT)) & NETC_F3_COMMON_UNIECR_RD_MASK) 407 /*! @} */ 408 409 /*! @name UNIESR - Uncorrectable non-fatal integrity error status register */ 410 /*! @{ */ 411 412 #define NETC_F3_COMMON_UNIESR_LINK_SLICE_ID_MASK (0xFU) 413 #define NETC_F3_COMMON_UNIESR_LINK_SLICE_ID_SHIFT (0U) 414 #define NETC_F3_COMMON_UNIESR_LINK_SLICE_ID_WIDTH (4U) 415 #define NETC_F3_COMMON_UNIESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNIESR_LINK_SLICE_ID_SHIFT)) & NETC_F3_COMMON_UNIESR_LINK_SLICE_ID_MASK) 416 417 #define NETC_F3_COMMON_UNIESR_BLOCK_ID_MASK (0xF0U) 418 #define NETC_F3_COMMON_UNIESR_BLOCK_ID_SHIFT (4U) 419 #define NETC_F3_COMMON_UNIESR_BLOCK_ID_WIDTH (4U) 420 #define NETC_F3_COMMON_UNIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNIESR_BLOCK_ID_SHIFT)) & NETC_F3_COMMON_UNIESR_BLOCK_ID_MASK) 421 422 #define NETC_F3_COMMON_UNIESR_SM_ID_MASK (0x3F00U) 423 #define NETC_F3_COMMON_UNIESR_SM_ID_SHIFT (8U) 424 #define NETC_F3_COMMON_UNIESR_SM_ID_WIDTH (6U) 425 #define NETC_F3_COMMON_UNIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNIESR_SM_ID_SHIFT)) & NETC_F3_COMMON_UNIESR_SM_ID_MASK) 426 427 #define NETC_F3_COMMON_UNIESR_ENGINE_ID_MASK (0x10000U) 428 #define NETC_F3_COMMON_UNIESR_ENGINE_ID_SHIFT (16U) 429 #define NETC_F3_COMMON_UNIESR_ENGINE_ID_WIDTH (1U) 430 #define NETC_F3_COMMON_UNIESR_ENGINE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNIESR_ENGINE_ID_SHIFT)) & NETC_F3_COMMON_UNIESR_ENGINE_ID_MASK) 431 432 #define NETC_F3_COMMON_UNIESR_INTERR_MASK (0x80000000U) 433 #define NETC_F3_COMMON_UNIESR_INTERR_SHIFT (31U) 434 #define NETC_F3_COMMON_UNIESR_INTERR_WIDTH (1U) 435 #define NETC_F3_COMMON_UNIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNIESR_INTERR_SHIFT)) & NETC_F3_COMMON_UNIESR_INTERR_MASK) 436 /*! @} */ 437 438 /*! @name UNIECTR - Uncorrectable non-fatal integrity error count register */ 439 /*! @{ */ 440 441 #define NETC_F3_COMMON_UNIECTR_COUNT_MASK (0xFFU) 442 #define NETC_F3_COMMON_UNIECTR_COUNT_SHIFT (0U) 443 #define NETC_F3_COMMON_UNIECTR_COUNT_WIDTH (8U) 444 #define NETC_F3_COMMON_UNIECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UNIECTR_COUNT_SHIFT)) & NETC_F3_COMMON_UNIECTR_COUNT_MASK) 445 /*! @} */ 446 447 /*! @name UFIECR - Uncorrectable fatal integrity error configuration register */ 448 /*! @{ */ 449 450 #define NETC_F3_COMMON_UFIECR_RD_MASK (0x80000000U) 451 #define NETC_F3_COMMON_UFIECR_RD_SHIFT (31U) 452 #define NETC_F3_COMMON_UFIECR_RD_WIDTH (1U) 453 #define NETC_F3_COMMON_UFIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFIECR_RD_SHIFT)) & NETC_F3_COMMON_UFIECR_RD_MASK) 454 /*! @} */ 455 456 /*! @name UFIESR - Uncorrectable fatal integrity error status register */ 457 /*! @{ */ 458 459 #define NETC_F3_COMMON_UFIESR_LINK_SLICE_ID_MASK (0xFU) 460 #define NETC_F3_COMMON_UFIESR_LINK_SLICE_ID_SHIFT (0U) 461 #define NETC_F3_COMMON_UFIESR_LINK_SLICE_ID_WIDTH (4U) 462 #define NETC_F3_COMMON_UFIESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFIESR_LINK_SLICE_ID_SHIFT)) & NETC_F3_COMMON_UFIESR_LINK_SLICE_ID_MASK) 463 464 #define NETC_F3_COMMON_UFIESR_BLOCK_ID_MASK (0xF0U) 465 #define NETC_F3_COMMON_UFIESR_BLOCK_ID_SHIFT (4U) 466 #define NETC_F3_COMMON_UFIESR_BLOCK_ID_WIDTH (4U) 467 #define NETC_F3_COMMON_UFIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFIESR_BLOCK_ID_SHIFT)) & NETC_F3_COMMON_UFIESR_BLOCK_ID_MASK) 468 469 #define NETC_F3_COMMON_UFIESR_SM_ID_MASK (0x3F00U) 470 #define NETC_F3_COMMON_UFIESR_SM_ID_SHIFT (8U) 471 #define NETC_F3_COMMON_UFIESR_SM_ID_WIDTH (6U) 472 #define NETC_F3_COMMON_UFIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFIESR_SM_ID_SHIFT)) & NETC_F3_COMMON_UFIESR_SM_ID_MASK) 473 474 #define NETC_F3_COMMON_UFIESR_ENGINE_ID_MASK (0x10000U) 475 #define NETC_F3_COMMON_UFIESR_ENGINE_ID_SHIFT (16U) 476 #define NETC_F3_COMMON_UFIESR_ENGINE_ID_WIDTH (1U) 477 #define NETC_F3_COMMON_UFIESR_ENGINE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFIESR_ENGINE_ID_SHIFT)) & NETC_F3_COMMON_UFIESR_ENGINE_ID_MASK) 478 479 #define NETC_F3_COMMON_UFIESR_M_MASK (0x40000000U) 480 #define NETC_F3_COMMON_UFIESR_M_SHIFT (30U) 481 #define NETC_F3_COMMON_UFIESR_M_WIDTH (1U) 482 #define NETC_F3_COMMON_UFIESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFIESR_M_SHIFT)) & NETC_F3_COMMON_UFIESR_M_MASK) 483 484 #define NETC_F3_COMMON_UFIESR_INTERR_MASK (0x80000000U) 485 #define NETC_F3_COMMON_UFIESR_INTERR_SHIFT (31U) 486 #define NETC_F3_COMMON_UFIESR_INTERR_WIDTH (1U) 487 #define NETC_F3_COMMON_UFIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_UFIESR_INTERR_SHIFT)) & NETC_F3_COMMON_UFIESR_INTERR_MASK) 488 /*! @} */ 489 490 /*! @name CVLANR1 - Custom VLAN Ethertype register 1 */ 491 /*! @{ */ 492 493 #define NETC_F3_COMMON_CVLANR1_ETYPE_MASK (0xFFFFU) 494 #define NETC_F3_COMMON_CVLANR1_ETYPE_SHIFT (0U) 495 #define NETC_F3_COMMON_CVLANR1_ETYPE_WIDTH (16U) 496 #define NETC_F3_COMMON_CVLANR1_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_CVLANR1_ETYPE_SHIFT)) & NETC_F3_COMMON_CVLANR1_ETYPE_MASK) 497 498 #define NETC_F3_COMMON_CVLANR1_V_MASK (0x80000000U) 499 #define NETC_F3_COMMON_CVLANR1_V_SHIFT (31U) 500 #define NETC_F3_COMMON_CVLANR1_V_WIDTH (1U) 501 #define NETC_F3_COMMON_CVLANR1_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_CVLANR1_V_SHIFT)) & NETC_F3_COMMON_CVLANR1_V_MASK) 502 /*! @} */ 503 504 /*! @name CVLANR2 - Custom VLAN Ethertype register 2 */ 505 /*! @{ */ 506 507 #define NETC_F3_COMMON_CVLANR2_ETYPE_MASK (0xFFFFU) 508 #define NETC_F3_COMMON_CVLANR2_ETYPE_SHIFT (0U) 509 #define NETC_F3_COMMON_CVLANR2_ETYPE_WIDTH (16U) 510 #define NETC_F3_COMMON_CVLANR2_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_CVLANR2_ETYPE_SHIFT)) & NETC_F3_COMMON_CVLANR2_ETYPE_MASK) 511 512 #define NETC_F3_COMMON_CVLANR2_V_MASK (0x80000000U) 513 #define NETC_F3_COMMON_CVLANR2_V_SHIFT (31U) 514 #define NETC_F3_COMMON_CVLANR2_V_WIDTH (1U) 515 #define NETC_F3_COMMON_CVLANR2_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_CVLANR2_V_SHIFT)) & NETC_F3_COMMON_CVLANR2_V_MASK) 516 /*! @} */ 517 518 /*! @name DOSL2CR - DoS L2 configuration register */ 519 /*! @{ */ 520 521 #define NETC_F3_COMMON_DOSL2CR_SAMEADDR_MASK (0x1U) 522 #define NETC_F3_COMMON_DOSL2CR_SAMEADDR_SHIFT (0U) 523 #define NETC_F3_COMMON_DOSL2CR_SAMEADDR_WIDTH (1U) 524 #define NETC_F3_COMMON_DOSL2CR_SAMEADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_DOSL2CR_SAMEADDR_SHIFT)) & NETC_F3_COMMON_DOSL2CR_SAMEADDR_MASK) 525 526 #define NETC_F3_COMMON_DOSL2CR_MSAMCC_MASK (0x2U) 527 #define NETC_F3_COMMON_DOSL2CR_MSAMCC_SHIFT (1U) 528 #define NETC_F3_COMMON_DOSL2CR_MSAMCC_WIDTH (1U) 529 #define NETC_F3_COMMON_DOSL2CR_MSAMCC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_DOSL2CR_MSAMCC_SHIFT)) & NETC_F3_COMMON_DOSL2CR_MSAMCC_MASK) 530 /*! @} */ 531 532 /*! @name VLANIPVMPR0 - VLAN to IPV mapping profile 0 register 0 */ 533 /*! @{ */ 534 535 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_0_MASK (0x7U) 536 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_0_SHIFT (0U) 537 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_0_WIDTH (3U) 538 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_0_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_0_MASK) 539 540 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_1_MASK (0x70U) 541 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_1_SHIFT (4U) 542 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_1_WIDTH (3U) 543 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_1_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_1_MASK) 544 545 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_2_MASK (0x700U) 546 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_2_SHIFT (8U) 547 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_2_WIDTH (3U) 548 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_2_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_2_MASK) 549 550 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_3_MASK (0x7000U) 551 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_3_SHIFT (12U) 552 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_3_WIDTH (3U) 553 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_3_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_3_MASK) 554 555 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_4_MASK (0x70000U) 556 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_4_SHIFT (16U) 557 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_4_WIDTH (3U) 558 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_4_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_4_MASK) 559 560 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_5_MASK (0x700000U) 561 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_5_SHIFT (20U) 562 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_5_WIDTH (3U) 563 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_5_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_5_MASK) 564 565 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_6_MASK (0x7000000U) 566 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_6_SHIFT (24U) 567 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_6_WIDTH (3U) 568 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_6_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_6_MASK) 569 570 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_7_MASK (0x70000000U) 571 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_7_SHIFT (28U) 572 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_7_WIDTH (3U) 573 #define NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_7_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR0_PCP_DEI_7_MASK) 574 /*! @} */ 575 576 /*! @name VLANIPVMPR1 - VLAN to IPV mapping profile 0 register 1 */ 577 /*! @{ */ 578 579 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_8_MASK (0x7U) 580 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_8_SHIFT (0U) 581 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_8_WIDTH (3U) 582 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_8_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_8_MASK) 583 584 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_9_MASK (0x70U) 585 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_9_SHIFT (4U) 586 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_9_WIDTH (3U) 587 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_9_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_9_MASK) 588 589 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_10_MASK (0x700U) 590 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_10_SHIFT (8U) 591 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_10_WIDTH (3U) 592 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_10_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_10_MASK) 593 594 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_11_MASK (0x7000U) 595 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_11_SHIFT (12U) 596 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_11_WIDTH (3U) 597 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_11_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_11_MASK) 598 599 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_12_MASK (0x70000U) 600 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_12_SHIFT (16U) 601 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_12_WIDTH (3U) 602 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_12_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_12_MASK) 603 604 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_13_MASK (0x700000U) 605 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_13_SHIFT (20U) 606 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_13_WIDTH (3U) 607 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_13_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_13_MASK) 608 609 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_14_MASK (0x7000000U) 610 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_14_SHIFT (24U) 611 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_14_WIDTH (3U) 612 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_14_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_14_MASK) 613 614 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_15_MASK (0x70000000U) 615 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_15_SHIFT (28U) 616 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_15_WIDTH (3U) 617 #define NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_15_SHIFT)) & NETC_F3_COMMON_VLANIPVMPR1_PCP_DEI_15_MASK) 618 /*! @} */ 619 620 /*! @name VLANDRMPR - VLAN to DR mapping profile 0 register */ 621 /*! @{ */ 622 623 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_0_MASK (0x3U) 624 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_0_SHIFT (0U) 625 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_0_WIDTH (2U) 626 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_0_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_0_MASK) 627 628 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_1_MASK (0xCU) 629 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_1_SHIFT (2U) 630 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_1_WIDTH (2U) 631 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_1_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_1_MASK) 632 633 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_2_MASK (0x30U) 634 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_2_SHIFT (4U) 635 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_2_WIDTH (2U) 636 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_2_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_2_MASK) 637 638 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_3_MASK (0xC0U) 639 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_3_SHIFT (6U) 640 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_3_WIDTH (2U) 641 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_3_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_3_MASK) 642 643 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_4_MASK (0x300U) 644 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_4_SHIFT (8U) 645 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_4_WIDTH (2U) 646 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_4_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_4_MASK) 647 648 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_5_MASK (0xC00U) 649 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_5_SHIFT (10U) 650 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_5_WIDTH (2U) 651 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_5_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_5_MASK) 652 653 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_6_MASK (0x3000U) 654 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_6_SHIFT (12U) 655 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_6_WIDTH (2U) 656 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_6_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_6_MASK) 657 658 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_7_MASK (0xC000U) 659 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_7_SHIFT (14U) 660 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_7_WIDTH (2U) 661 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_7_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_7_MASK) 662 663 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_8_MASK (0x30000U) 664 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_8_SHIFT (16U) 665 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_8_WIDTH (2U) 666 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_8_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_8_MASK) 667 668 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_9_MASK (0xC0000U) 669 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_9_SHIFT (18U) 670 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_9_WIDTH (2U) 671 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_9_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_9_MASK) 672 673 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_10_MASK (0x300000U) 674 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_10_SHIFT (20U) 675 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_10_WIDTH (2U) 676 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_10_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_10_MASK) 677 678 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_11_MASK (0xC00000U) 679 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_11_SHIFT (22U) 680 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_11_WIDTH (2U) 681 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_11_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_11_MASK) 682 683 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_12_MASK (0x3000000U) 684 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_12_SHIFT (24U) 685 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_12_WIDTH (2U) 686 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_12_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_12_MASK) 687 688 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_13_MASK (0xC000000U) 689 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_13_SHIFT (26U) 690 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_13_WIDTH (2U) 691 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_13_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_13_MASK) 692 693 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_14_MASK (0x30000000U) 694 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_14_SHIFT (28U) 695 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_14_WIDTH (2U) 696 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_14_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_14_MASK) 697 698 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_15_MASK (0xC0000000U) 699 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_15_SHIFT (30U) 700 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_15_WIDTH (2U) 701 #define NETC_F3_COMMON_VLANDRMPR_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_VLANDRMPR_PCP_DEI_15_SHIFT)) & NETC_F3_COMMON_VLANDRMPR_PCP_DEI_15_MASK) 702 /*! @} */ 703 704 /*! @name IPFCAPR - Ingress port filter capability register */ 705 /*! @{ */ 706 707 #define NETC_F3_COMMON_IPFCAPR_RP_MASK (0x1U) 708 #define NETC_F3_COMMON_IPFCAPR_RP_SHIFT (0U) 709 #define NETC_F3_COMMON_IPFCAPR_RP_WIDTH (1U) 710 #define NETC_F3_COMMON_IPFCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFCAPR_RP_SHIFT)) & NETC_F3_COMMON_IPFCAPR_RP_MASK) 711 712 #define NETC_F3_COMMON_IPFCAPR_ISID_MASK (0x2U) 713 #define NETC_F3_COMMON_IPFCAPR_ISID_SHIFT (1U) 714 #define NETC_F3_COMMON_IPFCAPR_ISID_WIDTH (1U) 715 #define NETC_F3_COMMON_IPFCAPR_ISID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFCAPR_ISID_SHIFT)) & NETC_F3_COMMON_IPFCAPR_ISID_MASK) 716 717 #define NETC_F3_COMMON_IPFCAPR_FWD_SI_MASK (0x4U) 718 #define NETC_F3_COMMON_IPFCAPR_FWD_SI_SHIFT (2U) 719 #define NETC_F3_COMMON_IPFCAPR_FWD_SI_WIDTH (1U) 720 #define NETC_F3_COMMON_IPFCAPR_FWD_SI(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFCAPR_FWD_SI_SHIFT)) & NETC_F3_COMMON_IPFCAPR_FWD_SI_MASK) 721 722 #define NETC_F3_COMMON_IPFCAPR_WOL_MASK (0x8U) 723 #define NETC_F3_COMMON_IPFCAPR_WOL_SHIFT (3U) 724 #define NETC_F3_COMMON_IPFCAPR_WOL_WIDTH (1U) 725 #define NETC_F3_COMMON_IPFCAPR_WOL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFCAPR_WOL_SHIFT)) & NETC_F3_COMMON_IPFCAPR_WOL_MASK) 726 /*! @} */ 727 728 /*! @name IPFTCAPR - Ingress port filter table capability register */ 729 /*! @{ */ 730 731 #define NETC_F3_COMMON_IPFTCAPR_NUM_WORDS_MASK (0xFFFFU) 732 #define NETC_F3_COMMON_IPFTCAPR_NUM_WORDS_SHIFT (0U) 733 #define NETC_F3_COMMON_IPFTCAPR_NUM_WORDS_WIDTH (16U) 734 #define NETC_F3_COMMON_IPFTCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFTCAPR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_IPFTCAPR_NUM_WORDS_MASK) 735 736 #define NETC_F3_COMMON_IPFTCAPR_MGMT_MASK (0x10000U) 737 #define NETC_F3_COMMON_IPFTCAPR_MGMT_SHIFT (16U) 738 #define NETC_F3_COMMON_IPFTCAPR_MGMT_WIDTH (1U) 739 #define NETC_F3_COMMON_IPFTCAPR_MGMT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFTCAPR_MGMT_SHIFT)) & NETC_F3_COMMON_IPFTCAPR_MGMT_MASK) 740 741 #define NETC_F3_COMMON_IPFTCAPR_ACCESS_METH_MASK (0xF00000U) 742 #define NETC_F3_COMMON_IPFTCAPR_ACCESS_METH_SHIFT (20U) 743 #define NETC_F3_COMMON_IPFTCAPR_ACCESS_METH_WIDTH (4U) 744 #define NETC_F3_COMMON_IPFTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFTCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_IPFTCAPR_ACCESS_METH_MASK) 745 746 #define NETC_F3_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_MASK (0xF000000U) 747 #define NETC_F3_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_SHIFT (24U) 748 #define NETC_F3_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_WIDTH (4U) 749 #define NETC_F3_COMMON_IPFTCAPR_ENTRY_MAX_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_SHIFT)) & NETC_F3_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_MASK) 750 751 #define NETC_F3_COMMON_IPFTCAPR_WORD_SIZE_MASK (0x30000000U) 752 #define NETC_F3_COMMON_IPFTCAPR_WORD_SIZE_SHIFT (28U) 753 #define NETC_F3_COMMON_IPFTCAPR_WORD_SIZE_WIDTH (2U) 754 #define NETC_F3_COMMON_IPFTCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFTCAPR_WORD_SIZE_SHIFT)) & NETC_F3_COMMON_IPFTCAPR_WORD_SIZE_MASK) 755 /*! @} */ 756 757 /*! @name IPFTMOR - Ingress port filter table memory operational register */ 758 /*! @{ */ 759 760 #define NETC_F3_COMMON_IPFTMOR_NUM_WORDS_MASK (0xFFFFU) 761 #define NETC_F3_COMMON_IPFTMOR_NUM_WORDS_SHIFT (0U) 762 #define NETC_F3_COMMON_IPFTMOR_NUM_WORDS_WIDTH (16U) 763 #define NETC_F3_COMMON_IPFTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_IPFTMOR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_IPFTMOR_NUM_WORDS_MASK) 764 /*! @} */ 765 766 /*! @name ITMCAPR - Index table memory capability register */ 767 /*! @{ */ 768 769 #define NETC_F3_COMMON_ITMCAPR_NUM_WORDS_MASK (0xFFFFU) 770 #define NETC_F3_COMMON_ITMCAPR_NUM_WORDS_SHIFT (0U) 771 #define NETC_F3_COMMON_ITMCAPR_NUM_WORDS_WIDTH (16U) 772 #define NETC_F3_COMMON_ITMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ITMCAPR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_ITMCAPR_NUM_WORDS_MASK) 773 774 #define NETC_F3_COMMON_ITMCAPR_WORD_SIZE_MASK (0x30000000U) 775 #define NETC_F3_COMMON_ITMCAPR_WORD_SIZE_SHIFT (28U) 776 #define NETC_F3_COMMON_ITMCAPR_WORD_SIZE_WIDTH (2U) 777 #define NETC_F3_COMMON_ITMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ITMCAPR_WORD_SIZE_SHIFT)) & NETC_F3_COMMON_ITMCAPR_WORD_SIZE_MASK) 778 779 #define NETC_F3_COMMON_ITMCAPR_MLOC_MASK (0xC0000000U) 780 #define NETC_F3_COMMON_ITMCAPR_MLOC_SHIFT (30U) 781 #define NETC_F3_COMMON_ITMCAPR_MLOC_WIDTH (2U) 782 #define NETC_F3_COMMON_ITMCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ITMCAPR_MLOC_SHIFT)) & NETC_F3_COMMON_ITMCAPR_MLOC_MASK) 783 /*! @} */ 784 785 /*! @name RPCAPR - Rate policer capability register */ 786 /*! @{ */ 787 788 #define NETC_F3_COMMON_RPCAPR_TRTCM_MASK (0x1U) 789 #define NETC_F3_COMMON_RPCAPR_TRTCM_SHIFT (0U) 790 #define NETC_F3_COMMON_RPCAPR_TRTCM_WIDTH (1U) 791 #define NETC_F3_COMMON_RPCAPR_TRTCM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_RPCAPR_TRTCM_SHIFT)) & NETC_F3_COMMON_RPCAPR_TRTCM_MASK) 792 793 #define NETC_F3_COMMON_RPCAPR_CM_MASK (0x2U) 794 #define NETC_F3_COMMON_RPCAPR_CM_SHIFT (1U) 795 #define NETC_F3_COMMON_RPCAPR_CM_WIDTH (1U) 796 #define NETC_F3_COMMON_RPCAPR_CM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_RPCAPR_CM_SHIFT)) & NETC_F3_COMMON_RPCAPR_CM_MASK) 797 /*! @} */ 798 799 /*! @name RPITCAPR - Rate policer index table capability register */ 800 /*! @{ */ 801 802 #define NETC_F3_COMMON_RPITCAPR_NUM_ENTRIES_MASK (0x3FFFU) 803 #define NETC_F3_COMMON_RPITCAPR_NUM_ENTRIES_SHIFT (0U) 804 #define NETC_F3_COMMON_RPITCAPR_NUM_ENTRIES_WIDTH (14U) 805 #define NETC_F3_COMMON_RPITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_RPITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_RPITCAPR_NUM_ENTRIES_MASK) 806 807 #define NETC_F3_COMMON_RPITCAPR_ACCESS_METH_MASK (0xF00000U) 808 #define NETC_F3_COMMON_RPITCAPR_ACCESS_METH_SHIFT (20U) 809 #define NETC_F3_COMMON_RPITCAPR_ACCESS_METH_WIDTH (4U) 810 #define NETC_F3_COMMON_RPITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_RPITCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_RPITCAPR_ACCESS_METH_MASK) 811 /*! @} */ 812 813 /*! @name RPITMAR - Rate policer index table memory allocation register */ 814 /*! @{ */ 815 816 #define NETC_F3_COMMON_RPITMAR_NUM_WORDS_MASK (0xFFFFU) 817 #define NETC_F3_COMMON_RPITMAR_NUM_WORDS_SHIFT (0U) 818 #define NETC_F3_COMMON_RPITMAR_NUM_WORDS_WIDTH (16U) 819 #define NETC_F3_COMMON_RPITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_RPITMAR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_RPITMAR_NUM_WORDS_MASK) 820 /*! @} */ 821 822 /*! @name RPITOR - Rate policer index table operational register */ 823 /*! @{ */ 824 825 #define NETC_F3_COMMON_RPITOR_NUM_ENTRIES_MASK (0x3FFFU) 826 #define NETC_F3_COMMON_RPITOR_NUM_ENTRIES_SHIFT (0U) 827 #define NETC_F3_COMMON_RPITOR_NUM_ENTRIES_WIDTH (14U) 828 #define NETC_F3_COMMON_RPITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_RPITOR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_RPITOR_NUM_ENTRIES_MASK) 829 /*! @} */ 830 831 /*! @name ISCITCAPR - Ingress stream counter index table capability register */ 832 /*! @{ */ 833 834 #define NETC_F3_COMMON_ISCITCAPR_NUM_ENTRIES_MASK (0xFFFFU) 835 #define NETC_F3_COMMON_ISCITCAPR_NUM_ENTRIES_SHIFT (0U) 836 #define NETC_F3_COMMON_ISCITCAPR_NUM_ENTRIES_WIDTH (16U) 837 #define NETC_F3_COMMON_ISCITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISCITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_ISCITCAPR_NUM_ENTRIES_MASK) 838 839 #define NETC_F3_COMMON_ISCITCAPR_ACCESS_METH_MASK (0xF00000U) 840 #define NETC_F3_COMMON_ISCITCAPR_ACCESS_METH_SHIFT (20U) 841 #define NETC_F3_COMMON_ISCITCAPR_ACCESS_METH_WIDTH (4U) 842 #define NETC_F3_COMMON_ISCITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISCITCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_ISCITCAPR_ACCESS_METH_MASK) 843 /*! @} */ 844 845 /*! @name ISCITMAR - Ingress stream counter index table memory allocation register */ 846 /*! @{ */ 847 848 #define NETC_F3_COMMON_ISCITMAR_NUM_WORDS_MASK (0xFFFFU) 849 #define NETC_F3_COMMON_ISCITMAR_NUM_WORDS_SHIFT (0U) 850 #define NETC_F3_COMMON_ISCITMAR_NUM_WORDS_WIDTH (16U) 851 #define NETC_F3_COMMON_ISCITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISCITMAR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_ISCITMAR_NUM_WORDS_MASK) 852 /*! @} */ 853 854 /*! @name ISCITOR - Ingress stream counter index table operational register */ 855 /*! @{ */ 856 857 #define NETC_F3_COMMON_ISCITOR_NUM_ENTRIES_MASK (0xFFFFU) 858 #define NETC_F3_COMMON_ISCITOR_NUM_ENTRIES_SHIFT (0U) 859 #define NETC_F3_COMMON_ISCITOR_NUM_ENTRIES_WIDTH (16U) 860 #define NETC_F3_COMMON_ISCITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISCITOR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_ISCITOR_NUM_ENTRIES_MASK) 861 /*! @} */ 862 863 /*! @name ISCAPR - Ingress stream capability register */ 864 /*! @{ */ 865 866 #define NETC_F3_COMMON_ISCAPR_SG_MASK (0x8U) 867 #define NETC_F3_COMMON_ISCAPR_SG_SHIFT (3U) 868 #define NETC_F3_COMMON_ISCAPR_SG_WIDTH (1U) 869 #define NETC_F3_COMMON_ISCAPR_SG(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISCAPR_SG_SHIFT)) & NETC_F3_COMMON_ISCAPR_SG_MASK) 870 871 #define NETC_F3_COMMON_ISCAPR_RP_MASK (0x10U) 872 #define NETC_F3_COMMON_ISCAPR_RP_SHIFT (4U) 873 #define NETC_F3_COMMON_ISCAPR_RP_WIDTH (1U) 874 #define NETC_F3_COMMON_ISCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISCAPR_RP_SHIFT)) & NETC_F3_COMMON_ISCAPR_RP_MASK) 875 876 #define NETC_F3_COMMON_ISCAPR_MAXSDU_MASK (0x20U) 877 #define NETC_F3_COMMON_ISCAPR_MAXSDU_SHIFT (5U) 878 #define NETC_F3_COMMON_ISCAPR_MAXSDU_WIDTH (1U) 879 #define NETC_F3_COMMON_ISCAPR_MAXSDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISCAPR_MAXSDU_SHIFT)) & NETC_F3_COMMON_ISCAPR_MAXSDU_MASK) 880 881 #define NETC_F3_COMMON_ISCAPR_FWD_MASK (0x200U) 882 #define NETC_F3_COMMON_ISCAPR_FWD_SHIFT (9U) 883 #define NETC_F3_COMMON_ISCAPR_FWD_WIDTH (1U) 884 #define NETC_F3_COMMON_ISCAPR_FWD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISCAPR_FWD_SHIFT)) & NETC_F3_COMMON_ISCAPR_FWD_MASK) 885 /*! @} */ 886 887 /*! @name ISITCAPR - Ingress stream index table capability register */ 888 /*! @{ */ 889 890 #define NETC_F3_COMMON_ISITCAPR_NUM_ENTRIES_MASK (0xFFFFU) 891 #define NETC_F3_COMMON_ISITCAPR_NUM_ENTRIES_SHIFT (0U) 892 #define NETC_F3_COMMON_ISITCAPR_NUM_ENTRIES_WIDTH (16U) 893 #define NETC_F3_COMMON_ISITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_ISITCAPR_NUM_ENTRIES_MASK) 894 895 #define NETC_F3_COMMON_ISITCAPR_ACCESS_METH_MASK (0xF00000U) 896 #define NETC_F3_COMMON_ISITCAPR_ACCESS_METH_SHIFT (20U) 897 #define NETC_F3_COMMON_ISITCAPR_ACCESS_METH_WIDTH (4U) 898 #define NETC_F3_COMMON_ISITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISITCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_ISITCAPR_ACCESS_METH_MASK) 899 /*! @} */ 900 901 /*! @name ISITMAR - Ingress stream index table memory allocation register */ 902 /*! @{ */ 903 904 #define NETC_F3_COMMON_ISITMAR_NUM_WORDS_MASK (0xFFFFU) 905 #define NETC_F3_COMMON_ISITMAR_NUM_WORDS_SHIFT (0U) 906 #define NETC_F3_COMMON_ISITMAR_NUM_WORDS_WIDTH (16U) 907 #define NETC_F3_COMMON_ISITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISITMAR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_ISITMAR_NUM_WORDS_MASK) 908 /*! @} */ 909 910 /*! @name ISITOR - Ingress stream index table operational register */ 911 /*! @{ */ 912 913 #define NETC_F3_COMMON_ISITOR_NUM_ENTRIES_MASK (0xFFFFU) 914 #define NETC_F3_COMMON_ISITOR_NUM_ENTRIES_SHIFT (0U) 915 #define NETC_F3_COMMON_ISITOR_NUM_ENTRIES_WIDTH (16U) 916 #define NETC_F3_COMMON_ISITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISITOR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_ISITOR_NUM_ENTRIES_MASK) 917 /*! @} */ 918 919 /*! @name SGCAPR - Stream gate capability register */ 920 /*! @{ */ 921 922 #define NETC_F3_COMMON_SGCAPR_GLC_AO_MASK (0x1U) 923 #define NETC_F3_COMMON_SGCAPR_GLC_AO_SHIFT (0U) 924 #define NETC_F3_COMMON_SGCAPR_GLC_AO_WIDTH (1U) 925 #define NETC_F3_COMMON_SGCAPR_GLC_AO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCAPR_GLC_AO_SHIFT)) & NETC_F3_COMMON_SGCAPR_GLC_AO_MASK) 926 927 #define NETC_F3_COMMON_SGCAPR_GLC_GC_MASK (0x2U) 928 #define NETC_F3_COMMON_SGCAPR_GLC_GC_SHIFT (1U) 929 #define NETC_F3_COMMON_SGCAPR_GLC_GC_WIDTH (1U) 930 #define NETC_F3_COMMON_SGCAPR_GLC_GC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCAPR_GLC_GC_SHIFT)) & NETC_F3_COMMON_SGCAPR_GLC_GC_MASK) 931 932 #define NETC_F3_COMMON_SGCAPR_GLC_IO_MASK (0x4U) 933 #define NETC_F3_COMMON_SGCAPR_GLC_IO_SHIFT (2U) 934 #define NETC_F3_COMMON_SGCAPR_GLC_IO_WIDTH (1U) 935 #define NETC_F3_COMMON_SGCAPR_GLC_IO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCAPR_GLC_IO_SHIFT)) & NETC_F3_COMMON_SGCAPR_GLC_IO_MASK) 936 937 #define NETC_F3_COMMON_SGCAPR_GLC_IPV_MASK (0x8U) 938 #define NETC_F3_COMMON_SGCAPR_GLC_IPV_SHIFT (3U) 939 #define NETC_F3_COMMON_SGCAPR_GLC_IPV_WIDTH (1U) 940 #define NETC_F3_COMMON_SGCAPR_GLC_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCAPR_GLC_IPV_SHIFT)) & NETC_F3_COMMON_SGCAPR_GLC_IPV_MASK) 941 942 #define NETC_F3_COMMON_SGCAPR_GLC_CTD_MASK (0x10U) 943 #define NETC_F3_COMMON_SGCAPR_GLC_CTD_SHIFT (4U) 944 #define NETC_F3_COMMON_SGCAPR_GLC_CTD_WIDTH (1U) 945 #define NETC_F3_COMMON_SGCAPR_GLC_CTD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCAPR_GLC_CTD_SHIFT)) & NETC_F3_COMMON_SGCAPR_GLC_CTD_MASK) 946 /*! @} */ 947 948 /*! @name SGIITCAPR - Stream gate instance index table capability register */ 949 /*! @{ */ 950 951 #define NETC_F3_COMMON_SGIITCAPR_NUM_ENTRIES_MASK (0xFFFFU) 952 #define NETC_F3_COMMON_SGIITCAPR_NUM_ENTRIES_SHIFT (0U) 953 #define NETC_F3_COMMON_SGIITCAPR_NUM_ENTRIES_WIDTH (16U) 954 #define NETC_F3_COMMON_SGIITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGIITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_SGIITCAPR_NUM_ENTRIES_MASK) 955 956 #define NETC_F3_COMMON_SGIITCAPR_ACCESS_METH_MASK (0xF00000U) 957 #define NETC_F3_COMMON_SGIITCAPR_ACCESS_METH_SHIFT (20U) 958 #define NETC_F3_COMMON_SGIITCAPR_ACCESS_METH_WIDTH (4U) 959 #define NETC_F3_COMMON_SGIITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGIITCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_SGIITCAPR_ACCESS_METH_MASK) 960 /*! @} */ 961 962 /*! @name SGIITMAR - Stream gate instance index table memory allocation register */ 963 /*! @{ */ 964 965 #define NETC_F3_COMMON_SGIITMAR_NUM_WORDS_MASK (0xFFFFU) 966 #define NETC_F3_COMMON_SGIITMAR_NUM_WORDS_SHIFT (0U) 967 #define NETC_F3_COMMON_SGIITMAR_NUM_WORDS_WIDTH (16U) 968 #define NETC_F3_COMMON_SGIITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGIITMAR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_SGIITMAR_NUM_WORDS_MASK) 969 /*! @} */ 970 971 /*! @name SGIITOR - Stream gate instance index table operational register */ 972 /*! @{ */ 973 974 #define NETC_F3_COMMON_SGIITOR_NUM_ENTRIES_MASK (0xFFFFU) 975 #define NETC_F3_COMMON_SGIITOR_NUM_ENTRIES_SHIFT (0U) 976 #define NETC_F3_COMMON_SGIITOR_NUM_ENTRIES_WIDTH (16U) 977 #define NETC_F3_COMMON_SGIITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGIITOR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_SGIITOR_NUM_ENTRIES_MASK) 978 /*! @} */ 979 980 /*! @name SGCLITCAPR - Stream gate control list index table capability register */ 981 /*! @{ */ 982 983 #define NETC_F3_COMMON_SGCLITCAPR_NUM_WORDS_MASK (0xFFFFU) 984 #define NETC_F3_COMMON_SGCLITCAPR_NUM_WORDS_SHIFT (0U) 985 #define NETC_F3_COMMON_SGCLITCAPR_NUM_WORDS_WIDTH (16U) 986 #define NETC_F3_COMMON_SGCLITCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCLITCAPR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_SGCLITCAPR_NUM_WORDS_MASK) 987 988 #define NETC_F3_COMMON_SGCLITCAPR_ACCESS_METH_MASK (0xF00000U) 989 #define NETC_F3_COMMON_SGCLITCAPR_ACCESS_METH_SHIFT (20U) 990 #define NETC_F3_COMMON_SGCLITCAPR_ACCESS_METH_WIDTH (4U) 991 #define NETC_F3_COMMON_SGCLITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCLITCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_SGCLITCAPR_ACCESS_METH_MASK) 992 /*! @} */ 993 994 /*! @name SGCLITMAR - Stream gate control list index table memory allocation register */ 995 /*! @{ */ 996 997 #define NETC_F3_COMMON_SGCLITMAR_NUM_WORDS_MASK (0xFFFFU) 998 #define NETC_F3_COMMON_SGCLITMAR_NUM_WORDS_SHIFT (0U) 999 #define NETC_F3_COMMON_SGCLITMAR_NUM_WORDS_WIDTH (16U) 1000 #define NETC_F3_COMMON_SGCLITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCLITMAR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_SGCLITMAR_NUM_WORDS_MASK) 1001 /*! @} */ 1002 1003 /*! @name SGCLTMOR - Stream gate control list table memory operational register */ 1004 /*! @{ */ 1005 1006 #define NETC_F3_COMMON_SGCLTMOR_NUM_WORDS_MASK (0xFFFFU) 1007 #define NETC_F3_COMMON_SGCLTMOR_NUM_WORDS_SHIFT (0U) 1008 #define NETC_F3_COMMON_SGCLTMOR_NUM_WORDS_WIDTH (16U) 1009 #define NETC_F3_COMMON_SGCLTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_SGCLTMOR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_SGCLTMOR_NUM_WORDS_MASK) 1010 /*! @} */ 1011 1012 /*! @name TGSTCAPR - Time gate scheduling table capability register */ 1013 /*! @{ */ 1014 1015 #define NETC_F3_COMMON_TGSTCAPR_NUM_WORDS_MASK (0xFFFFU) 1016 #define NETC_F3_COMMON_TGSTCAPR_NUM_WORDS_SHIFT (0U) 1017 #define NETC_F3_COMMON_TGSTCAPR_NUM_WORDS_WIDTH (16U) 1018 #define NETC_F3_COMMON_TGSTCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_TGSTCAPR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_TGSTCAPR_NUM_WORDS_MASK) 1019 1020 #define NETC_F3_COMMON_TGSTCAPR_ACCESS_METH_MASK (0xF00000U) 1021 #define NETC_F3_COMMON_TGSTCAPR_ACCESS_METH_SHIFT (20U) 1022 #define NETC_F3_COMMON_TGSTCAPR_ACCESS_METH_WIDTH (4U) 1023 #define NETC_F3_COMMON_TGSTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_TGSTCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_TGSTCAPR_ACCESS_METH_MASK) 1024 1025 #define NETC_F3_COMMON_TGSTCAPR_MAX_GCL_LEN_MASK (0x3000000U) 1026 #define NETC_F3_COMMON_TGSTCAPR_MAX_GCL_LEN_SHIFT (24U) 1027 #define NETC_F3_COMMON_TGSTCAPR_MAX_GCL_LEN_WIDTH (2U) 1028 #define NETC_F3_COMMON_TGSTCAPR_MAX_GCL_LEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_TGSTCAPR_MAX_GCL_LEN_SHIFT)) & NETC_F3_COMMON_TGSTCAPR_MAX_GCL_LEN_MASK) 1029 /*! @} */ 1030 1031 /*! @name TGSTMOR - Time gate scheduling table memory operation register */ 1032 /*! @{ */ 1033 1034 #define NETC_F3_COMMON_TGSTMOR_NUM_WORDS_MASK (0xFFFFU) 1035 #define NETC_F3_COMMON_TGSTMOR_NUM_WORDS_SHIFT (0U) 1036 #define NETC_F3_COMMON_TGSTMOR_NUM_WORDS_WIDTH (16U) 1037 #define NETC_F3_COMMON_TGSTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_TGSTMOR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_TGSTMOR_NUM_WORDS_MASK) 1038 /*! @} */ 1039 1040 /*! @name HTMCAPR - Hash table memory capability register */ 1041 /*! @{ */ 1042 1043 #define NETC_F3_COMMON_HTMCAPR_NUM_WORDS_MASK (0xFFFFU) 1044 #define NETC_F3_COMMON_HTMCAPR_NUM_WORDS_SHIFT (0U) 1045 #define NETC_F3_COMMON_HTMCAPR_NUM_WORDS_WIDTH (16U) 1046 #define NETC_F3_COMMON_HTMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_HTMCAPR_NUM_WORDS_SHIFT)) & NETC_F3_COMMON_HTMCAPR_NUM_WORDS_MASK) 1047 1048 #define NETC_F3_COMMON_HTMCAPR_WORD_SIZE_MASK (0x30000000U) 1049 #define NETC_F3_COMMON_HTMCAPR_WORD_SIZE_SHIFT (28U) 1050 #define NETC_F3_COMMON_HTMCAPR_WORD_SIZE_WIDTH (2U) 1051 #define NETC_F3_COMMON_HTMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_HTMCAPR_WORD_SIZE_SHIFT)) & NETC_F3_COMMON_HTMCAPR_WORD_SIZE_MASK) 1052 1053 #define NETC_F3_COMMON_HTMCAPR_MLOC_MASK (0xC0000000U) 1054 #define NETC_F3_COMMON_HTMCAPR_MLOC_SHIFT (30U) 1055 #define NETC_F3_COMMON_HTMCAPR_MLOC_WIDTH (2U) 1056 #define NETC_F3_COMMON_HTMCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_HTMCAPR_MLOC_SHIFT)) & NETC_F3_COMMON_HTMCAPR_MLOC_MASK) 1057 /*! @} */ 1058 1059 /*! @name HTMOR - Hash table memory operational register */ 1060 /*! @{ */ 1061 1062 #define NETC_F3_COMMON_HTMOR_AMOUNT_MASK (0xFFFFU) 1063 #define NETC_F3_COMMON_HTMOR_AMOUNT_SHIFT (0U) 1064 #define NETC_F3_COMMON_HTMOR_AMOUNT_WIDTH (16U) 1065 #define NETC_F3_COMMON_HTMOR_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_HTMOR_AMOUNT_SHIFT)) & NETC_F3_COMMON_HTMOR_AMOUNT_MASK) 1066 1067 #define NETC_F3_COMMON_HTMOR_WATERMARK_MASK (0xFFFF0000U) 1068 #define NETC_F3_COMMON_HTMOR_WATERMARK_SHIFT (16U) 1069 #define NETC_F3_COMMON_HTMOR_WATERMARK_WIDTH (16U) 1070 #define NETC_F3_COMMON_HTMOR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_HTMOR_WATERMARK_SHIFT)) & NETC_F3_COMMON_HTMOR_WATERMARK_MASK) 1071 /*! @} */ 1072 1073 /*! @name ISIDCAPR - Ingress stream identification capability register */ 1074 /*! @{ */ 1075 1076 #define NETC_F3_COMMON_ISIDCAPR_NUM_KC_MASK (0x3U) 1077 #define NETC_F3_COMMON_ISIDCAPR_NUM_KC_SHIFT (0U) 1078 #define NETC_F3_COMMON_ISIDCAPR_NUM_KC_WIDTH (2U) 1079 #define NETC_F3_COMMON_ISIDCAPR_NUM_KC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDCAPR_NUM_KC_SHIFT)) & NETC_F3_COMMON_ISIDCAPR_NUM_KC_MASK) 1080 1081 #define NETC_F3_COMMON_ISIDCAPR_NUM_PF_MASK (0x1CU) 1082 #define NETC_F3_COMMON_ISIDCAPR_NUM_PF_SHIFT (2U) 1083 #define NETC_F3_COMMON_ISIDCAPR_NUM_PF_WIDTH (3U) 1084 #define NETC_F3_COMMON_ISIDCAPR_NUM_PF(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDCAPR_NUM_PF_SHIFT)) & NETC_F3_COMMON_ISIDCAPR_NUM_PF_MASK) 1085 1086 #define NETC_F3_COMMON_ISIDCAPR_MAX_KSIZE_MASK (0x1F00U) 1087 #define NETC_F3_COMMON_ISIDCAPR_MAX_KSIZE_SHIFT (8U) 1088 #define NETC_F3_COMMON_ISIDCAPR_MAX_KSIZE_WIDTH (5U) 1089 #define NETC_F3_COMMON_ISIDCAPR_MAX_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDCAPR_MAX_KSIZE_SHIFT)) & NETC_F3_COMMON_ISIDCAPR_MAX_KSIZE_MASK) 1090 1091 #define NETC_F3_COMMON_ISIDCAPR_UFT_MASK (0x10000U) 1092 #define NETC_F3_COMMON_ISIDCAPR_UFT_SHIFT (16U) 1093 #define NETC_F3_COMMON_ISIDCAPR_UFT_WIDTH (1U) 1094 #define NETC_F3_COMMON_ISIDCAPR_UFT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDCAPR_UFT_SHIFT)) & NETC_F3_COMMON_ISIDCAPR_UFT_MASK) 1095 1096 #define NETC_F3_COMMON_ISIDCAPR_ETHFT_MASK (0x20000U) 1097 #define NETC_F3_COMMON_ISIDCAPR_ETHFT_SHIFT (17U) 1098 #define NETC_F3_COMMON_ISIDCAPR_ETHFT_WIDTH (1U) 1099 #define NETC_F3_COMMON_ISIDCAPR_ETHFT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDCAPR_ETHFT_SHIFT)) & NETC_F3_COMMON_ISIDCAPR_ETHFT_MASK) 1100 /*! @} */ 1101 1102 /*! @name ISIDHTCAPR - Ingress stream identification hash table capability register */ 1103 /*! @{ */ 1104 1105 #define NETC_F3_COMMON_ISIDHTCAPR_ACCESS_METH_MASK (0xF00000U) 1106 #define NETC_F3_COMMON_ISIDHTCAPR_ACCESS_METH_SHIFT (20U) 1107 #define NETC_F3_COMMON_ISIDHTCAPR_ACCESS_METH_WIDTH (4U) 1108 #define NETC_F3_COMMON_ISIDHTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDHTCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_ISIDHTCAPR_ACCESS_METH_MASK) 1109 /*! @} */ 1110 1111 /*! @name ISIDKC0OR - Ingress stream identification key construction 0 operational register */ 1112 /*! @{ */ 1113 1114 #define NETC_F3_COMMON_ISIDKC0OR_NUM_ENTRIES_MASK (0xFFFFU) 1115 #define NETC_F3_COMMON_ISIDKC0OR_NUM_ENTRIES_SHIFT (0U) 1116 #define NETC_F3_COMMON_ISIDKC0OR_NUM_ENTRIES_WIDTH (16U) 1117 #define NETC_F3_COMMON_ISIDKC0OR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0OR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_ISIDKC0OR_NUM_ENTRIES_MASK) 1118 1119 #define NETC_F3_COMMON_ISIDKC0OR_EN_MASK (0x80000000U) 1120 #define NETC_F3_COMMON_ISIDKC0OR_EN_SHIFT (31U) 1121 #define NETC_F3_COMMON_ISIDKC0OR_EN_WIDTH (1U) 1122 #define NETC_F3_COMMON_ISIDKC0OR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0OR_EN_SHIFT)) & NETC_F3_COMMON_ISIDKC0OR_EN_MASK) 1123 /*! @} */ 1124 1125 /*! @name ISIDKC0CR0 - Ingress stream identification key construction 0 configuration register 0 */ 1126 /*! @{ */ 1127 1128 #define NETC_F3_COMMON_ISIDKC0CR0_VALID_MASK (0x1U) 1129 #define NETC_F3_COMMON_ISIDKC0CR0_VALID_SHIFT (0U) 1130 #define NETC_F3_COMMON_ISIDKC0CR0_VALID_WIDTH (1U) 1131 #define NETC_F3_COMMON_ISIDKC0CR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_VALID_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_VALID_MASK) 1132 1133 #define NETC_F3_COMMON_ISIDKC0CR0_PORTP_MASK (0x2U) 1134 #define NETC_F3_COMMON_ISIDKC0CR0_PORTP_SHIFT (1U) 1135 #define NETC_F3_COMMON_ISIDKC0CR0_PORTP_WIDTH (1U) 1136 #define NETC_F3_COMMON_ISIDKC0CR0_PORTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_PORTP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_PORTP_MASK) 1137 1138 #define NETC_F3_COMMON_ISIDKC0CR0_SPMP_MASK (0x4U) 1139 #define NETC_F3_COMMON_ISIDKC0CR0_SPMP_SHIFT (2U) 1140 #define NETC_F3_COMMON_ISIDKC0CR0_SPMP_WIDTH (1U) 1141 #define NETC_F3_COMMON_ISIDKC0CR0_SPMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_SPMP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_SPMP_MASK) 1142 1143 #define NETC_F3_COMMON_ISIDKC0CR0_DMACP_MASK (0x8U) 1144 #define NETC_F3_COMMON_ISIDKC0CR0_DMACP_SHIFT (3U) 1145 #define NETC_F3_COMMON_ISIDKC0CR0_DMACP_WIDTH (1U) 1146 #define NETC_F3_COMMON_ISIDKC0CR0_DMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_DMACP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_DMACP_MASK) 1147 1148 #define NETC_F3_COMMON_ISIDKC0CR0_SMACP_MASK (0x10U) 1149 #define NETC_F3_COMMON_ISIDKC0CR0_SMACP_SHIFT (4U) 1150 #define NETC_F3_COMMON_ISIDKC0CR0_SMACP_WIDTH (1U) 1151 #define NETC_F3_COMMON_ISIDKC0CR0_SMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_SMACP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_SMACP_MASK) 1152 1153 #define NETC_F3_COMMON_ISIDKC0CR0_OVIDP_MASK (0x20U) 1154 #define NETC_F3_COMMON_ISIDKC0CR0_OVIDP_SHIFT (5U) 1155 #define NETC_F3_COMMON_ISIDKC0CR0_OVIDP_WIDTH (1U) 1156 #define NETC_F3_COMMON_ISIDKC0CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_OVIDP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_OVIDP_MASK) 1157 1158 #define NETC_F3_COMMON_ISIDKC0CR0_OPCPP_MASK (0x40U) 1159 #define NETC_F3_COMMON_ISIDKC0CR0_OPCPP_SHIFT (6U) 1160 #define NETC_F3_COMMON_ISIDKC0CR0_OPCPP_WIDTH (1U) 1161 #define NETC_F3_COMMON_ISIDKC0CR0_OPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_OPCPP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_OPCPP_MASK) 1162 1163 #define NETC_F3_COMMON_ISIDKC0CR0_IVIDP_MASK (0x80U) 1164 #define NETC_F3_COMMON_ISIDKC0CR0_IVIDP_SHIFT (7U) 1165 #define NETC_F3_COMMON_ISIDKC0CR0_IVIDP_WIDTH (1U) 1166 #define NETC_F3_COMMON_ISIDKC0CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_IVIDP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_IVIDP_MASK) 1167 1168 #define NETC_F3_COMMON_ISIDKC0CR0_IPCPP_MASK (0x100U) 1169 #define NETC_F3_COMMON_ISIDKC0CR0_IPCPP_SHIFT (8U) 1170 #define NETC_F3_COMMON_ISIDKC0CR0_IPCPP_WIDTH (1U) 1171 #define NETC_F3_COMMON_ISIDKC0CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_IPCPP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_IPCPP_MASK) 1172 1173 #define NETC_F3_COMMON_ISIDKC0CR0_SQTP_MASK (0x200U) 1174 #define NETC_F3_COMMON_ISIDKC0CR0_SQTP_SHIFT (9U) 1175 #define NETC_F3_COMMON_ISIDKC0CR0_SQTP_WIDTH (1U) 1176 #define NETC_F3_COMMON_ISIDKC0CR0_SQTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_SQTP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_SQTP_MASK) 1177 1178 #define NETC_F3_COMMON_ISIDKC0CR0_ETP_MASK (0x400U) 1179 #define NETC_F3_COMMON_ISIDKC0CR0_ETP_SHIFT (10U) 1180 #define NETC_F3_COMMON_ISIDKC0CR0_ETP_WIDTH (1U) 1181 #define NETC_F3_COMMON_ISIDKC0CR0_ETP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0CR0_ETP_SHIFT)) & NETC_F3_COMMON_ISIDKC0CR0_ETP_MASK) 1182 /*! @} */ 1183 1184 /*! @name ISIDKC0PF0CR - Ingress stream identification key construction 0 payload field 0 configuration register */ 1185 /*! @{ */ 1186 1187 #define NETC_F3_COMMON_ISIDKC0PF0CR_PFP_MASK (0x1U) 1188 #define NETC_F3_COMMON_ISIDKC0PF0CR_PFP_SHIFT (0U) 1189 #define NETC_F3_COMMON_ISIDKC0PF0CR_PFP_WIDTH (1U) 1190 #define NETC_F3_COMMON_ISIDKC0PF0CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF0CR_PFP_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF0CR_PFP_MASK) 1191 1192 #define NETC_F3_COMMON_ISIDKC0PF0CR_NUM_BYTES_MASK (0x1EU) 1193 #define NETC_F3_COMMON_ISIDKC0PF0CR_NUM_BYTES_SHIFT (1U) 1194 #define NETC_F3_COMMON_ISIDKC0PF0CR_NUM_BYTES_WIDTH (4U) 1195 #define NETC_F3_COMMON_ISIDKC0PF0CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF0CR_NUM_BYTES_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF0CR_NUM_BYTES_MASK) 1196 1197 #define NETC_F3_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_MASK (0x7F00U) 1198 #define NETC_F3_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_SHIFT (8U) 1199 #define NETC_F3_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_WIDTH (7U) 1200 #define NETC_F3_COMMON_ISIDKC0PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_MASK) 1201 1202 #define NETC_F3_COMMON_ISIDKC0PF0CR_FBMASK_MASK (0x70000U) 1203 #define NETC_F3_COMMON_ISIDKC0PF0CR_FBMASK_SHIFT (16U) 1204 #define NETC_F3_COMMON_ISIDKC0PF0CR_FBMASK_WIDTH (3U) 1205 #define NETC_F3_COMMON_ISIDKC0PF0CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF0CR_FBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF0CR_FBMASK_MASK) 1206 1207 #define NETC_F3_COMMON_ISIDKC0PF0CR_LBMASK_MASK (0x700000U) 1208 #define NETC_F3_COMMON_ISIDKC0PF0CR_LBMASK_SHIFT (20U) 1209 #define NETC_F3_COMMON_ISIDKC0PF0CR_LBMASK_WIDTH (3U) 1210 #define NETC_F3_COMMON_ISIDKC0PF0CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF0CR_LBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF0CR_LBMASK_MASK) 1211 /*! @} */ 1212 1213 /*! @name ISIDKC0PF1CR - Ingress stream identification key construction 0 payload field 1 configuration register */ 1214 /*! @{ */ 1215 1216 #define NETC_F3_COMMON_ISIDKC0PF1CR_PFP_MASK (0x1U) 1217 #define NETC_F3_COMMON_ISIDKC0PF1CR_PFP_SHIFT (0U) 1218 #define NETC_F3_COMMON_ISIDKC0PF1CR_PFP_WIDTH (1U) 1219 #define NETC_F3_COMMON_ISIDKC0PF1CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF1CR_PFP_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF1CR_PFP_MASK) 1220 1221 #define NETC_F3_COMMON_ISIDKC0PF1CR_NUM_BYTES_MASK (0x1EU) 1222 #define NETC_F3_COMMON_ISIDKC0PF1CR_NUM_BYTES_SHIFT (1U) 1223 #define NETC_F3_COMMON_ISIDKC0PF1CR_NUM_BYTES_WIDTH (4U) 1224 #define NETC_F3_COMMON_ISIDKC0PF1CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF1CR_NUM_BYTES_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF1CR_NUM_BYTES_MASK) 1225 1226 #define NETC_F3_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_MASK (0x7F00U) 1227 #define NETC_F3_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_SHIFT (8U) 1228 #define NETC_F3_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_WIDTH (7U) 1229 #define NETC_F3_COMMON_ISIDKC0PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_MASK) 1230 1231 #define NETC_F3_COMMON_ISIDKC0PF1CR_FBMASK_MASK (0x70000U) 1232 #define NETC_F3_COMMON_ISIDKC0PF1CR_FBMASK_SHIFT (16U) 1233 #define NETC_F3_COMMON_ISIDKC0PF1CR_FBMASK_WIDTH (3U) 1234 #define NETC_F3_COMMON_ISIDKC0PF1CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF1CR_FBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF1CR_FBMASK_MASK) 1235 1236 #define NETC_F3_COMMON_ISIDKC0PF1CR_LBMASK_MASK (0x700000U) 1237 #define NETC_F3_COMMON_ISIDKC0PF1CR_LBMASK_SHIFT (20U) 1238 #define NETC_F3_COMMON_ISIDKC0PF1CR_LBMASK_WIDTH (3U) 1239 #define NETC_F3_COMMON_ISIDKC0PF1CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF1CR_LBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF1CR_LBMASK_MASK) 1240 /*! @} */ 1241 1242 /*! @name ISIDKC0PF2CR - Ingress stream identification key construction 0 payload field 2 configuration register */ 1243 /*! @{ */ 1244 1245 #define NETC_F3_COMMON_ISIDKC0PF2CR_PFP_MASK (0x1U) 1246 #define NETC_F3_COMMON_ISIDKC0PF2CR_PFP_SHIFT (0U) 1247 #define NETC_F3_COMMON_ISIDKC0PF2CR_PFP_WIDTH (1U) 1248 #define NETC_F3_COMMON_ISIDKC0PF2CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF2CR_PFP_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF2CR_PFP_MASK) 1249 1250 #define NETC_F3_COMMON_ISIDKC0PF2CR_NUM_BYTES_MASK (0x1EU) 1251 #define NETC_F3_COMMON_ISIDKC0PF2CR_NUM_BYTES_SHIFT (1U) 1252 #define NETC_F3_COMMON_ISIDKC0PF2CR_NUM_BYTES_WIDTH (4U) 1253 #define NETC_F3_COMMON_ISIDKC0PF2CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF2CR_NUM_BYTES_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF2CR_NUM_BYTES_MASK) 1254 1255 #define NETC_F3_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_MASK (0x7F00U) 1256 #define NETC_F3_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_SHIFT (8U) 1257 #define NETC_F3_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_WIDTH (7U) 1258 #define NETC_F3_COMMON_ISIDKC0PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_MASK) 1259 1260 #define NETC_F3_COMMON_ISIDKC0PF2CR_FBMASK_MASK (0x70000U) 1261 #define NETC_F3_COMMON_ISIDKC0PF2CR_FBMASK_SHIFT (16U) 1262 #define NETC_F3_COMMON_ISIDKC0PF2CR_FBMASK_WIDTH (3U) 1263 #define NETC_F3_COMMON_ISIDKC0PF2CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF2CR_FBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF2CR_FBMASK_MASK) 1264 1265 #define NETC_F3_COMMON_ISIDKC0PF2CR_LBMASK_MASK (0x700000U) 1266 #define NETC_F3_COMMON_ISIDKC0PF2CR_LBMASK_SHIFT (20U) 1267 #define NETC_F3_COMMON_ISIDKC0PF2CR_LBMASK_WIDTH (3U) 1268 #define NETC_F3_COMMON_ISIDKC0PF2CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF2CR_LBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF2CR_LBMASK_MASK) 1269 /*! @} */ 1270 1271 /*! @name ISIDKC0PF3CR - Ingress stream identification key construction 0 payload field 3 configuration register */ 1272 /*! @{ */ 1273 1274 #define NETC_F3_COMMON_ISIDKC0PF3CR_PFP_MASK (0x1U) 1275 #define NETC_F3_COMMON_ISIDKC0PF3CR_PFP_SHIFT (0U) 1276 #define NETC_F3_COMMON_ISIDKC0PF3CR_PFP_WIDTH (1U) 1277 #define NETC_F3_COMMON_ISIDKC0PF3CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF3CR_PFP_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF3CR_PFP_MASK) 1278 1279 #define NETC_F3_COMMON_ISIDKC0PF3CR_NUM_BYTES_MASK (0x1EU) 1280 #define NETC_F3_COMMON_ISIDKC0PF3CR_NUM_BYTES_SHIFT (1U) 1281 #define NETC_F3_COMMON_ISIDKC0PF3CR_NUM_BYTES_WIDTH (4U) 1282 #define NETC_F3_COMMON_ISIDKC0PF3CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF3CR_NUM_BYTES_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF3CR_NUM_BYTES_MASK) 1283 1284 #define NETC_F3_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_MASK (0x7F00U) 1285 #define NETC_F3_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_SHIFT (8U) 1286 #define NETC_F3_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_WIDTH (7U) 1287 #define NETC_F3_COMMON_ISIDKC0PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_MASK) 1288 1289 #define NETC_F3_COMMON_ISIDKC0PF3CR_FBMASK_MASK (0x70000U) 1290 #define NETC_F3_COMMON_ISIDKC0PF3CR_FBMASK_SHIFT (16U) 1291 #define NETC_F3_COMMON_ISIDKC0PF3CR_FBMASK_WIDTH (3U) 1292 #define NETC_F3_COMMON_ISIDKC0PF3CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF3CR_FBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF3CR_FBMASK_MASK) 1293 1294 #define NETC_F3_COMMON_ISIDKC0PF3CR_LBMASK_MASK (0x700000U) 1295 #define NETC_F3_COMMON_ISIDKC0PF3CR_LBMASK_SHIFT (20U) 1296 #define NETC_F3_COMMON_ISIDKC0PF3CR_LBMASK_WIDTH (3U) 1297 #define NETC_F3_COMMON_ISIDKC0PF3CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC0PF3CR_LBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC0PF3CR_LBMASK_MASK) 1298 /*! @} */ 1299 1300 /*! @name ISIDKC1OR - Ingress stream identification key construction 1 operational register */ 1301 /*! @{ */ 1302 1303 #define NETC_F3_COMMON_ISIDKC1OR_NUM_ENTRIES_MASK (0xFFFFU) 1304 #define NETC_F3_COMMON_ISIDKC1OR_NUM_ENTRIES_SHIFT (0U) 1305 #define NETC_F3_COMMON_ISIDKC1OR_NUM_ENTRIES_WIDTH (16U) 1306 #define NETC_F3_COMMON_ISIDKC1OR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1OR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_ISIDKC1OR_NUM_ENTRIES_MASK) 1307 1308 #define NETC_F3_COMMON_ISIDKC1OR_EN_MASK (0x80000000U) 1309 #define NETC_F3_COMMON_ISIDKC1OR_EN_SHIFT (31U) 1310 #define NETC_F3_COMMON_ISIDKC1OR_EN_WIDTH (1U) 1311 #define NETC_F3_COMMON_ISIDKC1OR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1OR_EN_SHIFT)) & NETC_F3_COMMON_ISIDKC1OR_EN_MASK) 1312 /*! @} */ 1313 1314 /*! @name ISIDKC1CR0 - Ingress stream identification key construction 1 configuration register 0 */ 1315 /*! @{ */ 1316 1317 #define NETC_F3_COMMON_ISIDKC1CR0_VALID_MASK (0x1U) 1318 #define NETC_F3_COMMON_ISIDKC1CR0_VALID_SHIFT (0U) 1319 #define NETC_F3_COMMON_ISIDKC1CR0_VALID_WIDTH (1U) 1320 #define NETC_F3_COMMON_ISIDKC1CR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_VALID_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_VALID_MASK) 1321 1322 #define NETC_F3_COMMON_ISIDKC1CR0_PORTP_MASK (0x2U) 1323 #define NETC_F3_COMMON_ISIDKC1CR0_PORTP_SHIFT (1U) 1324 #define NETC_F3_COMMON_ISIDKC1CR0_PORTP_WIDTH (1U) 1325 #define NETC_F3_COMMON_ISIDKC1CR0_PORTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_PORTP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_PORTP_MASK) 1326 1327 #define NETC_F3_COMMON_ISIDKC1CR0_SPMP_MASK (0x4U) 1328 #define NETC_F3_COMMON_ISIDKC1CR0_SPMP_SHIFT (2U) 1329 #define NETC_F3_COMMON_ISIDKC1CR0_SPMP_WIDTH (1U) 1330 #define NETC_F3_COMMON_ISIDKC1CR0_SPMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_SPMP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_SPMP_MASK) 1331 1332 #define NETC_F3_COMMON_ISIDKC1CR0_DMACP_MASK (0x8U) 1333 #define NETC_F3_COMMON_ISIDKC1CR0_DMACP_SHIFT (3U) 1334 #define NETC_F3_COMMON_ISIDKC1CR0_DMACP_WIDTH (1U) 1335 #define NETC_F3_COMMON_ISIDKC1CR0_DMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_DMACP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_DMACP_MASK) 1336 1337 #define NETC_F3_COMMON_ISIDKC1CR0_SMACP_MASK (0x10U) 1338 #define NETC_F3_COMMON_ISIDKC1CR0_SMACP_SHIFT (4U) 1339 #define NETC_F3_COMMON_ISIDKC1CR0_SMACP_WIDTH (1U) 1340 #define NETC_F3_COMMON_ISIDKC1CR0_SMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_SMACP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_SMACP_MASK) 1341 1342 #define NETC_F3_COMMON_ISIDKC1CR0_OVIDP_MASK (0x20U) 1343 #define NETC_F3_COMMON_ISIDKC1CR0_OVIDP_SHIFT (5U) 1344 #define NETC_F3_COMMON_ISIDKC1CR0_OVIDP_WIDTH (1U) 1345 #define NETC_F3_COMMON_ISIDKC1CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_OVIDP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_OVIDP_MASK) 1346 1347 #define NETC_F3_COMMON_ISIDKC1CR0_OPCPP_MASK (0x40U) 1348 #define NETC_F3_COMMON_ISIDKC1CR0_OPCPP_SHIFT (6U) 1349 #define NETC_F3_COMMON_ISIDKC1CR0_OPCPP_WIDTH (1U) 1350 #define NETC_F3_COMMON_ISIDKC1CR0_OPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_OPCPP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_OPCPP_MASK) 1351 1352 #define NETC_F3_COMMON_ISIDKC1CR0_IVIDP_MASK (0x80U) 1353 #define NETC_F3_COMMON_ISIDKC1CR0_IVIDP_SHIFT (7U) 1354 #define NETC_F3_COMMON_ISIDKC1CR0_IVIDP_WIDTH (1U) 1355 #define NETC_F3_COMMON_ISIDKC1CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_IVIDP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_IVIDP_MASK) 1356 1357 #define NETC_F3_COMMON_ISIDKC1CR0_IPCPP_MASK (0x100U) 1358 #define NETC_F3_COMMON_ISIDKC1CR0_IPCPP_SHIFT (8U) 1359 #define NETC_F3_COMMON_ISIDKC1CR0_IPCPP_WIDTH (1U) 1360 #define NETC_F3_COMMON_ISIDKC1CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_IPCPP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_IPCPP_MASK) 1361 1362 #define NETC_F3_COMMON_ISIDKC1CR0_SQTP_MASK (0x200U) 1363 #define NETC_F3_COMMON_ISIDKC1CR0_SQTP_SHIFT (9U) 1364 #define NETC_F3_COMMON_ISIDKC1CR0_SQTP_WIDTH (1U) 1365 #define NETC_F3_COMMON_ISIDKC1CR0_SQTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_SQTP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_SQTP_MASK) 1366 1367 #define NETC_F3_COMMON_ISIDKC1CR0_ETP_MASK (0x400U) 1368 #define NETC_F3_COMMON_ISIDKC1CR0_ETP_SHIFT (10U) 1369 #define NETC_F3_COMMON_ISIDKC1CR0_ETP_WIDTH (1U) 1370 #define NETC_F3_COMMON_ISIDKC1CR0_ETP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1CR0_ETP_SHIFT)) & NETC_F3_COMMON_ISIDKC1CR0_ETP_MASK) 1371 /*! @} */ 1372 1373 /*! @name ISIDKC1PF0CR - Ingress stream identification key construction 1 payload field 0 configuration register */ 1374 /*! @{ */ 1375 1376 #define NETC_F3_COMMON_ISIDKC1PF0CR_PFP_MASK (0x1U) 1377 #define NETC_F3_COMMON_ISIDKC1PF0CR_PFP_SHIFT (0U) 1378 #define NETC_F3_COMMON_ISIDKC1PF0CR_PFP_WIDTH (1U) 1379 #define NETC_F3_COMMON_ISIDKC1PF0CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF0CR_PFP_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF0CR_PFP_MASK) 1380 1381 #define NETC_F3_COMMON_ISIDKC1PF0CR_NUM_BYTES_MASK (0x1EU) 1382 #define NETC_F3_COMMON_ISIDKC1PF0CR_NUM_BYTES_SHIFT (1U) 1383 #define NETC_F3_COMMON_ISIDKC1PF0CR_NUM_BYTES_WIDTH (4U) 1384 #define NETC_F3_COMMON_ISIDKC1PF0CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF0CR_NUM_BYTES_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF0CR_NUM_BYTES_MASK) 1385 1386 #define NETC_F3_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_MASK (0x7F00U) 1387 #define NETC_F3_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_SHIFT (8U) 1388 #define NETC_F3_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_WIDTH (7U) 1389 #define NETC_F3_COMMON_ISIDKC1PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_MASK) 1390 1391 #define NETC_F3_COMMON_ISIDKC1PF0CR_FBMASK_MASK (0x70000U) 1392 #define NETC_F3_COMMON_ISIDKC1PF0CR_FBMASK_SHIFT (16U) 1393 #define NETC_F3_COMMON_ISIDKC1PF0CR_FBMASK_WIDTH (3U) 1394 #define NETC_F3_COMMON_ISIDKC1PF0CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF0CR_FBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF0CR_FBMASK_MASK) 1395 1396 #define NETC_F3_COMMON_ISIDKC1PF0CR_LBMASK_MASK (0x700000U) 1397 #define NETC_F3_COMMON_ISIDKC1PF0CR_LBMASK_SHIFT (20U) 1398 #define NETC_F3_COMMON_ISIDKC1PF0CR_LBMASK_WIDTH (3U) 1399 #define NETC_F3_COMMON_ISIDKC1PF0CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF0CR_LBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF0CR_LBMASK_MASK) 1400 /*! @} */ 1401 1402 /*! @name ISIDKC1PF1CR - Ingress stream identification key construction 1 payload field 1 configuration register */ 1403 /*! @{ */ 1404 1405 #define NETC_F3_COMMON_ISIDKC1PF1CR_PFP_MASK (0x1U) 1406 #define NETC_F3_COMMON_ISIDKC1PF1CR_PFP_SHIFT (0U) 1407 #define NETC_F3_COMMON_ISIDKC1PF1CR_PFP_WIDTH (1U) 1408 #define NETC_F3_COMMON_ISIDKC1PF1CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF1CR_PFP_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF1CR_PFP_MASK) 1409 1410 #define NETC_F3_COMMON_ISIDKC1PF1CR_NUM_BYTES_MASK (0x1EU) 1411 #define NETC_F3_COMMON_ISIDKC1PF1CR_NUM_BYTES_SHIFT (1U) 1412 #define NETC_F3_COMMON_ISIDKC1PF1CR_NUM_BYTES_WIDTH (4U) 1413 #define NETC_F3_COMMON_ISIDKC1PF1CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF1CR_NUM_BYTES_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF1CR_NUM_BYTES_MASK) 1414 1415 #define NETC_F3_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_MASK (0x7F00U) 1416 #define NETC_F3_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_SHIFT (8U) 1417 #define NETC_F3_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_WIDTH (7U) 1418 #define NETC_F3_COMMON_ISIDKC1PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_MASK) 1419 1420 #define NETC_F3_COMMON_ISIDKC1PF1CR_FBMASK_MASK (0x70000U) 1421 #define NETC_F3_COMMON_ISIDKC1PF1CR_FBMASK_SHIFT (16U) 1422 #define NETC_F3_COMMON_ISIDKC1PF1CR_FBMASK_WIDTH (3U) 1423 #define NETC_F3_COMMON_ISIDKC1PF1CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF1CR_FBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF1CR_FBMASK_MASK) 1424 1425 #define NETC_F3_COMMON_ISIDKC1PF1CR_LBMASK_MASK (0x700000U) 1426 #define NETC_F3_COMMON_ISIDKC1PF1CR_LBMASK_SHIFT (20U) 1427 #define NETC_F3_COMMON_ISIDKC1PF1CR_LBMASK_WIDTH (3U) 1428 #define NETC_F3_COMMON_ISIDKC1PF1CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF1CR_LBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF1CR_LBMASK_MASK) 1429 /*! @} */ 1430 1431 /*! @name ISIDKC1PF2CR - Ingress stream identification key construction 1 payload field 2 configuration register */ 1432 /*! @{ */ 1433 1434 #define NETC_F3_COMMON_ISIDKC1PF2CR_PFP_MASK (0x1U) 1435 #define NETC_F3_COMMON_ISIDKC1PF2CR_PFP_SHIFT (0U) 1436 #define NETC_F3_COMMON_ISIDKC1PF2CR_PFP_WIDTH (1U) 1437 #define NETC_F3_COMMON_ISIDKC1PF2CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF2CR_PFP_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF2CR_PFP_MASK) 1438 1439 #define NETC_F3_COMMON_ISIDKC1PF2CR_NUM_BYTES_MASK (0x1EU) 1440 #define NETC_F3_COMMON_ISIDKC1PF2CR_NUM_BYTES_SHIFT (1U) 1441 #define NETC_F3_COMMON_ISIDKC1PF2CR_NUM_BYTES_WIDTH (4U) 1442 #define NETC_F3_COMMON_ISIDKC1PF2CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF2CR_NUM_BYTES_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF2CR_NUM_BYTES_MASK) 1443 1444 #define NETC_F3_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_MASK (0x7F00U) 1445 #define NETC_F3_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_SHIFT (8U) 1446 #define NETC_F3_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_WIDTH (7U) 1447 #define NETC_F3_COMMON_ISIDKC1PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_MASK) 1448 1449 #define NETC_F3_COMMON_ISIDKC1PF2CR_FBMASK_MASK (0x70000U) 1450 #define NETC_F3_COMMON_ISIDKC1PF2CR_FBMASK_SHIFT (16U) 1451 #define NETC_F3_COMMON_ISIDKC1PF2CR_FBMASK_WIDTH (3U) 1452 #define NETC_F3_COMMON_ISIDKC1PF2CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF2CR_FBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF2CR_FBMASK_MASK) 1453 1454 #define NETC_F3_COMMON_ISIDKC1PF2CR_LBMASK_MASK (0x700000U) 1455 #define NETC_F3_COMMON_ISIDKC1PF2CR_LBMASK_SHIFT (20U) 1456 #define NETC_F3_COMMON_ISIDKC1PF2CR_LBMASK_WIDTH (3U) 1457 #define NETC_F3_COMMON_ISIDKC1PF2CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF2CR_LBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF2CR_LBMASK_MASK) 1458 /*! @} */ 1459 1460 /*! @name ISIDKC1PF3CR - Ingress stream identification key construction 1 payload field 3 configuration register */ 1461 /*! @{ */ 1462 1463 #define NETC_F3_COMMON_ISIDKC1PF3CR_PFP_MASK (0x1U) 1464 #define NETC_F3_COMMON_ISIDKC1PF3CR_PFP_SHIFT (0U) 1465 #define NETC_F3_COMMON_ISIDKC1PF3CR_PFP_WIDTH (1U) 1466 #define NETC_F3_COMMON_ISIDKC1PF3CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF3CR_PFP_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF3CR_PFP_MASK) 1467 1468 #define NETC_F3_COMMON_ISIDKC1PF3CR_NUM_BYTES_MASK (0x1EU) 1469 #define NETC_F3_COMMON_ISIDKC1PF3CR_NUM_BYTES_SHIFT (1U) 1470 #define NETC_F3_COMMON_ISIDKC1PF3CR_NUM_BYTES_WIDTH (4U) 1471 #define NETC_F3_COMMON_ISIDKC1PF3CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF3CR_NUM_BYTES_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF3CR_NUM_BYTES_MASK) 1472 1473 #define NETC_F3_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_MASK (0x7F00U) 1474 #define NETC_F3_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_SHIFT (8U) 1475 #define NETC_F3_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_WIDTH (7U) 1476 #define NETC_F3_COMMON_ISIDKC1PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_MASK) 1477 1478 #define NETC_F3_COMMON_ISIDKC1PF3CR_FBMASK_MASK (0x70000U) 1479 #define NETC_F3_COMMON_ISIDKC1PF3CR_FBMASK_SHIFT (16U) 1480 #define NETC_F3_COMMON_ISIDKC1PF3CR_FBMASK_WIDTH (3U) 1481 #define NETC_F3_COMMON_ISIDKC1PF3CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF3CR_FBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF3CR_FBMASK_MASK) 1482 1483 #define NETC_F3_COMMON_ISIDKC1PF3CR_LBMASK_MASK (0x700000U) 1484 #define NETC_F3_COMMON_ISIDKC1PF3CR_LBMASK_SHIFT (20U) 1485 #define NETC_F3_COMMON_ISIDKC1PF3CR_LBMASK_WIDTH (3U) 1486 #define NETC_F3_COMMON_ISIDKC1PF3CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISIDKC1PF3CR_LBMASK_SHIFT)) & NETC_F3_COMMON_ISIDKC1PF3CR_LBMASK_MASK) 1487 /*! @} */ 1488 1489 /*! @name ISFHTCAPR - Ingress stream filter hash table capability register */ 1490 /*! @{ */ 1491 1492 #define NETC_F3_COMMON_ISFHTCAPR_ACCESS_METH_MASK (0xF00000U) 1493 #define NETC_F3_COMMON_ISFHTCAPR_ACCESS_METH_SHIFT (20U) 1494 #define NETC_F3_COMMON_ISFHTCAPR_ACCESS_METH_WIDTH (4U) 1495 #define NETC_F3_COMMON_ISFHTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISFHTCAPR_ACCESS_METH_SHIFT)) & NETC_F3_COMMON_ISFHTCAPR_ACCESS_METH_MASK) 1496 /*! @} */ 1497 1498 /*! @name ISFHTOR - Ingress stream filter hash table operational register */ 1499 /*! @{ */ 1500 1501 #define NETC_F3_COMMON_ISFHTOR_NUM_ENTRIES_MASK (0xFFFFU) 1502 #define NETC_F3_COMMON_ISFHTOR_NUM_ENTRIES_SHIFT (0U) 1503 #define NETC_F3_COMMON_ISFHTOR_NUM_ENTRIES_WIDTH (16U) 1504 #define NETC_F3_COMMON_ISFHTOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F3_COMMON_ISFHTOR_NUM_ENTRIES_SHIFT)) & NETC_F3_COMMON_ISFHTOR_NUM_ENTRIES_MASK) 1505 /*! @} */ 1506 1507 /*! 1508 * @} 1509 */ /* end of group NETC_F3_COMMON_Register_Masks */ 1510 1511 /*! 1512 * @} 1513 */ /* end of group NETC_F3_COMMON_Peripheral_Access_Layer */ 1514 1515 #endif /* #if !defined(S32Z2_NETC_F3_COMMON_H_) */ 1516
