1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F1_GLOBAL.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_NETC_F1_GLOBAL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F1_GLOBAL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F1_GLOBAL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F1_GLOBAL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F1_GLOBAL_Peripheral_Access_Layer NETC_F1_GLOBAL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F1_GLOBAL - Size of Registers Arrays */ 72 #define NETC_F1_GLOBAL_PCE_SL_COUNT 1u 73 #define NETC_F1_GLOBAL_HTA_LOOP_COUNT 1u 74 #define NETC_F1_GLOBAL_ARRAY_NUM_RC_COUNT 1u 75 #define NETC_F1_GLOBAL_G_BOOT_COUNT 2u 76 77 /** NETC_F1_GLOBAL - Register Layout Typedef */ 78 typedef struct { 79 __I uint32_t SMCAPR; /**< Shared memory capability register, offset: 0x0 */ 80 __I uint32_t SMDTR; /**< Shared memory depletion threshold register, offset: 0x4 */ 81 __I uint32_t SMACR; /**< Shared memory available count register, offset: 0x8 */ 82 uint8_t RESERVED_0[4]; 83 __I uint32_t SMCLWMR; /**< Shared memory count low watermark register, offset: 0x10 */ 84 __I uint32_t SMBUCR; /**< Shared memory buffer unassigned count register, offset: 0x14 */ 85 __I uint32_t SMBUCHWMR; /**< Shared memory buffer unassigned count high watermark register, offset: 0x18 */ 86 __I uint32_t SMLCR; /**< Shared memory loss count register, offset: 0x1C */ 87 __I uint32_t HBTCAPR; /**< Hash bucket table capability register, offset: 0x20 */ 88 __I uint32_t HBTOR0; /**< Hash bucket table operational register 0, offset: 0x24 */ 89 uint8_t RESERVED_1[4]; 90 __I uint32_t HBTOR2; /**< Hash bucket table operational register 2, offset: 0x2C */ 91 uint8_t RESERVED_2[16]; 92 __I uint32_t SMERBCAPR; /**< Shared memory ENETC receive buffer capability register, offset: 0x40 */ 93 __I uint32_t SMERBOR0; /**< Shared memory ENETC receive buffer operational register 0, offset: 0x44 */ 94 __I uint32_t SMERBOR1; /**< Shared memory ENETC receive buffer operational 1, offset: 0x48 */ 95 uint8_t RESERVED_3[180]; 96 struct { /* offset: 0x100, array step: 0x8 */ 97 __I uint32_t PCEOR; /**< PCE 0 operational register, array offset: 0x100, array step: 0x8 */ 98 __I uint32_t RFEOR; /**< Replication Forwarding Engine 0 operational register, array offset: 0x104, array step: 0x8 */ 99 } PCE_SL[NETC_F1_GLOBAL_PCE_SL_COUNT]; 100 uint8_t RESERVED_4[92]; 101 __I uint32_t NETCCLKR; /**< NETC clock register, offset: 0x164 */ 102 uint8_t RESERVED_5[152]; 103 struct { /* offset: 0x200, array step: 0x28 */ 104 __I uint32_t HTACAPR; /**< HTA 0 capability register, array offset: 0x200, array step: 0x28 */ 105 __I uint32_t HTARFCOR; /**< HTA 0 receive frame count operational register, array offset: 0x204, array step: 0x28 */ 106 __I uint32_t HTAHPBCOR; /**< HTA 0 high priority byte count operational register, array offset: 0x208, array step: 0x28 */ 107 __I uint32_t HTALPBCOR; /**< HTA 0 low priority byte count operational register, array offset: 0x20C, array step: 0x28 */ 108 uint8_t RESERVED_0[20]; 109 __I uint32_t HTATFCOR; /**< HTA 0 transmit frame count operational register, array offset: 0x224, array step: 0x28 */ 110 } HTA_LOOP[NETC_F1_GLOBAL_HTA_LOOP_COUNT]; 111 uint8_t RESERVED_6[216]; 112 struct { /* offset: 0x300, array step: 0x10 */ 113 __IO uint32_t RCSBRLAR; /**< Root complex 0 system bus read latency average register, array offset: 0x300, array step: 0x10 */ 114 __I uint32_t RCSBRLHWMR; /**< Root complex 0 system bus read latency high watermark register, array offset: 0x304, array step: 0x10 */ 115 __IO uint32_t RCSBWLAR; /**< Root complex 0 system bus write latency average register, array offset: 0x308, array step: 0x10 */ 116 __I uint32_t RCSBWLHWMR; /**< Root complex 0 system bus write latency high watermark register, array offset: 0x30C, array step: 0x10 */ 117 } ARRAY_NUM_RC[NETC_F1_GLOBAL_ARRAY_NUM_RC_COUNT]; 118 uint8_t RESERVED_7[2280]; 119 __I uint32_t IPBRR0; /**< IP block revision register 0, offset: 0xBF8 */ 120 __I uint32_t IPBRR1; /**< IP block revision register 1, offset: 0xBFC */ 121 uint8_t RESERVED_8[256]; 122 __I uint32_t FBLPR[NETC_F1_GLOBAL_G_BOOT_COUNT]; /**< Function boot loader parameter register 0..Function boot loader parameter register 1, array offset: 0xD00, array step: 0x4 */ 123 uint8_t RESERVED_9[280]; 124 union { /* offset: 0xE20 */ 125 struct { /* offset: 0xE20 */ 126 __IO uint32_t EMDIOUFSBECR; /**< EMDIO uncorrectable fatal system bus error configuration register, offset: 0xE20 */ 127 __IO uint32_t EMDIOUFSBESR; /**< EMDIO uncorrectable fatal system bus error status register, offset: 0xE24 */ 128 uint8_t RESERVED_0[40]; 129 __IO uint32_t EMDIOUNIECR; /**< EMDIO uncorrectable non-fatal integrity error configuration register, offset: 0xE50 */ 130 __IO uint32_t EMDIOUNIESR; /**< EMDIO uncorrectable non-fatal integrity error status register, offset: 0xE54 */ 131 uint8_t RESERVED_1[4]; 132 __I uint32_t EMDIOUNIECTR; /**< EMDIO uncorrectable non-fatal integrity error count register, offset: 0xE5C */ 133 } EMDIO; 134 } ERROR; 135 } NETC_F1_GLOBAL_Type, *NETC_F1_GLOBAL_MemMapPtr; 136 137 /** Number of instances of the NETC_F1_GLOBAL module. */ 138 #define NETC_F1_GLOBAL_INSTANCE_COUNT (1u) 139 140 /* NETC_F1_GLOBAL - Peripheral instance base addresses */ 141 /** Peripheral NETC__EMDIO_GLOBAL base address */ 142 #define IP_NETC__EMDIO_GLOBAL_BASE (0x74B70000u) 143 /** Peripheral NETC__EMDIO_GLOBAL base pointer */ 144 #define IP_NETC__EMDIO_GLOBAL ((NETC_F1_GLOBAL_Type *)IP_NETC__EMDIO_GLOBAL_BASE) 145 /** Array initializer of NETC_F1_GLOBAL peripheral base addresses */ 146 #define IP_NETC_F1_GLOBAL_BASE_ADDRS { IP_NETC__EMDIO_GLOBAL_BASE } 147 /** Array initializer of NETC_F1_GLOBAL peripheral base pointers */ 148 #define IP_NETC_F1_GLOBAL_BASE_PTRS { IP_NETC__EMDIO_GLOBAL } 149 150 /* ---------------------------------------------------------------------------- 151 -- NETC_F1_GLOBAL Register Masks 152 ---------------------------------------------------------------------------- */ 153 154 /*! 155 * @addtogroup NETC_F1_GLOBAL_Register_Masks NETC_F1_GLOBAL Register Masks 156 * @{ 157 */ 158 159 /*! @name SMCAPR - Shared memory capability register */ 160 /*! @{ */ 161 162 #define NETC_F1_GLOBAL_SMCAPR_NUM_WORDS_MASK (0xFFFFFFU) 163 #define NETC_F1_GLOBAL_SMCAPR_NUM_WORDS_SHIFT (0U) 164 #define NETC_F1_GLOBAL_SMCAPR_NUM_WORDS_WIDTH (24U) 165 #define NETC_F1_GLOBAL_SMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMCAPR_NUM_WORDS_SHIFT)) & NETC_F1_GLOBAL_SMCAPR_NUM_WORDS_MASK) 166 /*! @} */ 167 168 /*! @name SMDTR - Shared memory depletion threshold register */ 169 /*! @{ */ 170 171 #define NETC_F1_GLOBAL_SMDTR_THRESH_MASK (0xFFFFFFU) 172 #define NETC_F1_GLOBAL_SMDTR_THRESH_SHIFT (0U) 173 #define NETC_F1_GLOBAL_SMDTR_THRESH_WIDTH (24U) 174 #define NETC_F1_GLOBAL_SMDTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMDTR_THRESH_SHIFT)) & NETC_F1_GLOBAL_SMDTR_THRESH_MASK) 175 /*! @} */ 176 177 /*! @name SMACR - Shared memory available count register */ 178 /*! @{ */ 179 180 #define NETC_F1_GLOBAL_SMACR_COUNT_MASK (0xFFFFFFU) 181 #define NETC_F1_GLOBAL_SMACR_COUNT_SHIFT (0U) 182 #define NETC_F1_GLOBAL_SMACR_COUNT_WIDTH (24U) 183 #define NETC_F1_GLOBAL_SMACR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMACR_COUNT_SHIFT)) & NETC_F1_GLOBAL_SMACR_COUNT_MASK) 184 /*! @} */ 185 186 /*! @name SMCLWMR - Shared memory count low watermark register */ 187 /*! @{ */ 188 189 #define NETC_F1_GLOBAL_SMCLWMR_WATERMARK_MASK (0xFFFFFFU) 190 #define NETC_F1_GLOBAL_SMCLWMR_WATERMARK_SHIFT (0U) 191 #define NETC_F1_GLOBAL_SMCLWMR_WATERMARK_WIDTH (24U) 192 #define NETC_F1_GLOBAL_SMCLWMR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMCLWMR_WATERMARK_SHIFT)) & NETC_F1_GLOBAL_SMCLWMR_WATERMARK_MASK) 193 /*! @} */ 194 195 /*! @name SMBUCR - Shared memory buffer unassigned count register */ 196 /*! @{ */ 197 198 #define NETC_F1_GLOBAL_SMBUCR_COUNT_MASK (0xFFFFFFU) 199 #define NETC_F1_GLOBAL_SMBUCR_COUNT_SHIFT (0U) 200 #define NETC_F1_GLOBAL_SMBUCR_COUNT_WIDTH (24U) 201 #define NETC_F1_GLOBAL_SMBUCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMBUCR_COUNT_SHIFT)) & NETC_F1_GLOBAL_SMBUCR_COUNT_MASK) 202 /*! @} */ 203 204 /*! @name SMBUCHWMR - Shared memory buffer unassigned count high watermark register */ 205 /*! @{ */ 206 207 #define NETC_F1_GLOBAL_SMBUCHWMR_WATERMARK_MASK (0xFFFFFFU) 208 #define NETC_F1_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT (0U) 209 #define NETC_F1_GLOBAL_SMBUCHWMR_WATERMARK_WIDTH (24U) 210 #define NETC_F1_GLOBAL_SMBUCHWMR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT)) & NETC_F1_GLOBAL_SMBUCHWMR_WATERMARK_MASK) 211 /*! @} */ 212 213 /*! @name SMLCR - Shared memory loss count register */ 214 /*! @{ */ 215 216 #define NETC_F1_GLOBAL_SMLCR_COUNT_MASK (0xFFFFFFU) 217 #define NETC_F1_GLOBAL_SMLCR_COUNT_SHIFT (0U) 218 #define NETC_F1_GLOBAL_SMLCR_COUNT_WIDTH (24U) 219 #define NETC_F1_GLOBAL_SMLCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMLCR_COUNT_SHIFT)) & NETC_F1_GLOBAL_SMLCR_COUNT_MASK) 220 221 #define NETC_F1_GLOBAL_SMLCR_IFLC_MASK (0x40000000U) 222 #define NETC_F1_GLOBAL_SMLCR_IFLC_SHIFT (30U) 223 #define NETC_F1_GLOBAL_SMLCR_IFLC_WIDTH (1U) 224 #define NETC_F1_GLOBAL_SMLCR_IFLC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMLCR_IFLC_SHIFT)) & NETC_F1_GLOBAL_SMLCR_IFLC_MASK) 225 226 #define NETC_F1_GLOBAL_SMLCR_IFDC_MASK (0x80000000U) 227 #define NETC_F1_GLOBAL_SMLCR_IFDC_SHIFT (31U) 228 #define NETC_F1_GLOBAL_SMLCR_IFDC_WIDTH (1U) 229 #define NETC_F1_GLOBAL_SMLCR_IFDC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMLCR_IFDC_SHIFT)) & NETC_F1_GLOBAL_SMLCR_IFDC_MASK) 230 /*! @} */ 231 232 /*! @name HBTCAPR - Hash bucket table capability register */ 233 /*! @{ */ 234 235 #define NETC_F1_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK (0xFFFFU) 236 #define NETC_F1_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT (0U) 237 #define NETC_F1_GLOBAL_HBTCAPR_NUM_ENTRIES_WIDTH (16U) 238 #define NETC_F1_GLOBAL_HBTCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT)) & NETC_F1_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK) 239 240 #define NETC_F1_GLOBAL_HBTCAPR_MAX_COL_MASK (0x7000000U) 241 #define NETC_F1_GLOBAL_HBTCAPR_MAX_COL_SHIFT (24U) 242 #define NETC_F1_GLOBAL_HBTCAPR_MAX_COL_WIDTH (3U) 243 #define NETC_F1_GLOBAL_HBTCAPR_MAX_COL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HBTCAPR_MAX_COL_SHIFT)) & NETC_F1_GLOBAL_HBTCAPR_MAX_COL_MASK) 244 245 #define NETC_F1_GLOBAL_HBTCAPR_MAX_VISITS_MASK (0xF0000000U) 246 #define NETC_F1_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT (28U) 247 #define NETC_F1_GLOBAL_HBTCAPR_MAX_VISITS_WIDTH (4U) 248 #define NETC_F1_GLOBAL_HBTCAPR_MAX_VISITS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT)) & NETC_F1_GLOBAL_HBTCAPR_MAX_VISITS_MASK) 249 /*! @} */ 250 251 /*! @name HBTOR0 - Hash bucket table operational register 0 */ 252 /*! @{ */ 253 254 #define NETC_F1_GLOBAL_HBTOR0_NUM_ENTRIES_MASK (0xFFFFU) 255 #define NETC_F1_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT (0U) 256 #define NETC_F1_GLOBAL_HBTOR0_NUM_ENTRIES_WIDTH (16U) 257 #define NETC_F1_GLOBAL_HBTOR0_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT)) & NETC_F1_GLOBAL_HBTOR0_NUM_ENTRIES_MASK) 258 259 #define NETC_F1_GLOBAL_HBTOR0_HWM_ENTRIES_MASK (0xFFFF0000U) 260 #define NETC_F1_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT (16U) 261 #define NETC_F1_GLOBAL_HBTOR0_HWM_ENTRIES_WIDTH (16U) 262 #define NETC_F1_GLOBAL_HBTOR0_HWM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT)) & NETC_F1_GLOBAL_HBTOR0_HWM_ENTRIES_MASK) 263 /*! @} */ 264 265 /*! @name HBTOR2 - Hash bucket table operational register 2 */ 266 /*! @{ */ 267 268 #define NETC_F1_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK (0xFFU) 269 #define NETC_F1_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT (0U) 270 #define NETC_F1_GLOBAL_HBTOR2_RUN_AVG_FRACT_WIDTH (8U) 271 #define NETC_F1_GLOBAL_HBTOR2_RUN_AVG_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT)) & NETC_F1_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK) 272 273 #define NETC_F1_GLOBAL_HBTOR2_RUN_AVG_INT_MASK (0xFF00U) 274 #define NETC_F1_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT (8U) 275 #define NETC_F1_GLOBAL_HBTOR2_RUN_AVG_INT_WIDTH (8U) 276 #define NETC_F1_GLOBAL_HBTOR2_RUN_AVG_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT)) & NETC_F1_GLOBAL_HBTOR2_RUN_AVG_INT_MASK) 277 278 #define NETC_F1_GLOBAL_HBTOR2_HWM_COL_MASK (0xF0000U) 279 #define NETC_F1_GLOBAL_HBTOR2_HWM_COL_SHIFT (16U) 280 #define NETC_F1_GLOBAL_HBTOR2_HWM_COL_WIDTH (4U) 281 #define NETC_F1_GLOBAL_HBTOR2_HWM_COL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HBTOR2_HWM_COL_SHIFT)) & NETC_F1_GLOBAL_HBTOR2_HWM_COL_MASK) 282 /*! @} */ 283 284 /*! @name SMERBCAPR - Shared memory ENETC receive buffer capability register */ 285 /*! @{ */ 286 287 #define NETC_F1_GLOBAL_SMERBCAPR_THRESH_MASK (0xFFFFFFU) 288 #define NETC_F1_GLOBAL_SMERBCAPR_THRESH_SHIFT (0U) 289 #define NETC_F1_GLOBAL_SMERBCAPR_THRESH_WIDTH (24U) 290 #define NETC_F1_GLOBAL_SMERBCAPR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMERBCAPR_THRESH_SHIFT)) & NETC_F1_GLOBAL_SMERBCAPR_THRESH_MASK) 291 292 #define NETC_F1_GLOBAL_SMERBCAPR_WORD_SIZE_MASK (0x30000000U) 293 #define NETC_F1_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT (28U) 294 #define NETC_F1_GLOBAL_SMERBCAPR_WORD_SIZE_WIDTH (2U) 295 #define NETC_F1_GLOBAL_SMERBCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT)) & NETC_F1_GLOBAL_SMERBCAPR_WORD_SIZE_MASK) 296 297 #define NETC_F1_GLOBAL_SMERBCAPR_MLOC_MASK (0xC0000000U) 298 #define NETC_F1_GLOBAL_SMERBCAPR_MLOC_SHIFT (30U) 299 #define NETC_F1_GLOBAL_SMERBCAPR_MLOC_WIDTH (2U) 300 #define NETC_F1_GLOBAL_SMERBCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMERBCAPR_MLOC_SHIFT)) & NETC_F1_GLOBAL_SMERBCAPR_MLOC_MASK) 301 /*! @} */ 302 303 /*! @name SMERBOR0 - Shared memory ENETC receive buffer operational register 0 */ 304 /*! @{ */ 305 306 #define NETC_F1_GLOBAL_SMERBOR0_AMOUNT_MASK (0xFFFFFFU) 307 #define NETC_F1_GLOBAL_SMERBOR0_AMOUNT_SHIFT (0U) 308 #define NETC_F1_GLOBAL_SMERBOR0_AMOUNT_WIDTH (24U) 309 #define NETC_F1_GLOBAL_SMERBOR0_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMERBOR0_AMOUNT_SHIFT)) & NETC_F1_GLOBAL_SMERBOR0_AMOUNT_MASK) 310 /*! @} */ 311 312 /*! @name SMERBOR1 - Shared memory ENETC receive buffer operational 1 */ 313 /*! @{ */ 314 315 #define NETC_F1_GLOBAL_SMERBOR1_WATERMARK_MASK (0xFFFFFFU) 316 #define NETC_F1_GLOBAL_SMERBOR1_WATERMARK_SHIFT (0U) 317 #define NETC_F1_GLOBAL_SMERBOR1_WATERMARK_WIDTH (24U) 318 #define NETC_F1_GLOBAL_SMERBOR1_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_SMERBOR1_WATERMARK_SHIFT)) & NETC_F1_GLOBAL_SMERBOR1_WATERMARK_MASK) 319 /*! @} */ 320 321 /*! @name PCEOR - PCE 0 operational register */ 322 /*! @{ */ 323 324 #define NETC_F1_GLOBAL_PCEOR_NUM_FRAMES_MASK (0x3FU) 325 #define NETC_F1_GLOBAL_PCEOR_NUM_FRAMES_SHIFT (0U) 326 #define NETC_F1_GLOBAL_PCEOR_NUM_FRAMES_WIDTH (6U) 327 #define NETC_F1_GLOBAL_PCEOR_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_PCEOR_NUM_FRAMES_SHIFT)) & NETC_F1_GLOBAL_PCEOR_NUM_FRAMES_MASK) 328 329 #define NETC_F1_GLOBAL_PCEOR_HWM_FRAMES_MASK (0x3F00U) 330 #define NETC_F1_GLOBAL_PCEOR_HWM_FRAMES_SHIFT (8U) 331 #define NETC_F1_GLOBAL_PCEOR_HWM_FRAMES_WIDTH (6U) 332 #define NETC_F1_GLOBAL_PCEOR_HWM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_PCEOR_HWM_FRAMES_SHIFT)) & NETC_F1_GLOBAL_PCEOR_HWM_FRAMES_MASK) 333 334 #define NETC_F1_GLOBAL_PCEOR_MAX_FRAMES_MASK (0x3F0000U) 335 #define NETC_F1_GLOBAL_PCEOR_MAX_FRAMES_SHIFT (16U) 336 #define NETC_F1_GLOBAL_PCEOR_MAX_FRAMES_WIDTH (6U) 337 #define NETC_F1_GLOBAL_PCEOR_MAX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_PCEOR_MAX_FRAMES_SHIFT)) & NETC_F1_GLOBAL_PCEOR_MAX_FRAMES_MASK) 338 /*! @} */ 339 340 /*! @name RFEOR - Replication Forwarding Engine 0 operational register */ 341 /*! @{ */ 342 343 #define NETC_F1_GLOBAL_RFEOR_NUM_FRAMES_MASK (0x3FU) 344 #define NETC_F1_GLOBAL_RFEOR_NUM_FRAMES_SHIFT (0U) 345 #define NETC_F1_GLOBAL_RFEOR_NUM_FRAMES_WIDTH (6U) 346 #define NETC_F1_GLOBAL_RFEOR_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RFEOR_NUM_FRAMES_SHIFT)) & NETC_F1_GLOBAL_RFEOR_NUM_FRAMES_MASK) 347 348 #define NETC_F1_GLOBAL_RFEOR_HWM_FRAMES_MASK (0x3F00U) 349 #define NETC_F1_GLOBAL_RFEOR_HWM_FRAMES_SHIFT (8U) 350 #define NETC_F1_GLOBAL_RFEOR_HWM_FRAMES_WIDTH (6U) 351 #define NETC_F1_GLOBAL_RFEOR_HWM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RFEOR_HWM_FRAMES_SHIFT)) & NETC_F1_GLOBAL_RFEOR_HWM_FRAMES_MASK) 352 353 #define NETC_F1_GLOBAL_RFEOR_MAX_FRAMES_MASK (0x3F0000U) 354 #define NETC_F1_GLOBAL_RFEOR_MAX_FRAMES_SHIFT (16U) 355 #define NETC_F1_GLOBAL_RFEOR_MAX_FRAMES_WIDTH (6U) 356 #define NETC_F1_GLOBAL_RFEOR_MAX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RFEOR_MAX_FRAMES_SHIFT)) & NETC_F1_GLOBAL_RFEOR_MAX_FRAMES_MASK) 357 /*! @} */ 358 359 /*! @name NETCCLKR - NETC clock register */ 360 /*! @{ */ 361 362 #define NETC_F1_GLOBAL_NETCCLKR_FREQ_MASK (0x7FFU) 363 #define NETC_F1_GLOBAL_NETCCLKR_FREQ_SHIFT (0U) 364 #define NETC_F1_GLOBAL_NETCCLKR_FREQ_WIDTH (11U) 365 #define NETC_F1_GLOBAL_NETCCLKR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_NETCCLKR_FREQ_SHIFT)) & NETC_F1_GLOBAL_NETCCLKR_FREQ_MASK) 366 /*! @} */ 367 368 /*! @name HTACAPR - HTA 0 capability register */ 369 /*! @{ */ 370 371 #define NETC_F1_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK (0xFFU) 372 #define NETC_F1_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT (0U) 373 #define NETC_F1_GLOBAL_HTACAPR_MAX_RX_FRAMES_WIDTH (8U) 374 #define NETC_F1_GLOBAL_HTACAPR_MAX_RX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT)) & NETC_F1_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK) 375 376 #define NETC_F1_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK (0xFF00U) 377 #define NETC_F1_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT (8U) 378 #define NETC_F1_GLOBAL_HTACAPR_MAX_TX_FRAMES_WIDTH (8U) 379 #define NETC_F1_GLOBAL_HTACAPR_MAX_TX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT)) & NETC_F1_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK) 380 /*! @} */ 381 382 /*! @name HTARFCOR - HTA 0 receive frame count operational register */ 383 /*! @{ */ 384 385 #define NETC_F1_GLOBAL_HTARFCOR_HP_COUNT_MASK (0xFFU) 386 #define NETC_F1_GLOBAL_HTARFCOR_HP_COUNT_SHIFT (0U) 387 #define NETC_F1_GLOBAL_HTARFCOR_HP_COUNT_WIDTH (8U) 388 #define NETC_F1_GLOBAL_HTARFCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTARFCOR_HP_COUNT_SHIFT)) & NETC_F1_GLOBAL_HTARFCOR_HP_COUNT_MASK) 389 390 #define NETC_F1_GLOBAL_HTARFCOR_HP_HWM_MASK (0xFF00U) 391 #define NETC_F1_GLOBAL_HTARFCOR_HP_HWM_SHIFT (8U) 392 #define NETC_F1_GLOBAL_HTARFCOR_HP_HWM_WIDTH (8U) 393 #define NETC_F1_GLOBAL_HTARFCOR_HP_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTARFCOR_HP_HWM_SHIFT)) & NETC_F1_GLOBAL_HTARFCOR_HP_HWM_MASK) 394 395 #define NETC_F1_GLOBAL_HTARFCOR_LP_COUNT_MASK (0xFF0000U) 396 #define NETC_F1_GLOBAL_HTARFCOR_LP_COUNT_SHIFT (16U) 397 #define NETC_F1_GLOBAL_HTARFCOR_LP_COUNT_WIDTH (8U) 398 #define NETC_F1_GLOBAL_HTARFCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTARFCOR_LP_COUNT_SHIFT)) & NETC_F1_GLOBAL_HTARFCOR_LP_COUNT_MASK) 399 400 #define NETC_F1_GLOBAL_HTARFCOR_LP_HWM_MASK (0xFF000000U) 401 #define NETC_F1_GLOBAL_HTARFCOR_LP_HWM_SHIFT (24U) 402 #define NETC_F1_GLOBAL_HTARFCOR_LP_HWM_WIDTH (8U) 403 #define NETC_F1_GLOBAL_HTARFCOR_LP_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTARFCOR_LP_HWM_SHIFT)) & NETC_F1_GLOBAL_HTARFCOR_LP_HWM_MASK) 404 /*! @} */ 405 406 /*! @name HTAHPBCOR - HTA 0 high priority byte count operational register */ 407 /*! @{ */ 408 409 #define NETC_F1_GLOBAL_HTAHPBCOR_HP_COUNT_MASK (0xFFFFU) 410 #define NETC_F1_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT (0U) 411 #define NETC_F1_GLOBAL_HTAHPBCOR_HP_COUNT_WIDTH (16U) 412 #define NETC_F1_GLOBAL_HTAHPBCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT)) & NETC_F1_GLOBAL_HTAHPBCOR_HP_COUNT_MASK) 413 414 #define NETC_F1_GLOBAL_HTAHPBCOR_HWM_MASK (0xFFFF0000U) 415 #define NETC_F1_GLOBAL_HTAHPBCOR_HWM_SHIFT (16U) 416 #define NETC_F1_GLOBAL_HTAHPBCOR_HWM_WIDTH (16U) 417 #define NETC_F1_GLOBAL_HTAHPBCOR_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTAHPBCOR_HWM_SHIFT)) & NETC_F1_GLOBAL_HTAHPBCOR_HWM_MASK) 418 /*! @} */ 419 420 /*! @name HTALPBCOR - HTA 0 low priority byte count operational register */ 421 /*! @{ */ 422 423 #define NETC_F1_GLOBAL_HTALPBCOR_LP_COUNT_MASK (0xFFFFU) 424 #define NETC_F1_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT (0U) 425 #define NETC_F1_GLOBAL_HTALPBCOR_LP_COUNT_WIDTH (16U) 426 #define NETC_F1_GLOBAL_HTALPBCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT)) & NETC_F1_GLOBAL_HTALPBCOR_LP_COUNT_MASK) 427 428 #define NETC_F1_GLOBAL_HTALPBCOR_HWM_MASK (0xFFFF0000U) 429 #define NETC_F1_GLOBAL_HTALPBCOR_HWM_SHIFT (16U) 430 #define NETC_F1_GLOBAL_HTALPBCOR_HWM_WIDTH (16U) 431 #define NETC_F1_GLOBAL_HTALPBCOR_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTALPBCOR_HWM_SHIFT)) & NETC_F1_GLOBAL_HTALPBCOR_HWM_MASK) 432 /*! @} */ 433 434 /*! @name HTATFCOR - HTA 0 transmit frame count operational register */ 435 /*! @{ */ 436 437 #define NETC_F1_GLOBAL_HTATFCOR_HP_COUNT_MASK (0xFFU) 438 #define NETC_F1_GLOBAL_HTATFCOR_HP_COUNT_SHIFT (0U) 439 #define NETC_F1_GLOBAL_HTATFCOR_HP_COUNT_WIDTH (8U) 440 #define NETC_F1_GLOBAL_HTATFCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTATFCOR_HP_COUNT_SHIFT)) & NETC_F1_GLOBAL_HTATFCOR_HP_COUNT_MASK) 441 442 #define NETC_F1_GLOBAL_HTATFCOR_HP_HWM_MASK (0xFF00U) 443 #define NETC_F1_GLOBAL_HTATFCOR_HP_HWM_SHIFT (8U) 444 #define NETC_F1_GLOBAL_HTATFCOR_HP_HWM_WIDTH (8U) 445 #define NETC_F1_GLOBAL_HTATFCOR_HP_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTATFCOR_HP_HWM_SHIFT)) & NETC_F1_GLOBAL_HTATFCOR_HP_HWM_MASK) 446 447 #define NETC_F1_GLOBAL_HTATFCOR_LP_COUNT_MASK (0xFF0000U) 448 #define NETC_F1_GLOBAL_HTATFCOR_LP_COUNT_SHIFT (16U) 449 #define NETC_F1_GLOBAL_HTATFCOR_LP_COUNT_WIDTH (8U) 450 #define NETC_F1_GLOBAL_HTATFCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTATFCOR_LP_COUNT_SHIFT)) & NETC_F1_GLOBAL_HTATFCOR_LP_COUNT_MASK) 451 452 #define NETC_F1_GLOBAL_HTATFCOR_LP_HWM_MASK (0xFF000000U) 453 #define NETC_F1_GLOBAL_HTATFCOR_LP_HWM_SHIFT (24U) 454 #define NETC_F1_GLOBAL_HTATFCOR_LP_HWM_WIDTH (8U) 455 #define NETC_F1_GLOBAL_HTATFCOR_LP_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_HTATFCOR_LP_HWM_SHIFT)) & NETC_F1_GLOBAL_HTATFCOR_LP_HWM_MASK) 456 /*! @} */ 457 458 /*! @name RCSBRLAR - Root complex 0 system bus read latency average register */ 459 /*! @{ */ 460 461 #define NETC_F1_GLOBAL_RCSBRLAR_FRACT_MASK (0xFFU) 462 #define NETC_F1_GLOBAL_RCSBRLAR_FRACT_SHIFT (0U) 463 #define NETC_F1_GLOBAL_RCSBRLAR_FRACT_WIDTH (8U) 464 #define NETC_F1_GLOBAL_RCSBRLAR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RCSBRLAR_FRACT_SHIFT)) & NETC_F1_GLOBAL_RCSBRLAR_FRACT_MASK) 465 466 #define NETC_F1_GLOBAL_RCSBRLAR_INT_MASK (0xFFF00U) 467 #define NETC_F1_GLOBAL_RCSBRLAR_INT_SHIFT (8U) 468 #define NETC_F1_GLOBAL_RCSBRLAR_INT_WIDTH (12U) 469 #define NETC_F1_GLOBAL_RCSBRLAR_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RCSBRLAR_INT_SHIFT)) & NETC_F1_GLOBAL_RCSBRLAR_INT_MASK) 470 /*! @} */ 471 472 /*! @name RCSBRLHWMR - Root complex 0 system bus read latency high watermark register */ 473 /*! @{ */ 474 475 #define NETC_F1_GLOBAL_RCSBRLHWMR_FRACT_MASK (0xFFU) 476 #define NETC_F1_GLOBAL_RCSBRLHWMR_FRACT_SHIFT (0U) 477 #define NETC_F1_GLOBAL_RCSBRLHWMR_FRACT_WIDTH (8U) 478 #define NETC_F1_GLOBAL_RCSBRLHWMR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RCSBRLHWMR_FRACT_SHIFT)) & NETC_F1_GLOBAL_RCSBRLHWMR_FRACT_MASK) 479 480 #define NETC_F1_GLOBAL_RCSBRLHWMR_INT_MASK (0xFFF00U) 481 #define NETC_F1_GLOBAL_RCSBRLHWMR_INT_SHIFT (8U) 482 #define NETC_F1_GLOBAL_RCSBRLHWMR_INT_WIDTH (12U) 483 #define NETC_F1_GLOBAL_RCSBRLHWMR_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RCSBRLHWMR_INT_SHIFT)) & NETC_F1_GLOBAL_RCSBRLHWMR_INT_MASK) 484 /*! @} */ 485 486 /*! @name RCSBWLAR - Root complex 0 system bus write latency average register */ 487 /*! @{ */ 488 489 #define NETC_F1_GLOBAL_RCSBWLAR_FRACT_MASK (0xFFU) 490 #define NETC_F1_GLOBAL_RCSBWLAR_FRACT_SHIFT (0U) 491 #define NETC_F1_GLOBAL_RCSBWLAR_FRACT_WIDTH (8U) 492 #define NETC_F1_GLOBAL_RCSBWLAR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RCSBWLAR_FRACT_SHIFT)) & NETC_F1_GLOBAL_RCSBWLAR_FRACT_MASK) 493 494 #define NETC_F1_GLOBAL_RCSBWLAR_INT_MASK (0xFFF00U) 495 #define NETC_F1_GLOBAL_RCSBWLAR_INT_SHIFT (8U) 496 #define NETC_F1_GLOBAL_RCSBWLAR_INT_WIDTH (12U) 497 #define NETC_F1_GLOBAL_RCSBWLAR_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RCSBWLAR_INT_SHIFT)) & NETC_F1_GLOBAL_RCSBWLAR_INT_MASK) 498 /*! @} */ 499 500 /*! @name RCSBWLHWMR - Root complex 0 system bus write latency high watermark register */ 501 /*! @{ */ 502 503 #define NETC_F1_GLOBAL_RCSBWLHWMR_FRACT_MASK (0xFFU) 504 #define NETC_F1_GLOBAL_RCSBWLHWMR_FRACT_SHIFT (0U) 505 #define NETC_F1_GLOBAL_RCSBWLHWMR_FRACT_WIDTH (8U) 506 #define NETC_F1_GLOBAL_RCSBWLHWMR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RCSBWLHWMR_FRACT_SHIFT)) & NETC_F1_GLOBAL_RCSBWLHWMR_FRACT_MASK) 507 508 #define NETC_F1_GLOBAL_RCSBWLHWMR_INT_MASK (0xFFF00U) 509 #define NETC_F1_GLOBAL_RCSBWLHWMR_INT_SHIFT (8U) 510 #define NETC_F1_GLOBAL_RCSBWLHWMR_INT_WIDTH (12U) 511 #define NETC_F1_GLOBAL_RCSBWLHWMR_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_RCSBWLHWMR_INT_SHIFT)) & NETC_F1_GLOBAL_RCSBWLHWMR_INT_MASK) 512 /*! @} */ 513 514 /*! @name IPBRR0 - IP block revision register 0 */ 515 /*! @{ */ 516 517 #define NETC_F1_GLOBAL_IPBRR0_IP_MN_MASK (0xFFU) 518 #define NETC_F1_GLOBAL_IPBRR0_IP_MN_SHIFT (0U) 519 #define NETC_F1_GLOBAL_IPBRR0_IP_MN_WIDTH (8U) 520 #define NETC_F1_GLOBAL_IPBRR0_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_IPBRR0_IP_MN_SHIFT)) & NETC_F1_GLOBAL_IPBRR0_IP_MN_MASK) 521 522 #define NETC_F1_GLOBAL_IPBRR0_IP_MJ_MASK (0xFF00U) 523 #define NETC_F1_GLOBAL_IPBRR0_IP_MJ_SHIFT (8U) 524 #define NETC_F1_GLOBAL_IPBRR0_IP_MJ_WIDTH (8U) 525 #define NETC_F1_GLOBAL_IPBRR0_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_IPBRR0_IP_MJ_SHIFT)) & NETC_F1_GLOBAL_IPBRR0_IP_MJ_MASK) 526 527 #define NETC_F1_GLOBAL_IPBRR0_IP_ID_MASK (0xFFFF0000U) 528 #define NETC_F1_GLOBAL_IPBRR0_IP_ID_SHIFT (16U) 529 #define NETC_F1_GLOBAL_IPBRR0_IP_ID_WIDTH (16U) 530 #define NETC_F1_GLOBAL_IPBRR0_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_IPBRR0_IP_ID_SHIFT)) & NETC_F1_GLOBAL_IPBRR0_IP_ID_MASK) 531 /*! @} */ 532 533 /*! @name IPBRR1 - IP block revision register 1 */ 534 /*! @{ */ 535 536 #define NETC_F1_GLOBAL_IPBRR1_IP_CFG_MASK (0xFFU) 537 #define NETC_F1_GLOBAL_IPBRR1_IP_CFG_SHIFT (0U) 538 #define NETC_F1_GLOBAL_IPBRR1_IP_CFG_WIDTH (8U) 539 #define NETC_F1_GLOBAL_IPBRR1_IP_CFG(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_IPBRR1_IP_CFG_SHIFT)) & NETC_F1_GLOBAL_IPBRR1_IP_CFG_MASK) 540 541 #define NETC_F1_GLOBAL_IPBRR1_IP_MNT_MASK (0xFF00U) 542 #define NETC_F1_GLOBAL_IPBRR1_IP_MNT_SHIFT (8U) 543 #define NETC_F1_GLOBAL_IPBRR1_IP_MNT_WIDTH (8U) 544 #define NETC_F1_GLOBAL_IPBRR1_IP_MNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_IPBRR1_IP_MNT_SHIFT)) & NETC_F1_GLOBAL_IPBRR1_IP_MNT_MASK) 545 546 #define NETC_F1_GLOBAL_IPBRR1_IP_INT_MASK (0xFF0000U) 547 #define NETC_F1_GLOBAL_IPBRR1_IP_INT_SHIFT (16U) 548 #define NETC_F1_GLOBAL_IPBRR1_IP_INT_WIDTH (8U) 549 #define NETC_F1_GLOBAL_IPBRR1_IP_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_IPBRR1_IP_INT_SHIFT)) & NETC_F1_GLOBAL_IPBRR1_IP_INT_MASK) 550 /*! @} */ 551 552 /*! @name FBLPR - Function boot loader parameter register 0..Function boot loader parameter register 1 */ 553 /*! @{ */ 554 555 #define NETC_F1_GLOBAL_FBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) 556 #define NETC_F1_GLOBAL_FBLPR_PARAM_VAL_SHIFT (0U) 557 #define NETC_F1_GLOBAL_FBLPR_PARAM_VAL_WIDTH (32U) 558 #define NETC_F1_GLOBAL_FBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_FBLPR_PARAM_VAL_SHIFT)) & NETC_F1_GLOBAL_FBLPR_PARAM_VAL_MASK) 559 /*! @} */ 560 561 /*! @name EMDIOUFSBECR - EMDIO uncorrectable fatal system bus error configuration register */ 562 /*! @{ */ 563 564 #define NETC_F1_GLOBAL_EMDIOUFSBECR_RD_MASK (0x80000000U) 565 #define NETC_F1_GLOBAL_EMDIOUFSBECR_RD_SHIFT (31U) 566 #define NETC_F1_GLOBAL_EMDIOUFSBECR_RD_WIDTH (1U) 567 #define NETC_F1_GLOBAL_EMDIOUFSBECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUFSBECR_RD_SHIFT)) & NETC_F1_GLOBAL_EMDIOUFSBECR_RD_MASK) 568 /*! @} */ 569 570 /*! @name EMDIOUFSBESR - EMDIO uncorrectable fatal system bus error status register */ 571 /*! @{ */ 572 573 #define NETC_F1_GLOBAL_EMDIOUFSBESR_SB_ID_MASK (0xFU) 574 #define NETC_F1_GLOBAL_EMDIOUFSBESR_SB_ID_SHIFT (0U) 575 #define NETC_F1_GLOBAL_EMDIOUFSBESR_SB_ID_WIDTH (4U) 576 #define NETC_F1_GLOBAL_EMDIOUFSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUFSBESR_SB_ID_SHIFT)) & NETC_F1_GLOBAL_EMDIOUFSBESR_SB_ID_MASK) 577 578 #define NETC_F1_GLOBAL_EMDIOUFSBESR_M_MASK (0x40000000U) 579 #define NETC_F1_GLOBAL_EMDIOUFSBESR_M_SHIFT (30U) 580 #define NETC_F1_GLOBAL_EMDIOUFSBESR_M_WIDTH (1U) 581 #define NETC_F1_GLOBAL_EMDIOUFSBESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUFSBESR_M_SHIFT)) & NETC_F1_GLOBAL_EMDIOUFSBESR_M_MASK) 582 583 #define NETC_F1_GLOBAL_EMDIOUFSBESR_SBE_MASK (0x80000000U) 584 #define NETC_F1_GLOBAL_EMDIOUFSBESR_SBE_SHIFT (31U) 585 #define NETC_F1_GLOBAL_EMDIOUFSBESR_SBE_WIDTH (1U) 586 #define NETC_F1_GLOBAL_EMDIOUFSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUFSBESR_SBE_SHIFT)) & NETC_F1_GLOBAL_EMDIOUFSBESR_SBE_MASK) 587 /*! @} */ 588 589 /*! @name EMDIOUNIECR - EMDIO uncorrectable non-fatal integrity error configuration register */ 590 /*! @{ */ 591 592 #define NETC_F1_GLOBAL_EMDIOUNIECR_THRESHOLD_MASK (0xFFU) 593 #define NETC_F1_GLOBAL_EMDIOUNIECR_THRESHOLD_SHIFT (0U) 594 #define NETC_F1_GLOBAL_EMDIOUNIECR_THRESHOLD_WIDTH (8U) 595 #define NETC_F1_GLOBAL_EMDIOUNIECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUNIECR_THRESHOLD_SHIFT)) & NETC_F1_GLOBAL_EMDIOUNIECR_THRESHOLD_MASK) 596 597 #define NETC_F1_GLOBAL_EMDIOUNIECR_RD_MASK (0x80000000U) 598 #define NETC_F1_GLOBAL_EMDIOUNIECR_RD_SHIFT (31U) 599 #define NETC_F1_GLOBAL_EMDIOUNIECR_RD_WIDTH (1U) 600 #define NETC_F1_GLOBAL_EMDIOUNIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUNIECR_RD_SHIFT)) & NETC_F1_GLOBAL_EMDIOUNIECR_RD_MASK) 601 /*! @} */ 602 603 /*! @name EMDIOUNIESR - EMDIO uncorrectable non-fatal integrity error status register */ 604 /*! @{ */ 605 606 #define NETC_F1_GLOBAL_EMDIOUNIESR_BLOCK_ID_MASK (0xF0U) 607 #define NETC_F1_GLOBAL_EMDIOUNIESR_BLOCK_ID_SHIFT (4U) 608 #define NETC_F1_GLOBAL_EMDIOUNIESR_BLOCK_ID_WIDTH (4U) 609 #define NETC_F1_GLOBAL_EMDIOUNIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUNIESR_BLOCK_ID_SHIFT)) & NETC_F1_GLOBAL_EMDIOUNIESR_BLOCK_ID_MASK) 610 611 #define NETC_F1_GLOBAL_EMDIOUNIESR_SM_ID_MASK (0x3F00U) 612 #define NETC_F1_GLOBAL_EMDIOUNIESR_SM_ID_SHIFT (8U) 613 #define NETC_F1_GLOBAL_EMDIOUNIESR_SM_ID_WIDTH (6U) 614 #define NETC_F1_GLOBAL_EMDIOUNIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUNIESR_SM_ID_SHIFT)) & NETC_F1_GLOBAL_EMDIOUNIESR_SM_ID_MASK) 615 616 #define NETC_F1_GLOBAL_EMDIOUNIESR_INTERR_MASK (0x80000000U) 617 #define NETC_F1_GLOBAL_EMDIOUNIESR_INTERR_SHIFT (31U) 618 #define NETC_F1_GLOBAL_EMDIOUNIESR_INTERR_WIDTH (1U) 619 #define NETC_F1_GLOBAL_EMDIOUNIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUNIESR_INTERR_SHIFT)) & NETC_F1_GLOBAL_EMDIOUNIESR_INTERR_MASK) 620 /*! @} */ 621 622 /*! @name EMDIOUNIECTR - EMDIO uncorrectable non-fatal integrity error count register */ 623 /*! @{ */ 624 625 #define NETC_F1_GLOBAL_EMDIOUNIECTR_COUNT_MASK (0xFFU) 626 #define NETC_F1_GLOBAL_EMDIOUNIECTR_COUNT_SHIFT (0U) 627 #define NETC_F1_GLOBAL_EMDIOUNIECTR_COUNT_WIDTH (8U) 628 #define NETC_F1_GLOBAL_EMDIOUNIECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F1_GLOBAL_EMDIOUNIECTR_COUNT_SHIFT)) & NETC_F1_GLOBAL_EMDIOUNIECTR_COUNT_MASK) 629 /*! @} */ 630 631 /*! 632 * @} 633 */ /* end of group NETC_F1_GLOBAL_Register_Masks */ 634 635 /*! 636 * @} 637 */ /* end of group NETC_F1_GLOBAL_Peripheral_Access_Layer */ 638 639 #endif /* #if !defined(S32Z2_NETC_F1_GLOBAL_H_) */ 640
