1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F0_GLOBAL.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_NETC_F0_GLOBAL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F0_GLOBAL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F0_GLOBAL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F0_GLOBAL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F0_GLOBAL_Peripheral_Access_Layer NETC_F0_GLOBAL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F0_GLOBAL - Size of Registers Arrays */ 72 #define NETC_F0_GLOBAL_PCE_SL_COUNT 1u 73 #define NETC_F0_GLOBAL_HTA_LOOP_COUNT 1u 74 #define NETC_F0_GLOBAL_ARRAY_NUM_RC_COUNT 1u 75 #define NETC_F0_GLOBAL_G_BOOT_COUNT 2u 76 77 /** NETC_F0_GLOBAL - Register Layout Typedef */ 78 typedef struct { 79 __I uint32_t SMCAPR; /**< Shared memory capability register, offset: 0x0 */ 80 __I uint32_t SMDTR; /**< Shared memory depletion threshold register, offset: 0x4 */ 81 __I uint32_t SMACR; /**< Shared memory available count register, offset: 0x8 */ 82 uint8_t RESERVED_0[4]; 83 __I uint32_t SMCLWMR; /**< Shared memory count low watermark register, offset: 0x10 */ 84 __I uint32_t SMBUCR; /**< Shared memory buffer unassigned count register, offset: 0x14 */ 85 __I uint32_t SMBUCHWMR; /**< Shared memory buffer unassigned count high watermark register, offset: 0x18 */ 86 __I uint32_t SMLCR; /**< Shared memory loss count register, offset: 0x1C */ 87 __I uint32_t HBTCAPR; /**< Hash bucket table capability register, offset: 0x20 */ 88 __I uint32_t HBTOR0; /**< Hash bucket table operational register 0, offset: 0x24 */ 89 uint8_t RESERVED_1[4]; 90 __I uint32_t HBTOR2; /**< Hash bucket table operational register 2, offset: 0x2C */ 91 uint8_t RESERVED_2[16]; 92 __I uint32_t SMERBCAPR; /**< Shared memory ENETC receive buffer capability register, offset: 0x40 */ 93 __I uint32_t SMERBOR0; /**< Shared memory ENETC receive buffer operational register 0, offset: 0x44 */ 94 __I uint32_t SMERBOR1; /**< Shared memory ENETC receive buffer operational 1, offset: 0x48 */ 95 uint8_t RESERVED_3[180]; 96 struct { /* offset: 0x100, array step: 0x8 */ 97 __I uint32_t PCEOR; /**< PCE 0 operational register, array offset: 0x100, array step: 0x8 */ 98 __I uint32_t RFEOR; /**< Replication Forwarding Engine 0 operational register, array offset: 0x104, array step: 0x8 */ 99 } PCE_SL[NETC_F0_GLOBAL_PCE_SL_COUNT]; 100 uint8_t RESERVED_4[92]; 101 __I uint32_t NETCCLKR; /**< NETC clock register, offset: 0x164 */ 102 uint8_t RESERVED_5[152]; 103 struct { /* offset: 0x200, array step: 0x28 */ 104 __I uint32_t HTACAPR; /**< HTA 0 capability register, array offset: 0x200, array step: 0x28 */ 105 __I uint32_t HTARFCOR; /**< HTA 0 receive frame count operational register, array offset: 0x204, array step: 0x28 */ 106 __I uint32_t HTAHPBCOR; /**< HTA 0 high priority byte count operational register, array offset: 0x208, array step: 0x28 */ 107 __I uint32_t HTALPBCOR; /**< HTA 0 low priority byte count operational register, array offset: 0x20C, array step: 0x28 */ 108 uint8_t RESERVED_0[20]; 109 __I uint32_t HTATFCOR; /**< HTA 0 transmit frame count operational register, array offset: 0x224, array step: 0x28 */ 110 } HTA_LOOP[NETC_F0_GLOBAL_HTA_LOOP_COUNT]; 111 uint8_t RESERVED_6[216]; 112 struct { /* offset: 0x300, array step: 0x10 */ 113 __IO uint32_t RCSBRLAR; /**< Root complex 0 system bus read latency average register, array offset: 0x300, array step: 0x10 */ 114 __I uint32_t RCSBRLHWMR; /**< Root complex 0 system bus read latency high watermark register, array offset: 0x304, array step: 0x10 */ 115 __IO uint32_t RCSBWLAR; /**< Root complex 0 system bus write latency average register, array offset: 0x308, array step: 0x10 */ 116 __I uint32_t RCSBWLHWMR; /**< Root complex 0 system bus write latency high watermark register, array offset: 0x30C, array step: 0x10 */ 117 } ARRAY_NUM_RC[NETC_F0_GLOBAL_ARRAY_NUM_RC_COUNT]; 118 uint8_t RESERVED_7[2280]; 119 __I uint32_t IPBRR0; /**< IP block revision register 0, offset: 0xBF8 */ 120 __I uint32_t IPBRR1; /**< IP block revision register 1, offset: 0xBFC */ 121 uint8_t RESERVED_8[256]; 122 __I uint32_t FBLPR[NETC_F0_GLOBAL_G_BOOT_COUNT]; /**< Function boot loader parameter register 0..Function boot loader parameter register 1, array offset: 0xD00, array step: 0x4 */ 123 uint8_t RESERVED_9[280]; 124 union { /* offset: 0xE20 */ 125 struct { /* offset: 0xE20 */ 126 __IO uint32_t TUFSBECR; /**< Timer uncorrectable fatal system bus error configuration register, offset: 0xE20 */ 127 __IO uint32_t TUFSBESR; /**< Timer uncorrectable fatal system bus error status register, offset: 0xE24 */ 128 } TIMER; 129 } ERROR; 130 } NETC_F0_GLOBAL_Type, *NETC_F0_GLOBAL_MemMapPtr; 131 132 /** Number of instances of the NETC_F0_GLOBAL module. */ 133 #define NETC_F0_GLOBAL_INSTANCE_COUNT (1u) 134 135 /* NETC_F0_GLOBAL - Peripheral instance base addresses */ 136 /** Peripheral NETC__TMR0_GLOBAL base address */ 137 #define IP_NETC__TMR0_GLOBAL_BASE (0x74B50000u) 138 /** Peripheral NETC__TMR0_GLOBAL base pointer */ 139 #define IP_NETC__TMR0_GLOBAL ((NETC_F0_GLOBAL_Type *)IP_NETC__TMR0_GLOBAL_BASE) 140 /** Array initializer of NETC_F0_GLOBAL peripheral base addresses */ 141 #define IP_NETC_F0_GLOBAL_BASE_ADDRS { IP_NETC__TMR0_GLOBAL_BASE } 142 /** Array initializer of NETC_F0_GLOBAL peripheral base pointers */ 143 #define IP_NETC_F0_GLOBAL_BASE_PTRS { IP_NETC__TMR0_GLOBAL } 144 145 /* ---------------------------------------------------------------------------- 146 -- NETC_F0_GLOBAL Register Masks 147 ---------------------------------------------------------------------------- */ 148 149 /*! 150 * @addtogroup NETC_F0_GLOBAL_Register_Masks NETC_F0_GLOBAL Register Masks 151 * @{ 152 */ 153 154 /*! @name SMCAPR - Shared memory capability register */ 155 /*! @{ */ 156 157 #define NETC_F0_GLOBAL_SMCAPR_NUM_WORDS_MASK (0xFFFFFFU) 158 #define NETC_F0_GLOBAL_SMCAPR_NUM_WORDS_SHIFT (0U) 159 #define NETC_F0_GLOBAL_SMCAPR_NUM_WORDS_WIDTH (24U) 160 #define NETC_F0_GLOBAL_SMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMCAPR_NUM_WORDS_SHIFT)) & NETC_F0_GLOBAL_SMCAPR_NUM_WORDS_MASK) 161 /*! @} */ 162 163 /*! @name SMDTR - Shared memory depletion threshold register */ 164 /*! @{ */ 165 166 #define NETC_F0_GLOBAL_SMDTR_THRESH_MASK (0xFFFFFFU) 167 #define NETC_F0_GLOBAL_SMDTR_THRESH_SHIFT (0U) 168 #define NETC_F0_GLOBAL_SMDTR_THRESH_WIDTH (24U) 169 #define NETC_F0_GLOBAL_SMDTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMDTR_THRESH_SHIFT)) & NETC_F0_GLOBAL_SMDTR_THRESH_MASK) 170 /*! @} */ 171 172 /*! @name SMACR - Shared memory available count register */ 173 /*! @{ */ 174 175 #define NETC_F0_GLOBAL_SMACR_COUNT_MASK (0xFFFFFFU) 176 #define NETC_F0_GLOBAL_SMACR_COUNT_SHIFT (0U) 177 #define NETC_F0_GLOBAL_SMACR_COUNT_WIDTH (24U) 178 #define NETC_F0_GLOBAL_SMACR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMACR_COUNT_SHIFT)) & NETC_F0_GLOBAL_SMACR_COUNT_MASK) 179 /*! @} */ 180 181 /*! @name SMCLWMR - Shared memory count low watermark register */ 182 /*! @{ */ 183 184 #define NETC_F0_GLOBAL_SMCLWMR_WATERMARK_MASK (0xFFFFFFU) 185 #define NETC_F0_GLOBAL_SMCLWMR_WATERMARK_SHIFT (0U) 186 #define NETC_F0_GLOBAL_SMCLWMR_WATERMARK_WIDTH (24U) 187 #define NETC_F0_GLOBAL_SMCLWMR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMCLWMR_WATERMARK_SHIFT)) & NETC_F0_GLOBAL_SMCLWMR_WATERMARK_MASK) 188 /*! @} */ 189 190 /*! @name SMBUCR - Shared memory buffer unassigned count register */ 191 /*! @{ */ 192 193 #define NETC_F0_GLOBAL_SMBUCR_COUNT_MASK (0xFFFFFFU) 194 #define NETC_F0_GLOBAL_SMBUCR_COUNT_SHIFT (0U) 195 #define NETC_F0_GLOBAL_SMBUCR_COUNT_WIDTH (24U) 196 #define NETC_F0_GLOBAL_SMBUCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMBUCR_COUNT_SHIFT)) & NETC_F0_GLOBAL_SMBUCR_COUNT_MASK) 197 /*! @} */ 198 199 /*! @name SMBUCHWMR - Shared memory buffer unassigned count high watermark register */ 200 /*! @{ */ 201 202 #define NETC_F0_GLOBAL_SMBUCHWMR_WATERMARK_MASK (0xFFFFFFU) 203 #define NETC_F0_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT (0U) 204 #define NETC_F0_GLOBAL_SMBUCHWMR_WATERMARK_WIDTH (24U) 205 #define NETC_F0_GLOBAL_SMBUCHWMR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMBUCHWMR_WATERMARK_SHIFT)) & NETC_F0_GLOBAL_SMBUCHWMR_WATERMARK_MASK) 206 /*! @} */ 207 208 /*! @name SMLCR - Shared memory loss count register */ 209 /*! @{ */ 210 211 #define NETC_F0_GLOBAL_SMLCR_COUNT_MASK (0xFFFFFFU) 212 #define NETC_F0_GLOBAL_SMLCR_COUNT_SHIFT (0U) 213 #define NETC_F0_GLOBAL_SMLCR_COUNT_WIDTH (24U) 214 #define NETC_F0_GLOBAL_SMLCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMLCR_COUNT_SHIFT)) & NETC_F0_GLOBAL_SMLCR_COUNT_MASK) 215 216 #define NETC_F0_GLOBAL_SMLCR_IFLC_MASK (0x40000000U) 217 #define NETC_F0_GLOBAL_SMLCR_IFLC_SHIFT (30U) 218 #define NETC_F0_GLOBAL_SMLCR_IFLC_WIDTH (1U) 219 #define NETC_F0_GLOBAL_SMLCR_IFLC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMLCR_IFLC_SHIFT)) & NETC_F0_GLOBAL_SMLCR_IFLC_MASK) 220 221 #define NETC_F0_GLOBAL_SMLCR_IFDC_MASK (0x80000000U) 222 #define NETC_F0_GLOBAL_SMLCR_IFDC_SHIFT (31U) 223 #define NETC_F0_GLOBAL_SMLCR_IFDC_WIDTH (1U) 224 #define NETC_F0_GLOBAL_SMLCR_IFDC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMLCR_IFDC_SHIFT)) & NETC_F0_GLOBAL_SMLCR_IFDC_MASK) 225 /*! @} */ 226 227 /*! @name HBTCAPR - Hash bucket table capability register */ 228 /*! @{ */ 229 230 #define NETC_F0_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK (0xFFFFU) 231 #define NETC_F0_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT (0U) 232 #define NETC_F0_GLOBAL_HBTCAPR_NUM_ENTRIES_WIDTH (16U) 233 #define NETC_F0_GLOBAL_HBTCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HBTCAPR_NUM_ENTRIES_SHIFT)) & NETC_F0_GLOBAL_HBTCAPR_NUM_ENTRIES_MASK) 234 235 #define NETC_F0_GLOBAL_HBTCAPR_MAX_COL_MASK (0x7000000U) 236 #define NETC_F0_GLOBAL_HBTCAPR_MAX_COL_SHIFT (24U) 237 #define NETC_F0_GLOBAL_HBTCAPR_MAX_COL_WIDTH (3U) 238 #define NETC_F0_GLOBAL_HBTCAPR_MAX_COL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HBTCAPR_MAX_COL_SHIFT)) & NETC_F0_GLOBAL_HBTCAPR_MAX_COL_MASK) 239 240 #define NETC_F0_GLOBAL_HBTCAPR_MAX_VISITS_MASK (0xF0000000U) 241 #define NETC_F0_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT (28U) 242 #define NETC_F0_GLOBAL_HBTCAPR_MAX_VISITS_WIDTH (4U) 243 #define NETC_F0_GLOBAL_HBTCAPR_MAX_VISITS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HBTCAPR_MAX_VISITS_SHIFT)) & NETC_F0_GLOBAL_HBTCAPR_MAX_VISITS_MASK) 244 /*! @} */ 245 246 /*! @name HBTOR0 - Hash bucket table operational register 0 */ 247 /*! @{ */ 248 249 #define NETC_F0_GLOBAL_HBTOR0_NUM_ENTRIES_MASK (0xFFFFU) 250 #define NETC_F0_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT (0U) 251 #define NETC_F0_GLOBAL_HBTOR0_NUM_ENTRIES_WIDTH (16U) 252 #define NETC_F0_GLOBAL_HBTOR0_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HBTOR0_NUM_ENTRIES_SHIFT)) & NETC_F0_GLOBAL_HBTOR0_NUM_ENTRIES_MASK) 253 254 #define NETC_F0_GLOBAL_HBTOR0_HWM_ENTRIES_MASK (0xFFFF0000U) 255 #define NETC_F0_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT (16U) 256 #define NETC_F0_GLOBAL_HBTOR0_HWM_ENTRIES_WIDTH (16U) 257 #define NETC_F0_GLOBAL_HBTOR0_HWM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HBTOR0_HWM_ENTRIES_SHIFT)) & NETC_F0_GLOBAL_HBTOR0_HWM_ENTRIES_MASK) 258 /*! @} */ 259 260 /*! @name HBTOR2 - Hash bucket table operational register 2 */ 261 /*! @{ */ 262 263 #define NETC_F0_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK (0xFFU) 264 #define NETC_F0_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT (0U) 265 #define NETC_F0_GLOBAL_HBTOR2_RUN_AVG_FRACT_WIDTH (8U) 266 #define NETC_F0_GLOBAL_HBTOR2_RUN_AVG_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HBTOR2_RUN_AVG_FRACT_SHIFT)) & NETC_F0_GLOBAL_HBTOR2_RUN_AVG_FRACT_MASK) 267 268 #define NETC_F0_GLOBAL_HBTOR2_RUN_AVG_INT_MASK (0xFF00U) 269 #define NETC_F0_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT (8U) 270 #define NETC_F0_GLOBAL_HBTOR2_RUN_AVG_INT_WIDTH (8U) 271 #define NETC_F0_GLOBAL_HBTOR2_RUN_AVG_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HBTOR2_RUN_AVG_INT_SHIFT)) & NETC_F0_GLOBAL_HBTOR2_RUN_AVG_INT_MASK) 272 273 #define NETC_F0_GLOBAL_HBTOR2_HWM_COL_MASK (0xF0000U) 274 #define NETC_F0_GLOBAL_HBTOR2_HWM_COL_SHIFT (16U) 275 #define NETC_F0_GLOBAL_HBTOR2_HWM_COL_WIDTH (4U) 276 #define NETC_F0_GLOBAL_HBTOR2_HWM_COL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HBTOR2_HWM_COL_SHIFT)) & NETC_F0_GLOBAL_HBTOR2_HWM_COL_MASK) 277 /*! @} */ 278 279 /*! @name SMERBCAPR - Shared memory ENETC receive buffer capability register */ 280 /*! @{ */ 281 282 #define NETC_F0_GLOBAL_SMERBCAPR_THRESH_MASK (0xFFFFFFU) 283 #define NETC_F0_GLOBAL_SMERBCAPR_THRESH_SHIFT (0U) 284 #define NETC_F0_GLOBAL_SMERBCAPR_THRESH_WIDTH (24U) 285 #define NETC_F0_GLOBAL_SMERBCAPR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMERBCAPR_THRESH_SHIFT)) & NETC_F0_GLOBAL_SMERBCAPR_THRESH_MASK) 286 287 #define NETC_F0_GLOBAL_SMERBCAPR_WORD_SIZE_MASK (0x30000000U) 288 #define NETC_F0_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT (28U) 289 #define NETC_F0_GLOBAL_SMERBCAPR_WORD_SIZE_WIDTH (2U) 290 #define NETC_F0_GLOBAL_SMERBCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMERBCAPR_WORD_SIZE_SHIFT)) & NETC_F0_GLOBAL_SMERBCAPR_WORD_SIZE_MASK) 291 292 #define NETC_F0_GLOBAL_SMERBCAPR_MLOC_MASK (0xC0000000U) 293 #define NETC_F0_GLOBAL_SMERBCAPR_MLOC_SHIFT (30U) 294 #define NETC_F0_GLOBAL_SMERBCAPR_MLOC_WIDTH (2U) 295 #define NETC_F0_GLOBAL_SMERBCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMERBCAPR_MLOC_SHIFT)) & NETC_F0_GLOBAL_SMERBCAPR_MLOC_MASK) 296 /*! @} */ 297 298 /*! @name SMERBOR0 - Shared memory ENETC receive buffer operational register 0 */ 299 /*! @{ */ 300 301 #define NETC_F0_GLOBAL_SMERBOR0_AMOUNT_MASK (0xFFFFFFU) 302 #define NETC_F0_GLOBAL_SMERBOR0_AMOUNT_SHIFT (0U) 303 #define NETC_F0_GLOBAL_SMERBOR0_AMOUNT_WIDTH (24U) 304 #define NETC_F0_GLOBAL_SMERBOR0_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMERBOR0_AMOUNT_SHIFT)) & NETC_F0_GLOBAL_SMERBOR0_AMOUNT_MASK) 305 /*! @} */ 306 307 /*! @name SMERBOR1 - Shared memory ENETC receive buffer operational 1 */ 308 /*! @{ */ 309 310 #define NETC_F0_GLOBAL_SMERBOR1_WATERMARK_MASK (0xFFFFFFU) 311 #define NETC_F0_GLOBAL_SMERBOR1_WATERMARK_SHIFT (0U) 312 #define NETC_F0_GLOBAL_SMERBOR1_WATERMARK_WIDTH (24U) 313 #define NETC_F0_GLOBAL_SMERBOR1_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_SMERBOR1_WATERMARK_SHIFT)) & NETC_F0_GLOBAL_SMERBOR1_WATERMARK_MASK) 314 /*! @} */ 315 316 /*! @name PCEOR - PCE 0 operational register */ 317 /*! @{ */ 318 319 #define NETC_F0_GLOBAL_PCEOR_NUM_FRAMES_MASK (0x3FU) 320 #define NETC_F0_GLOBAL_PCEOR_NUM_FRAMES_SHIFT (0U) 321 #define NETC_F0_GLOBAL_PCEOR_NUM_FRAMES_WIDTH (6U) 322 #define NETC_F0_GLOBAL_PCEOR_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_PCEOR_NUM_FRAMES_SHIFT)) & NETC_F0_GLOBAL_PCEOR_NUM_FRAMES_MASK) 323 324 #define NETC_F0_GLOBAL_PCEOR_HWM_FRAMES_MASK (0x3F00U) 325 #define NETC_F0_GLOBAL_PCEOR_HWM_FRAMES_SHIFT (8U) 326 #define NETC_F0_GLOBAL_PCEOR_HWM_FRAMES_WIDTH (6U) 327 #define NETC_F0_GLOBAL_PCEOR_HWM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_PCEOR_HWM_FRAMES_SHIFT)) & NETC_F0_GLOBAL_PCEOR_HWM_FRAMES_MASK) 328 329 #define NETC_F0_GLOBAL_PCEOR_MAX_FRAMES_MASK (0x3F0000U) 330 #define NETC_F0_GLOBAL_PCEOR_MAX_FRAMES_SHIFT (16U) 331 #define NETC_F0_GLOBAL_PCEOR_MAX_FRAMES_WIDTH (6U) 332 #define NETC_F0_GLOBAL_PCEOR_MAX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_PCEOR_MAX_FRAMES_SHIFT)) & NETC_F0_GLOBAL_PCEOR_MAX_FRAMES_MASK) 333 /*! @} */ 334 335 /*! @name RFEOR - Replication Forwarding Engine 0 operational register */ 336 /*! @{ */ 337 338 #define NETC_F0_GLOBAL_RFEOR_NUM_FRAMES_MASK (0x3FU) 339 #define NETC_F0_GLOBAL_RFEOR_NUM_FRAMES_SHIFT (0U) 340 #define NETC_F0_GLOBAL_RFEOR_NUM_FRAMES_WIDTH (6U) 341 #define NETC_F0_GLOBAL_RFEOR_NUM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RFEOR_NUM_FRAMES_SHIFT)) & NETC_F0_GLOBAL_RFEOR_NUM_FRAMES_MASK) 342 343 #define NETC_F0_GLOBAL_RFEOR_HWM_FRAMES_MASK (0x3F00U) 344 #define NETC_F0_GLOBAL_RFEOR_HWM_FRAMES_SHIFT (8U) 345 #define NETC_F0_GLOBAL_RFEOR_HWM_FRAMES_WIDTH (6U) 346 #define NETC_F0_GLOBAL_RFEOR_HWM_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RFEOR_HWM_FRAMES_SHIFT)) & NETC_F0_GLOBAL_RFEOR_HWM_FRAMES_MASK) 347 348 #define NETC_F0_GLOBAL_RFEOR_MAX_FRAMES_MASK (0x3F0000U) 349 #define NETC_F0_GLOBAL_RFEOR_MAX_FRAMES_SHIFT (16U) 350 #define NETC_F0_GLOBAL_RFEOR_MAX_FRAMES_WIDTH (6U) 351 #define NETC_F0_GLOBAL_RFEOR_MAX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RFEOR_MAX_FRAMES_SHIFT)) & NETC_F0_GLOBAL_RFEOR_MAX_FRAMES_MASK) 352 /*! @} */ 353 354 /*! @name NETCCLKR - NETC clock register */ 355 /*! @{ */ 356 357 #define NETC_F0_GLOBAL_NETCCLKR_FREQ_MASK (0x7FFU) 358 #define NETC_F0_GLOBAL_NETCCLKR_FREQ_SHIFT (0U) 359 #define NETC_F0_GLOBAL_NETCCLKR_FREQ_WIDTH (11U) 360 #define NETC_F0_GLOBAL_NETCCLKR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_NETCCLKR_FREQ_SHIFT)) & NETC_F0_GLOBAL_NETCCLKR_FREQ_MASK) 361 /*! @} */ 362 363 /*! @name HTACAPR - HTA 0 capability register */ 364 /*! @{ */ 365 366 #define NETC_F0_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK (0xFFU) 367 #define NETC_F0_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT (0U) 368 #define NETC_F0_GLOBAL_HTACAPR_MAX_RX_FRAMES_WIDTH (8U) 369 #define NETC_F0_GLOBAL_HTACAPR_MAX_RX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTACAPR_MAX_RX_FRAMES_SHIFT)) & NETC_F0_GLOBAL_HTACAPR_MAX_RX_FRAMES_MASK) 370 371 #define NETC_F0_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK (0xFF00U) 372 #define NETC_F0_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT (8U) 373 #define NETC_F0_GLOBAL_HTACAPR_MAX_TX_FRAMES_WIDTH (8U) 374 #define NETC_F0_GLOBAL_HTACAPR_MAX_TX_FRAMES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTACAPR_MAX_TX_FRAMES_SHIFT)) & NETC_F0_GLOBAL_HTACAPR_MAX_TX_FRAMES_MASK) 375 /*! @} */ 376 377 /*! @name HTARFCOR - HTA 0 receive frame count operational register */ 378 /*! @{ */ 379 380 #define NETC_F0_GLOBAL_HTARFCOR_HP_COUNT_MASK (0xFFU) 381 #define NETC_F0_GLOBAL_HTARFCOR_HP_COUNT_SHIFT (0U) 382 #define NETC_F0_GLOBAL_HTARFCOR_HP_COUNT_WIDTH (8U) 383 #define NETC_F0_GLOBAL_HTARFCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTARFCOR_HP_COUNT_SHIFT)) & NETC_F0_GLOBAL_HTARFCOR_HP_COUNT_MASK) 384 385 #define NETC_F0_GLOBAL_HTARFCOR_HP_HWM_MASK (0xFF00U) 386 #define NETC_F0_GLOBAL_HTARFCOR_HP_HWM_SHIFT (8U) 387 #define NETC_F0_GLOBAL_HTARFCOR_HP_HWM_WIDTH (8U) 388 #define NETC_F0_GLOBAL_HTARFCOR_HP_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTARFCOR_HP_HWM_SHIFT)) & NETC_F0_GLOBAL_HTARFCOR_HP_HWM_MASK) 389 390 #define NETC_F0_GLOBAL_HTARFCOR_LP_COUNT_MASK (0xFF0000U) 391 #define NETC_F0_GLOBAL_HTARFCOR_LP_COUNT_SHIFT (16U) 392 #define NETC_F0_GLOBAL_HTARFCOR_LP_COUNT_WIDTH (8U) 393 #define NETC_F0_GLOBAL_HTARFCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTARFCOR_LP_COUNT_SHIFT)) & NETC_F0_GLOBAL_HTARFCOR_LP_COUNT_MASK) 394 395 #define NETC_F0_GLOBAL_HTARFCOR_LP_HWM_MASK (0xFF000000U) 396 #define NETC_F0_GLOBAL_HTARFCOR_LP_HWM_SHIFT (24U) 397 #define NETC_F0_GLOBAL_HTARFCOR_LP_HWM_WIDTH (8U) 398 #define NETC_F0_GLOBAL_HTARFCOR_LP_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTARFCOR_LP_HWM_SHIFT)) & NETC_F0_GLOBAL_HTARFCOR_LP_HWM_MASK) 399 /*! @} */ 400 401 /*! @name HTAHPBCOR - HTA 0 high priority byte count operational register */ 402 /*! @{ */ 403 404 #define NETC_F0_GLOBAL_HTAHPBCOR_HP_COUNT_MASK (0xFFFFU) 405 #define NETC_F0_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT (0U) 406 #define NETC_F0_GLOBAL_HTAHPBCOR_HP_COUNT_WIDTH (16U) 407 #define NETC_F0_GLOBAL_HTAHPBCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTAHPBCOR_HP_COUNT_SHIFT)) & NETC_F0_GLOBAL_HTAHPBCOR_HP_COUNT_MASK) 408 409 #define NETC_F0_GLOBAL_HTAHPBCOR_HWM_MASK (0xFFFF0000U) 410 #define NETC_F0_GLOBAL_HTAHPBCOR_HWM_SHIFT (16U) 411 #define NETC_F0_GLOBAL_HTAHPBCOR_HWM_WIDTH (16U) 412 #define NETC_F0_GLOBAL_HTAHPBCOR_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTAHPBCOR_HWM_SHIFT)) & NETC_F0_GLOBAL_HTAHPBCOR_HWM_MASK) 413 /*! @} */ 414 415 /*! @name HTALPBCOR - HTA 0 low priority byte count operational register */ 416 /*! @{ */ 417 418 #define NETC_F0_GLOBAL_HTALPBCOR_LP_COUNT_MASK (0xFFFFU) 419 #define NETC_F0_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT (0U) 420 #define NETC_F0_GLOBAL_HTALPBCOR_LP_COUNT_WIDTH (16U) 421 #define NETC_F0_GLOBAL_HTALPBCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTALPBCOR_LP_COUNT_SHIFT)) & NETC_F0_GLOBAL_HTALPBCOR_LP_COUNT_MASK) 422 423 #define NETC_F0_GLOBAL_HTALPBCOR_HWM_MASK (0xFFFF0000U) 424 #define NETC_F0_GLOBAL_HTALPBCOR_HWM_SHIFT (16U) 425 #define NETC_F0_GLOBAL_HTALPBCOR_HWM_WIDTH (16U) 426 #define NETC_F0_GLOBAL_HTALPBCOR_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTALPBCOR_HWM_SHIFT)) & NETC_F0_GLOBAL_HTALPBCOR_HWM_MASK) 427 /*! @} */ 428 429 /*! @name HTATFCOR - HTA 0 transmit frame count operational register */ 430 /*! @{ */ 431 432 #define NETC_F0_GLOBAL_HTATFCOR_HP_COUNT_MASK (0xFFU) 433 #define NETC_F0_GLOBAL_HTATFCOR_HP_COUNT_SHIFT (0U) 434 #define NETC_F0_GLOBAL_HTATFCOR_HP_COUNT_WIDTH (8U) 435 #define NETC_F0_GLOBAL_HTATFCOR_HP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTATFCOR_HP_COUNT_SHIFT)) & NETC_F0_GLOBAL_HTATFCOR_HP_COUNT_MASK) 436 437 #define NETC_F0_GLOBAL_HTATFCOR_HP_HWM_MASK (0xFF00U) 438 #define NETC_F0_GLOBAL_HTATFCOR_HP_HWM_SHIFT (8U) 439 #define NETC_F0_GLOBAL_HTATFCOR_HP_HWM_WIDTH (8U) 440 #define NETC_F0_GLOBAL_HTATFCOR_HP_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTATFCOR_HP_HWM_SHIFT)) & NETC_F0_GLOBAL_HTATFCOR_HP_HWM_MASK) 441 442 #define NETC_F0_GLOBAL_HTATFCOR_LP_COUNT_MASK (0xFF0000U) 443 #define NETC_F0_GLOBAL_HTATFCOR_LP_COUNT_SHIFT (16U) 444 #define NETC_F0_GLOBAL_HTATFCOR_LP_COUNT_WIDTH (8U) 445 #define NETC_F0_GLOBAL_HTATFCOR_LP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTATFCOR_LP_COUNT_SHIFT)) & NETC_F0_GLOBAL_HTATFCOR_LP_COUNT_MASK) 446 447 #define NETC_F0_GLOBAL_HTATFCOR_LP_HWM_MASK (0xFF000000U) 448 #define NETC_F0_GLOBAL_HTATFCOR_LP_HWM_SHIFT (24U) 449 #define NETC_F0_GLOBAL_HTATFCOR_LP_HWM_WIDTH (8U) 450 #define NETC_F0_GLOBAL_HTATFCOR_LP_HWM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_HTATFCOR_LP_HWM_SHIFT)) & NETC_F0_GLOBAL_HTATFCOR_LP_HWM_MASK) 451 /*! @} */ 452 453 /*! @name RCSBRLAR - Root complex 0 system bus read latency average register */ 454 /*! @{ */ 455 456 #define NETC_F0_GLOBAL_RCSBRLAR_FRACT_MASK (0xFFU) 457 #define NETC_F0_GLOBAL_RCSBRLAR_FRACT_SHIFT (0U) 458 #define NETC_F0_GLOBAL_RCSBRLAR_FRACT_WIDTH (8U) 459 #define NETC_F0_GLOBAL_RCSBRLAR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RCSBRLAR_FRACT_SHIFT)) & NETC_F0_GLOBAL_RCSBRLAR_FRACT_MASK) 460 461 #define NETC_F0_GLOBAL_RCSBRLAR_INT_MASK (0xFFF00U) 462 #define NETC_F0_GLOBAL_RCSBRLAR_INT_SHIFT (8U) 463 #define NETC_F0_GLOBAL_RCSBRLAR_INT_WIDTH (12U) 464 #define NETC_F0_GLOBAL_RCSBRLAR_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RCSBRLAR_INT_SHIFT)) & NETC_F0_GLOBAL_RCSBRLAR_INT_MASK) 465 /*! @} */ 466 467 /*! @name RCSBRLHWMR - Root complex 0 system bus read latency high watermark register */ 468 /*! @{ */ 469 470 #define NETC_F0_GLOBAL_RCSBRLHWMR_FRACT_MASK (0xFFU) 471 #define NETC_F0_GLOBAL_RCSBRLHWMR_FRACT_SHIFT (0U) 472 #define NETC_F0_GLOBAL_RCSBRLHWMR_FRACT_WIDTH (8U) 473 #define NETC_F0_GLOBAL_RCSBRLHWMR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RCSBRLHWMR_FRACT_SHIFT)) & NETC_F0_GLOBAL_RCSBRLHWMR_FRACT_MASK) 474 475 #define NETC_F0_GLOBAL_RCSBRLHWMR_INT_MASK (0xFFF00U) 476 #define NETC_F0_GLOBAL_RCSBRLHWMR_INT_SHIFT (8U) 477 #define NETC_F0_GLOBAL_RCSBRLHWMR_INT_WIDTH (12U) 478 #define NETC_F0_GLOBAL_RCSBRLHWMR_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RCSBRLHWMR_INT_SHIFT)) & NETC_F0_GLOBAL_RCSBRLHWMR_INT_MASK) 479 /*! @} */ 480 481 /*! @name RCSBWLAR - Root complex 0 system bus write latency average register */ 482 /*! @{ */ 483 484 #define NETC_F0_GLOBAL_RCSBWLAR_FRACT_MASK (0xFFU) 485 #define NETC_F0_GLOBAL_RCSBWLAR_FRACT_SHIFT (0U) 486 #define NETC_F0_GLOBAL_RCSBWLAR_FRACT_WIDTH (8U) 487 #define NETC_F0_GLOBAL_RCSBWLAR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RCSBWLAR_FRACT_SHIFT)) & NETC_F0_GLOBAL_RCSBWLAR_FRACT_MASK) 488 489 #define NETC_F0_GLOBAL_RCSBWLAR_INT_MASK (0xFFF00U) 490 #define NETC_F0_GLOBAL_RCSBWLAR_INT_SHIFT (8U) 491 #define NETC_F0_GLOBAL_RCSBWLAR_INT_WIDTH (12U) 492 #define NETC_F0_GLOBAL_RCSBWLAR_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RCSBWLAR_INT_SHIFT)) & NETC_F0_GLOBAL_RCSBWLAR_INT_MASK) 493 /*! @} */ 494 495 /*! @name RCSBWLHWMR - Root complex 0 system bus write latency high watermark register */ 496 /*! @{ */ 497 498 #define NETC_F0_GLOBAL_RCSBWLHWMR_FRACT_MASK (0xFFU) 499 #define NETC_F0_GLOBAL_RCSBWLHWMR_FRACT_SHIFT (0U) 500 #define NETC_F0_GLOBAL_RCSBWLHWMR_FRACT_WIDTH (8U) 501 #define NETC_F0_GLOBAL_RCSBWLHWMR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RCSBWLHWMR_FRACT_SHIFT)) & NETC_F0_GLOBAL_RCSBWLHWMR_FRACT_MASK) 502 503 #define NETC_F0_GLOBAL_RCSBWLHWMR_INT_MASK (0xFFF00U) 504 #define NETC_F0_GLOBAL_RCSBWLHWMR_INT_SHIFT (8U) 505 #define NETC_F0_GLOBAL_RCSBWLHWMR_INT_WIDTH (12U) 506 #define NETC_F0_GLOBAL_RCSBWLHWMR_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_RCSBWLHWMR_INT_SHIFT)) & NETC_F0_GLOBAL_RCSBWLHWMR_INT_MASK) 507 /*! @} */ 508 509 /*! @name IPBRR0 - IP block revision register 0 */ 510 /*! @{ */ 511 512 #define NETC_F0_GLOBAL_IPBRR0_IP_MN_MASK (0xFFU) 513 #define NETC_F0_GLOBAL_IPBRR0_IP_MN_SHIFT (0U) 514 #define NETC_F0_GLOBAL_IPBRR0_IP_MN_WIDTH (8U) 515 #define NETC_F0_GLOBAL_IPBRR0_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_IPBRR0_IP_MN_SHIFT)) & NETC_F0_GLOBAL_IPBRR0_IP_MN_MASK) 516 517 #define NETC_F0_GLOBAL_IPBRR0_IP_MJ_MASK (0xFF00U) 518 #define NETC_F0_GLOBAL_IPBRR0_IP_MJ_SHIFT (8U) 519 #define NETC_F0_GLOBAL_IPBRR0_IP_MJ_WIDTH (8U) 520 #define NETC_F0_GLOBAL_IPBRR0_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_IPBRR0_IP_MJ_SHIFT)) & NETC_F0_GLOBAL_IPBRR0_IP_MJ_MASK) 521 522 #define NETC_F0_GLOBAL_IPBRR0_IP_ID_MASK (0xFFFF0000U) 523 #define NETC_F0_GLOBAL_IPBRR0_IP_ID_SHIFT (16U) 524 #define NETC_F0_GLOBAL_IPBRR0_IP_ID_WIDTH (16U) 525 #define NETC_F0_GLOBAL_IPBRR0_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_IPBRR0_IP_ID_SHIFT)) & NETC_F0_GLOBAL_IPBRR0_IP_ID_MASK) 526 /*! @} */ 527 528 /*! @name IPBRR1 - IP block revision register 1 */ 529 /*! @{ */ 530 531 #define NETC_F0_GLOBAL_IPBRR1_IP_CFG_MASK (0xFFU) 532 #define NETC_F0_GLOBAL_IPBRR1_IP_CFG_SHIFT (0U) 533 #define NETC_F0_GLOBAL_IPBRR1_IP_CFG_WIDTH (8U) 534 #define NETC_F0_GLOBAL_IPBRR1_IP_CFG(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_IPBRR1_IP_CFG_SHIFT)) & NETC_F0_GLOBAL_IPBRR1_IP_CFG_MASK) 535 536 #define NETC_F0_GLOBAL_IPBRR1_IP_MNT_MASK (0xFF00U) 537 #define NETC_F0_GLOBAL_IPBRR1_IP_MNT_SHIFT (8U) 538 #define NETC_F0_GLOBAL_IPBRR1_IP_MNT_WIDTH (8U) 539 #define NETC_F0_GLOBAL_IPBRR1_IP_MNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_IPBRR1_IP_MNT_SHIFT)) & NETC_F0_GLOBAL_IPBRR1_IP_MNT_MASK) 540 541 #define NETC_F0_GLOBAL_IPBRR1_IP_INT_MASK (0xFF0000U) 542 #define NETC_F0_GLOBAL_IPBRR1_IP_INT_SHIFT (16U) 543 #define NETC_F0_GLOBAL_IPBRR1_IP_INT_WIDTH (8U) 544 #define NETC_F0_GLOBAL_IPBRR1_IP_INT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_IPBRR1_IP_INT_SHIFT)) & NETC_F0_GLOBAL_IPBRR1_IP_INT_MASK) 545 /*! @} */ 546 547 /*! @name FBLPR - Function boot loader parameter register 0..Function boot loader parameter register 1 */ 548 /*! @{ */ 549 550 #define NETC_F0_GLOBAL_FBLPR_PARAM_VAL_MASK (0xFFFFFFFFU) 551 #define NETC_F0_GLOBAL_FBLPR_PARAM_VAL_SHIFT (0U) 552 #define NETC_F0_GLOBAL_FBLPR_PARAM_VAL_WIDTH (32U) 553 #define NETC_F0_GLOBAL_FBLPR_PARAM_VAL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_FBLPR_PARAM_VAL_SHIFT)) & NETC_F0_GLOBAL_FBLPR_PARAM_VAL_MASK) 554 /*! @} */ 555 556 /*! @name TUFSBECR - Timer uncorrectable fatal system bus error configuration register */ 557 /*! @{ */ 558 559 #define NETC_F0_GLOBAL_TUFSBECR_RD_MASK (0x80000000U) 560 #define NETC_F0_GLOBAL_TUFSBECR_RD_SHIFT (31U) 561 #define NETC_F0_GLOBAL_TUFSBECR_RD_WIDTH (1U) 562 #define NETC_F0_GLOBAL_TUFSBECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_TUFSBECR_RD_SHIFT)) & NETC_F0_GLOBAL_TUFSBECR_RD_MASK) 563 /*! @} */ 564 565 /*! @name TUFSBESR - Timer uncorrectable fatal system bus error status register */ 566 /*! @{ */ 567 568 #define NETC_F0_GLOBAL_TUFSBESR_SB_ID_MASK (0xFU) 569 #define NETC_F0_GLOBAL_TUFSBESR_SB_ID_SHIFT (0U) 570 #define NETC_F0_GLOBAL_TUFSBESR_SB_ID_WIDTH (4U) 571 #define NETC_F0_GLOBAL_TUFSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_TUFSBESR_SB_ID_SHIFT)) & NETC_F0_GLOBAL_TUFSBESR_SB_ID_MASK) 572 573 #define NETC_F0_GLOBAL_TUFSBESR_M_MASK (0x40000000U) 574 #define NETC_F0_GLOBAL_TUFSBESR_M_SHIFT (30U) 575 #define NETC_F0_GLOBAL_TUFSBESR_M_WIDTH (1U) 576 #define NETC_F0_GLOBAL_TUFSBESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_TUFSBESR_M_SHIFT)) & NETC_F0_GLOBAL_TUFSBESR_M_MASK) 577 578 #define NETC_F0_GLOBAL_TUFSBESR_SBE_MASK (0x80000000U) 579 #define NETC_F0_GLOBAL_TUFSBESR_SBE_SHIFT (31U) 580 #define NETC_F0_GLOBAL_TUFSBESR_SBE_WIDTH (1U) 581 #define NETC_F0_GLOBAL_TUFSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F0_GLOBAL_TUFSBESR_SBE_SHIFT)) & NETC_F0_GLOBAL_TUFSBESR_SBE_MASK) 582 /*! @} */ 583 584 /*! 585 * @} 586 */ /* end of group NETC_F0_GLOBAL_Register_Masks */ 587 588 /*! 589 * @} 590 */ /* end of group NETC_F0_GLOBAL_Peripheral_Access_Layer */ 591 592 #endif /* #if !defined(S32Z2_NETC_F0_GLOBAL_H_) */ 593
