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Searched refs:Mask (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/Uart/include/
DLinflexd_Uart_Ip_HwAccess.h657 uint32 Mask; in Linflexd_Uart_Ip_SetTxDataBuffer2Bytes() local
664 Mask = LINFLEXD_BDRL_DATA0_MASK | LINFLEXD_BDRL_DATA1_MASK; in Linflexd_Uart_Ip_SetTxDataBuffer2Bytes()
665 Base->BDRL = ((uint32)DataTemp & Mask); in Linflexd_Uart_Ip_SetTxDataBuffer2Bytes()
693 uint32 Mask = LINFLEXD_BDRM_DATA4_MASK | LINFLEXD_BDRM_DATA5_MASK; in Linflexd_Uart_Ip_GetRxDataBuffer2Bytes() local
694 Data = (uint16)(Base->BDRM & Mask); in Linflexd_Uart_Ip_GetRxDataBuffer2Bytes()
/hal_nxp-3.6.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h884 uint32 Mask in Qspi_Ip_EnableInt() argument
887 BaseAddr->RSER |= Mask; in Qspi_Ip_EnableInt()
895 uint32 Mask in Qspi_Ip_DisableInt() argument
898 BaseAddr->RSER &= ~Mask; in Qspi_Ip_DisableInt()
906 uint32 Mask in Qspi_Ip_ClearIntFlag() argument
909 BaseAddr->FR = Mask; in Qspi_Ip_ClearIntFlag()
1164 uint8 Mask) in Qspi_Ip_Sfp_SetTgMask() argument
1170 RegValue |= QuadSPI_TGMDAD_MASK(Mask); in Qspi_Ip_Sfp_SetTgMask()
DQspi_Ip_Types.h381 uint8 Mask; member
/hal_nxp-3.6.0/s32/drivers/s32k3/Adc/src/
DAdc_Sar_Ip.c371 const uint32 * const Mask);
373 const uint32 * const Mask);
1435 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx); in Adc_Sar_CheckAndCallEocNotification() local
1445 Cimr = (CIMR(AdcAEBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1452 Cimr = (CIMR(AdcBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1455 Ceocfr = ((*CEOCFRAddr) & Mask); in Adc_Sar_CheckAndCallEocNotification()
1460 *CEOCFRAddr = Mask; in Adc_Sar_CheckAndCallEocNotification()
1490 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx); in Adc_Sar_CheckAndCallWorrNotification() local
1504 Cwenr = (CWENR(AdcAEBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallWorrNotification()
1513 Cwenr = (CWENR(AdcBasePtr, VectAdr) & Mask); in Adc_Sar_CheckAndCallWorrNotification()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcl/src/
DLcu_Ip_Hw_Access.c405 uint8 Mask = 1U << HwOutput; in HwAcc_Lcu_AsyncGetCombineForceInput() local
409 ReturnValue = (uint8)((ReturnValue & Mask) >> HwOutput); in HwAcc_Lcu_AsyncGetCombineForceInput()
597 uint8 Mask = 1U << HwOutput; in HwAcc_Lcu_AsyncGetCombineForce() local
601 *Value = (uint8)((ReturnValue & Mask) >> HwOutput); in HwAcc_Lcu_AsyncGetCombineForce()
/hal_nxp-3.6.0/s32/drivers/s32ze/Dio/include/
DSiul2_Dio_Ip_TrustedFunctions.h129 Dio_PortLevelType Mask
/hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/include/
DGmac_Ip.h649 const uint8 Mask,
/hal_nxp-3.6.0/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Controller.c1823 Qspi_Ip_Sfp_SetTgMask(baseAddr, Index, userConfigPtr->SfpCfg.Tg[Index].Mask); in Qspi_Ip_Sfp_Configure_Mdad()
/hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip.c2546 const uint8 Mask, in Gmac_Ip_SetAddrPerfectFilter() argument
2580 Base->MAC_ADDRESS1_HIGH |= GMAC_MAC_ADDRESS1_HIGH_MBC(Mask); in Gmac_Ip_SetAddrPerfectFilter()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX9352/iar/
Dstartup_MIMX9352_cm33.s358 CPSID I ; Mask interrupts