1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MU.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_MU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MU - Size of Registers Arrays */ 72 #define MU_TR_COUNT 16u 73 #define MU_RR_COUNT 16u 74 75 /** MU - Register Layout Typedef */ 76 typedef struct { 77 __I uint32_t VER; /**< Version ID, offset: 0x0 */ 78 __I uint32_t PAR; /**< Parameter Register, offset: 0x4 */ 79 __IO uint32_t CR; /**< Control Register, offset: 0x8 */ 80 __IO uint32_t SR; /**< Status Register, offset: 0xC */ 81 __IO uint32_t CCR0; /**< Core Control Register 0, offset: 0x10 */ 82 uint8_t RESERVED_0[4]; 83 __IO uint32_t CSSR0; /**< Core Sticky Status Register 0, offset: 0x18 */ 84 uint8_t RESERVED_1[228]; 85 __IO uint32_t FCR; /**< Flag Control Register, offset: 0x100 */ 86 __I uint32_t FSR; /**< Flag Status Register, offset: 0x104 */ 87 uint8_t RESERVED_2[8]; 88 __IO uint32_t GIER; /**< General-purpose Interrupt Enable Register, offset: 0x110 */ 89 __IO uint32_t GCR; /**< General-purpose Control Register, offset: 0x114 */ 90 __IO uint32_t GSR; /**< General-purpose Status Register, offset: 0x118 */ 91 uint8_t RESERVED_3[4]; 92 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0x120 */ 93 __I uint32_t TSR; /**< Transmit Status Register, offset: 0x124 */ 94 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x128 */ 95 __I uint32_t RSR; /**< Receive Status Register, offset: 0x12C */ 96 uint8_t RESERVED_4[208]; 97 __O uint32_t TR[MU_TR_COUNT]; /**< Transmit Register, array offset: 0x200, array step: 0x4 */ 98 uint8_t RESERVED_5[64]; 99 __I uint32_t RR[MU_RR_COUNT]; /**< Receive Register, array offset: 0x280, array step: 0x4 */ 100 } MU_Type, *MU_MemMapPtr; 101 102 /** Number of instances of the MU module. */ 103 #define MU_INSTANCE_COUNT (16u) 104 105 /* MU - Peripheral instance base addresses */ 106 /** Peripheral MU0__MUA base address */ 107 #define IP_MU0__MUA_BASE (0x23258000u) 108 /** Peripheral MU0__MUA base pointer */ 109 #define IP_MU0__MUA ((MU_Type *)IP_MU0__MUA_BASE) 110 /** Peripheral MU0__MUB base address */ 111 #define IP_MU0__MUB_BASE (0x42200000u) 112 /** Peripheral MU0__MUB base pointer */ 113 #define IP_MU0__MUB ((MU_Type *)IP_MU0__MUB_BASE) 114 /** Peripheral MU1__MUA base address */ 115 #define IP_MU1__MUA_BASE (0x23259000u) 116 /** Peripheral MU1__MUA base pointer */ 117 #define IP_MU1__MUA ((MU_Type *)IP_MU1__MUA_BASE) 118 /** Peripheral MU1__MUB base address */ 119 #define IP_MU1__MUB_BASE (0x42210000u) 120 /** Peripheral MU1__MUB base pointer */ 121 #define IP_MU1__MUB ((MU_Type *)IP_MU1__MUB_BASE) 122 /** Peripheral MU2__MUA base address */ 123 #define IP_MU2__MUA_BASE (0x2325A000u) 124 /** Peripheral MU2__MUA base pointer */ 125 #define IP_MU2__MUA ((MU_Type *)IP_MU2__MUA_BASE) 126 /** Peripheral MU2__MUB base address */ 127 #define IP_MU2__MUB_BASE (0x42220000u) 128 /** Peripheral MU2__MUB base pointer */ 129 #define IP_MU2__MUB ((MU_Type *)IP_MU2__MUB_BASE) 130 /** Peripheral MU3__MUA base address */ 131 #define IP_MU3__MUA_BASE (0x2325B000u) 132 /** Peripheral MU3__MUA base pointer */ 133 #define IP_MU3__MUA ((MU_Type *)IP_MU3__MUA_BASE) 134 /** Peripheral MU3__MUB base address */ 135 #define IP_MU3__MUB_BASE (0x42230000u) 136 /** Peripheral MU3__MUB base pointer */ 137 #define IP_MU3__MUB ((MU_Type *)IP_MU3__MUB_BASE) 138 /** Peripheral MU4__MUA base address */ 139 #define IP_MU4__MUA_BASE (0x2325C000u) 140 /** Peripheral MU4__MUA base pointer */ 141 #define IP_MU4__MUA ((MU_Type *)IP_MU4__MUA_BASE) 142 /** Peripheral MU4__MUB base address */ 143 #define IP_MU4__MUB_BASE (0x42240000u) 144 /** Peripheral MU4__MUB base pointer */ 145 #define IP_MU4__MUB ((MU_Type *)IP_MU4__MUB_BASE) 146 /** Peripheral MU5__MUA base address */ 147 #define IP_MU5__MUA_BASE (0x2325D000u) 148 /** Peripheral MU5__MUA base pointer */ 149 #define IP_MU5__MUA ((MU_Type *)IP_MU5__MUA_BASE) 150 /** Peripheral MU5__MUB base address */ 151 #define IP_MU5__MUB_BASE (0x42250000u) 152 /** Peripheral MU5__MUB base pointer */ 153 #define IP_MU5__MUB ((MU_Type *)IP_MU5__MUB_BASE) 154 /** Peripheral MU6__MUA base address */ 155 #define IP_MU6__MUA_BASE (0x2325E000u) 156 /** Peripheral MU6__MUA base pointer */ 157 #define IP_MU6__MUA ((MU_Type *)IP_MU6__MUA_BASE) 158 /** Peripheral MU6__MUB base address */ 159 #define IP_MU6__MUB_BASE (0x42260000u) 160 /** Peripheral MU6__MUB base pointer */ 161 #define IP_MU6__MUB ((MU_Type *)IP_MU6__MUB_BASE) 162 /** Peripheral MU7__MUA base address */ 163 #define IP_MU7__MUA_BASE (0x2325F000u) 164 /** Peripheral MU7__MUA base pointer */ 165 #define IP_MU7__MUA ((MU_Type *)IP_MU7__MUA_BASE) 166 /** Peripheral MU7__MUB base address */ 167 #define IP_MU7__MUB_BASE (0x42270000u) 168 /** Peripheral MU7__MUB base pointer */ 169 #define IP_MU7__MUB ((MU_Type *)IP_MU7__MUB_BASE) 170 /** Array initializer of MU peripheral base addresses */ 171 #define IP_MU_BASE_ADDRS { IP_MU0__MUA_BASE, IP_MU0__MUB_BASE, IP_MU1__MUA_BASE, IP_MU1__MUB_BASE, IP_MU2__MUA_BASE, IP_MU2__MUB_BASE, IP_MU3__MUA_BASE, IP_MU3__MUB_BASE, IP_MU4__MUA_BASE, IP_MU4__MUB_BASE, IP_MU5__MUA_BASE, IP_MU5__MUB_BASE, IP_MU6__MUA_BASE, IP_MU6__MUB_BASE, IP_MU7__MUA_BASE, IP_MU7__MUB_BASE } 172 /** Array initializer of MU peripheral base pointers */ 173 #define IP_MU_BASE_PTRS { IP_MU0__MUA, IP_MU0__MUB, IP_MU1__MUA, IP_MU1__MUB, IP_MU2__MUA, IP_MU2__MUB, IP_MU3__MUA, IP_MU3__MUB, IP_MU4__MUA, IP_MU4__MUB, IP_MU5__MUA, IP_MU5__MUB, IP_MU6__MUA, IP_MU6__MUB, IP_MU7__MUA, IP_MU7__MUB } 174 175 /* ---------------------------------------------------------------------------- 176 -- MU Register Masks 177 ---------------------------------------------------------------------------- */ 178 179 /*! 180 * @addtogroup MU_Register_Masks MU Register Masks 181 * @{ 182 */ 183 184 /*! @name VER - Version ID */ 185 /*! @{ */ 186 187 #define MU_VER_FEATURE_MASK (0xFFFFU) 188 #define MU_VER_FEATURE_SHIFT (0U) 189 #define MU_VER_FEATURE_WIDTH (16U) 190 #define MU_VER_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_FEATURE_SHIFT)) & MU_VER_FEATURE_MASK) 191 192 #define MU_VER_MINOR_MASK (0xFF0000U) 193 #define MU_VER_MINOR_SHIFT (16U) 194 #define MU_VER_MINOR_WIDTH (8U) 195 #define MU_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MINOR_SHIFT)) & MU_VER_MINOR_MASK) 196 197 #define MU_VER_MAJOR_MASK (0xFF000000U) 198 #define MU_VER_MAJOR_SHIFT (24U) 199 #define MU_VER_MAJOR_WIDTH (8U) 200 #define MU_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MU_VER_MAJOR_SHIFT)) & MU_VER_MAJOR_MASK) 201 /*! @} */ 202 203 /*! @name PAR - Parameter Register */ 204 /*! @{ */ 205 206 #define MU_PAR_TR_NUM_MASK (0xFFU) 207 #define MU_PAR_TR_NUM_SHIFT (0U) 208 #define MU_PAR_TR_NUM_WIDTH (8U) 209 #define MU_PAR_TR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_TR_NUM_SHIFT)) & MU_PAR_TR_NUM_MASK) 210 211 #define MU_PAR_RR_NUM_MASK (0xFF00U) 212 #define MU_PAR_RR_NUM_SHIFT (8U) 213 #define MU_PAR_RR_NUM_WIDTH (8U) 214 #define MU_PAR_RR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_RR_NUM_SHIFT)) & MU_PAR_RR_NUM_MASK) 215 216 #define MU_PAR_GIR_NUM_MASK (0xFF0000U) 217 #define MU_PAR_GIR_NUM_SHIFT (16U) 218 #define MU_PAR_GIR_NUM_WIDTH (8U) 219 #define MU_PAR_GIR_NUM(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_GIR_NUM_SHIFT)) & MU_PAR_GIR_NUM_MASK) 220 221 #define MU_PAR_FLAG_WIDTH_MASK (0xFF000000U) 222 #define MU_PAR_FLAG_WIDTH_SHIFT (24U) 223 #define MU_PAR_FLAG_WIDTH_WIDTH (8U) 224 #define MU_PAR_FLAG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MU_PAR_FLAG_WIDTH_SHIFT)) & MU_PAR_FLAG_WIDTH_MASK) 225 /*! @} */ 226 227 /*! @name CR - Control Register */ 228 /*! @{ */ 229 230 #define MU_CR_MUR_MASK (0x1U) 231 #define MU_CR_MUR_SHIFT (0U) 232 #define MU_CR_MUR_WIDTH (1U) 233 #define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) 234 235 #define MU_CR_MURIE_MASK (0x2U) 236 #define MU_CR_MURIE_SHIFT (1U) 237 #define MU_CR_MURIE_WIDTH (1U) 238 #define MU_CR_MURIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MURIE_SHIFT)) & MU_CR_MURIE_MASK) 239 /*! @} */ 240 241 /*! @name SR - Status Register */ 242 /*! @{ */ 243 244 #define MU_SR_MURS_MASK (0x1U) 245 #define MU_SR_MURS_SHIFT (0U) 246 #define MU_SR_MURS_WIDTH (1U) 247 #define MU_SR_MURS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURS_SHIFT)) & MU_SR_MURS_MASK) 248 249 #define MU_SR_MURIP_MASK (0x2U) 250 #define MU_SR_MURIP_SHIFT (1U) 251 #define MU_SR_MURIP_WIDTH (1U) 252 #define MU_SR_MURIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_MURIP_SHIFT)) & MU_SR_MURIP_MASK) 253 254 #define MU_SR_EP_MASK (0x4U) 255 #define MU_SR_EP_SHIFT (2U) 256 #define MU_SR_EP_WIDTH (1U) 257 #define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) 258 259 #define MU_SR_FUP_MASK (0x8U) 260 #define MU_SR_FUP_SHIFT (3U) 261 #define MU_SR_FUP_WIDTH (1U) 262 #define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) 263 264 #define MU_SR_GIRP_MASK (0x10U) 265 #define MU_SR_GIRP_SHIFT (4U) 266 #define MU_SR_GIRP_WIDTH (1U) 267 #define MU_SR_GIRP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIRP_SHIFT)) & MU_SR_GIRP_MASK) 268 269 #define MU_SR_TEP_MASK (0x20U) 270 #define MU_SR_TEP_SHIFT (5U) 271 #define MU_SR_TEP_WIDTH (1U) 272 #define MU_SR_TEP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEP_SHIFT)) & MU_SR_TEP_MASK) 273 274 #define MU_SR_RFP_MASK (0x40U) 275 #define MU_SR_RFP_SHIFT (6U) 276 #define MU_SR_RFP_WIDTH (1U) 277 #define MU_SR_RFP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFP_SHIFT)) & MU_SR_RFP_MASK) 278 /*! @} */ 279 280 /*! @name CCR0 - Core Control Register 0 */ 281 /*! @{ */ 282 283 #define MU_CCR0_NMI_MASK (0x1U) 284 #define MU_CCR0_NMI_SHIFT (0U) 285 #define MU_CCR0_NMI_WIDTH (1U) 286 #define MU_CCR0_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CCR0_NMI_SHIFT)) & MU_CCR0_NMI_MASK) 287 /*! @} */ 288 289 /*! @name CSSR0 - Core Sticky Status Register 0 */ 290 /*! @{ */ 291 292 #define MU_CSSR0_NMIC_MASK (0x1U) 293 #define MU_CSSR0_NMIC_SHIFT (0U) 294 #define MU_CSSR0_NMIC_WIDTH (1U) 295 #define MU_CSSR0_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_CSSR0_NMIC_SHIFT)) & MU_CSSR0_NMIC_MASK) 296 /*! @} */ 297 298 /*! @name FCR - Flag Control Register */ 299 /*! @{ */ 300 301 #define MU_FCR_F0_MASK (0x1U) 302 #define MU_FCR_F0_SHIFT (0U) 303 #define MU_FCR_F0_WIDTH (1U) 304 #define MU_FCR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F0_SHIFT)) & MU_FCR_F0_MASK) 305 306 #define MU_FCR_F1_MASK (0x2U) 307 #define MU_FCR_F1_SHIFT (1U) 308 #define MU_FCR_F1_WIDTH (1U) 309 #define MU_FCR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F1_SHIFT)) & MU_FCR_F1_MASK) 310 311 #define MU_FCR_F2_MASK (0x4U) 312 #define MU_FCR_F2_SHIFT (2U) 313 #define MU_FCR_F2_WIDTH (1U) 314 #define MU_FCR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F2_SHIFT)) & MU_FCR_F2_MASK) 315 316 #define MU_FCR_F3_MASK (0x8U) 317 #define MU_FCR_F3_SHIFT (3U) 318 #define MU_FCR_F3_WIDTH (1U) 319 #define MU_FCR_F3(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F3_SHIFT)) & MU_FCR_F3_MASK) 320 321 #define MU_FCR_F4_MASK (0x10U) 322 #define MU_FCR_F4_SHIFT (4U) 323 #define MU_FCR_F4_WIDTH (1U) 324 #define MU_FCR_F4(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F4_SHIFT)) & MU_FCR_F4_MASK) 325 326 #define MU_FCR_F5_MASK (0x20U) 327 #define MU_FCR_F5_SHIFT (5U) 328 #define MU_FCR_F5_WIDTH (1U) 329 #define MU_FCR_F5(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F5_SHIFT)) & MU_FCR_F5_MASK) 330 331 #define MU_FCR_F6_MASK (0x40U) 332 #define MU_FCR_F6_SHIFT (6U) 333 #define MU_FCR_F6_WIDTH (1U) 334 #define MU_FCR_F6(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F6_SHIFT)) & MU_FCR_F6_MASK) 335 336 #define MU_FCR_F7_MASK (0x80U) 337 #define MU_FCR_F7_SHIFT (7U) 338 #define MU_FCR_F7_WIDTH (1U) 339 #define MU_FCR_F7(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F7_SHIFT)) & MU_FCR_F7_MASK) 340 341 #define MU_FCR_F8_MASK (0x100U) 342 #define MU_FCR_F8_SHIFT (8U) 343 #define MU_FCR_F8_WIDTH (1U) 344 #define MU_FCR_F8(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F8_SHIFT)) & MU_FCR_F8_MASK) 345 346 #define MU_FCR_F9_MASK (0x200U) 347 #define MU_FCR_F9_SHIFT (9U) 348 #define MU_FCR_F9_WIDTH (1U) 349 #define MU_FCR_F9(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F9_SHIFT)) & MU_FCR_F9_MASK) 350 351 #define MU_FCR_F10_MASK (0x400U) 352 #define MU_FCR_F10_SHIFT (10U) 353 #define MU_FCR_F10_WIDTH (1U) 354 #define MU_FCR_F10(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F10_SHIFT)) & MU_FCR_F10_MASK) 355 356 #define MU_FCR_F11_MASK (0x800U) 357 #define MU_FCR_F11_SHIFT (11U) 358 #define MU_FCR_F11_WIDTH (1U) 359 #define MU_FCR_F11(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F11_SHIFT)) & MU_FCR_F11_MASK) 360 361 #define MU_FCR_F12_MASK (0x1000U) 362 #define MU_FCR_F12_SHIFT (12U) 363 #define MU_FCR_F12_WIDTH (1U) 364 #define MU_FCR_F12(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F12_SHIFT)) & MU_FCR_F12_MASK) 365 366 #define MU_FCR_F13_MASK (0x2000U) 367 #define MU_FCR_F13_SHIFT (13U) 368 #define MU_FCR_F13_WIDTH (1U) 369 #define MU_FCR_F13(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F13_SHIFT)) & MU_FCR_F13_MASK) 370 371 #define MU_FCR_F14_MASK (0x4000U) 372 #define MU_FCR_F14_SHIFT (14U) 373 #define MU_FCR_F14_WIDTH (1U) 374 #define MU_FCR_F14(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F14_SHIFT)) & MU_FCR_F14_MASK) 375 376 #define MU_FCR_F15_MASK (0x8000U) 377 #define MU_FCR_F15_SHIFT (15U) 378 #define MU_FCR_F15_WIDTH (1U) 379 #define MU_FCR_F15(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F15_SHIFT)) & MU_FCR_F15_MASK) 380 381 #define MU_FCR_F16_MASK (0x10000U) 382 #define MU_FCR_F16_SHIFT (16U) 383 #define MU_FCR_F16_WIDTH (1U) 384 #define MU_FCR_F16(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F16_SHIFT)) & MU_FCR_F16_MASK) 385 386 #define MU_FCR_F17_MASK (0x20000U) 387 #define MU_FCR_F17_SHIFT (17U) 388 #define MU_FCR_F17_WIDTH (1U) 389 #define MU_FCR_F17(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F17_SHIFT)) & MU_FCR_F17_MASK) 390 391 #define MU_FCR_F18_MASK (0x40000U) 392 #define MU_FCR_F18_SHIFT (18U) 393 #define MU_FCR_F18_WIDTH (1U) 394 #define MU_FCR_F18(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F18_SHIFT)) & MU_FCR_F18_MASK) 395 396 #define MU_FCR_F19_MASK (0x80000U) 397 #define MU_FCR_F19_SHIFT (19U) 398 #define MU_FCR_F19_WIDTH (1U) 399 #define MU_FCR_F19(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F19_SHIFT)) & MU_FCR_F19_MASK) 400 401 #define MU_FCR_F20_MASK (0x100000U) 402 #define MU_FCR_F20_SHIFT (20U) 403 #define MU_FCR_F20_WIDTH (1U) 404 #define MU_FCR_F20(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F20_SHIFT)) & MU_FCR_F20_MASK) 405 406 #define MU_FCR_F21_MASK (0x200000U) 407 #define MU_FCR_F21_SHIFT (21U) 408 #define MU_FCR_F21_WIDTH (1U) 409 #define MU_FCR_F21(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F21_SHIFT)) & MU_FCR_F21_MASK) 410 411 #define MU_FCR_F22_MASK (0x400000U) 412 #define MU_FCR_F22_SHIFT (22U) 413 #define MU_FCR_F22_WIDTH (1U) 414 #define MU_FCR_F22(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F22_SHIFT)) & MU_FCR_F22_MASK) 415 416 #define MU_FCR_F23_MASK (0x800000U) 417 #define MU_FCR_F23_SHIFT (23U) 418 #define MU_FCR_F23_WIDTH (1U) 419 #define MU_FCR_F23(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F23_SHIFT)) & MU_FCR_F23_MASK) 420 421 #define MU_FCR_F24_MASK (0x1000000U) 422 #define MU_FCR_F24_SHIFT (24U) 423 #define MU_FCR_F24_WIDTH (1U) 424 #define MU_FCR_F24(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F24_SHIFT)) & MU_FCR_F24_MASK) 425 426 #define MU_FCR_F25_MASK (0x2000000U) 427 #define MU_FCR_F25_SHIFT (25U) 428 #define MU_FCR_F25_WIDTH (1U) 429 #define MU_FCR_F25(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F25_SHIFT)) & MU_FCR_F25_MASK) 430 431 #define MU_FCR_F26_MASK (0x4000000U) 432 #define MU_FCR_F26_SHIFT (26U) 433 #define MU_FCR_F26_WIDTH (1U) 434 #define MU_FCR_F26(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F26_SHIFT)) & MU_FCR_F26_MASK) 435 436 #define MU_FCR_F27_MASK (0x8000000U) 437 #define MU_FCR_F27_SHIFT (27U) 438 #define MU_FCR_F27_WIDTH (1U) 439 #define MU_FCR_F27(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F27_SHIFT)) & MU_FCR_F27_MASK) 440 441 #define MU_FCR_F28_MASK (0x10000000U) 442 #define MU_FCR_F28_SHIFT (28U) 443 #define MU_FCR_F28_WIDTH (1U) 444 #define MU_FCR_F28(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F28_SHIFT)) & MU_FCR_F28_MASK) 445 446 #define MU_FCR_F29_MASK (0x20000000U) 447 #define MU_FCR_F29_SHIFT (29U) 448 #define MU_FCR_F29_WIDTH (1U) 449 #define MU_FCR_F29(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F29_SHIFT)) & MU_FCR_F29_MASK) 450 451 #define MU_FCR_F30_MASK (0x40000000U) 452 #define MU_FCR_F30_SHIFT (30U) 453 #define MU_FCR_F30_WIDTH (1U) 454 #define MU_FCR_F30(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F30_SHIFT)) & MU_FCR_F30_MASK) 455 456 #define MU_FCR_F31_MASK (0x80000000U) 457 #define MU_FCR_F31_SHIFT (31U) 458 #define MU_FCR_F31_WIDTH (1U) 459 #define MU_FCR_F31(x) (((uint32_t)(((uint32_t)(x)) << MU_FCR_F31_SHIFT)) & MU_FCR_F31_MASK) 460 /*! @} */ 461 462 /*! @name FSR - Flag Status Register */ 463 /*! @{ */ 464 465 #define MU_FSR_F0_MASK (0x1U) 466 #define MU_FSR_F0_SHIFT (0U) 467 #define MU_FSR_F0_WIDTH (1U) 468 #define MU_FSR_F0(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F0_SHIFT)) & MU_FSR_F0_MASK) 469 470 #define MU_FSR_F1_MASK (0x2U) 471 #define MU_FSR_F1_SHIFT (1U) 472 #define MU_FSR_F1_WIDTH (1U) 473 #define MU_FSR_F1(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F1_SHIFT)) & MU_FSR_F1_MASK) 474 475 #define MU_FSR_F2_MASK (0x4U) 476 #define MU_FSR_F2_SHIFT (2U) 477 #define MU_FSR_F2_WIDTH (1U) 478 #define MU_FSR_F2(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F2_SHIFT)) & MU_FSR_F2_MASK) 479 480 #define MU_FSR_F3_MASK (0x8U) 481 #define MU_FSR_F3_SHIFT (3U) 482 #define MU_FSR_F3_WIDTH (1U) 483 #define MU_FSR_F3(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F3_SHIFT)) & MU_FSR_F3_MASK) 484 485 #define MU_FSR_F4_MASK (0x10U) 486 #define MU_FSR_F4_SHIFT (4U) 487 #define MU_FSR_F4_WIDTH (1U) 488 #define MU_FSR_F4(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F4_SHIFT)) & MU_FSR_F4_MASK) 489 490 #define MU_FSR_F5_MASK (0x20U) 491 #define MU_FSR_F5_SHIFT (5U) 492 #define MU_FSR_F5_WIDTH (1U) 493 #define MU_FSR_F5(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F5_SHIFT)) & MU_FSR_F5_MASK) 494 495 #define MU_FSR_F6_MASK (0x40U) 496 #define MU_FSR_F6_SHIFT (6U) 497 #define MU_FSR_F6_WIDTH (1U) 498 #define MU_FSR_F6(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F6_SHIFT)) & MU_FSR_F6_MASK) 499 500 #define MU_FSR_F7_MASK (0x80U) 501 #define MU_FSR_F7_SHIFT (7U) 502 #define MU_FSR_F7_WIDTH (1U) 503 #define MU_FSR_F7(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F7_SHIFT)) & MU_FSR_F7_MASK) 504 505 #define MU_FSR_F8_MASK (0x100U) 506 #define MU_FSR_F8_SHIFT (8U) 507 #define MU_FSR_F8_WIDTH (1U) 508 #define MU_FSR_F8(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F8_SHIFT)) & MU_FSR_F8_MASK) 509 510 #define MU_FSR_F9_MASK (0x200U) 511 #define MU_FSR_F9_SHIFT (9U) 512 #define MU_FSR_F9_WIDTH (1U) 513 #define MU_FSR_F9(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F9_SHIFT)) & MU_FSR_F9_MASK) 514 515 #define MU_FSR_F10_MASK (0x400U) 516 #define MU_FSR_F10_SHIFT (10U) 517 #define MU_FSR_F10_WIDTH (1U) 518 #define MU_FSR_F10(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F10_SHIFT)) & MU_FSR_F10_MASK) 519 520 #define MU_FSR_F11_MASK (0x800U) 521 #define MU_FSR_F11_SHIFT (11U) 522 #define MU_FSR_F11_WIDTH (1U) 523 #define MU_FSR_F11(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F11_SHIFT)) & MU_FSR_F11_MASK) 524 525 #define MU_FSR_F12_MASK (0x1000U) 526 #define MU_FSR_F12_SHIFT (12U) 527 #define MU_FSR_F12_WIDTH (1U) 528 #define MU_FSR_F12(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F12_SHIFT)) & MU_FSR_F12_MASK) 529 530 #define MU_FSR_F13_MASK (0x2000U) 531 #define MU_FSR_F13_SHIFT (13U) 532 #define MU_FSR_F13_WIDTH (1U) 533 #define MU_FSR_F13(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F13_SHIFT)) & MU_FSR_F13_MASK) 534 535 #define MU_FSR_F14_MASK (0x4000U) 536 #define MU_FSR_F14_SHIFT (14U) 537 #define MU_FSR_F14_WIDTH (1U) 538 #define MU_FSR_F14(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F14_SHIFT)) & MU_FSR_F14_MASK) 539 540 #define MU_FSR_F15_MASK (0x8000U) 541 #define MU_FSR_F15_SHIFT (15U) 542 #define MU_FSR_F15_WIDTH (1U) 543 #define MU_FSR_F15(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F15_SHIFT)) & MU_FSR_F15_MASK) 544 545 #define MU_FSR_F16_MASK (0x10000U) 546 #define MU_FSR_F16_SHIFT (16U) 547 #define MU_FSR_F16_WIDTH (1U) 548 #define MU_FSR_F16(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F16_SHIFT)) & MU_FSR_F16_MASK) 549 550 #define MU_FSR_F17_MASK (0x20000U) 551 #define MU_FSR_F17_SHIFT (17U) 552 #define MU_FSR_F17_WIDTH (1U) 553 #define MU_FSR_F17(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F17_SHIFT)) & MU_FSR_F17_MASK) 554 555 #define MU_FSR_F18_MASK (0x40000U) 556 #define MU_FSR_F18_SHIFT (18U) 557 #define MU_FSR_F18_WIDTH (1U) 558 #define MU_FSR_F18(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F18_SHIFT)) & MU_FSR_F18_MASK) 559 560 #define MU_FSR_F19_MASK (0x80000U) 561 #define MU_FSR_F19_SHIFT (19U) 562 #define MU_FSR_F19_WIDTH (1U) 563 #define MU_FSR_F19(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F19_SHIFT)) & MU_FSR_F19_MASK) 564 565 #define MU_FSR_F20_MASK (0x100000U) 566 #define MU_FSR_F20_SHIFT (20U) 567 #define MU_FSR_F20_WIDTH (1U) 568 #define MU_FSR_F20(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F20_SHIFT)) & MU_FSR_F20_MASK) 569 570 #define MU_FSR_F21_MASK (0x200000U) 571 #define MU_FSR_F21_SHIFT (21U) 572 #define MU_FSR_F21_WIDTH (1U) 573 #define MU_FSR_F21(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F21_SHIFT)) & MU_FSR_F21_MASK) 574 575 #define MU_FSR_F22_MASK (0x400000U) 576 #define MU_FSR_F22_SHIFT (22U) 577 #define MU_FSR_F22_WIDTH (1U) 578 #define MU_FSR_F22(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F22_SHIFT)) & MU_FSR_F22_MASK) 579 580 #define MU_FSR_F23_MASK (0x800000U) 581 #define MU_FSR_F23_SHIFT (23U) 582 #define MU_FSR_F23_WIDTH (1U) 583 #define MU_FSR_F23(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F23_SHIFT)) & MU_FSR_F23_MASK) 584 585 #define MU_FSR_F24_MASK (0x1000000U) 586 #define MU_FSR_F24_SHIFT (24U) 587 #define MU_FSR_F24_WIDTH (1U) 588 #define MU_FSR_F24(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F24_SHIFT)) & MU_FSR_F24_MASK) 589 590 #define MU_FSR_F25_MASK (0x2000000U) 591 #define MU_FSR_F25_SHIFT (25U) 592 #define MU_FSR_F25_WIDTH (1U) 593 #define MU_FSR_F25(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F25_SHIFT)) & MU_FSR_F25_MASK) 594 595 #define MU_FSR_F26_MASK (0x4000000U) 596 #define MU_FSR_F26_SHIFT (26U) 597 #define MU_FSR_F26_WIDTH (1U) 598 #define MU_FSR_F26(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F26_SHIFT)) & MU_FSR_F26_MASK) 599 600 #define MU_FSR_F27_MASK (0x8000000U) 601 #define MU_FSR_F27_SHIFT (27U) 602 #define MU_FSR_F27_WIDTH (1U) 603 #define MU_FSR_F27(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F27_SHIFT)) & MU_FSR_F27_MASK) 604 605 #define MU_FSR_F28_MASK (0x10000000U) 606 #define MU_FSR_F28_SHIFT (28U) 607 #define MU_FSR_F28_WIDTH (1U) 608 #define MU_FSR_F28(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F28_SHIFT)) & MU_FSR_F28_MASK) 609 610 #define MU_FSR_F29_MASK (0x20000000U) 611 #define MU_FSR_F29_SHIFT (29U) 612 #define MU_FSR_F29_WIDTH (1U) 613 #define MU_FSR_F29(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F29_SHIFT)) & MU_FSR_F29_MASK) 614 615 #define MU_FSR_F30_MASK (0x40000000U) 616 #define MU_FSR_F30_SHIFT (30U) 617 #define MU_FSR_F30_WIDTH (1U) 618 #define MU_FSR_F30(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F30_SHIFT)) & MU_FSR_F30_MASK) 619 620 #define MU_FSR_F31_MASK (0x80000000U) 621 #define MU_FSR_F31_SHIFT (31U) 622 #define MU_FSR_F31_WIDTH (1U) 623 #define MU_FSR_F31(x) (((uint32_t)(((uint32_t)(x)) << MU_FSR_F31_SHIFT)) & MU_FSR_F31_MASK) 624 /*! @} */ 625 626 /*! @name GIER - General-purpose Interrupt Enable Register */ 627 /*! @{ */ 628 629 #define MU_GIER_GIE0_MASK (0x1U) 630 #define MU_GIER_GIE0_SHIFT (0U) 631 #define MU_GIER_GIE0_WIDTH (1U) 632 #define MU_GIER_GIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE0_SHIFT)) & MU_GIER_GIE0_MASK) 633 634 #define MU_GIER_GIE1_MASK (0x2U) 635 #define MU_GIER_GIE1_SHIFT (1U) 636 #define MU_GIER_GIE1_WIDTH (1U) 637 #define MU_GIER_GIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE1_SHIFT)) & MU_GIER_GIE1_MASK) 638 639 #define MU_GIER_GIE2_MASK (0x4U) 640 #define MU_GIER_GIE2_SHIFT (2U) 641 #define MU_GIER_GIE2_WIDTH (1U) 642 #define MU_GIER_GIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE2_SHIFT)) & MU_GIER_GIE2_MASK) 643 644 #define MU_GIER_GIE3_MASK (0x8U) 645 #define MU_GIER_GIE3_SHIFT (3U) 646 #define MU_GIER_GIE3_WIDTH (1U) 647 #define MU_GIER_GIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE3_SHIFT)) & MU_GIER_GIE3_MASK) 648 649 #define MU_GIER_GIE4_MASK (0x10U) 650 #define MU_GIER_GIE4_SHIFT (4U) 651 #define MU_GIER_GIE4_WIDTH (1U) 652 #define MU_GIER_GIE4(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE4_SHIFT)) & MU_GIER_GIE4_MASK) 653 654 #define MU_GIER_GIE5_MASK (0x20U) 655 #define MU_GIER_GIE5_SHIFT (5U) 656 #define MU_GIER_GIE5_WIDTH (1U) 657 #define MU_GIER_GIE5(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE5_SHIFT)) & MU_GIER_GIE5_MASK) 658 659 #define MU_GIER_GIE6_MASK (0x40U) 660 #define MU_GIER_GIE6_SHIFT (6U) 661 #define MU_GIER_GIE6_WIDTH (1U) 662 #define MU_GIER_GIE6(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE6_SHIFT)) & MU_GIER_GIE6_MASK) 663 664 #define MU_GIER_GIE7_MASK (0x80U) 665 #define MU_GIER_GIE7_SHIFT (7U) 666 #define MU_GIER_GIE7_WIDTH (1U) 667 #define MU_GIER_GIE7(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE7_SHIFT)) & MU_GIER_GIE7_MASK) 668 669 #define MU_GIER_GIE8_MASK (0x100U) 670 #define MU_GIER_GIE8_SHIFT (8U) 671 #define MU_GIER_GIE8_WIDTH (1U) 672 #define MU_GIER_GIE8(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE8_SHIFT)) & MU_GIER_GIE8_MASK) 673 674 #define MU_GIER_GIE9_MASK (0x200U) 675 #define MU_GIER_GIE9_SHIFT (9U) 676 #define MU_GIER_GIE9_WIDTH (1U) 677 #define MU_GIER_GIE9(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE9_SHIFT)) & MU_GIER_GIE9_MASK) 678 679 #define MU_GIER_GIE10_MASK (0x400U) 680 #define MU_GIER_GIE10_SHIFT (10U) 681 #define MU_GIER_GIE10_WIDTH (1U) 682 #define MU_GIER_GIE10(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE10_SHIFT)) & MU_GIER_GIE10_MASK) 683 684 #define MU_GIER_GIE11_MASK (0x800U) 685 #define MU_GIER_GIE11_SHIFT (11U) 686 #define MU_GIER_GIE11_WIDTH (1U) 687 #define MU_GIER_GIE11(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE11_SHIFT)) & MU_GIER_GIE11_MASK) 688 689 #define MU_GIER_GIE12_MASK (0x1000U) 690 #define MU_GIER_GIE12_SHIFT (12U) 691 #define MU_GIER_GIE12_WIDTH (1U) 692 #define MU_GIER_GIE12(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE12_SHIFT)) & MU_GIER_GIE12_MASK) 693 694 #define MU_GIER_GIE13_MASK (0x2000U) 695 #define MU_GIER_GIE13_SHIFT (13U) 696 #define MU_GIER_GIE13_WIDTH (1U) 697 #define MU_GIER_GIE13(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE13_SHIFT)) & MU_GIER_GIE13_MASK) 698 699 #define MU_GIER_GIE14_MASK (0x4000U) 700 #define MU_GIER_GIE14_SHIFT (14U) 701 #define MU_GIER_GIE14_WIDTH (1U) 702 #define MU_GIER_GIE14(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE14_SHIFT)) & MU_GIER_GIE14_MASK) 703 704 #define MU_GIER_GIE15_MASK (0x8000U) 705 #define MU_GIER_GIE15_SHIFT (15U) 706 #define MU_GIER_GIE15_WIDTH (1U) 707 #define MU_GIER_GIE15(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE15_SHIFT)) & MU_GIER_GIE15_MASK) 708 709 #define MU_GIER_GIE16_MASK (0x10000U) 710 #define MU_GIER_GIE16_SHIFT (16U) 711 #define MU_GIER_GIE16_WIDTH (1U) 712 #define MU_GIER_GIE16(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE16_SHIFT)) & MU_GIER_GIE16_MASK) 713 714 #define MU_GIER_GIE17_MASK (0x20000U) 715 #define MU_GIER_GIE17_SHIFT (17U) 716 #define MU_GIER_GIE17_WIDTH (1U) 717 #define MU_GIER_GIE17(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE17_SHIFT)) & MU_GIER_GIE17_MASK) 718 719 #define MU_GIER_GIE18_MASK (0x40000U) 720 #define MU_GIER_GIE18_SHIFT (18U) 721 #define MU_GIER_GIE18_WIDTH (1U) 722 #define MU_GIER_GIE18(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE18_SHIFT)) & MU_GIER_GIE18_MASK) 723 724 #define MU_GIER_GIE19_MASK (0x80000U) 725 #define MU_GIER_GIE19_SHIFT (19U) 726 #define MU_GIER_GIE19_WIDTH (1U) 727 #define MU_GIER_GIE19(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE19_SHIFT)) & MU_GIER_GIE19_MASK) 728 729 #define MU_GIER_GIE20_MASK (0x100000U) 730 #define MU_GIER_GIE20_SHIFT (20U) 731 #define MU_GIER_GIE20_WIDTH (1U) 732 #define MU_GIER_GIE20(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE20_SHIFT)) & MU_GIER_GIE20_MASK) 733 734 #define MU_GIER_GIE21_MASK (0x200000U) 735 #define MU_GIER_GIE21_SHIFT (21U) 736 #define MU_GIER_GIE21_WIDTH (1U) 737 #define MU_GIER_GIE21(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE21_SHIFT)) & MU_GIER_GIE21_MASK) 738 739 #define MU_GIER_GIE22_MASK (0x400000U) 740 #define MU_GIER_GIE22_SHIFT (22U) 741 #define MU_GIER_GIE22_WIDTH (1U) 742 #define MU_GIER_GIE22(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE22_SHIFT)) & MU_GIER_GIE22_MASK) 743 744 #define MU_GIER_GIE23_MASK (0x800000U) 745 #define MU_GIER_GIE23_SHIFT (23U) 746 #define MU_GIER_GIE23_WIDTH (1U) 747 #define MU_GIER_GIE23(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE23_SHIFT)) & MU_GIER_GIE23_MASK) 748 749 #define MU_GIER_GIE24_MASK (0x1000000U) 750 #define MU_GIER_GIE24_SHIFT (24U) 751 #define MU_GIER_GIE24_WIDTH (1U) 752 #define MU_GIER_GIE24(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE24_SHIFT)) & MU_GIER_GIE24_MASK) 753 754 #define MU_GIER_GIE25_MASK (0x2000000U) 755 #define MU_GIER_GIE25_SHIFT (25U) 756 #define MU_GIER_GIE25_WIDTH (1U) 757 #define MU_GIER_GIE25(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE25_SHIFT)) & MU_GIER_GIE25_MASK) 758 759 #define MU_GIER_GIE26_MASK (0x4000000U) 760 #define MU_GIER_GIE26_SHIFT (26U) 761 #define MU_GIER_GIE26_WIDTH (1U) 762 #define MU_GIER_GIE26(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE26_SHIFT)) & MU_GIER_GIE26_MASK) 763 764 #define MU_GIER_GIE27_MASK (0x8000000U) 765 #define MU_GIER_GIE27_SHIFT (27U) 766 #define MU_GIER_GIE27_WIDTH (1U) 767 #define MU_GIER_GIE27(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE27_SHIFT)) & MU_GIER_GIE27_MASK) 768 769 #define MU_GIER_GIE28_MASK (0x10000000U) 770 #define MU_GIER_GIE28_SHIFT (28U) 771 #define MU_GIER_GIE28_WIDTH (1U) 772 #define MU_GIER_GIE28(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE28_SHIFT)) & MU_GIER_GIE28_MASK) 773 774 #define MU_GIER_GIE29_MASK (0x20000000U) 775 #define MU_GIER_GIE29_SHIFT (29U) 776 #define MU_GIER_GIE29_WIDTH (1U) 777 #define MU_GIER_GIE29(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE29_SHIFT)) & MU_GIER_GIE29_MASK) 778 779 #define MU_GIER_GIE30_MASK (0x40000000U) 780 #define MU_GIER_GIE30_SHIFT (30U) 781 #define MU_GIER_GIE30_WIDTH (1U) 782 #define MU_GIER_GIE30(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE30_SHIFT)) & MU_GIER_GIE30_MASK) 783 784 #define MU_GIER_GIE31_MASK (0x80000000U) 785 #define MU_GIER_GIE31_SHIFT (31U) 786 #define MU_GIER_GIE31_WIDTH (1U) 787 #define MU_GIER_GIE31(x) (((uint32_t)(((uint32_t)(x)) << MU_GIER_GIE31_SHIFT)) & MU_GIER_GIE31_MASK) 788 /*! @} */ 789 790 /*! @name GCR - General-purpose Control Register */ 791 /*! @{ */ 792 793 #define MU_GCR_GIR0_MASK (0x1U) 794 #define MU_GCR_GIR0_SHIFT (0U) 795 #define MU_GCR_GIR0_WIDTH (1U) 796 #define MU_GCR_GIR0(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR0_SHIFT)) & MU_GCR_GIR0_MASK) 797 798 #define MU_GCR_GIR1_MASK (0x2U) 799 #define MU_GCR_GIR1_SHIFT (1U) 800 #define MU_GCR_GIR1_WIDTH (1U) 801 #define MU_GCR_GIR1(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR1_SHIFT)) & MU_GCR_GIR1_MASK) 802 803 #define MU_GCR_GIR2_MASK (0x4U) 804 #define MU_GCR_GIR2_SHIFT (2U) 805 #define MU_GCR_GIR2_WIDTH (1U) 806 #define MU_GCR_GIR2(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR2_SHIFT)) & MU_GCR_GIR2_MASK) 807 808 #define MU_GCR_GIR3_MASK (0x8U) 809 #define MU_GCR_GIR3_SHIFT (3U) 810 #define MU_GCR_GIR3_WIDTH (1U) 811 #define MU_GCR_GIR3(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR3_SHIFT)) & MU_GCR_GIR3_MASK) 812 813 #define MU_GCR_GIR4_MASK (0x10U) 814 #define MU_GCR_GIR4_SHIFT (4U) 815 #define MU_GCR_GIR4_WIDTH (1U) 816 #define MU_GCR_GIR4(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR4_SHIFT)) & MU_GCR_GIR4_MASK) 817 818 #define MU_GCR_GIR5_MASK (0x20U) 819 #define MU_GCR_GIR5_SHIFT (5U) 820 #define MU_GCR_GIR5_WIDTH (1U) 821 #define MU_GCR_GIR5(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR5_SHIFT)) & MU_GCR_GIR5_MASK) 822 823 #define MU_GCR_GIR6_MASK (0x40U) 824 #define MU_GCR_GIR6_SHIFT (6U) 825 #define MU_GCR_GIR6_WIDTH (1U) 826 #define MU_GCR_GIR6(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR6_SHIFT)) & MU_GCR_GIR6_MASK) 827 828 #define MU_GCR_GIR7_MASK (0x80U) 829 #define MU_GCR_GIR7_SHIFT (7U) 830 #define MU_GCR_GIR7_WIDTH (1U) 831 #define MU_GCR_GIR7(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR7_SHIFT)) & MU_GCR_GIR7_MASK) 832 833 #define MU_GCR_GIR8_MASK (0x100U) 834 #define MU_GCR_GIR8_SHIFT (8U) 835 #define MU_GCR_GIR8_WIDTH (1U) 836 #define MU_GCR_GIR8(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR8_SHIFT)) & MU_GCR_GIR8_MASK) 837 838 #define MU_GCR_GIR9_MASK (0x200U) 839 #define MU_GCR_GIR9_SHIFT (9U) 840 #define MU_GCR_GIR9_WIDTH (1U) 841 #define MU_GCR_GIR9(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR9_SHIFT)) & MU_GCR_GIR9_MASK) 842 843 #define MU_GCR_GIR10_MASK (0x400U) 844 #define MU_GCR_GIR10_SHIFT (10U) 845 #define MU_GCR_GIR10_WIDTH (1U) 846 #define MU_GCR_GIR10(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR10_SHIFT)) & MU_GCR_GIR10_MASK) 847 848 #define MU_GCR_GIR11_MASK (0x800U) 849 #define MU_GCR_GIR11_SHIFT (11U) 850 #define MU_GCR_GIR11_WIDTH (1U) 851 #define MU_GCR_GIR11(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR11_SHIFT)) & MU_GCR_GIR11_MASK) 852 853 #define MU_GCR_GIR12_MASK (0x1000U) 854 #define MU_GCR_GIR12_SHIFT (12U) 855 #define MU_GCR_GIR12_WIDTH (1U) 856 #define MU_GCR_GIR12(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR12_SHIFT)) & MU_GCR_GIR12_MASK) 857 858 #define MU_GCR_GIR13_MASK (0x2000U) 859 #define MU_GCR_GIR13_SHIFT (13U) 860 #define MU_GCR_GIR13_WIDTH (1U) 861 #define MU_GCR_GIR13(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR13_SHIFT)) & MU_GCR_GIR13_MASK) 862 863 #define MU_GCR_GIR14_MASK (0x4000U) 864 #define MU_GCR_GIR14_SHIFT (14U) 865 #define MU_GCR_GIR14_WIDTH (1U) 866 #define MU_GCR_GIR14(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR14_SHIFT)) & MU_GCR_GIR14_MASK) 867 868 #define MU_GCR_GIR15_MASK (0x8000U) 869 #define MU_GCR_GIR15_SHIFT (15U) 870 #define MU_GCR_GIR15_WIDTH (1U) 871 #define MU_GCR_GIR15(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR15_SHIFT)) & MU_GCR_GIR15_MASK) 872 873 #define MU_GCR_GIR16_MASK (0x10000U) 874 #define MU_GCR_GIR16_SHIFT (16U) 875 #define MU_GCR_GIR16_WIDTH (1U) 876 #define MU_GCR_GIR16(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR16_SHIFT)) & MU_GCR_GIR16_MASK) 877 878 #define MU_GCR_GIR17_MASK (0x20000U) 879 #define MU_GCR_GIR17_SHIFT (17U) 880 #define MU_GCR_GIR17_WIDTH (1U) 881 #define MU_GCR_GIR17(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR17_SHIFT)) & MU_GCR_GIR17_MASK) 882 883 #define MU_GCR_GIR18_MASK (0x40000U) 884 #define MU_GCR_GIR18_SHIFT (18U) 885 #define MU_GCR_GIR18_WIDTH (1U) 886 #define MU_GCR_GIR18(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR18_SHIFT)) & MU_GCR_GIR18_MASK) 887 888 #define MU_GCR_GIR19_MASK (0x80000U) 889 #define MU_GCR_GIR19_SHIFT (19U) 890 #define MU_GCR_GIR19_WIDTH (1U) 891 #define MU_GCR_GIR19(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR19_SHIFT)) & MU_GCR_GIR19_MASK) 892 893 #define MU_GCR_GIR20_MASK (0x100000U) 894 #define MU_GCR_GIR20_SHIFT (20U) 895 #define MU_GCR_GIR20_WIDTH (1U) 896 #define MU_GCR_GIR20(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR20_SHIFT)) & MU_GCR_GIR20_MASK) 897 898 #define MU_GCR_GIR21_MASK (0x200000U) 899 #define MU_GCR_GIR21_SHIFT (21U) 900 #define MU_GCR_GIR21_WIDTH (1U) 901 #define MU_GCR_GIR21(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR21_SHIFT)) & MU_GCR_GIR21_MASK) 902 903 #define MU_GCR_GIR22_MASK (0x400000U) 904 #define MU_GCR_GIR22_SHIFT (22U) 905 #define MU_GCR_GIR22_WIDTH (1U) 906 #define MU_GCR_GIR22(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR22_SHIFT)) & MU_GCR_GIR22_MASK) 907 908 #define MU_GCR_GIR23_MASK (0x800000U) 909 #define MU_GCR_GIR23_SHIFT (23U) 910 #define MU_GCR_GIR23_WIDTH (1U) 911 #define MU_GCR_GIR23(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR23_SHIFT)) & MU_GCR_GIR23_MASK) 912 913 #define MU_GCR_GIR24_MASK (0x1000000U) 914 #define MU_GCR_GIR24_SHIFT (24U) 915 #define MU_GCR_GIR24_WIDTH (1U) 916 #define MU_GCR_GIR24(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR24_SHIFT)) & MU_GCR_GIR24_MASK) 917 918 #define MU_GCR_GIR25_MASK (0x2000000U) 919 #define MU_GCR_GIR25_SHIFT (25U) 920 #define MU_GCR_GIR25_WIDTH (1U) 921 #define MU_GCR_GIR25(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR25_SHIFT)) & MU_GCR_GIR25_MASK) 922 923 #define MU_GCR_GIR26_MASK (0x4000000U) 924 #define MU_GCR_GIR26_SHIFT (26U) 925 #define MU_GCR_GIR26_WIDTH (1U) 926 #define MU_GCR_GIR26(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR26_SHIFT)) & MU_GCR_GIR26_MASK) 927 928 #define MU_GCR_GIR27_MASK (0x8000000U) 929 #define MU_GCR_GIR27_SHIFT (27U) 930 #define MU_GCR_GIR27_WIDTH (1U) 931 #define MU_GCR_GIR27(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR27_SHIFT)) & MU_GCR_GIR27_MASK) 932 933 #define MU_GCR_GIR28_MASK (0x10000000U) 934 #define MU_GCR_GIR28_SHIFT (28U) 935 #define MU_GCR_GIR28_WIDTH (1U) 936 #define MU_GCR_GIR28(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR28_SHIFT)) & MU_GCR_GIR28_MASK) 937 938 #define MU_GCR_GIR29_MASK (0x20000000U) 939 #define MU_GCR_GIR29_SHIFT (29U) 940 #define MU_GCR_GIR29_WIDTH (1U) 941 #define MU_GCR_GIR29(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR29_SHIFT)) & MU_GCR_GIR29_MASK) 942 943 #define MU_GCR_GIR30_MASK (0x40000000U) 944 #define MU_GCR_GIR30_SHIFT (30U) 945 #define MU_GCR_GIR30_WIDTH (1U) 946 #define MU_GCR_GIR30(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR30_SHIFT)) & MU_GCR_GIR30_MASK) 947 948 #define MU_GCR_GIR31_MASK (0x80000000U) 949 #define MU_GCR_GIR31_SHIFT (31U) 950 #define MU_GCR_GIR31_WIDTH (1U) 951 #define MU_GCR_GIR31(x) (((uint32_t)(((uint32_t)(x)) << MU_GCR_GIR31_SHIFT)) & MU_GCR_GIR31_MASK) 952 /*! @} */ 953 954 /*! @name GSR - General-purpose Status Register */ 955 /*! @{ */ 956 957 #define MU_GSR_GIP0_MASK (0x1U) 958 #define MU_GSR_GIP0_SHIFT (0U) 959 #define MU_GSR_GIP0_WIDTH (1U) 960 #define MU_GSR_GIP0(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP0_SHIFT)) & MU_GSR_GIP0_MASK) 961 962 #define MU_GSR_GIP1_MASK (0x2U) 963 #define MU_GSR_GIP1_SHIFT (1U) 964 #define MU_GSR_GIP1_WIDTH (1U) 965 #define MU_GSR_GIP1(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP1_SHIFT)) & MU_GSR_GIP1_MASK) 966 967 #define MU_GSR_GIP2_MASK (0x4U) 968 #define MU_GSR_GIP2_SHIFT (2U) 969 #define MU_GSR_GIP2_WIDTH (1U) 970 #define MU_GSR_GIP2(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP2_SHIFT)) & MU_GSR_GIP2_MASK) 971 972 #define MU_GSR_GIP3_MASK (0x8U) 973 #define MU_GSR_GIP3_SHIFT (3U) 974 #define MU_GSR_GIP3_WIDTH (1U) 975 #define MU_GSR_GIP3(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP3_SHIFT)) & MU_GSR_GIP3_MASK) 976 977 #define MU_GSR_GIP4_MASK (0x10U) 978 #define MU_GSR_GIP4_SHIFT (4U) 979 #define MU_GSR_GIP4_WIDTH (1U) 980 #define MU_GSR_GIP4(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP4_SHIFT)) & MU_GSR_GIP4_MASK) 981 982 #define MU_GSR_GIP5_MASK (0x20U) 983 #define MU_GSR_GIP5_SHIFT (5U) 984 #define MU_GSR_GIP5_WIDTH (1U) 985 #define MU_GSR_GIP5(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP5_SHIFT)) & MU_GSR_GIP5_MASK) 986 987 #define MU_GSR_GIP6_MASK (0x40U) 988 #define MU_GSR_GIP6_SHIFT (6U) 989 #define MU_GSR_GIP6_WIDTH (1U) 990 #define MU_GSR_GIP6(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP6_SHIFT)) & MU_GSR_GIP6_MASK) 991 992 #define MU_GSR_GIP7_MASK (0x80U) 993 #define MU_GSR_GIP7_SHIFT (7U) 994 #define MU_GSR_GIP7_WIDTH (1U) 995 #define MU_GSR_GIP7(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP7_SHIFT)) & MU_GSR_GIP7_MASK) 996 997 #define MU_GSR_GIP8_MASK (0x100U) 998 #define MU_GSR_GIP8_SHIFT (8U) 999 #define MU_GSR_GIP8_WIDTH (1U) 1000 #define MU_GSR_GIP8(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP8_SHIFT)) & MU_GSR_GIP8_MASK) 1001 1002 #define MU_GSR_GIP9_MASK (0x200U) 1003 #define MU_GSR_GIP9_SHIFT (9U) 1004 #define MU_GSR_GIP9_WIDTH (1U) 1005 #define MU_GSR_GIP9(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP9_SHIFT)) & MU_GSR_GIP9_MASK) 1006 1007 #define MU_GSR_GIP10_MASK (0x400U) 1008 #define MU_GSR_GIP10_SHIFT (10U) 1009 #define MU_GSR_GIP10_WIDTH (1U) 1010 #define MU_GSR_GIP10(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP10_SHIFT)) & MU_GSR_GIP10_MASK) 1011 1012 #define MU_GSR_GIP11_MASK (0x800U) 1013 #define MU_GSR_GIP11_SHIFT (11U) 1014 #define MU_GSR_GIP11_WIDTH (1U) 1015 #define MU_GSR_GIP11(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP11_SHIFT)) & MU_GSR_GIP11_MASK) 1016 1017 #define MU_GSR_GIP12_MASK (0x1000U) 1018 #define MU_GSR_GIP12_SHIFT (12U) 1019 #define MU_GSR_GIP12_WIDTH (1U) 1020 #define MU_GSR_GIP12(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP12_SHIFT)) & MU_GSR_GIP12_MASK) 1021 1022 #define MU_GSR_GIP13_MASK (0x2000U) 1023 #define MU_GSR_GIP13_SHIFT (13U) 1024 #define MU_GSR_GIP13_WIDTH (1U) 1025 #define MU_GSR_GIP13(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP13_SHIFT)) & MU_GSR_GIP13_MASK) 1026 1027 #define MU_GSR_GIP14_MASK (0x4000U) 1028 #define MU_GSR_GIP14_SHIFT (14U) 1029 #define MU_GSR_GIP14_WIDTH (1U) 1030 #define MU_GSR_GIP14(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP14_SHIFT)) & MU_GSR_GIP14_MASK) 1031 1032 #define MU_GSR_GIP15_MASK (0x8000U) 1033 #define MU_GSR_GIP15_SHIFT (15U) 1034 #define MU_GSR_GIP15_WIDTH (1U) 1035 #define MU_GSR_GIP15(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP15_SHIFT)) & MU_GSR_GIP15_MASK) 1036 1037 #define MU_GSR_GIP16_MASK (0x10000U) 1038 #define MU_GSR_GIP16_SHIFT (16U) 1039 #define MU_GSR_GIP16_WIDTH (1U) 1040 #define MU_GSR_GIP16(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP16_SHIFT)) & MU_GSR_GIP16_MASK) 1041 1042 #define MU_GSR_GIP17_MASK (0x20000U) 1043 #define MU_GSR_GIP17_SHIFT (17U) 1044 #define MU_GSR_GIP17_WIDTH (1U) 1045 #define MU_GSR_GIP17(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP17_SHIFT)) & MU_GSR_GIP17_MASK) 1046 1047 #define MU_GSR_GIP18_MASK (0x40000U) 1048 #define MU_GSR_GIP18_SHIFT (18U) 1049 #define MU_GSR_GIP18_WIDTH (1U) 1050 #define MU_GSR_GIP18(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP18_SHIFT)) & MU_GSR_GIP18_MASK) 1051 1052 #define MU_GSR_GIP19_MASK (0x80000U) 1053 #define MU_GSR_GIP19_SHIFT (19U) 1054 #define MU_GSR_GIP19_WIDTH (1U) 1055 #define MU_GSR_GIP19(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP19_SHIFT)) & MU_GSR_GIP19_MASK) 1056 1057 #define MU_GSR_GIP20_MASK (0x100000U) 1058 #define MU_GSR_GIP20_SHIFT (20U) 1059 #define MU_GSR_GIP20_WIDTH (1U) 1060 #define MU_GSR_GIP20(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP20_SHIFT)) & MU_GSR_GIP20_MASK) 1061 1062 #define MU_GSR_GIP21_MASK (0x200000U) 1063 #define MU_GSR_GIP21_SHIFT (21U) 1064 #define MU_GSR_GIP21_WIDTH (1U) 1065 #define MU_GSR_GIP21(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP21_SHIFT)) & MU_GSR_GIP21_MASK) 1066 1067 #define MU_GSR_GIP22_MASK (0x400000U) 1068 #define MU_GSR_GIP22_SHIFT (22U) 1069 #define MU_GSR_GIP22_WIDTH (1U) 1070 #define MU_GSR_GIP22(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP22_SHIFT)) & MU_GSR_GIP22_MASK) 1071 1072 #define MU_GSR_GIP23_MASK (0x800000U) 1073 #define MU_GSR_GIP23_SHIFT (23U) 1074 #define MU_GSR_GIP23_WIDTH (1U) 1075 #define MU_GSR_GIP23(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP23_SHIFT)) & MU_GSR_GIP23_MASK) 1076 1077 #define MU_GSR_GIP24_MASK (0x1000000U) 1078 #define MU_GSR_GIP24_SHIFT (24U) 1079 #define MU_GSR_GIP24_WIDTH (1U) 1080 #define MU_GSR_GIP24(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP24_SHIFT)) & MU_GSR_GIP24_MASK) 1081 1082 #define MU_GSR_GIP25_MASK (0x2000000U) 1083 #define MU_GSR_GIP25_SHIFT (25U) 1084 #define MU_GSR_GIP25_WIDTH (1U) 1085 #define MU_GSR_GIP25(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP25_SHIFT)) & MU_GSR_GIP25_MASK) 1086 1087 #define MU_GSR_GIP26_MASK (0x4000000U) 1088 #define MU_GSR_GIP26_SHIFT (26U) 1089 #define MU_GSR_GIP26_WIDTH (1U) 1090 #define MU_GSR_GIP26(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP26_SHIFT)) & MU_GSR_GIP26_MASK) 1091 1092 #define MU_GSR_GIP27_MASK (0x8000000U) 1093 #define MU_GSR_GIP27_SHIFT (27U) 1094 #define MU_GSR_GIP27_WIDTH (1U) 1095 #define MU_GSR_GIP27(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP27_SHIFT)) & MU_GSR_GIP27_MASK) 1096 1097 #define MU_GSR_GIP28_MASK (0x10000000U) 1098 #define MU_GSR_GIP28_SHIFT (28U) 1099 #define MU_GSR_GIP28_WIDTH (1U) 1100 #define MU_GSR_GIP28(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP28_SHIFT)) & MU_GSR_GIP28_MASK) 1101 1102 #define MU_GSR_GIP29_MASK (0x20000000U) 1103 #define MU_GSR_GIP29_SHIFT (29U) 1104 #define MU_GSR_GIP29_WIDTH (1U) 1105 #define MU_GSR_GIP29(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP29_SHIFT)) & MU_GSR_GIP29_MASK) 1106 1107 #define MU_GSR_GIP30_MASK (0x40000000U) 1108 #define MU_GSR_GIP30_SHIFT (30U) 1109 #define MU_GSR_GIP30_WIDTH (1U) 1110 #define MU_GSR_GIP30(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP30_SHIFT)) & MU_GSR_GIP30_MASK) 1111 1112 #define MU_GSR_GIP31_MASK (0x80000000U) 1113 #define MU_GSR_GIP31_SHIFT (31U) 1114 #define MU_GSR_GIP31_WIDTH (1U) 1115 #define MU_GSR_GIP31(x) (((uint32_t)(((uint32_t)(x)) << MU_GSR_GIP31_SHIFT)) & MU_GSR_GIP31_MASK) 1116 /*! @} */ 1117 1118 /*! @name TCR - Transmit Control Register */ 1119 /*! @{ */ 1120 1121 #define MU_TCR_TIE0_MASK (0x1U) 1122 #define MU_TCR_TIE0_SHIFT (0U) 1123 #define MU_TCR_TIE0_WIDTH (1U) 1124 #define MU_TCR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE0_SHIFT)) & MU_TCR_TIE0_MASK) 1125 1126 #define MU_TCR_TIE1_MASK (0x2U) 1127 #define MU_TCR_TIE1_SHIFT (1U) 1128 #define MU_TCR_TIE1_WIDTH (1U) 1129 #define MU_TCR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE1_SHIFT)) & MU_TCR_TIE1_MASK) 1130 1131 #define MU_TCR_TIE2_MASK (0x4U) 1132 #define MU_TCR_TIE2_SHIFT (2U) 1133 #define MU_TCR_TIE2_WIDTH (1U) 1134 #define MU_TCR_TIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE2_SHIFT)) & MU_TCR_TIE2_MASK) 1135 1136 #define MU_TCR_TIE3_MASK (0x8U) 1137 #define MU_TCR_TIE3_SHIFT (3U) 1138 #define MU_TCR_TIE3_WIDTH (1U) 1139 #define MU_TCR_TIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE3_SHIFT)) & MU_TCR_TIE3_MASK) 1140 1141 #define MU_TCR_TIE4_MASK (0x10U) 1142 #define MU_TCR_TIE4_SHIFT (4U) 1143 #define MU_TCR_TIE4_WIDTH (1U) 1144 #define MU_TCR_TIE4(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE4_SHIFT)) & MU_TCR_TIE4_MASK) 1145 1146 #define MU_TCR_TIE5_MASK (0x20U) 1147 #define MU_TCR_TIE5_SHIFT (5U) 1148 #define MU_TCR_TIE5_WIDTH (1U) 1149 #define MU_TCR_TIE5(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE5_SHIFT)) & MU_TCR_TIE5_MASK) 1150 1151 #define MU_TCR_TIE6_MASK (0x40U) 1152 #define MU_TCR_TIE6_SHIFT (6U) 1153 #define MU_TCR_TIE6_WIDTH (1U) 1154 #define MU_TCR_TIE6(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE6_SHIFT)) & MU_TCR_TIE6_MASK) 1155 1156 #define MU_TCR_TIE7_MASK (0x80U) 1157 #define MU_TCR_TIE7_SHIFT (7U) 1158 #define MU_TCR_TIE7_WIDTH (1U) 1159 #define MU_TCR_TIE7(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE7_SHIFT)) & MU_TCR_TIE7_MASK) 1160 1161 #define MU_TCR_TIE8_MASK (0x100U) 1162 #define MU_TCR_TIE8_SHIFT (8U) 1163 #define MU_TCR_TIE8_WIDTH (1U) 1164 #define MU_TCR_TIE8(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE8_SHIFT)) & MU_TCR_TIE8_MASK) 1165 1166 #define MU_TCR_TIE9_MASK (0x200U) 1167 #define MU_TCR_TIE9_SHIFT (9U) 1168 #define MU_TCR_TIE9_WIDTH (1U) 1169 #define MU_TCR_TIE9(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE9_SHIFT)) & MU_TCR_TIE9_MASK) 1170 1171 #define MU_TCR_TIE10_MASK (0x400U) 1172 #define MU_TCR_TIE10_SHIFT (10U) 1173 #define MU_TCR_TIE10_WIDTH (1U) 1174 #define MU_TCR_TIE10(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE10_SHIFT)) & MU_TCR_TIE10_MASK) 1175 1176 #define MU_TCR_TIE11_MASK (0x800U) 1177 #define MU_TCR_TIE11_SHIFT (11U) 1178 #define MU_TCR_TIE11_WIDTH (1U) 1179 #define MU_TCR_TIE11(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE11_SHIFT)) & MU_TCR_TIE11_MASK) 1180 1181 #define MU_TCR_TIE12_MASK (0x1000U) 1182 #define MU_TCR_TIE12_SHIFT (12U) 1183 #define MU_TCR_TIE12_WIDTH (1U) 1184 #define MU_TCR_TIE12(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE12_SHIFT)) & MU_TCR_TIE12_MASK) 1185 1186 #define MU_TCR_TIE13_MASK (0x2000U) 1187 #define MU_TCR_TIE13_SHIFT (13U) 1188 #define MU_TCR_TIE13_WIDTH (1U) 1189 #define MU_TCR_TIE13(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE13_SHIFT)) & MU_TCR_TIE13_MASK) 1190 1191 #define MU_TCR_TIE14_MASK (0x4000U) 1192 #define MU_TCR_TIE14_SHIFT (14U) 1193 #define MU_TCR_TIE14_WIDTH (1U) 1194 #define MU_TCR_TIE14(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE14_SHIFT)) & MU_TCR_TIE14_MASK) 1195 1196 #define MU_TCR_TIE15_MASK (0x8000U) 1197 #define MU_TCR_TIE15_SHIFT (15U) 1198 #define MU_TCR_TIE15_WIDTH (1U) 1199 #define MU_TCR_TIE15(x) (((uint32_t)(((uint32_t)(x)) << MU_TCR_TIE15_SHIFT)) & MU_TCR_TIE15_MASK) 1200 /*! @} */ 1201 1202 /*! @name TSR - Transmit Status Register */ 1203 /*! @{ */ 1204 1205 #define MU_TSR_TE0_MASK (0x1U) 1206 #define MU_TSR_TE0_SHIFT (0U) 1207 #define MU_TSR_TE0_WIDTH (1U) 1208 #define MU_TSR_TE0(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE0_SHIFT)) & MU_TSR_TE0_MASK) 1209 1210 #define MU_TSR_TE1_MASK (0x2U) 1211 #define MU_TSR_TE1_SHIFT (1U) 1212 #define MU_TSR_TE1_WIDTH (1U) 1213 #define MU_TSR_TE1(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE1_SHIFT)) & MU_TSR_TE1_MASK) 1214 1215 #define MU_TSR_TE2_MASK (0x4U) 1216 #define MU_TSR_TE2_SHIFT (2U) 1217 #define MU_TSR_TE2_WIDTH (1U) 1218 #define MU_TSR_TE2(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE2_SHIFT)) & MU_TSR_TE2_MASK) 1219 1220 #define MU_TSR_TE3_MASK (0x8U) 1221 #define MU_TSR_TE3_SHIFT (3U) 1222 #define MU_TSR_TE3_WIDTH (1U) 1223 #define MU_TSR_TE3(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE3_SHIFT)) & MU_TSR_TE3_MASK) 1224 1225 #define MU_TSR_TE4_MASK (0x10U) 1226 #define MU_TSR_TE4_SHIFT (4U) 1227 #define MU_TSR_TE4_WIDTH (1U) 1228 #define MU_TSR_TE4(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE4_SHIFT)) & MU_TSR_TE4_MASK) 1229 1230 #define MU_TSR_TE5_MASK (0x20U) 1231 #define MU_TSR_TE5_SHIFT (5U) 1232 #define MU_TSR_TE5_WIDTH (1U) 1233 #define MU_TSR_TE5(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE5_SHIFT)) & MU_TSR_TE5_MASK) 1234 1235 #define MU_TSR_TE6_MASK (0x40U) 1236 #define MU_TSR_TE6_SHIFT (6U) 1237 #define MU_TSR_TE6_WIDTH (1U) 1238 #define MU_TSR_TE6(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE6_SHIFT)) & MU_TSR_TE6_MASK) 1239 1240 #define MU_TSR_TE7_MASK (0x80U) 1241 #define MU_TSR_TE7_SHIFT (7U) 1242 #define MU_TSR_TE7_WIDTH (1U) 1243 #define MU_TSR_TE7(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE7_SHIFT)) & MU_TSR_TE7_MASK) 1244 1245 #define MU_TSR_TE8_MASK (0x100U) 1246 #define MU_TSR_TE8_SHIFT (8U) 1247 #define MU_TSR_TE8_WIDTH (1U) 1248 #define MU_TSR_TE8(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE8_SHIFT)) & MU_TSR_TE8_MASK) 1249 1250 #define MU_TSR_TE9_MASK (0x200U) 1251 #define MU_TSR_TE9_SHIFT (9U) 1252 #define MU_TSR_TE9_WIDTH (1U) 1253 #define MU_TSR_TE9(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE9_SHIFT)) & MU_TSR_TE9_MASK) 1254 1255 #define MU_TSR_TE10_MASK (0x400U) 1256 #define MU_TSR_TE10_SHIFT (10U) 1257 #define MU_TSR_TE10_WIDTH (1U) 1258 #define MU_TSR_TE10(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE10_SHIFT)) & MU_TSR_TE10_MASK) 1259 1260 #define MU_TSR_TE11_MASK (0x800U) 1261 #define MU_TSR_TE11_SHIFT (11U) 1262 #define MU_TSR_TE11_WIDTH (1U) 1263 #define MU_TSR_TE11(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE11_SHIFT)) & MU_TSR_TE11_MASK) 1264 1265 #define MU_TSR_TE12_MASK (0x1000U) 1266 #define MU_TSR_TE12_SHIFT (12U) 1267 #define MU_TSR_TE12_WIDTH (1U) 1268 #define MU_TSR_TE12(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE12_SHIFT)) & MU_TSR_TE12_MASK) 1269 1270 #define MU_TSR_TE13_MASK (0x2000U) 1271 #define MU_TSR_TE13_SHIFT (13U) 1272 #define MU_TSR_TE13_WIDTH (1U) 1273 #define MU_TSR_TE13(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE13_SHIFT)) & MU_TSR_TE13_MASK) 1274 1275 #define MU_TSR_TE14_MASK (0x4000U) 1276 #define MU_TSR_TE14_SHIFT (14U) 1277 #define MU_TSR_TE14_WIDTH (1U) 1278 #define MU_TSR_TE14(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE14_SHIFT)) & MU_TSR_TE14_MASK) 1279 1280 #define MU_TSR_TE15_MASK (0x8000U) 1281 #define MU_TSR_TE15_SHIFT (15U) 1282 #define MU_TSR_TE15_WIDTH (1U) 1283 #define MU_TSR_TE15(x) (((uint32_t)(((uint32_t)(x)) << MU_TSR_TE15_SHIFT)) & MU_TSR_TE15_MASK) 1284 /*! @} */ 1285 1286 /*! @name RCR - Receive Control Register */ 1287 /*! @{ */ 1288 1289 #define MU_RCR_RIE0_MASK (0x1U) 1290 #define MU_RCR_RIE0_SHIFT (0U) 1291 #define MU_RCR_RIE0_WIDTH (1U) 1292 #define MU_RCR_RIE0(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE0_SHIFT)) & MU_RCR_RIE0_MASK) 1293 1294 #define MU_RCR_RIE1_MASK (0x2U) 1295 #define MU_RCR_RIE1_SHIFT (1U) 1296 #define MU_RCR_RIE1_WIDTH (1U) 1297 #define MU_RCR_RIE1(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE1_SHIFT)) & MU_RCR_RIE1_MASK) 1298 1299 #define MU_RCR_RIE2_MASK (0x4U) 1300 #define MU_RCR_RIE2_SHIFT (2U) 1301 #define MU_RCR_RIE2_WIDTH (1U) 1302 #define MU_RCR_RIE2(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE2_SHIFT)) & MU_RCR_RIE2_MASK) 1303 1304 #define MU_RCR_RIE3_MASK (0x8U) 1305 #define MU_RCR_RIE3_SHIFT (3U) 1306 #define MU_RCR_RIE3_WIDTH (1U) 1307 #define MU_RCR_RIE3(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE3_SHIFT)) & MU_RCR_RIE3_MASK) 1308 1309 #define MU_RCR_RIE4_MASK (0x10U) 1310 #define MU_RCR_RIE4_SHIFT (4U) 1311 #define MU_RCR_RIE4_WIDTH (1U) 1312 #define MU_RCR_RIE4(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE4_SHIFT)) & MU_RCR_RIE4_MASK) 1313 1314 #define MU_RCR_RIE5_MASK (0x20U) 1315 #define MU_RCR_RIE5_SHIFT (5U) 1316 #define MU_RCR_RIE5_WIDTH (1U) 1317 #define MU_RCR_RIE5(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE5_SHIFT)) & MU_RCR_RIE5_MASK) 1318 1319 #define MU_RCR_RIE6_MASK (0x40U) 1320 #define MU_RCR_RIE6_SHIFT (6U) 1321 #define MU_RCR_RIE6_WIDTH (1U) 1322 #define MU_RCR_RIE6(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE6_SHIFT)) & MU_RCR_RIE6_MASK) 1323 1324 #define MU_RCR_RIE7_MASK (0x80U) 1325 #define MU_RCR_RIE7_SHIFT (7U) 1326 #define MU_RCR_RIE7_WIDTH (1U) 1327 #define MU_RCR_RIE7(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE7_SHIFT)) & MU_RCR_RIE7_MASK) 1328 1329 #define MU_RCR_RIE8_MASK (0x100U) 1330 #define MU_RCR_RIE8_SHIFT (8U) 1331 #define MU_RCR_RIE8_WIDTH (1U) 1332 #define MU_RCR_RIE8(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE8_SHIFT)) & MU_RCR_RIE8_MASK) 1333 1334 #define MU_RCR_RIE9_MASK (0x200U) 1335 #define MU_RCR_RIE9_SHIFT (9U) 1336 #define MU_RCR_RIE9_WIDTH (1U) 1337 #define MU_RCR_RIE9(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE9_SHIFT)) & MU_RCR_RIE9_MASK) 1338 1339 #define MU_RCR_RIE10_MASK (0x400U) 1340 #define MU_RCR_RIE10_SHIFT (10U) 1341 #define MU_RCR_RIE10_WIDTH (1U) 1342 #define MU_RCR_RIE10(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE10_SHIFT)) & MU_RCR_RIE10_MASK) 1343 1344 #define MU_RCR_RIE11_MASK (0x800U) 1345 #define MU_RCR_RIE11_SHIFT (11U) 1346 #define MU_RCR_RIE11_WIDTH (1U) 1347 #define MU_RCR_RIE11(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE11_SHIFT)) & MU_RCR_RIE11_MASK) 1348 1349 #define MU_RCR_RIE12_MASK (0x1000U) 1350 #define MU_RCR_RIE12_SHIFT (12U) 1351 #define MU_RCR_RIE12_WIDTH (1U) 1352 #define MU_RCR_RIE12(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE12_SHIFT)) & MU_RCR_RIE12_MASK) 1353 1354 #define MU_RCR_RIE13_MASK (0x2000U) 1355 #define MU_RCR_RIE13_SHIFT (13U) 1356 #define MU_RCR_RIE13_WIDTH (1U) 1357 #define MU_RCR_RIE13(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE13_SHIFT)) & MU_RCR_RIE13_MASK) 1358 1359 #define MU_RCR_RIE14_MASK (0x4000U) 1360 #define MU_RCR_RIE14_SHIFT (14U) 1361 #define MU_RCR_RIE14_WIDTH (1U) 1362 #define MU_RCR_RIE14(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE14_SHIFT)) & MU_RCR_RIE14_MASK) 1363 1364 #define MU_RCR_RIE15_MASK (0x8000U) 1365 #define MU_RCR_RIE15_SHIFT (15U) 1366 #define MU_RCR_RIE15_WIDTH (1U) 1367 #define MU_RCR_RIE15(x) (((uint32_t)(((uint32_t)(x)) << MU_RCR_RIE15_SHIFT)) & MU_RCR_RIE15_MASK) 1368 /*! @} */ 1369 1370 /*! @name RSR - Receive Status Register */ 1371 /*! @{ */ 1372 1373 #define MU_RSR_RF0_MASK (0x1U) 1374 #define MU_RSR_RF0_SHIFT (0U) 1375 #define MU_RSR_RF0_WIDTH (1U) 1376 #define MU_RSR_RF0(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF0_SHIFT)) & MU_RSR_RF0_MASK) 1377 1378 #define MU_RSR_RF1_MASK (0x2U) 1379 #define MU_RSR_RF1_SHIFT (1U) 1380 #define MU_RSR_RF1_WIDTH (1U) 1381 #define MU_RSR_RF1(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF1_SHIFT)) & MU_RSR_RF1_MASK) 1382 1383 #define MU_RSR_RF2_MASK (0x4U) 1384 #define MU_RSR_RF2_SHIFT (2U) 1385 #define MU_RSR_RF2_WIDTH (1U) 1386 #define MU_RSR_RF2(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF2_SHIFT)) & MU_RSR_RF2_MASK) 1387 1388 #define MU_RSR_RF3_MASK (0x8U) 1389 #define MU_RSR_RF3_SHIFT (3U) 1390 #define MU_RSR_RF3_WIDTH (1U) 1391 #define MU_RSR_RF3(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF3_SHIFT)) & MU_RSR_RF3_MASK) 1392 1393 #define MU_RSR_RF4_MASK (0x10U) 1394 #define MU_RSR_RF4_SHIFT (4U) 1395 #define MU_RSR_RF4_WIDTH (1U) 1396 #define MU_RSR_RF4(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF4_SHIFT)) & MU_RSR_RF4_MASK) 1397 1398 #define MU_RSR_RF5_MASK (0x20U) 1399 #define MU_RSR_RF5_SHIFT (5U) 1400 #define MU_RSR_RF5_WIDTH (1U) 1401 #define MU_RSR_RF5(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF5_SHIFT)) & MU_RSR_RF5_MASK) 1402 1403 #define MU_RSR_RF6_MASK (0x40U) 1404 #define MU_RSR_RF6_SHIFT (6U) 1405 #define MU_RSR_RF6_WIDTH (1U) 1406 #define MU_RSR_RF6(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF6_SHIFT)) & MU_RSR_RF6_MASK) 1407 1408 #define MU_RSR_RF7_MASK (0x80U) 1409 #define MU_RSR_RF7_SHIFT (7U) 1410 #define MU_RSR_RF7_WIDTH (1U) 1411 #define MU_RSR_RF7(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF7_SHIFT)) & MU_RSR_RF7_MASK) 1412 1413 #define MU_RSR_RF8_MASK (0x100U) 1414 #define MU_RSR_RF8_SHIFT (8U) 1415 #define MU_RSR_RF8_WIDTH (1U) 1416 #define MU_RSR_RF8(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF8_SHIFT)) & MU_RSR_RF8_MASK) 1417 1418 #define MU_RSR_RF9_MASK (0x200U) 1419 #define MU_RSR_RF9_SHIFT (9U) 1420 #define MU_RSR_RF9_WIDTH (1U) 1421 #define MU_RSR_RF9(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF9_SHIFT)) & MU_RSR_RF9_MASK) 1422 1423 #define MU_RSR_RF10_MASK (0x400U) 1424 #define MU_RSR_RF10_SHIFT (10U) 1425 #define MU_RSR_RF10_WIDTH (1U) 1426 #define MU_RSR_RF10(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF10_SHIFT)) & MU_RSR_RF10_MASK) 1427 1428 #define MU_RSR_RF11_MASK (0x800U) 1429 #define MU_RSR_RF11_SHIFT (11U) 1430 #define MU_RSR_RF11_WIDTH (1U) 1431 #define MU_RSR_RF11(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF11_SHIFT)) & MU_RSR_RF11_MASK) 1432 1433 #define MU_RSR_RF12_MASK (0x1000U) 1434 #define MU_RSR_RF12_SHIFT (12U) 1435 #define MU_RSR_RF12_WIDTH (1U) 1436 #define MU_RSR_RF12(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF12_SHIFT)) & MU_RSR_RF12_MASK) 1437 1438 #define MU_RSR_RF13_MASK (0x2000U) 1439 #define MU_RSR_RF13_SHIFT (13U) 1440 #define MU_RSR_RF13_WIDTH (1U) 1441 #define MU_RSR_RF13(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF13_SHIFT)) & MU_RSR_RF13_MASK) 1442 1443 #define MU_RSR_RF14_MASK (0x4000U) 1444 #define MU_RSR_RF14_SHIFT (14U) 1445 #define MU_RSR_RF14_WIDTH (1U) 1446 #define MU_RSR_RF14(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF14_SHIFT)) & MU_RSR_RF14_MASK) 1447 1448 #define MU_RSR_RF15_MASK (0x8000U) 1449 #define MU_RSR_RF15_SHIFT (15U) 1450 #define MU_RSR_RF15_WIDTH (1U) 1451 #define MU_RSR_RF15(x) (((uint32_t)(((uint32_t)(x)) << MU_RSR_RF15_SHIFT)) & MU_RSR_RF15_MASK) 1452 /*! @} */ 1453 1454 /*! @name TR - Transmit Register */ 1455 /*! @{ */ 1456 1457 #define MU_TR_TR_DATA_MASK (0xFFFFFFFFU) 1458 #define MU_TR_TR_DATA_SHIFT (0U) 1459 #define MU_TR_TR_DATA_WIDTH (32U) 1460 #define MU_TR_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_TR_DATA_SHIFT)) & MU_TR_TR_DATA_MASK) 1461 /*! @} */ 1462 1463 /*! @name RR - Receive Register */ 1464 /*! @{ */ 1465 1466 #define MU_RR_RR_DATA_MASK (0xFFFFFFFFU) 1467 #define MU_RR_RR_DATA_SHIFT (0U) 1468 #define MU_RR_RR_DATA_WIDTH (32U) 1469 #define MU_RR_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_RR_DATA_SHIFT)) & MU_RR_RR_DATA_MASK) 1470 /*! @} */ 1471 1472 /*! 1473 * @} 1474 */ /* end of group MU_Register_Masks */ 1475 1476 /*! 1477 * @} 1478 */ /* end of group MU_Peripheral_Access_Layer */ 1479 1480 #endif /* #if !defined(S32Z2_MU_H_) */ 1481
