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Searched refs:MU_CR_GIRn_MASK (Results 1 – 25 of 88) sorted by relevance

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/hal_nxp-3.6.0/imx/drivers/
Dmu_imx.h148 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in MU_Init()
214 base->CR = (base->CR & ~ MU_CR_GIRn_MASK) // Clear GIRn in MU_EnableTxEmptyInt()
234 base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_TIE0_MASK>>index)); // Clear GIRn , clear TIEn in MU_DisableTxEmptyInt()
300 base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn in MU_EnableRxFullInt()
320 base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_RIE0_MASK>>index)); // Clear GIRn, clear RIEn in MU_DisableRxFullInt()
346 base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn in MU_EnableGeneralInt()
366 base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_GIE0_MASK>>index)); // Clear GIRn, clear GIEn in MU_DisableGeneralInt()
Dmu_imx.c116 base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn in MU_TriggerGeneralInt()
137 base->CR = (base->CR & ~(MU_CR_GIRn_MASK | MU_CR_Fn_MASK)) | flags; in MU_TrySetFlags()
150 base->CR = (base->CR & ~(MU_CR_GIRn_MASK | MU_CR_Fn_MASK)) | flags; in MU_SetFlags()
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/mu/
Dfsl_mu.h291 reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_Fn_MASK)) | MU_CR_Fn(flags); in MU_SetFlagsNonBlocking()
454 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; in MU_EnableInterrupts()
475 reg &= ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | mask); in MU_DisableInterrupts()
551 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_RSTH_MASK; in MU_HoldCoreBReset()
598 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_MUR_MASK; in MU_ResetBothSides()
712 reg &= ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK); in MU_SetClockOnOtherCoreEnable()
Dfsl_mu.c176 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; in MU_TriggerInterrupts()
215 …reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BBOOT_… in MU_BootCoreB()
368 …uint32_t cr = base->CR & ~(MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BOOT_MASK | MU_CR_GIRn_MASK | M… in MU_HardwareResetOtherCore()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX6/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX2/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX1/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QM6/scfw_api/main/
Dipc_imx8qm.c68 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX4/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX3/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX3/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX2/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX1/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX4/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX5/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX6/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX5/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX6/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX5/scfw_api/main/
Dipc_imx8qx.c64 …base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MAS… in sc_ipc_open()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm0plus.h13751 #define MU_CR_GIRn_MASK (0xF0000U) macro
13757 …x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
DK32L3A60_cm4.h13847 #define MU_CR_GIRn_MASK (0xF0000U) macro
13853 …x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h16581 #define MU_CR_GIRn_MASK (0xF0000U) macro
16587 …x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h19415 #define MU_CR_GIRn_MASK (0xF0000U) macro
19421 …x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h19416 #define MU_CR_GIRn_MASK (0xF0000U) macro
19422 …x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h23581 #define MU_CR_GIRn_MASK (0xF0000U) macro
23587 …x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)

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