Searched refs:MUX_6_DC_0 (Results 1 – 4 of 4) sorted by relevance
1657 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_FR_PE_CLK_Frequency()1658 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_P0_FR_PE_CLK_Frequency()1666 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_FRAY0_CLK_Frequency()1667 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_FRAY0_CLK_Frequency()1676 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_FRAY1_CLK_Frequency()1677 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_FRAY1_CLK_Frequency()2515 …Frequency /= (((IP_MC_CGM_4->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_CLKOUT2_CLK_Frequency()2614 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency()2615 …Frequency /= (((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency()2625 …Frequency /= (((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_ENET0_CLK_Frequency()
119 …__IO uint32_t MUX_6_DC_0; /**< Clock Mux 6 Divider 0 Control Register, offs… member
2004 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_CLKOUT_RUN_CLK_Frequency()2005 …Frequency /= (((IP_MC_CGM->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT… in Clock_Ip_Get_CLKOUT_RUN_CLK_Frequency()
135 …__IO uint32_t MUX_6_DC_0; /**< Clock Mux 6 Divider 0 Control Register, offs… member
