| /hal_nxp-3.6.0/s32/drivers/s32ze/Port/src/ |
| D | Siul2_Port_Ip.c | 628 config->baseAE->MSCR[config->pinPortIdx] = pinsValues; in Siul2_Port_Ip_PinInit()
633 config->base->MSCR[config->pinPortIdx] = pinsValues; in Siul2_Port_Ip_PinInit()
827 u32RegVal = base->MSCR[pin]; in Siul2_Port_Ip_GetMSCRConfiguration()
1031 base->MSCR[pin] &= ~pueVal; in Siul2_Port_Ip_ConfigInternalResistor()
1036 regVal = base->MSCR[pin]; in Siul2_Port_Ip_ConfigInternalResistor()
1041 base->MSCR[pin] = regVal; in Siul2_Port_Ip_ConfigInternalResistor()
1046 regVal = base->MSCR[pin]; in Siul2_Port_Ip_ConfigInternalResistor()
1051 base->MSCR[pin] = regVal; in Siul2_Port_Ip_ConfigInternalResistor()
1097 base->MSCR[pin] &= ~SIUL2_AE_MSCR_OBE_MASK; in Siul2_Port_Ip_ConfigOutputBuffer()
1099 base->MSCR[pin] |= SIUL2_AE_MSCR_OBE(enable ? 1UL : 0UL); in Siul2_Port_Ip_ConfigOutputBuffer()
[all …]
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| /hal_nxp-3.6.0/s32/drivers/s32k3/Port/src/ |
| D | Siul2_Port_Ip.c | 376 config->base->MSCR[config->pinPortIdx] = pinsValues; in Siul2_Port_Ip_PinInit()
508 u32RegVal = base->MSCR[pin]; in Siul2_Port_Ip_GetMSCRConfiguration()
676 base->MSCR[pin] &= ~pueVal; in Siul2_Port_Ip_SetPullSel()
682 regVal = base->MSCR[pin]; in Siul2_Port_Ip_SetPullSel()
687 base->MSCR[pin] = regVal; in Siul2_Port_Ip_SetPullSel()
692 regVal = base->MSCR[pin]; in Siul2_Port_Ip_SetPullSel()
697 base->MSCR[pin] = regVal; in Siul2_Port_Ip_SetPullSel()
730 base->MSCR[pin] &= ~SIUL2_MSCR_OBE_MASK; in Siul2_Port_Ip_SetOutputBuffer()
732 base->MSCR[pin] |= SIUL2_MSCR_OBE(enable ? 1UL : 0UL); in Siul2_Port_Ip_SetOutputBuffer()
735 base->MSCR[pin] &= ~SIUL2_MSCR_SSS_MASK; in Siul2_Port_Ip_SetOutputBuffer()
[all …]
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| /hal_nxp-3.6.0/s32/soc/s32z27/include/ |
| D | Siul2_Port_Ip_Defines.h | 97 #define SIUL2_0_MSCR_BASE (IP_SIUL2_0->MSCR)
98 #define SIUL2_1_MSCR_BASE (IP_SIUL2_1->MSCR)
99 #define SIUL2_3_MSCR_BASE (IP_SIUL2_3->MSCR)
100 #define SIUL2_4_MSCR_BASE (IP_SIUL2_4->MSCR)
101 #define SIUL2_5_MSCR_BASE (IP_SIUL2_5->MSCR)
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| /hal_nxp-3.6.0/s32/soc/s32k344/include/ |
| D | Siul2_Port_Ip_Defines.h | 107 #define SIUL2_MSCR_BASE (IP_SIUL2->MSCR)
|
| /hal_nxp-3.6.0/s32/drivers/s32k3/Port/include/ |
| D | Siul2_Port_Ip_Types.h | 322 __IO uint32 MSCR[16]; member
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| /hal_nxp-3.6.0/s32/drivers/s32ze/Port/include/ |
| D | Siul2_Port_Ip_Types.h | 396 __IO uint32 MSCR[16]; member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/enet/ |
| D | fsl_enet.h | 963 return (0U != (base->MSCR & 0x7EU)); in ENET_GetSMI()
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| D | fsl_enet.c | 1189 base->MSCR = mscr; in ENET_SetSMI()
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| /hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/header/ |
| D | S32K148_ENET.h | 86 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
|
| /hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_SIUL2.h | 102 …__IO uint32_t MSCR[SIUL2_MSCR_COUNT]; /**< SIUL2 Multiplexed Signal Configuration Regis… member
|
| /hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_SIUL2.h | 101 …__IO uint32_t MSCR[SIUL2_MSCR_COUNT]; /**< SIUL2 Multiplexed Signal Configuration Regis… member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK63F12/ |
| D | MK63F12.h | 9708 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK64F12/ |
| D | MK64F12.h | 9721 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV58F24/ |
| D | MKV58F24.h | 11963 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
|
| /hal_nxp-3.6.0/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 8455 …__IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x… member
8596 #define ENET_MSCR_REG(base) ((base)->MSCR)
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK65F18/ |
| D | MK65F18.h | 11350 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK66F18/ |
| D | MK66F18.h | 11350 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
|
| /hal_nxp-3.6.0/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 13097 …__IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x… member
13238 #define ENET_MSCR_REG(base) ((base)->MSCR)
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 16680 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 16696 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 17730 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 18972 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 18974 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 18515 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
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| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 19341 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ member
|
