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Searched refs:MINTSTS (Results 1 – 24 of 24) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/sdif/
Dfsl_sdif.h786 return base->MINTSTS; in SDIF_GetInterruptStatus()
795 uint32_t intStatus = base->MINTSTS; in SDIF_GetEnabledInterruptStatus()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h9899 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h9714 …__I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h8922 …__I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h9255 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h13478 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h12501 …__I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h13403 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h14121 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54618/
DLPC54618.h14123 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h13207 …__I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54608/
DLPC54608.h14046 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h14607 …__I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h14607 …__I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h13815 …__I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h13815 …__I uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5528/
DLPC5528.h17162 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5526/
DLPC5526.h17162 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h18818 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h18818 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core0.h19416 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
DLPC55S66_cm33_core1.h19416 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h19416 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member
DLPC55S69_cm33_core0.h19416 …__IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x… member