1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Emios_Mcl_Ip_Irq.c
9 *
10 * @brief AUTOSAR Mcl EMIOS interrupt common part.
11 *
12 * @addtogroup
13 * @{
14 */
15
16 #ifdef __cplusplus
17 extern "C"{
18 #endif
19
20 /*==================================================================================================
21 * INCLUDE FILES
22 * 1) system and project includes
23 * 2) needed interfaces from external units
24 * 3) internal and external interfaces from this unit
25 ==================================================================================================*/
26 #include "Emios_Mcl_Ip_Irq.h"
27
28 /*==================================================================================================
29 * SOURCE FILE VERSION INFORMATION
30 ==================================================================================================*/
31 #define EMIOS_MCL_IP_IRQ_VENDOR_ID_C 43
32 #define EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C 4
33 #define EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION_C 7
34 #define EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION_C 0
35 #define EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION_C 3
36 #define EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION_C 0
37 #define EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION_C 0
38 /*==================================================================================================
39 * FILE VERSION CHECKS
40 ==================================================================================================*/
41 #if (EMIOS_MCL_IP_IRQ_VENDOR_ID_C != EMIOS_MCL_IP_IRQ_VENDOR_ID)
42 #error "Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h have different vendor ids"
43 #endif
44
45 /* Check if source file and Emios_Mcl_Ip_Irq.h file are of the same Autosar version */
46 #if ((EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
47 (EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
48 (EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION))
49 #error "AutoSar Version Numbers of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different"
50 #endif
51
52 /* Check if source file and Emios_Mcl_Ip_Irq.h file are of the same Software version */
53 #if ((EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION_C != EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION) || \
54 (EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION_C != EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION) || \
55 (EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION_C != EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION))
56 #error "Software Version Numbers of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different"
57 #endif
58
59 /*==================================================================================================
60 * FILE VERSION CHECKS
61 ==================================================================================================*/
62
63 /* Check if Emios_Mcl_Ip_Irq.c file and Emios_Mcl_Ip_Irq header file are of the same vendor. */
64 #if (EMIOS_MCL_IP_IRQ_VENDOR_ID_C != EMIOS_MCL_IP_IRQ_VENDOR_ID)
65 #error "Vendor IDs of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different."
66 #endif
67
68 /* Check if Emios_Mcl_Ip_Irq.c file and Emios_Mcl_Ip_Irq header file are of the same AUTOSAR version. */
69 #if ((EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
70 (EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
71 (EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != EMIOS_MCL_IP_IRQ_AR_RELEASE_REVISION_VERSION))
72 #error "AUTOSAR version numbers of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different."
73 #endif
74
75 /* Check if Emios_Mcl_Ip_Irq.c file and Emios_Mcl_Ip_Irq header file are of the same software version */
76 #if ((EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION_C != EMIOS_MCL_IP_IRQ_SW_MAJOR_VERSION) || \
77 (EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION_C != EMIOS_MCL_IP_IRQ_SW_MINOR_VERSION) || \
78 (EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION_C != EMIOS_MCL_IP_IRQ_SW_PATCH_VERSION))
79 #error "Software version numbers of Emios_Mcl_Ip_Irq.c and Emios_Mcl_Ip_Irq.h are different."
80 #endif
81
82 /*==================================================================================================
83 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
84 ==================================================================================================*/
85
86 /*==================================================================================================
87 * LOCAL MACROS
88 ==================================================================================================*/
89 #if (\
90 (defined GPT_EMIOS_0_CH_0_ISR_USED) ||\
91 (defined GPT_EMIOS_0_CH_1_ISR_USED) ||\
92 (defined GPT_EMIOS_0_CH_2_ISR_USED) ||\
93 (defined GPT_EMIOS_0_CH_3_ISR_USED) ||\
94 (defined GPT_EMIOS_0_CH_4_ISR_USED) ||\
95 (defined GPT_EMIOS_0_CH_5_ISR_USED) ||\
96 (defined GPT_EMIOS_0_CH_6_ISR_USED) ||\
97 (defined GPT_EMIOS_0_CH_7_ISR_USED) ||\
98 (defined GPT_EMIOS_0_CH_8_ISR_USED) ||\
99 (defined GPT_EMIOS_0_CH_9_ISR_USED) ||\
100 (defined GPT_EMIOS_0_CH_10_ISR_USED) ||\
101 (defined GPT_EMIOS_0_CH_11_ISR_USED) ||\
102 (defined GPT_EMIOS_0_CH_12_ISR_USED) ||\
103 (defined GPT_EMIOS_0_CH_13_ISR_USED) ||\
104 (defined GPT_EMIOS_0_CH_14_ISR_USED) ||\
105 (defined GPT_EMIOS_0_CH_15_ISR_USED) ||\
106 (defined GPT_EMIOS_0_CH_16_ISR_USED) ||\
107 (defined GPT_EMIOS_0_CH_17_ISR_USED) ||\
108 (defined GPT_EMIOS_0_CH_18_ISR_USED) ||\
109 (defined GPT_EMIOS_0_CH_19_ISR_USED) ||\
110 (defined GPT_EMIOS_0_CH_20_ISR_USED) ||\
111 (defined GPT_EMIOS_0_CH_21_ISR_USED) ||\
112 (defined GPT_EMIOS_0_CH_22_ISR_USED) ||\
113 (defined GPT_EMIOS_0_CH_23_ISR_USED) ||\
114 (defined GPT_EMIOS_0_CH_24_ISR_USED) ||\
115 (defined GPT_EMIOS_0_CH_25_ISR_USED) ||\
116 (defined GPT_EMIOS_0_CH_26_ISR_USED) ||\
117 (defined GPT_EMIOS_0_CH_27_ISR_USED) ||\
118 (defined GPT_EMIOS_0_CH_28_ISR_USED) ||\
119 (defined GPT_EMIOS_0_CH_29_ISR_USED) ||\
120 (defined GPT_EMIOS_0_CH_30_ISR_USED) ||\
121 (defined GPT_EMIOS_0_CH_31_ISR_USED) ||\
122 (defined GPT_EMIOS_1_CH_0_ISR_USED) ||\
123 (defined GPT_EMIOS_1_CH_1_ISR_USED) ||\
124 (defined GPT_EMIOS_1_CH_2_ISR_USED) ||\
125 (defined GPT_EMIOS_1_CH_3_ISR_USED) ||\
126 (defined GPT_EMIOS_1_CH_4_ISR_USED) ||\
127 (defined GPT_EMIOS_1_CH_5_ISR_USED) ||\
128 (defined GPT_EMIOS_1_CH_6_ISR_USED) ||\
129 (defined GPT_EMIOS_1_CH_7_ISR_USED) ||\
130 (defined GPT_EMIOS_1_CH_8_ISR_USED) ||\
131 (defined GPT_EMIOS_1_CH_9_ISR_USED) ||\
132 (defined GPT_EMIOS_1_CH_10_ISR_USED) ||\
133 (defined GPT_EMIOS_1_CH_11_ISR_USED) ||\
134 (defined GPT_EMIOS_1_CH_12_ISR_USED) ||\
135 (defined GPT_EMIOS_1_CH_13_ISR_USED) ||\
136 (defined GPT_EMIOS_1_CH_14_ISR_USED) ||\
137 (defined GPT_EMIOS_1_CH_15_ISR_USED) ||\
138 (defined GPT_EMIOS_1_CH_16_ISR_USED) ||\
139 (defined GPT_EMIOS_1_CH_17_ISR_USED) ||\
140 (defined GPT_EMIOS_1_CH_18_ISR_USED) ||\
141 (defined GPT_EMIOS_1_CH_19_ISR_USED) ||\
142 (defined GPT_EMIOS_1_CH_20_ISR_USED) ||\
143 (defined GPT_EMIOS_1_CH_21_ISR_USED) ||\
144 (defined GPT_EMIOS_1_CH_22_ISR_USED) ||\
145 (defined GPT_EMIOS_1_CH_23_ISR_USED) ||\
146 (defined GPT_EMIOS_1_CH_24_ISR_USED) ||\
147 (defined GPT_EMIOS_1_CH_25_ISR_USED) ||\
148 (defined GPT_EMIOS_1_CH_26_ISR_USED) ||\
149 (defined GPT_EMIOS_1_CH_27_ISR_USED) ||\
150 (defined GPT_EMIOS_1_CH_28_ISR_USED) ||\
151 (defined GPT_EMIOS_1_CH_29_ISR_USED) ||\
152 (defined GPT_EMIOS_1_CH_30_ISR_USED) ||\
153 (defined GPT_EMIOS_1_CH_31_ISR_USED) ||\
154 (defined GPT_EMIOS_2_CH_0_ISR_USED) ||\
155 (defined GPT_EMIOS_2_CH_1_ISR_USED) ||\
156 (defined GPT_EMIOS_2_CH_2_ISR_USED) ||\
157 (defined GPT_EMIOS_2_CH_3_ISR_USED) ||\
158 (defined GPT_EMIOS_2_CH_4_ISR_USED) ||\
159 (defined GPT_EMIOS_2_CH_5_ISR_USED) ||\
160 (defined GPT_EMIOS_2_CH_6_ISR_USED) ||\
161 (defined GPT_EMIOS_2_CH_7_ISR_USED) ||\
162 (defined GPT_EMIOS_2_CH_8_ISR_USED) ||\
163 (defined GPT_EMIOS_2_CH_9_ISR_USED) ||\
164 (defined GPT_EMIOS_2_CH_10_ISR_USED) ||\
165 (defined GPT_EMIOS_2_CH_11_ISR_USED) ||\
166 (defined GPT_EMIOS_2_CH_12_ISR_USED) ||\
167 (defined GPT_EMIOS_2_CH_13_ISR_USED) ||\
168 (defined GPT_EMIOS_2_CH_14_ISR_USED) ||\
169 (defined GPT_EMIOS_2_CH_15_ISR_USED) ||\
170 (defined GPT_EMIOS_2_CH_16_ISR_USED) ||\
171 (defined GPT_EMIOS_2_CH_17_ISR_USED) ||\
172 (defined GPT_EMIOS_2_CH_18_ISR_USED) ||\
173 (defined GPT_EMIOS_2_CH_19_ISR_USED) ||\
174 (defined GPT_EMIOS_2_CH_20_ISR_USED) ||\
175 (defined GPT_EMIOS_2_CH_21_ISR_USED) ||\
176 (defined GPT_EMIOS_2_CH_22_ISR_USED) ||\
177 (defined GPT_EMIOS_2_CH_23_ISR_USED) ||\
178 (defined GPT_EMIOS_2_CH_24_ISR_USED) ||\
179 (defined GPT_EMIOS_2_CH_25_ISR_USED) ||\
180 (defined GPT_EMIOS_2_CH_26_ISR_USED) ||\
181 (defined GPT_EMIOS_2_CH_27_ISR_USED) ||\
182 (defined GPT_EMIOS_2_CH_28_ISR_USED) ||\
183 (defined GPT_EMIOS_2_CH_29_ISR_USED) ||\
184 (defined GPT_EMIOS_2_CH_30_ISR_USED) ||\
185 (defined GPT_EMIOS_2_CH_31_ISR_USED) ||\
186 (defined ICU_EMIOS_0_CH_0_ISR_USED) ||\
187 (defined ICU_EMIOS_0_CH_1_ISR_USED) ||\
188 (defined ICU_EMIOS_0_CH_2_ISR_USED) ||\
189 (defined ICU_EMIOS_0_CH_3_ISR_USED) ||\
190 (defined ICU_EMIOS_0_CH_4_ISR_USED) ||\
191 (defined ICU_EMIOS_0_CH_5_ISR_USED) ||\
192 (defined ICU_EMIOS_0_CH_6_ISR_USED) ||\
193 (defined ICU_EMIOS_0_CH_7_ISR_USED) ||\
194 (defined ICU_EMIOS_0_CH_8_ISR_USED) ||\
195 (defined ICU_EMIOS_0_CH_9_ISR_USED) ||\
196 (defined ICU_EMIOS_0_CH_10_ISR_USED) ||\
197 (defined ICU_EMIOS_0_CH_11_ISR_USED) ||\
198 (defined ICU_EMIOS_0_CH_12_ISR_USED) ||\
199 (defined ICU_EMIOS_0_CH_13_ISR_USED) ||\
200 (defined ICU_EMIOS_0_CH_14_ISR_USED) ||\
201 (defined ICU_EMIOS_0_CH_15_ISR_USED) ||\
202 (defined ICU_EMIOS_0_CH_16_ISR_USED) ||\
203 (defined ICU_EMIOS_0_CH_17_ISR_USED) ||\
204 (defined ICU_EMIOS_0_CH_18_ISR_USED) ||\
205 (defined ICU_EMIOS_0_CH_19_ISR_USED) ||\
206 (defined ICU_EMIOS_0_CH_20_ISR_USED) ||\
207 (defined ICU_EMIOS_0_CH_21_ISR_USED) ||\
208 (defined ICU_EMIOS_0_CH_22_ISR_USED) ||\
209 (defined ICU_EMIOS_0_CH_23_ISR_USED) ||\
210 (defined ICU_EMIOS_0_CH_24_ISR_USED) ||\
211 (defined ICU_EMIOS_0_CH_25_ISR_USED) ||\
212 (defined ICU_EMIOS_0_CH_26_ISR_USED) ||\
213 (defined ICU_EMIOS_0_CH_27_ISR_USED) ||\
214 (defined ICU_EMIOS_0_CH_28_ISR_USED) ||\
215 (defined ICU_EMIOS_0_CH_29_ISR_USED) ||\
216 (defined ICU_EMIOS_0_CH_30_ISR_USED) ||\
217 (defined ICU_EMIOS_0_CH_31_ISR_USED) ||\
218 (defined ICU_EMIOS_1_CH_0_ISR_USED) ||\
219 (defined ICU_EMIOS_1_CH_1_ISR_USED) ||\
220 (defined ICU_EMIOS_1_CH_2_ISR_USED) ||\
221 (defined ICU_EMIOS_1_CH_3_ISR_USED) ||\
222 (defined ICU_EMIOS_1_CH_4_ISR_USED) ||\
223 (defined ICU_EMIOS_1_CH_5_ISR_USED) ||\
224 (defined ICU_EMIOS_1_CH_6_ISR_USED) ||\
225 (defined ICU_EMIOS_1_CH_7_ISR_USED) ||\
226 (defined ICU_EMIOS_1_CH_8_ISR_USED) ||\
227 (defined ICU_EMIOS_1_CH_9_ISR_USED) ||\
228 (defined ICU_EMIOS_1_CH_10_ISR_USED) ||\
229 (defined ICU_EMIOS_1_CH_11_ISR_USED) ||\
230 (defined ICU_EMIOS_1_CH_12_ISR_USED) ||\
231 (defined ICU_EMIOS_1_CH_13_ISR_USED) ||\
232 (defined ICU_EMIOS_1_CH_14_ISR_USED) ||\
233 (defined ICU_EMIOS_1_CH_15_ISR_USED) ||\
234 (defined ICU_EMIOS_1_CH_16_ISR_USED) ||\
235 (defined ICU_EMIOS_1_CH_17_ISR_USED) ||\
236 (defined ICU_EMIOS_1_CH_18_ISR_USED) ||\
237 (defined ICU_EMIOS_1_CH_19_ISR_USED) ||\
238 (defined ICU_EMIOS_1_CH_20_ISR_USED) ||\
239 (defined ICU_EMIOS_1_CH_21_ISR_USED) ||\
240 (defined ICU_EMIOS_1_CH_22_ISR_USED) ||\
241 (defined ICU_EMIOS_1_CH_23_ISR_USED) ||\
242 (defined ICU_EMIOS_1_CH_24_ISR_USED) ||\
243 (defined ICU_EMIOS_1_CH_25_ISR_USED) ||\
244 (defined ICU_EMIOS_1_CH_26_ISR_USED) ||\
245 (defined ICU_EMIOS_1_CH_27_ISR_USED) ||\
246 (defined ICU_EMIOS_1_CH_28_ISR_USED) ||\
247 (defined ICU_EMIOS_1_CH_29_ISR_USED) ||\
248 (defined ICU_EMIOS_1_CH_30_ISR_USED) ||\
249 (defined ICU_EMIOS_1_CH_31_ISR_USED) ||\
250 (defined ICU_EMIOS_2_CH_0_ISR_USED) ||\
251 (defined ICU_EMIOS_2_CH_1_ISR_USED) ||\
252 (defined ICU_EMIOS_2_CH_2_ISR_USED) ||\
253 (defined ICU_EMIOS_2_CH_3_ISR_USED) ||\
254 (defined ICU_EMIOS_2_CH_4_ISR_USED) ||\
255 (defined ICU_EMIOS_2_CH_5_ISR_USED) ||\
256 (defined ICU_EMIOS_2_CH_6_ISR_USED) ||\
257 (defined ICU_EMIOS_2_CH_7_ISR_USED) ||\
258 (defined ICU_EMIOS_2_CH_8_ISR_USED) ||\
259 (defined ICU_EMIOS_2_CH_9_ISR_USED) ||\
260 (defined ICU_EMIOS_2_CH_10_ISR_USED) ||\
261 (defined ICU_EMIOS_2_CH_11_ISR_USED) ||\
262 (defined ICU_EMIOS_2_CH_12_ISR_USED) ||\
263 (defined ICU_EMIOS_2_CH_13_ISR_USED) ||\
264 (defined ICU_EMIOS_2_CH_14_ISR_USED) ||\
265 (defined ICU_EMIOS_2_CH_15_ISR_USED) ||\
266 (defined ICU_EMIOS_2_CH_16_ISR_USED) ||\
267 (defined ICU_EMIOS_2_CH_17_ISR_USED) ||\
268 (defined ICU_EMIOS_2_CH_18_ISR_USED) ||\
269 (defined ICU_EMIOS_2_CH_19_ISR_USED) ||\
270 (defined ICU_EMIOS_2_CH_20_ISR_USED) ||\
271 (defined ICU_EMIOS_2_CH_21_ISR_USED) ||\
272 (defined ICU_EMIOS_2_CH_22_ISR_USED) ||\
273 (defined ICU_EMIOS_2_CH_23_ISR_USED) ||\
274 (defined ICU_EMIOS_2_CH_24_ISR_USED) ||\
275 (defined ICU_EMIOS_2_CH_25_ISR_USED) ||\
276 (defined ICU_EMIOS_2_CH_26_ISR_USED) ||\
277 (defined ICU_EMIOS_2_CH_27_ISR_USED) ||\
278 (defined ICU_EMIOS_2_CH_28_ISR_USED) ||\
279 (defined ICU_EMIOS_2_CH_29_ISR_USED) ||\
280 (defined ICU_EMIOS_2_CH_30_ISR_USED) ||\
281 (defined ICU_EMIOS_2_CH_31_ISR_USED) ||\
282 (defined OCU_EMIOS_0_CH_0_ISR_USED) ||\
283 (defined OCU_EMIOS_0_CH_1_ISR_USED) ||\
284 (defined OCU_EMIOS_0_CH_2_ISR_USED) ||\
285 (defined OCU_EMIOS_0_CH_3_ISR_USED) ||\
286 (defined OCU_EMIOS_0_CH_4_ISR_USED) ||\
287 (defined OCU_EMIOS_0_CH_5_ISR_USED) ||\
288 (defined OCU_EMIOS_0_CH_6_ISR_USED) ||\
289 (defined OCU_EMIOS_0_CH_7_ISR_USED) ||\
290 (defined OCU_EMIOS_0_CH_8_ISR_USED) ||\
291 (defined OCU_EMIOS_0_CH_9_ISR_USED) ||\
292 (defined OCU_EMIOS_0_CH_10_ISR_USED) ||\
293 (defined OCU_EMIOS_0_CH_11_ISR_USED) ||\
294 (defined OCU_EMIOS_0_CH_12_ISR_USED) ||\
295 (defined OCU_EMIOS_0_CH_13_ISR_USED) ||\
296 (defined OCU_EMIOS_0_CH_14_ISR_USED) ||\
297 (defined OCU_EMIOS_0_CH_15_ISR_USED) ||\
298 (defined OCU_EMIOS_0_CH_16_ISR_USED) ||\
299 (defined OCU_EMIOS_0_CH_17_ISR_USED) ||\
300 (defined OCU_EMIOS_0_CH_18_ISR_USED) ||\
301 (defined OCU_EMIOS_0_CH_19_ISR_USED) ||\
302 (defined OCU_EMIOS_0_CH_20_ISR_USED) ||\
303 (defined OCU_EMIOS_0_CH_21_ISR_USED) ||\
304 (defined OCU_EMIOS_0_CH_22_ISR_USED) ||\
305 (defined OCU_EMIOS_0_CH_23_ISR_USED) ||\
306 (defined OCU_EMIOS_0_CH_24_ISR_USED) ||\
307 (defined OCU_EMIOS_0_CH_25_ISR_USED) ||\
308 (defined OCU_EMIOS_0_CH_26_ISR_USED) ||\
309 (defined OCU_EMIOS_0_CH_27_ISR_USED) ||\
310 (defined OCU_EMIOS_0_CH_28_ISR_USED) ||\
311 (defined OCU_EMIOS_0_CH_29_ISR_USED) ||\
312 (defined OCU_EMIOS_0_CH_30_ISR_USED) ||\
313 (defined OCU_EMIOS_0_CH_31_ISR_USED) ||\
314 (defined OCU_EMIOS_1_CH_0_ISR_USED) ||\
315 (defined OCU_EMIOS_1_CH_1_ISR_USED) ||\
316 (defined OCU_EMIOS_1_CH_2_ISR_USED) ||\
317 (defined OCU_EMIOS_1_CH_3_ISR_USED) ||\
318 (defined OCU_EMIOS_1_CH_4_ISR_USED) ||\
319 (defined OCU_EMIOS_1_CH_5_ISR_USED) ||\
320 (defined OCU_EMIOS_1_CH_6_ISR_USED) ||\
321 (defined OCU_EMIOS_1_CH_7_ISR_USED) ||\
322 (defined OCU_EMIOS_1_CH_8_ISR_USED) ||\
323 (defined OCU_EMIOS_1_CH_9_ISR_USED) ||\
324 (defined OCU_EMIOS_1_CH_10_ISR_USED) ||\
325 (defined OCU_EMIOS_1_CH_11_ISR_USED) ||\
326 (defined OCU_EMIOS_1_CH_12_ISR_USED) ||\
327 (defined OCU_EMIOS_1_CH_13_ISR_USED) ||\
328 (defined OCU_EMIOS_1_CH_14_ISR_USED) ||\
329 (defined OCU_EMIOS_1_CH_15_ISR_USED) ||\
330 (defined OCU_EMIOS_1_CH_16_ISR_USED) ||\
331 (defined OCU_EMIOS_1_CH_17_ISR_USED) ||\
332 (defined OCU_EMIOS_1_CH_18_ISR_USED) ||\
333 (defined OCU_EMIOS_1_CH_19_ISR_USED) ||\
334 (defined OCU_EMIOS_1_CH_20_ISR_USED) ||\
335 (defined OCU_EMIOS_1_CH_21_ISR_USED) ||\
336 (defined OCU_EMIOS_1_CH_22_ISR_USED) ||\
337 (defined OCU_EMIOS_1_CH_23_ISR_USED) ||\
338 (defined OCU_EMIOS_1_CH_24_ISR_USED) ||\
339 (defined OCU_EMIOS_1_CH_25_ISR_USED) ||\
340 (defined OCU_EMIOS_1_CH_26_ISR_USED) ||\
341 (defined OCU_EMIOS_1_CH_27_ISR_USED) ||\
342 (defined OCU_EMIOS_1_CH_28_ISR_USED) ||\
343 (defined OCU_EMIOS_1_CH_29_ISR_USED) ||\
344 (defined OCU_EMIOS_1_CH_30_ISR_USED) ||\
345 (defined OCU_EMIOS_1_CH_31_ISR_USED) ||\
346 (defined OCU_EMIOS_2_CH_0_ISR_USED) ||\
347 (defined OCU_EMIOS_2_CH_1_ISR_USED) ||\
348 (defined OCU_EMIOS_2_CH_2_ISR_USED) ||\
349 (defined OCU_EMIOS_2_CH_3_ISR_USED) ||\
350 (defined OCU_EMIOS_2_CH_4_ISR_USED) ||\
351 (defined OCU_EMIOS_2_CH_5_ISR_USED) ||\
352 (defined OCU_EMIOS_2_CH_6_ISR_USED) ||\
353 (defined OCU_EMIOS_2_CH_7_ISR_USED) ||\
354 (defined OCU_EMIOS_2_CH_8_ISR_USED) ||\
355 (defined OCU_EMIOS_2_CH_9_ISR_USED) ||\
356 (defined OCU_EMIOS_2_CH_10_ISR_USED) ||\
357 (defined OCU_EMIOS_2_CH_11_ISR_USED) ||\
358 (defined OCU_EMIOS_2_CH_12_ISR_USED) ||\
359 (defined OCU_EMIOS_2_CH_13_ISR_USED) ||\
360 (defined OCU_EMIOS_2_CH_14_ISR_USED) ||\
361 (defined OCU_EMIOS_2_CH_15_ISR_USED) ||\
362 (defined OCU_EMIOS_2_CH_16_ISR_USED) ||\
363 (defined OCU_EMIOS_2_CH_17_ISR_USED) ||\
364 (defined OCU_EMIOS_2_CH_18_ISR_USED) ||\
365 (defined OCU_EMIOS_2_CH_19_ISR_USED) ||\
366 (defined OCU_EMIOS_2_CH_20_ISR_USED) ||\
367 (defined OCU_EMIOS_2_CH_21_ISR_USED) ||\
368 (defined OCU_EMIOS_2_CH_22_ISR_USED) ||\
369 (defined OCU_EMIOS_2_CH_23_ISR_USED) ||\
370 (defined OCU_EMIOS_2_CH_24_ISR_USED) ||\
371 (defined OCU_EMIOS_2_CH_25_ISR_USED) ||\
372 (defined OCU_EMIOS_2_CH_26_ISR_USED) ||\
373 (defined OCU_EMIOS_2_CH_27_ISR_USED) ||\
374 (defined OCU_EMIOS_2_CH_28_ISR_USED) ||\
375 (defined OCU_EMIOS_2_CH_29_ISR_USED) ||\
376 (defined OCU_EMIOS_2_CH_30_ISR_USED) ||\
377 (defined OCU_EMIOS_2_CH_31_ISR_USED) ||\
378 (defined PWM_EMIOS_0_CH_0_ISR_USED) ||\
379 (defined PWM_EMIOS_0_CH_1_ISR_USED) ||\
380 (defined PWM_EMIOS_0_CH_2_ISR_USED) ||\
381 (defined PWM_EMIOS_0_CH_3_ISR_USED) ||\
382 (defined PWM_EMIOS_0_CH_4_ISR_USED) ||\
383 (defined PWM_EMIOS_0_CH_5_ISR_USED) ||\
384 (defined PWM_EMIOS_0_CH_6_ISR_USED) ||\
385 (defined PWM_EMIOS_0_CH_7_ISR_USED) ||\
386 (defined PWM_EMIOS_0_CH_8_ISR_USED) ||\
387 (defined PWM_EMIOS_0_CH_9_ISR_USED) ||\
388 (defined PWM_EMIOS_0_CH_10_ISR_USED) ||\
389 (defined PWM_EMIOS_0_CH_11_ISR_USED) ||\
390 (defined PWM_EMIOS_0_CH_12_ISR_USED) ||\
391 (defined PWM_EMIOS_0_CH_13_ISR_USED) ||\
392 (defined PWM_EMIOS_0_CH_14_ISR_USED) ||\
393 (defined PWM_EMIOS_0_CH_15_ISR_USED) ||\
394 (defined PWM_EMIOS_0_CH_16_ISR_USED) ||\
395 (defined PWM_EMIOS_0_CH_17_ISR_USED) ||\
396 (defined PWM_EMIOS_0_CH_18_ISR_USED) ||\
397 (defined PWM_EMIOS_0_CH_19_ISR_USED) ||\
398 (defined PWM_EMIOS_0_CH_20_ISR_USED) ||\
399 (defined PWM_EMIOS_0_CH_21_ISR_USED) ||\
400 (defined PWM_EMIOS_0_CH_22_ISR_USED) ||\
401 (defined PWM_EMIOS_0_CH_23_ISR_USED) ||\
402 (defined PWM_EMIOS_0_CH_24_ISR_USED) ||\
403 (defined PWM_EMIOS_0_CH_25_ISR_USED) ||\
404 (defined PWM_EMIOS_0_CH_26_ISR_USED) ||\
405 (defined PWM_EMIOS_0_CH_27_ISR_USED) ||\
406 (defined PWM_EMIOS_0_CH_28_ISR_USED) ||\
407 (defined PWM_EMIOS_0_CH_29_ISR_USED) ||\
408 (defined PWM_EMIOS_0_CH_30_ISR_USED) ||\
409 (defined PWM_EMIOS_0_CH_31_ISR_USED) ||\
410 (defined PWM_EMIOS_1_CH_0_ISR_USED) ||\
411 (defined PWM_EMIOS_1_CH_1_ISR_USED) ||\
412 (defined PWM_EMIOS_1_CH_2_ISR_USED) ||\
413 (defined PWM_EMIOS_1_CH_3_ISR_USED) ||\
414 (defined PWM_EMIOS_1_CH_4_ISR_USED) ||\
415 (defined PWM_EMIOS_1_CH_5_ISR_USED) ||\
416 (defined PWM_EMIOS_1_CH_6_ISR_USED) ||\
417 (defined PWM_EMIOS_1_CH_7_ISR_USED) ||\
418 (defined PWM_EMIOS_1_CH_8_ISR_USED) ||\
419 (defined PWM_EMIOS_1_CH_9_ISR_USED) ||\
420 (defined PWM_EMIOS_1_CH_10_ISR_USED) ||\
421 (defined PWM_EMIOS_1_CH_11_ISR_USED) ||\
422 (defined PWM_EMIOS_1_CH_12_ISR_USED) ||\
423 (defined PWM_EMIOS_1_CH_13_ISR_USED) ||\
424 (defined PWM_EMIOS_1_CH_14_ISR_USED) ||\
425 (defined PWM_EMIOS_1_CH_15_ISR_USED) ||\
426 (defined PWM_EMIOS_1_CH_16_ISR_USED) ||\
427 (defined PWM_EMIOS_1_CH_17_ISR_USED) ||\
428 (defined PWM_EMIOS_1_CH_18_ISR_USED) ||\
429 (defined PWM_EMIOS_1_CH_19_ISR_USED) ||\
430 (defined PWM_EMIOS_1_CH_20_ISR_USED) ||\
431 (defined PWM_EMIOS_1_CH_21_ISR_USED) ||\
432 (defined PWM_EMIOS_1_CH_22_ISR_USED) ||\
433 (defined PWM_EMIOS_1_CH_23_ISR_USED) ||\
434 (defined PWM_EMIOS_1_CH_24_ISR_USED) ||\
435 (defined PWM_EMIOS_1_CH_25_ISR_USED) ||\
436 (defined PWM_EMIOS_1_CH_26_ISR_USED) ||\
437 (defined PWM_EMIOS_1_CH_27_ISR_USED) ||\
438 (defined PWM_EMIOS_1_CH_28_ISR_USED) ||\
439 (defined PWM_EMIOS_1_CH_29_ISR_USED) ||\
440 (defined PWM_EMIOS_1_CH_30_ISR_USED) ||\
441 (defined PWM_EMIOS_1_CH_31_ISR_USED) ||\
442 (defined PWM_EMIOS_2_CH_0_ISR_USED) ||\
443 (defined PWM_EMIOS_2_CH_1_ISR_USED) ||\
444 (defined PWM_EMIOS_2_CH_2_ISR_USED) ||\
445 (defined PWM_EMIOS_2_CH_3_ISR_USED) ||\
446 (defined PWM_EMIOS_2_CH_4_ISR_USED) ||\
447 (defined PWM_EMIOS_2_CH_5_ISR_USED) ||\
448 (defined PWM_EMIOS_2_CH_6_ISR_USED) ||\
449 (defined PWM_EMIOS_2_CH_7_ISR_USED) ||\
450 (defined PWM_EMIOS_2_CH_8_ISR_USED) ||\
451 (defined PWM_EMIOS_2_CH_9_ISR_USED) ||\
452 (defined PWM_EMIOS_2_CH_10_ISR_USED) ||\
453 (defined PWM_EMIOS_2_CH_11_ISR_USED) ||\
454 (defined PWM_EMIOS_2_CH_12_ISR_USED) ||\
455 (defined PWM_EMIOS_2_CH_13_ISR_USED) ||\
456 (defined PWM_EMIOS_2_CH_14_ISR_USED) ||\
457 (defined PWM_EMIOS_2_CH_15_ISR_USED) ||\
458 (defined PWM_EMIOS_2_CH_16_ISR_USED) ||\
459 (defined PWM_EMIOS_2_CH_17_ISR_USED) ||\
460 (defined PWM_EMIOS_2_CH_18_ISR_USED) ||\
461 (defined PWM_EMIOS_2_CH_19_ISR_USED) ||\
462 (defined PWM_EMIOS_2_CH_20_ISR_USED) ||\
463 (defined PWM_EMIOS_2_CH_21_ISR_USED) ||\
464 (defined PWM_EMIOS_2_CH_22_ISR_USED) ||\
465 (defined PWM_EMIOS_2_CH_23_ISR_USED) ||\
466 (defined PWM_EMIOS_2_CH_24_ISR_USED) ||\
467 (defined PWM_EMIOS_2_CH_25_ISR_USED) ||\
468 (defined PWM_EMIOS_2_CH_26_ISR_USED) ||\
469 (defined PWM_EMIOS_2_CH_27_ISR_USED) ||\
470 (defined PWM_EMIOS_2_CH_28_ISR_USED) ||\
471 (defined PWM_EMIOS_2_CH_29_ISR_USED) ||\
472 (defined PWM_EMIOS_2_CH_30_ISR_USED) ||\
473 (defined PWM_EMIOS_2_CH_31_ISR_USED)\
474 )
475
476 /*==================================================================================================
477 * LOCAL CONSTANTS
478 ==================================================================================================*/
479
480 /*==================================================================================================
481 * LOCAL VARIABLES
482 ==================================================================================================*/
483
484 /*==================================================================================================
485 * GLOBAL CONSTANTS
486 ==================================================================================================*/
487
488 /*==================================================================================================
489 * GLOBAL VARIABLES
490 ==================================================================================================*/
491 #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED
492 #include "Mcl_MemMap.h"
493
494 /* Array with EMIOS bases addresses. */
495 extern eMIOS_Type* Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT];
496
497 #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED
498 #include "Mcl_MemMap.h"
499
500 #endif /* All platfrom includes. */
501
502
503 /*==================================================================================================
504 * LOCAL FUNCTION PROTOTYPES
505 ==================================================================================================*/
506
507 /*==================================================================================================
508 * LOCAL FUNCTIONS
509 ==================================================================================================*/
510
511 /*==================================================================================================
512 * GLOBAL FUNCTIONS
513 ==================================================================================================*/
514 #define MCL_START_SEC_CODE
515 #include "Mcl_MemMap.h"
516
517 #if (\
518 (defined GPT_EMIOS_0_CH_0_ISR_USED) ||\
519 (defined GPT_EMIOS_0_CH_1_ISR_USED) ||\
520 (defined GPT_EMIOS_0_CH_2_ISR_USED) ||\
521 (defined GPT_EMIOS_0_CH_3_ISR_USED) ||\
522 (defined ICU_EMIOS_0_CH_0_ISR_USED) ||\
523 (defined ICU_EMIOS_0_CH_1_ISR_USED) ||\
524 (defined ICU_EMIOS_0_CH_2_ISR_USED) ||\
525 (defined ICU_EMIOS_0_CH_3_ISR_USED) ||\
526 (defined OCU_EMIOS_0_CH_0_ISR_USED) ||\
527 (defined OCU_EMIOS_0_CH_1_ISR_USED) ||\
528 (defined OCU_EMIOS_0_CH_2_ISR_USED) ||\
529 (defined OCU_EMIOS_0_CH_3_ISR_USED) ||\
530 (defined PWM_EMIOS_0_CH_0_ISR_USED) ||\
531 (defined PWM_EMIOS_0_CH_1_ISR_USED) ||\
532 (defined PWM_EMIOS_0_CH_2_ISR_USED) ||\
533 (defined PWM_EMIOS_0_CH_3_ISR_USED)\
534 )
535 /**
536 * @brief Interrupt handler for Emios channels 0-3 for Emios instance 0
537 * @details Process the interrupt of eMios channels 0-3
538 *
539 * @note This will be defined only if EMIOS channels 0, 1, 2, 3 are configured in GPT, ICU,
540 * OCU or PWM mode.
541 */
ISR(EMIOS0_5_IRQ)542 ISR(EMIOS0_5_IRQ)
543 {
544 #if (defined EMIOS_0_CH_0_ISR_USED)
545 /* Check that an event occurred on Emios channel 0 */
546 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[0].S) & (uint32)eMIOS_S_FLAG_MASK) )
547 {
548 /* Check that an event occurred on EMIOS channel 0 */
549 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[0].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
550 {
551 #if (defined GPT_EMIOS_0_CH_0_ISR_USED)
552 Emios_Gpt_Ip_IrqHandler(0, 0);
553 #endif
554
555 #if (defined ICU_EMIOS_0_CH_0_ISR_USED)
556 Emios_Icu_Ip_IrqHandler(0, 0);
557 #endif
558
559 #if (defined OCU_EMIOS_0_CH_0_ISR_USED)
560 Emios_Ocu_Ip_IrqHandler(0, 0);
561 #endif
562
563 #if (defined PWM_EMIOS_0_CH_0_ISR_USED)
564 Emios_Pwm_Ip_IrqHandler(0, 0);
565 #endif
566
567 }
568 else
569 {
570 /* Do nothing - in case of spurious interrupts, return immediately */
571 }
572 }
573 #endif
574
575 #if (defined EMIOS_0_CH_1_ISR_USED)
576 /* Check that an event occurred on Emios channel 1 */
577 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[1].S) & (uint32)eMIOS_S_FLAG_MASK) )
578 {
579 /* Check that an event occurred on EMIOS channel 1 */
580 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[1].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
581 {
582 #if (defined GPT_EMIOS_0_CH_1_ISR_USED)
583 Emios_Gpt_Ip_IrqHandler(0, 1);
584 #endif
585
586 #if (defined ICU_EMIOS_0_CH_1_ISR_USED)
587 Emios_Icu_Ip_IrqHandler(0, 1);
588 #endif
589
590 #if (defined OCU_EMIOS_0_CH_1_ISR_USED)
591 Emios_Ocu_Ip_IrqHandler(0, 1);
592 #endif
593
594 #if (defined PWM_EMIOS_0_CH_1_ISR_USED)
595 Emios_Pwm_Ip_IrqHandler(0, 1);
596 #endif
597
598 }
599 else
600 {
601 /* Do nothing - in case of spurious interrupts, return immediately */
602 }
603 }
604 #endif
605
606 #if (defined EMIOS_0_CH_2_ISR_USED)
607 /* Check that an event occurred on Emios channel 2 */
608 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[2].S) & (uint32)eMIOS_S_FLAG_MASK) )
609 {
610 /* Check that an event occurred on EMIOS channel 2 */
611 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[2].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
612 {
613 #if (defined GPT_EMIOS_0_CH_2_ISR_USED)
614 Emios_Gpt_Ip_IrqHandler(0, 2);
615 #endif
616
617 #if (defined ICU_EMIOS_0_CH_2_ISR_USED)
618 Emios_Icu_Ip_IrqHandler(0, 2);
619 #endif
620
621 #if (defined OCU_EMIOS_0_CH_2_ISR_USED)
622 Emios_Ocu_Ip_IrqHandler(0, 2);
623 #endif
624
625 #if (defined PWM_EMIOS_0_CH_2_ISR_USED)
626 Emios_Pwm_Ip_IrqHandler(0, 2);
627 #endif
628
629 }
630 else
631 {
632 /* Do nothing - in case of spurious interrupts, return immediately */
633 }
634 }
635 #endif
636
637 #if (defined EMIOS_0_CH_3_ISR_USED)
638 /* Check that an event occurred on Emios channel 3 */
639 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[3].S) & (uint32)eMIOS_S_FLAG_MASK) )
640 {
641 /* Check that an event occurred on EMIOS channel 3 */
642 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[3].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
643 {
644 #if (defined GPT_EMIOS_0_CH_3_ISR_USED)
645 Emios_Gpt_Ip_IrqHandler(0, 3);
646 #endif
647
648 #if (defined ICU_EMIOS_0_CH_3_ISR_USED)
649 Emios_Icu_Ip_IrqHandler(0, 3);
650 #endif
651
652 #if (defined OCU_EMIOS_0_CH_3_ISR_USED)
653 Emios_Ocu_Ip_IrqHandler(0, 3);
654 #endif
655
656 #if (defined PWM_EMIOS_0_CH_3_ISR_USED)
657 Emios_Pwm_Ip_IrqHandler(0, 3);
658 #endif
659
660 }
661 else
662 {
663 /* Do nothing - in case of spurious interrupts, return immediately */
664 }
665 }
666 #endif
667
668 }
669 #endif
670 #if (\
671 (defined GPT_EMIOS_0_CH_4_ISR_USED) ||\
672 (defined GPT_EMIOS_0_CH_5_ISR_USED) ||\
673 (defined GPT_EMIOS_0_CH_6_ISR_USED) ||\
674 (defined GPT_EMIOS_0_CH_7_ISR_USED) ||\
675 (defined ICU_EMIOS_0_CH_4_ISR_USED) ||\
676 (defined ICU_EMIOS_0_CH_5_ISR_USED) ||\
677 (defined ICU_EMIOS_0_CH_6_ISR_USED) ||\
678 (defined ICU_EMIOS_0_CH_7_ISR_USED) ||\
679 (defined OCU_EMIOS_0_CH_4_ISR_USED) ||\
680 (defined OCU_EMIOS_0_CH_5_ISR_USED) ||\
681 (defined OCU_EMIOS_0_CH_6_ISR_USED) ||\
682 (defined OCU_EMIOS_0_CH_7_ISR_USED) ||\
683 (defined PWM_EMIOS_0_CH_4_ISR_USED) ||\
684 (defined PWM_EMIOS_0_CH_5_ISR_USED) ||\
685 (defined PWM_EMIOS_0_CH_6_ISR_USED) ||\
686 (defined PWM_EMIOS_0_CH_7_ISR_USED)\
687 )
688 /**
689 * @brief Interrupt handler for Emios channels 4-7 for Emios instance 0
690 * @details Process the interrupt of eMios channels 4-7
691 *
692 * @note This will be defined only if EMIOS channels 4, 5, 6, 7 are configured in GPT, ICU,
693 * OCU or PWM mode.
694 */
ISR(EMIOS0_4_IRQ)695 ISR(EMIOS0_4_IRQ)
696 {
697 #if (defined EMIOS_0_CH_4_ISR_USED)
698 /* Check that an event occurred on Emios channel 4 */
699 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[4].S) & (uint32)eMIOS_S_FLAG_MASK) )
700 {
701 /* Check that an event occurred on EMIOS channel 4 */
702 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[4].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
703 {
704 #if (defined GPT_EMIOS_0_CH_4_ISR_USED)
705 Emios_Gpt_Ip_IrqHandler(0, 4);
706 #endif
707
708 #if (defined ICU_EMIOS_0_CH_4_ISR_USED)
709 Emios_Icu_Ip_IrqHandler(0, 4);
710 #endif
711
712 #if (defined OCU_EMIOS_0_CH_4_ISR_USED)
713 Emios_Ocu_Ip_IrqHandler(0, 4);
714 #endif
715
716 #if (defined PWM_EMIOS_0_CH_4_ISR_USED)
717 Emios_Pwm_Ip_IrqHandler(0, 4);
718 #endif
719
720 }
721 else
722 {
723 /* Do nothing - in case of spurious interrupts, return immediately */
724 }
725 }
726 #endif
727
728 #if (defined EMIOS_0_CH_5_ISR_USED)
729 /* Check that an event occurred on Emios channel 5 */
730 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[5].S) & (uint32)eMIOS_S_FLAG_MASK) )
731 {
732 /* Check that an event occurred on EMIOS channel 5 */
733 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[5].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
734 {
735 #if (defined GPT_EMIOS_0_CH_5_ISR_USED)
736 Emios_Gpt_Ip_IrqHandler(0, 5);
737 #endif
738
739 #if (defined ICU_EMIOS_0_CH_5_ISR_USED)
740 Emios_Icu_Ip_IrqHandler(0, 5);
741 #endif
742
743 #if (defined OCU_EMIOS_0_CH_5_ISR_USED)
744 Emios_Ocu_Ip_IrqHandler(0, 5);
745 #endif
746
747 #if (defined PWM_EMIOS_0_CH_5_ISR_USED)
748 Emios_Pwm_Ip_IrqHandler(0, 5);
749 #endif
750
751 }
752 else
753 {
754 /* Do nothing - in case of spurious interrupts, return immediately */
755 }
756 }
757 #endif
758
759 #if (defined EMIOS_0_CH_6_ISR_USED)
760 /* Check that an event occurred on Emios channel 6 */
761 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[6].S) & (uint32)eMIOS_S_FLAG_MASK) )
762 {
763 /* Check that an event occurred on EMIOS channel 6 */
764 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[6].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
765 {
766 #if (defined GPT_EMIOS_0_CH_6_ISR_USED)
767 Emios_Gpt_Ip_IrqHandler(0, 6);
768 #endif
769
770 #if (defined ICU_EMIOS_0_CH_6_ISR_USED)
771 Emios_Icu_Ip_IrqHandler(0, 6);
772 #endif
773
774 #if (defined OCU_EMIOS_0_CH_6_ISR_USED)
775 Emios_Ocu_Ip_IrqHandler(0, 6);
776 #endif
777
778 #if (defined PWM_EMIOS_0_CH_6_ISR_USED)
779 Emios_Pwm_Ip_IrqHandler(0, 6);
780 #endif
781
782 }
783 else
784 {
785 /* Do nothing - in case of spurious interrupts, return immediately */
786 }
787 }
788 #endif
789
790 #if (defined EMIOS_0_CH_7_ISR_USED)
791 /* Check that an event occurred on Emios channel 7 */
792 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[7].S) & (uint32)eMIOS_S_FLAG_MASK) )
793 {
794 /* Check that an event occurred on EMIOS channel 7 */
795 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[7].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
796 {
797 #if (defined GPT_EMIOS_0_CH_7_ISR_USED)
798 Emios_Gpt_Ip_IrqHandler(0, 7);
799 #endif
800
801 #if (defined ICU_EMIOS_0_CH_7_ISR_USED)
802 Emios_Icu_Ip_IrqHandler(0, 7);
803 #endif
804
805 #if (defined OCU_EMIOS_0_CH_7_ISR_USED)
806 Emios_Ocu_Ip_IrqHandler(0, 7);
807 #endif
808
809 #if (defined PWM_EMIOS_0_CH_7_ISR_USED)
810 Emios_Pwm_Ip_IrqHandler(0, 7);
811 #endif
812
813 }
814 else
815 {
816 /* Do nothing - in case of spurious interrupts, return immediately */
817 }
818 }
819 #endif
820
821 }
822 #endif
823 #if (\
824 (defined GPT_EMIOS_0_CH_8_ISR_USED) ||\
825 (defined GPT_EMIOS_0_CH_9_ISR_USED) ||\
826 (defined GPT_EMIOS_0_CH_10_ISR_USED) ||\
827 (defined GPT_EMIOS_0_CH_11_ISR_USED) ||\
828 (defined ICU_EMIOS_0_CH_8_ISR_USED) ||\
829 (defined ICU_EMIOS_0_CH_9_ISR_USED) ||\
830 (defined ICU_EMIOS_0_CH_10_ISR_USED) ||\
831 (defined ICU_EMIOS_0_CH_11_ISR_USED) ||\
832 (defined OCU_EMIOS_0_CH_8_ISR_USED) ||\
833 (defined OCU_EMIOS_0_CH_9_ISR_USED) ||\
834 (defined OCU_EMIOS_0_CH_10_ISR_USED) ||\
835 (defined OCU_EMIOS_0_CH_11_ISR_USED) ||\
836 (defined PWM_EMIOS_0_CH_8_ISR_USED) ||\
837 (defined PWM_EMIOS_0_CH_9_ISR_USED) ||\
838 (defined PWM_EMIOS_0_CH_10_ISR_USED) ||\
839 (defined PWM_EMIOS_0_CH_11_ISR_USED)\
840 )
841 /**
842 * @brief Interrupt handler for Emios channels 8-11 for Emios instance 0
843 * @details Process the interrupt of eMios channels 8-11
844 *
845 * @note This will be defined only if EMIOS channels 8, 9, 10, 11 are configured in GPT, ICU,
846 * OCU or PWM mode.
847 */
ISR(EMIOS0_3_IRQ)848 ISR(EMIOS0_3_IRQ)
849 {
850 #if (defined EMIOS_0_CH_8_ISR_USED)
851 /* Check that an event occurred on Emios channel 8 */
852 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[8].S) & (uint32)eMIOS_S_FLAG_MASK) )
853 {
854 /* Check that an event occurred on EMIOS channel 8 */
855 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[8].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
856 {
857 #if (defined GPT_EMIOS_0_CH_8_ISR_USED)
858 Emios_Gpt_Ip_IrqHandler(0, 8);
859 #endif
860
861 #if (defined ICU_EMIOS_0_CH_8_ISR_USED)
862 Emios_Icu_Ip_IrqHandler(0, 8);
863 #endif
864
865 #if (defined OCU_EMIOS_0_CH_8_ISR_USED)
866 Emios_Ocu_Ip_IrqHandler(0, 8);
867 #endif
868
869 #if (defined PWM_EMIOS_0_CH_8_ISR_USED)
870 Emios_Pwm_Ip_IrqHandler(0, 8);
871 #endif
872
873 }
874 else
875 {
876 /* Do nothing - in case of spurious interrupts, return immediately */
877 }
878 }
879 #endif
880
881 #if (defined EMIOS_0_CH_9_ISR_USED)
882 /* Check that an event occurred on Emios channel 9 */
883 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[9].S) & (uint32)eMIOS_S_FLAG_MASK) )
884 {
885 /* Check that an event occurred on EMIOS channel 9 */
886 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[9].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
887 {
888 #if (defined GPT_EMIOS_0_CH_9_ISR_USED)
889 Emios_Gpt_Ip_IrqHandler(0, 9);
890 #endif
891
892 #if (defined ICU_EMIOS_0_CH_9_ISR_USED)
893 Emios_Icu_Ip_IrqHandler(0, 9);
894 #endif
895
896 #if (defined OCU_EMIOS_0_CH_9_ISR_USED)
897 Emios_Ocu_Ip_IrqHandler(0, 9);
898 #endif
899
900 #if (defined PWM_EMIOS_0_CH_9_ISR_USED)
901 Emios_Pwm_Ip_IrqHandler(0, 9);
902 #endif
903
904 }
905 else
906 {
907 /* Do nothing - in case of spurious interrupts, return immediately */
908 }
909 }
910 #endif
911
912 #if (defined EMIOS_0_CH_10_ISR_USED)
913 /* Check that an event occurred on Emios channel 10 */
914 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[10].S) & (uint32)eMIOS_S_FLAG_MASK) )
915 {
916 /* Check that an event occurred on EMIOS channel 10 */
917 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[10].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
918 {
919 #if (defined GPT_EMIOS_0_CH_10_ISR_USED)
920 Emios_Gpt_Ip_IrqHandler(0, 10);
921 #endif
922
923 #if (defined ICU_EMIOS_0_CH_10_ISR_USED)
924 Emios_Icu_Ip_IrqHandler(0, 10);
925 #endif
926
927 #if (defined OCU_EMIOS_0_CH_10_ISR_USED)
928 Emios_Ocu_Ip_IrqHandler(0, 10);
929 #endif
930
931 #if (defined PWM_EMIOS_0_CH_10_ISR_USED)
932 Emios_Pwm_Ip_IrqHandler(0, 10);
933 #endif
934
935 }
936 else
937 {
938 /* Do nothing - in case of spurious interrupts, return immediately */
939 }
940 }
941 #endif
942
943 #if (defined EMIOS_0_CH_11_ISR_USED)
944 /* Check that an event occurred on Emios channel 11 */
945 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[11].S) & (uint32)eMIOS_S_FLAG_MASK) )
946 {
947 /* Check that an event occurred on EMIOS channel 11 */
948 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[11].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
949 {
950 #if (defined GPT_EMIOS_0_CH_11_ISR_USED)
951 Emios_Gpt_Ip_IrqHandler(0, 11);
952 #endif
953
954 #if (defined ICU_EMIOS_0_CH_11_ISR_USED)
955 Emios_Icu_Ip_IrqHandler(0, 11);
956 #endif
957
958 #if (defined OCU_EMIOS_0_CH_11_ISR_USED)
959 Emios_Ocu_Ip_IrqHandler(0, 11);
960 #endif
961
962 #if (defined PWM_EMIOS_0_CH_11_ISR_USED)
963 Emios_Pwm_Ip_IrqHandler(0, 11);
964 #endif
965
966 }
967 else
968 {
969 /* Do nothing - in case of spurious interrupts, return immediately */
970 }
971 }
972 #endif
973
974 }
975 #endif
976 #if (\
977 (defined GPT_EMIOS_0_CH_12_ISR_USED) ||\
978 (defined GPT_EMIOS_0_CH_13_ISR_USED) ||\
979 (defined GPT_EMIOS_0_CH_14_ISR_USED) ||\
980 (defined GPT_EMIOS_0_CH_15_ISR_USED) ||\
981 (defined ICU_EMIOS_0_CH_12_ISR_USED) ||\
982 (defined ICU_EMIOS_0_CH_13_ISR_USED) ||\
983 (defined ICU_EMIOS_0_CH_14_ISR_USED) ||\
984 (defined ICU_EMIOS_0_CH_15_ISR_USED) ||\
985 (defined OCU_EMIOS_0_CH_12_ISR_USED) ||\
986 (defined OCU_EMIOS_0_CH_13_ISR_USED) ||\
987 (defined OCU_EMIOS_0_CH_14_ISR_USED) ||\
988 (defined OCU_EMIOS_0_CH_15_ISR_USED) ||\
989 (defined PWM_EMIOS_0_CH_12_ISR_USED) ||\
990 (defined PWM_EMIOS_0_CH_13_ISR_USED) ||\
991 (defined PWM_EMIOS_0_CH_14_ISR_USED) ||\
992 (defined PWM_EMIOS_0_CH_15_ISR_USED)\
993 )
994 /**
995 * @brief Interrupt handler for Emios channels 12-15 for Emios instance 0
996 * @details Process the interrupt of eMios channels 12-15
997 *
998 * @note This will be defined only if EMIOS channels 12, 13, 14, 15 are configured in GPT, ICU,
999 * OCU or PWM mode.
1000 */
ISR(EMIOS0_2_IRQ)1001 ISR(EMIOS0_2_IRQ)
1002 {
1003 #if (defined EMIOS_0_CH_12_ISR_USED)
1004 /* Check that an event occurred on Emios channel 12 */
1005 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[12].S) & (uint32)eMIOS_S_FLAG_MASK) )
1006 {
1007 /* Check that an event occurred on EMIOS channel 12 */
1008 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[12].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1009 {
1010 #if (defined GPT_EMIOS_0_CH_12_ISR_USED)
1011 Emios_Gpt_Ip_IrqHandler(0, 12);
1012 #endif
1013
1014 #if (defined ICU_EMIOS_0_CH_12_ISR_USED)
1015 Emios_Icu_Ip_IrqHandler(0, 12);
1016 #endif
1017
1018 #if (defined OCU_EMIOS_0_CH_12_ISR_USED)
1019 Emios_Ocu_Ip_IrqHandler(0, 12);
1020 #endif
1021
1022 #if (defined PWM_EMIOS_0_CH_12_ISR_USED)
1023 Emios_Pwm_Ip_IrqHandler(0, 12);
1024 #endif
1025
1026 }
1027 else
1028 {
1029 /* Do nothing - in case of spurious interrupts, return immediately */
1030 }
1031 }
1032 #endif
1033
1034 #if (defined EMIOS_0_CH_13_ISR_USED)
1035 /* Check that an event occurred on Emios channel 13 */
1036 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[13].S) & (uint32)eMIOS_S_FLAG_MASK) )
1037 {
1038 /* Check that an event occurred on EMIOS channel 13 */
1039 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[13].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1040 {
1041 #if (defined GPT_EMIOS_0_CH_13_ISR_USED)
1042 Emios_Gpt_Ip_IrqHandler(0, 13);
1043 #endif
1044
1045 #if (defined ICU_EMIOS_0_CH_13_ISR_USED)
1046 Emios_Icu_Ip_IrqHandler(0, 13);
1047 #endif
1048
1049 #if (defined OCU_EMIOS_0_CH_13_ISR_USED)
1050 Emios_Ocu_Ip_IrqHandler(0, 13);
1051 #endif
1052
1053 #if (defined PWM_EMIOS_0_CH_13_ISR_USED)
1054 Emios_Pwm_Ip_IrqHandler(0, 13);
1055 #endif
1056
1057 }
1058 else
1059 {
1060 /* Do nothing - in case of spurious interrupts, return immediately */
1061 }
1062 }
1063 #endif
1064
1065 #if (defined EMIOS_0_CH_14_ISR_USED)
1066 /* Check that an event occurred on Emios channel 14 */
1067 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[14].S) & (uint32)eMIOS_S_FLAG_MASK) )
1068 {
1069 /* Check that an event occurred on EMIOS channel 14 */
1070 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[14].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1071 {
1072 #if (defined GPT_EMIOS_0_CH_14_ISR_USED)
1073 Emios_Gpt_Ip_IrqHandler(0, 14);
1074 #endif
1075
1076 #if (defined ICU_EMIOS_0_CH_14_ISR_USED)
1077 Emios_Icu_Ip_IrqHandler(0, 14);
1078 #endif
1079
1080 #if (defined OCU_EMIOS_0_CH_14_ISR_USED)
1081 Emios_Ocu_Ip_IrqHandler(0, 14);
1082 #endif
1083
1084 #if (defined PWM_EMIOS_0_CH_14_ISR_USED)
1085 Emios_Pwm_Ip_IrqHandler(0, 14);
1086 #endif
1087
1088 }
1089 else
1090 {
1091 /* Do nothing - in case of spurious interrupts, return immediately */
1092 }
1093 }
1094 #endif
1095
1096 #if (defined EMIOS_0_CH_15_ISR_USED)
1097 /* Check that an event occurred on Emios channel 15 */
1098 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[15].S) & (uint32)eMIOS_S_FLAG_MASK) )
1099 {
1100 /* Check that an event occurred on EMIOS channel 15 */
1101 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[15].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1102 {
1103 #if (defined GPT_EMIOS_0_CH_15_ISR_USED)
1104 Emios_Gpt_Ip_IrqHandler(0, 15);
1105 #endif
1106
1107 #if (defined ICU_EMIOS_0_CH_15_ISR_USED)
1108 Emios_Icu_Ip_IrqHandler(0, 15);
1109 #endif
1110
1111 #if (defined OCU_EMIOS_0_CH_15_ISR_USED)
1112 Emios_Ocu_Ip_IrqHandler(0, 15);
1113 #endif
1114
1115 #if (defined PWM_EMIOS_0_CH_15_ISR_USED)
1116 Emios_Pwm_Ip_IrqHandler(0, 15);
1117 #endif
1118
1119 }
1120 else
1121 {
1122 /* Do nothing - in case of spurious interrupts, return immediately */
1123 }
1124 }
1125 #endif
1126
1127 }
1128 #endif
1129 #if (\
1130 (defined GPT_EMIOS_0_CH_16_ISR_USED) ||\
1131 (defined GPT_EMIOS_0_CH_17_ISR_USED) ||\
1132 (defined GPT_EMIOS_0_CH_18_ISR_USED) ||\
1133 (defined GPT_EMIOS_0_CH_19_ISR_USED) ||\
1134 (defined ICU_EMIOS_0_CH_16_ISR_USED) ||\
1135 (defined ICU_EMIOS_0_CH_17_ISR_USED) ||\
1136 (defined ICU_EMIOS_0_CH_18_ISR_USED) ||\
1137 (defined ICU_EMIOS_0_CH_19_ISR_USED) ||\
1138 (defined OCU_EMIOS_0_CH_16_ISR_USED) ||\
1139 (defined OCU_EMIOS_0_CH_17_ISR_USED) ||\
1140 (defined OCU_EMIOS_0_CH_18_ISR_USED) ||\
1141 (defined OCU_EMIOS_0_CH_19_ISR_USED) ||\
1142 (defined PWM_EMIOS_0_CH_16_ISR_USED) ||\
1143 (defined PWM_EMIOS_0_CH_17_ISR_USED) ||\
1144 (defined PWM_EMIOS_0_CH_18_ISR_USED) ||\
1145 (defined PWM_EMIOS_0_CH_19_ISR_USED)\
1146 )
1147 /**
1148 * @brief Interrupt handler for Emios channels 16-19 for Emios instance 0
1149 * @details Process the interrupt of eMios channels 16-19
1150 *
1151 * @note This will be defined only if EMIOS channels 16, 17, 18, 19 are configured in GPT, ICU,
1152 * OCU or PWM mode.
1153 */
ISR(EMIOS0_1_IRQ)1154 ISR(EMIOS0_1_IRQ)
1155 {
1156 #if (defined EMIOS_0_CH_16_ISR_USED)
1157 /* Check that an event occurred on Emios channel 16 */
1158 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[16].S) & (uint32)eMIOS_S_FLAG_MASK) )
1159 {
1160 /* Check that an event occurred on EMIOS channel 16 */
1161 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[16].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1162 {
1163 #if (defined GPT_EMIOS_0_CH_16_ISR_USED)
1164 Emios_Gpt_Ip_IrqHandler(0, 16);
1165 #endif
1166
1167 #if (defined ICU_EMIOS_0_CH_16_ISR_USED)
1168 Emios_Icu_Ip_IrqHandler(0, 16);
1169 #endif
1170
1171 #if (defined OCU_EMIOS_0_CH_16_ISR_USED)
1172 Emios_Ocu_Ip_IrqHandler(0, 16);
1173 #endif
1174
1175 #if (defined PWM_EMIOS_0_CH_16_ISR_USED)
1176 Emios_Pwm_Ip_IrqHandler(0, 16);
1177 #endif
1178
1179 }
1180 else
1181 {
1182 /* Do nothing - in case of spurious interrupts, return immediately */
1183 }
1184 }
1185 #endif
1186
1187 #if (defined EMIOS_0_CH_17_ISR_USED)
1188 /* Check that an event occurred on Emios channel 17 */
1189 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[17].S) & (uint32)eMIOS_S_FLAG_MASK) )
1190 {
1191 /* Check that an event occurred on EMIOS channel 17 */
1192 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[17].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1193 {
1194 #if (defined GPT_EMIOS_0_CH_17_ISR_USED)
1195 Emios_Gpt_Ip_IrqHandler(0, 17);
1196 #endif
1197
1198 #if (defined ICU_EMIOS_0_CH_17_ISR_USED)
1199 Emios_Icu_Ip_IrqHandler(0, 17);
1200 #endif
1201
1202 #if (defined OCU_EMIOS_0_CH_17_ISR_USED)
1203 Emios_Ocu_Ip_IrqHandler(0, 17);
1204 #endif
1205
1206 #if (defined PWM_EMIOS_0_CH_17_ISR_USED)
1207 Emios_Pwm_Ip_IrqHandler(0, 17);
1208 #endif
1209
1210 }
1211 else
1212 {
1213 /* Do nothing - in case of spurious interrupts, return immediately */
1214 }
1215 }
1216 #endif
1217
1218 #if (defined EMIOS_0_CH_18_ISR_USED)
1219 /* Check that an event occurred on Emios channel 18 */
1220 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[18].S) & (uint32)eMIOS_S_FLAG_MASK) )
1221 {
1222 /* Check that an event occurred on EMIOS channel 18 */
1223 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[18].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1224 {
1225 #if (defined GPT_EMIOS_0_CH_18_ISR_USED)
1226 Emios_Gpt_Ip_IrqHandler(0, 18);
1227 #endif
1228
1229 #if (defined ICU_EMIOS_0_CH_18_ISR_USED)
1230 Emios_Icu_Ip_IrqHandler(0, 18);
1231 #endif
1232
1233 #if (defined OCU_EMIOS_0_CH_18_ISR_USED)
1234 Emios_Ocu_Ip_IrqHandler(0, 18);
1235 #endif
1236
1237 #if (defined PWM_EMIOS_0_CH_18_ISR_USED)
1238 Emios_Pwm_Ip_IrqHandler(0, 18);
1239 #endif
1240
1241 }
1242 else
1243 {
1244 /* Do nothing - in case of spurious interrupts, return immediately */
1245 }
1246 }
1247 #endif
1248
1249 #if (defined EMIOS_0_CH_19_ISR_USED)
1250 /* Check that an event occurred on Emios channel 19 */
1251 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[19].S) & (uint32)eMIOS_S_FLAG_MASK) )
1252 {
1253 /* Check that an event occurred on EMIOS channel 19 */
1254 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[19].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1255 {
1256 #if (defined GPT_EMIOS_0_CH_19_ISR_USED)
1257 Emios_Gpt_Ip_IrqHandler(0, 19);
1258 #endif
1259
1260 #if (defined ICU_EMIOS_0_CH_19_ISR_USED)
1261 Emios_Icu_Ip_IrqHandler(0, 19);
1262 #endif
1263
1264 #if (defined OCU_EMIOS_0_CH_19_ISR_USED)
1265 Emios_Ocu_Ip_IrqHandler(0, 19);
1266 #endif
1267
1268 #if (defined PWM_EMIOS_0_CH_19_ISR_USED)
1269 Emios_Pwm_Ip_IrqHandler(0, 19);
1270 #endif
1271
1272 }
1273 else
1274 {
1275 /* Do nothing - in case of spurious interrupts, return immediately */
1276 }
1277 }
1278 #endif
1279
1280 }
1281 #endif
1282 #if (\
1283 (defined GPT_EMIOS_0_CH_20_ISR_USED) ||\
1284 (defined GPT_EMIOS_0_CH_21_ISR_USED) ||\
1285 (defined GPT_EMIOS_0_CH_22_ISR_USED) ||\
1286 (defined GPT_EMIOS_0_CH_23_ISR_USED) ||\
1287 (defined ICU_EMIOS_0_CH_20_ISR_USED) ||\
1288 (defined ICU_EMIOS_0_CH_21_ISR_USED) ||\
1289 (defined ICU_EMIOS_0_CH_22_ISR_USED) ||\
1290 (defined ICU_EMIOS_0_CH_23_ISR_USED) ||\
1291 (defined OCU_EMIOS_0_CH_20_ISR_USED) ||\
1292 (defined OCU_EMIOS_0_CH_21_ISR_USED) ||\
1293 (defined OCU_EMIOS_0_CH_22_ISR_USED) ||\
1294 (defined OCU_EMIOS_0_CH_23_ISR_USED) ||\
1295 (defined PWM_EMIOS_0_CH_20_ISR_USED) ||\
1296 (defined PWM_EMIOS_0_CH_21_ISR_USED) ||\
1297 (defined PWM_EMIOS_0_CH_22_ISR_USED) ||\
1298 (defined PWM_EMIOS_0_CH_23_ISR_USED)\
1299 )
1300 /**
1301 * @brief Interrupt handler for Emios channels 20-23 for Emios instance 0
1302 * @details Process the interrupt of eMios channels 20-23
1303 *
1304 * @note This will be defined only if EMIOS channels 20, 21, 22, 23 are configured in GPT, ICU,
1305 * OCU or PWM mode.
1306 */
ISR(EMIOS0_0_IRQ)1307 ISR(EMIOS0_0_IRQ)
1308 {
1309 #if (defined EMIOS_0_CH_20_ISR_USED)
1310 /* Check that an event occurred on Emios channel 20 */
1311 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[20].S) & (uint32)eMIOS_S_FLAG_MASK) )
1312 {
1313 /* Check that an event occurred on EMIOS channel 20 */
1314 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[20].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1315 {
1316 #if (defined GPT_EMIOS_0_CH_20_ISR_USED)
1317 Emios_Gpt_Ip_IrqHandler(0, 20);
1318 #endif
1319
1320 #if (defined ICU_EMIOS_0_CH_20_ISR_USED)
1321 Emios_Icu_Ip_IrqHandler(0, 20);
1322 #endif
1323
1324 #if (defined OCU_EMIOS_0_CH_20_ISR_USED)
1325 Emios_Ocu_Ip_IrqHandler(0, 20);
1326 #endif
1327
1328 #if (defined PWM_EMIOS_0_CH_20_ISR_USED)
1329 Emios_Pwm_Ip_IrqHandler(0, 20);
1330 #endif
1331
1332 }
1333 else
1334 {
1335 /* Do nothing - in case of spurious interrupts, return immediately */
1336 }
1337 }
1338 #endif
1339
1340 #if (defined EMIOS_0_CH_21_ISR_USED)
1341 /* Check that an event occurred on Emios channel 21 */
1342 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[21].S) & (uint32)eMIOS_S_FLAG_MASK) )
1343 {
1344 /* Check that an event occurred on EMIOS channel 21 */
1345 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[21].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1346 {
1347 #if (defined GPT_EMIOS_0_CH_21_ISR_USED)
1348 Emios_Gpt_Ip_IrqHandler(0, 21);
1349 #endif
1350
1351 #if (defined ICU_EMIOS_0_CH_21_ISR_USED)
1352 Emios_Icu_Ip_IrqHandler(0, 21);
1353 #endif
1354
1355 #if (defined OCU_EMIOS_0_CH_21_ISR_USED)
1356 Emios_Ocu_Ip_IrqHandler(0, 21);
1357 #endif
1358
1359 #if (defined PWM_EMIOS_0_CH_21_ISR_USED)
1360 Emios_Pwm_Ip_IrqHandler(0, 21);
1361 #endif
1362
1363 }
1364 else
1365 {
1366 /* Do nothing - in case of spurious interrupts, return immediately */
1367 }
1368 }
1369 #endif
1370
1371 #if (defined EMIOS_0_CH_22_ISR_USED)
1372 /* Check that an event occurred on Emios channel 22 */
1373 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[22].S) & (uint32)eMIOS_S_FLAG_MASK) )
1374 {
1375 /* Check that an event occurred on EMIOS channel 22 */
1376 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[22].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1377 {
1378 #if (defined GPT_EMIOS_0_CH_22_ISR_USED)
1379 Emios_Gpt_Ip_IrqHandler(0, 22);
1380 #endif
1381
1382 #if (defined ICU_EMIOS_0_CH_22_ISR_USED)
1383 Emios_Icu_Ip_IrqHandler(0, 22);
1384 #endif
1385
1386 #if (defined OCU_EMIOS_0_CH_22_ISR_USED)
1387 Emios_Ocu_Ip_IrqHandler(0, 22);
1388 #endif
1389
1390 #if (defined PWM_EMIOS_0_CH_22_ISR_USED)
1391 Emios_Pwm_Ip_IrqHandler(0, 22);
1392 #endif
1393
1394 }
1395 else
1396 {
1397 /* Do nothing - in case of spurious interrupts, return immediately */
1398 }
1399 }
1400 #endif
1401
1402 #if (defined EMIOS_0_CH_23_ISR_USED)
1403 /* Check that an event occurred on Emios channel 23 */
1404 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[23].S) & (uint32)eMIOS_S_FLAG_MASK) )
1405 {
1406 /* Check that an event occurred on EMIOS channel 23 */
1407 if ( 0U != ((Emios_Ip_paxBase[0]->CH.UC[23].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1408 {
1409 #if (defined GPT_EMIOS_0_CH_23_ISR_USED)
1410 Emios_Gpt_Ip_IrqHandler(0, 23);
1411 #endif
1412
1413 #if (defined ICU_EMIOS_0_CH_23_ISR_USED)
1414 Emios_Icu_Ip_IrqHandler(0, 23);
1415 #endif
1416
1417 #if (defined OCU_EMIOS_0_CH_23_ISR_USED)
1418 Emios_Ocu_Ip_IrqHandler(0, 23);
1419 #endif
1420
1421 #if (defined PWM_EMIOS_0_CH_23_ISR_USED)
1422 Emios_Pwm_Ip_IrqHandler(0, 23);
1423 #endif
1424
1425 }
1426 else
1427 {
1428 /* Do nothing - in case of spurious interrupts, return immediately */
1429 }
1430 }
1431 #endif
1432
1433 }
1434 #endif
1435
1436 #if (\
1437 (defined GPT_EMIOS_1_CH_0_ISR_USED) ||\
1438 (defined GPT_EMIOS_1_CH_1_ISR_USED) ||\
1439 (defined GPT_EMIOS_1_CH_2_ISR_USED) ||\
1440 (defined GPT_EMIOS_1_CH_3_ISR_USED) ||\
1441 (defined ICU_EMIOS_1_CH_0_ISR_USED) ||\
1442 (defined ICU_EMIOS_1_CH_1_ISR_USED) ||\
1443 (defined ICU_EMIOS_1_CH_2_ISR_USED) ||\
1444 (defined ICU_EMIOS_1_CH_3_ISR_USED) ||\
1445 (defined OCU_EMIOS_1_CH_0_ISR_USED) ||\
1446 (defined OCU_EMIOS_1_CH_1_ISR_USED) ||\
1447 (defined OCU_EMIOS_1_CH_2_ISR_USED) ||\
1448 (defined OCU_EMIOS_1_CH_3_ISR_USED) ||\
1449 (defined PWM_EMIOS_1_CH_0_ISR_USED) ||\
1450 (defined PWM_EMIOS_1_CH_1_ISR_USED) ||\
1451 (defined PWM_EMIOS_1_CH_2_ISR_USED) ||\
1452 (defined PWM_EMIOS_1_CH_3_ISR_USED)\
1453 )
1454 /**
1455 * @brief Interrupt handler for Emios channels 0-3 for Emios instance 1
1456 * @details Process the interrupt of eMios channels 0-3
1457 *
1458 * @note This will be defined only if EMIOS channels 0, 1, 2, 3 are configured in GPT, ICU,
1459 * OCU or PWM mode.
1460 */
ISR(EMIOS1_5_IRQ)1461 ISR(EMIOS1_5_IRQ)
1462 {
1463 #if (defined EMIOS_1_CH_0_ISR_USED)
1464 /* Check that an event occurred on Emios channel 0 */
1465 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[0].S) & (uint32)eMIOS_S_FLAG_MASK) )
1466 {
1467 /* Check that an event occurred on EMIOS channel 0 */
1468 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[0].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1469 {
1470 #if (defined GPT_EMIOS_1_CH_0_ISR_USED)
1471 Emios_Gpt_Ip_IrqHandler(1, 0);
1472 #endif
1473
1474 #if (defined ICU_EMIOS_1_CH_0_ISR_USED)
1475 Emios_Icu_Ip_IrqHandler(1, 0);
1476 #endif
1477
1478 #if (defined OCU_EMIOS_1_CH_0_ISR_USED)
1479 Emios_Ocu_Ip_IrqHandler(1, 0);
1480 #endif
1481
1482 #if (defined PWM_EMIOS_1_CH_0_ISR_USED)
1483 Emios_Pwm_Ip_IrqHandler(1, 0);
1484 #endif
1485
1486 }
1487 else
1488 {
1489 /* Do nothing - in case of spurious interrupts, return immediately */
1490 }
1491 }
1492 #endif
1493
1494 #if (defined EMIOS_1_CH_1_ISR_USED)
1495 /* Check that an event occurred on Emios channel 1 */
1496 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[1].S) & (uint32)eMIOS_S_FLAG_MASK) )
1497 {
1498 /* Check that an event occurred on EMIOS channel 1 */
1499 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[1].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1500 {
1501 #if (defined GPT_EMIOS_1_CH_1_ISR_USED)
1502 Emios_Gpt_Ip_IrqHandler(1, 1);
1503 #endif
1504
1505 #if (defined ICU_EMIOS_1_CH_1_ISR_USED)
1506 Emios_Icu_Ip_IrqHandler(1, 1);
1507 #endif
1508
1509 #if (defined OCU_EMIOS_1_CH_1_ISR_USED)
1510 Emios_Ocu_Ip_IrqHandler(1, 1);
1511 #endif
1512
1513 #if (defined PWM_EMIOS_1_CH_1_ISR_USED)
1514 Emios_Pwm_Ip_IrqHandler(1, 1);
1515 #endif
1516
1517 }
1518 else
1519 {
1520 /* Do nothing - in case of spurious interrupts, return immediately */
1521 }
1522 }
1523 #endif
1524
1525 #if (defined EMIOS_1_CH_2_ISR_USED)
1526 /* Check that an event occurred on Emios channel 2 */
1527 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[2].S) & (uint32)eMIOS_S_FLAG_MASK) )
1528 {
1529 /* Check that an event occurred on EMIOS channel 2 */
1530 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[2].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1531 {
1532 #if (defined GPT_EMIOS_1_CH_2_ISR_USED)
1533 Emios_Gpt_Ip_IrqHandler(1, 2);
1534 #endif
1535
1536 #if (defined ICU_EMIOS_1_CH_2_ISR_USED)
1537 Emios_Icu_Ip_IrqHandler(1, 2);
1538 #endif
1539
1540 #if (defined OCU_EMIOS_1_CH_2_ISR_USED)
1541 Emios_Ocu_Ip_IrqHandler(1, 2);
1542 #endif
1543
1544 #if (defined PWM_EMIOS_1_CH_2_ISR_USED)
1545 Emios_Pwm_Ip_IrqHandler(1, 2);
1546 #endif
1547
1548 }
1549 else
1550 {
1551 /* Do nothing - in case of spurious interrupts, return immediately */
1552 }
1553 }
1554 #endif
1555
1556 #if (defined EMIOS_1_CH_3_ISR_USED)
1557 /* Check that an event occurred on Emios channel 3 */
1558 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[3].S) & (uint32)eMIOS_S_FLAG_MASK) )
1559 {
1560 /* Check that an event occurred on EMIOS channel 3 */
1561 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[3].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1562 {
1563 #if (defined GPT_EMIOS_1_CH_3_ISR_USED)
1564 Emios_Gpt_Ip_IrqHandler(1, 3);
1565 #endif
1566
1567 #if (defined ICU_EMIOS_1_CH_3_ISR_USED)
1568 Emios_Icu_Ip_IrqHandler(1, 3);
1569 #endif
1570
1571 #if (defined OCU_EMIOS_1_CH_3_ISR_USED)
1572 Emios_Ocu_Ip_IrqHandler(1, 3);
1573 #endif
1574
1575 #if (defined PWM_EMIOS_1_CH_3_ISR_USED)
1576 Emios_Pwm_Ip_IrqHandler(1, 3);
1577 #endif
1578
1579 }
1580 else
1581 {
1582 /* Do nothing - in case of spurious interrupts, return immediately */
1583 }
1584 }
1585 #endif
1586
1587 }
1588 #endif
1589 #if (\
1590 (defined GPT_EMIOS_1_CH_4_ISR_USED) ||\
1591 (defined GPT_EMIOS_1_CH_5_ISR_USED) ||\
1592 (defined GPT_EMIOS_1_CH_6_ISR_USED) ||\
1593 (defined GPT_EMIOS_1_CH_7_ISR_USED) ||\
1594 (defined ICU_EMIOS_1_CH_4_ISR_USED) ||\
1595 (defined ICU_EMIOS_1_CH_5_ISR_USED) ||\
1596 (defined ICU_EMIOS_1_CH_6_ISR_USED) ||\
1597 (defined ICU_EMIOS_1_CH_7_ISR_USED) ||\
1598 (defined OCU_EMIOS_1_CH_4_ISR_USED) ||\
1599 (defined OCU_EMIOS_1_CH_5_ISR_USED) ||\
1600 (defined OCU_EMIOS_1_CH_6_ISR_USED) ||\
1601 (defined OCU_EMIOS_1_CH_7_ISR_USED) ||\
1602 (defined PWM_EMIOS_1_CH_4_ISR_USED) ||\
1603 (defined PWM_EMIOS_1_CH_5_ISR_USED) ||\
1604 (defined PWM_EMIOS_1_CH_6_ISR_USED) ||\
1605 (defined PWM_EMIOS_1_CH_7_ISR_USED)\
1606 )
1607 /**
1608 * @brief Interrupt handler for Emios channels 4-7 for Emios instance 1
1609 * @details Process the interrupt of eMios channels 4-7
1610 *
1611 * @note This will be defined only if EMIOS channels 4, 5, 6, 7 are configured in GPT, ICU,
1612 * OCU or PWM mode.
1613 */
ISR(EMIOS1_4_IRQ)1614 ISR(EMIOS1_4_IRQ)
1615 {
1616 #if (defined EMIOS_1_CH_4_ISR_USED)
1617 /* Check that an event occurred on Emios channel 4 */
1618 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[4].S) & (uint32)eMIOS_S_FLAG_MASK) )
1619 {
1620 /* Check that an event occurred on EMIOS channel 4 */
1621 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[4].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1622 {
1623 #if (defined GPT_EMIOS_1_CH_4_ISR_USED)
1624 Emios_Gpt_Ip_IrqHandler(1, 4);
1625 #endif
1626
1627 #if (defined ICU_EMIOS_1_CH_4_ISR_USED)
1628 Emios_Icu_Ip_IrqHandler(1, 4);
1629 #endif
1630
1631 #if (defined OCU_EMIOS_1_CH_4_ISR_USED)
1632 Emios_Ocu_Ip_IrqHandler(1, 4);
1633 #endif
1634
1635 #if (defined PWM_EMIOS_1_CH_4_ISR_USED)
1636 Emios_Pwm_Ip_IrqHandler(1, 4);
1637 #endif
1638
1639 }
1640 else
1641 {
1642 /* Do nothing - in case of spurious interrupts, return immediately */
1643 }
1644 }
1645 #endif
1646
1647 #if (defined EMIOS_1_CH_5_ISR_USED)
1648 /* Check that an event occurred on Emios channel 5 */
1649 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[5].S) & (uint32)eMIOS_S_FLAG_MASK) )
1650 {
1651 /* Check that an event occurred on EMIOS channel 5 */
1652 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[5].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1653 {
1654 #if (defined GPT_EMIOS_1_CH_5_ISR_USED)
1655 Emios_Gpt_Ip_IrqHandler(1, 5);
1656 #endif
1657
1658 #if (defined ICU_EMIOS_1_CH_5_ISR_USED)
1659 Emios_Icu_Ip_IrqHandler(1, 5);
1660 #endif
1661
1662 #if (defined OCU_EMIOS_1_CH_5_ISR_USED)
1663 Emios_Ocu_Ip_IrqHandler(1, 5);
1664 #endif
1665
1666 #if (defined PWM_EMIOS_1_CH_5_ISR_USED)
1667 Emios_Pwm_Ip_IrqHandler(1, 5);
1668 #endif
1669
1670 }
1671 else
1672 {
1673 /* Do nothing - in case of spurious interrupts, return immediately */
1674 }
1675 }
1676 #endif
1677
1678 #if (defined EMIOS_1_CH_6_ISR_USED)
1679 /* Check that an event occurred on Emios channel 6 */
1680 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[6].S) & (uint32)eMIOS_S_FLAG_MASK) )
1681 {
1682 /* Check that an event occurred on EMIOS channel 6 */
1683 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[6].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1684 {
1685 #if (defined GPT_EMIOS_1_CH_6_ISR_USED)
1686 Emios_Gpt_Ip_IrqHandler(1, 6);
1687 #endif
1688
1689 #if (defined ICU_EMIOS_1_CH_6_ISR_USED)
1690 Emios_Icu_Ip_IrqHandler(1, 6);
1691 #endif
1692
1693 #if (defined OCU_EMIOS_1_CH_6_ISR_USED)
1694 Emios_Ocu_Ip_IrqHandler(1, 6);
1695 #endif
1696
1697 #if (defined PWM_EMIOS_1_CH_6_ISR_USED)
1698 Emios_Pwm_Ip_IrqHandler(1, 6);
1699 #endif
1700
1701 }
1702 else
1703 {
1704 /* Do nothing - in case of spurious interrupts, return immediately */
1705 }
1706 }
1707 #endif
1708
1709 #if (defined EMIOS_1_CH_7_ISR_USED)
1710 /* Check that an event occurred on Emios channel 7 */
1711 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[7].S) & (uint32)eMIOS_S_FLAG_MASK) )
1712 {
1713 /* Check that an event occurred on EMIOS channel 7 */
1714 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[7].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1715 {
1716 #if (defined GPT_EMIOS_1_CH_7_ISR_USED)
1717 Emios_Gpt_Ip_IrqHandler(1, 7);
1718 #endif
1719
1720 #if (defined ICU_EMIOS_1_CH_7_ISR_USED)
1721 Emios_Icu_Ip_IrqHandler(1, 7);
1722 #endif
1723
1724 #if (defined OCU_EMIOS_1_CH_7_ISR_USED)
1725 Emios_Ocu_Ip_IrqHandler(1, 7);
1726 #endif
1727
1728 #if (defined PWM_EMIOS_1_CH_7_ISR_USED)
1729 Emios_Pwm_Ip_IrqHandler(1, 7);
1730 #endif
1731
1732 }
1733 else
1734 {
1735 /* Do nothing - in case of spurious interrupts, return immediately */
1736 }
1737 }
1738 #endif
1739
1740 }
1741 #endif
1742 #if (\
1743 (defined GPT_EMIOS_1_CH_8_ISR_USED) ||\
1744 (defined GPT_EMIOS_1_CH_9_ISR_USED) ||\
1745 (defined GPT_EMIOS_1_CH_10_ISR_USED) ||\
1746 (defined GPT_EMIOS_1_CH_11_ISR_USED) ||\
1747 (defined ICU_EMIOS_1_CH_8_ISR_USED) ||\
1748 (defined ICU_EMIOS_1_CH_9_ISR_USED) ||\
1749 (defined ICU_EMIOS_1_CH_10_ISR_USED) ||\
1750 (defined ICU_EMIOS_1_CH_11_ISR_USED) ||\
1751 (defined OCU_EMIOS_1_CH_8_ISR_USED) ||\
1752 (defined OCU_EMIOS_1_CH_9_ISR_USED) ||\
1753 (defined OCU_EMIOS_1_CH_10_ISR_USED) ||\
1754 (defined OCU_EMIOS_1_CH_11_ISR_USED) ||\
1755 (defined PWM_EMIOS_1_CH_8_ISR_USED) ||\
1756 (defined PWM_EMIOS_1_CH_9_ISR_USED) ||\
1757 (defined PWM_EMIOS_1_CH_10_ISR_USED) ||\
1758 (defined PWM_EMIOS_1_CH_11_ISR_USED)\
1759 )
1760 /**
1761 * @brief Interrupt handler for Emios channels 8-11 for Emios instance 1
1762 * @details Process the interrupt of eMios channels 8-11
1763 *
1764 * @note This will be defined only if EMIOS channels 8, 9, 10, 11 are configured in GPT, ICU,
1765 * OCU or PWM mode.
1766 */
ISR(EMIOS1_3_IRQ)1767 ISR(EMIOS1_3_IRQ)
1768 {
1769 #if (defined EMIOS_1_CH_8_ISR_USED)
1770 /* Check that an event occurred on Emios channel 8 */
1771 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[8].S) & (uint32)eMIOS_S_FLAG_MASK) )
1772 {
1773 /* Check that an event occurred on EMIOS channel 8 */
1774 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[8].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1775 {
1776 #if (defined GPT_EMIOS_1_CH_8_ISR_USED)
1777 Emios_Gpt_Ip_IrqHandler(1, 8);
1778 #endif
1779
1780 #if (defined ICU_EMIOS_1_CH_8_ISR_USED)
1781 Emios_Icu_Ip_IrqHandler(1, 8);
1782 #endif
1783
1784 #if (defined OCU_EMIOS_1_CH_8_ISR_USED)
1785 Emios_Ocu_Ip_IrqHandler(1, 8);
1786 #endif
1787
1788 #if (defined PWM_EMIOS_1_CH_8_ISR_USED)
1789 Emios_Pwm_Ip_IrqHandler(1, 8);
1790 #endif
1791
1792 }
1793 else
1794 {
1795 /* Do nothing - in case of spurious interrupts, return immediately */
1796 }
1797 }
1798 #endif
1799
1800 #if (defined EMIOS_1_CH_9_ISR_USED)
1801 /* Check that an event occurred on Emios channel 9 */
1802 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[9].S) & (uint32)eMIOS_S_FLAG_MASK) )
1803 {
1804 /* Check that an event occurred on EMIOS channel 9 */
1805 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[9].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1806 {
1807 #if (defined GPT_EMIOS_1_CH_9_ISR_USED)
1808 Emios_Gpt_Ip_IrqHandler(1, 9);
1809 #endif
1810
1811 #if (defined ICU_EMIOS_1_CH_9_ISR_USED)
1812 Emios_Icu_Ip_IrqHandler(1, 9);
1813 #endif
1814
1815 #if (defined OCU_EMIOS_1_CH_9_ISR_USED)
1816 Emios_Ocu_Ip_IrqHandler(1, 9);
1817 #endif
1818
1819 #if (defined PWM_EMIOS_1_CH_9_ISR_USED)
1820 Emios_Pwm_Ip_IrqHandler(1, 9);
1821 #endif
1822
1823 }
1824 else
1825 {
1826 /* Do nothing - in case of spurious interrupts, return immediately */
1827 }
1828 }
1829 #endif
1830
1831 #if (defined EMIOS_1_CH_10_ISR_USED)
1832 /* Check that an event occurred on Emios channel 10 */
1833 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[10].S) & (uint32)eMIOS_S_FLAG_MASK) )
1834 {
1835 /* Check that an event occurred on EMIOS channel 10 */
1836 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[10].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1837 {
1838 #if (defined GPT_EMIOS_1_CH_10_ISR_USED)
1839 Emios_Gpt_Ip_IrqHandler(1, 10);
1840 #endif
1841
1842 #if (defined ICU_EMIOS_1_CH_10_ISR_USED)
1843 Emios_Icu_Ip_IrqHandler(1, 10);
1844 #endif
1845
1846 #if (defined OCU_EMIOS_1_CH_10_ISR_USED)
1847 Emios_Ocu_Ip_IrqHandler(1, 10);
1848 #endif
1849
1850 #if (defined PWM_EMIOS_1_CH_10_ISR_USED)
1851 Emios_Pwm_Ip_IrqHandler(1, 10);
1852 #endif
1853
1854 }
1855 else
1856 {
1857 /* Do nothing - in case of spurious interrupts, return immediately */
1858 }
1859 }
1860 #endif
1861
1862 #if (defined EMIOS_1_CH_11_ISR_USED)
1863 /* Check that an event occurred on Emios channel 11 */
1864 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[11].S) & (uint32)eMIOS_S_FLAG_MASK) )
1865 {
1866 /* Check that an event occurred on EMIOS channel 11 */
1867 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[11].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1868 {
1869 #if (defined GPT_EMIOS_1_CH_11_ISR_USED)
1870 Emios_Gpt_Ip_IrqHandler(1, 11);
1871 #endif
1872
1873 #if (defined ICU_EMIOS_1_CH_11_ISR_USED)
1874 Emios_Icu_Ip_IrqHandler(1, 11);
1875 #endif
1876
1877 #if (defined OCU_EMIOS_1_CH_11_ISR_USED)
1878 Emios_Ocu_Ip_IrqHandler(1, 11);
1879 #endif
1880
1881 #if (defined PWM_EMIOS_1_CH_11_ISR_USED)
1882 Emios_Pwm_Ip_IrqHandler(1, 11);
1883 #endif
1884
1885 }
1886 else
1887 {
1888 /* Do nothing - in case of spurious interrupts, return immediately */
1889 }
1890 }
1891 #endif
1892
1893 }
1894 #endif
1895 #if (\
1896 (defined GPT_EMIOS_1_CH_12_ISR_USED) ||\
1897 (defined GPT_EMIOS_1_CH_13_ISR_USED) ||\
1898 (defined GPT_EMIOS_1_CH_14_ISR_USED) ||\
1899 (defined GPT_EMIOS_1_CH_15_ISR_USED) ||\
1900 (defined ICU_EMIOS_1_CH_12_ISR_USED) ||\
1901 (defined ICU_EMIOS_1_CH_13_ISR_USED) ||\
1902 (defined ICU_EMIOS_1_CH_14_ISR_USED) ||\
1903 (defined ICU_EMIOS_1_CH_15_ISR_USED) ||\
1904 (defined OCU_EMIOS_1_CH_12_ISR_USED) ||\
1905 (defined OCU_EMIOS_1_CH_13_ISR_USED) ||\
1906 (defined OCU_EMIOS_1_CH_14_ISR_USED) ||\
1907 (defined OCU_EMIOS_1_CH_15_ISR_USED) ||\
1908 (defined PWM_EMIOS_1_CH_12_ISR_USED) ||\
1909 (defined PWM_EMIOS_1_CH_13_ISR_USED) ||\
1910 (defined PWM_EMIOS_1_CH_14_ISR_USED) ||\
1911 (defined PWM_EMIOS_1_CH_15_ISR_USED)\
1912 )
1913 /**
1914 * @brief Interrupt handler for Emios channels 12-15 for Emios instance 1
1915 * @details Process the interrupt of eMios channels 12-15
1916 *
1917 * @note This will be defined only if EMIOS channels 12, 13, 14, 15 are configured in GPT, ICU,
1918 * OCU or PWM mode.
1919 */
ISR(EMIOS1_2_IRQ)1920 ISR(EMIOS1_2_IRQ)
1921 {
1922 #if (defined EMIOS_1_CH_12_ISR_USED)
1923 /* Check that an event occurred on Emios channel 12 */
1924 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[12].S) & (uint32)eMIOS_S_FLAG_MASK) )
1925 {
1926 /* Check that an event occurred on EMIOS channel 12 */
1927 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[12].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1928 {
1929 #if (defined GPT_EMIOS_1_CH_12_ISR_USED)
1930 Emios_Gpt_Ip_IrqHandler(1, 12);
1931 #endif
1932
1933 #if (defined ICU_EMIOS_1_CH_12_ISR_USED)
1934 Emios_Icu_Ip_IrqHandler(1, 12);
1935 #endif
1936
1937 #if (defined OCU_EMIOS_1_CH_12_ISR_USED)
1938 Emios_Ocu_Ip_IrqHandler(1, 12);
1939 #endif
1940
1941 #if (defined PWM_EMIOS_1_CH_12_ISR_USED)
1942 Emios_Pwm_Ip_IrqHandler(1, 12);
1943 #endif
1944
1945 }
1946 else
1947 {
1948 /* Do nothing - in case of spurious interrupts, return immediately */
1949 }
1950 }
1951 #endif
1952
1953 #if (defined EMIOS_1_CH_13_ISR_USED)
1954 /* Check that an event occurred on Emios channel 13 */
1955 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[13].S) & (uint32)eMIOS_S_FLAG_MASK) )
1956 {
1957 /* Check that an event occurred on EMIOS channel 13 */
1958 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[13].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1959 {
1960 #if (defined GPT_EMIOS_1_CH_13_ISR_USED)
1961 Emios_Gpt_Ip_IrqHandler(1, 13);
1962 #endif
1963
1964 #if (defined ICU_EMIOS_1_CH_13_ISR_USED)
1965 Emios_Icu_Ip_IrqHandler(1, 13);
1966 #endif
1967
1968 #if (defined OCU_EMIOS_1_CH_13_ISR_USED)
1969 Emios_Ocu_Ip_IrqHandler(1, 13);
1970 #endif
1971
1972 #if (defined PWM_EMIOS_1_CH_13_ISR_USED)
1973 Emios_Pwm_Ip_IrqHandler(1, 13);
1974 #endif
1975
1976 }
1977 else
1978 {
1979 /* Do nothing - in case of spurious interrupts, return immediately */
1980 }
1981 }
1982 #endif
1983
1984 #if (defined EMIOS_1_CH_14_ISR_USED)
1985 /* Check that an event occurred on Emios channel 14 */
1986 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[14].S) & (uint32)eMIOS_S_FLAG_MASK) )
1987 {
1988 /* Check that an event occurred on EMIOS channel 14 */
1989 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[14].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
1990 {
1991 #if (defined GPT_EMIOS_1_CH_14_ISR_USED)
1992 Emios_Gpt_Ip_IrqHandler(1, 14);
1993 #endif
1994
1995 #if (defined ICU_EMIOS_1_CH_14_ISR_USED)
1996 Emios_Icu_Ip_IrqHandler(1, 14);
1997 #endif
1998
1999 #if (defined OCU_EMIOS_1_CH_14_ISR_USED)
2000 Emios_Ocu_Ip_IrqHandler(1, 14);
2001 #endif
2002
2003 #if (defined PWM_EMIOS_1_CH_14_ISR_USED)
2004 Emios_Pwm_Ip_IrqHandler(1, 14);
2005 #endif
2006
2007 }
2008 else
2009 {
2010 /* Do nothing - in case of spurious interrupts, return immediately */
2011 }
2012 }
2013 #endif
2014
2015 #if (defined EMIOS_1_CH_15_ISR_USED)
2016 /* Check that an event occurred on Emios channel 15 */
2017 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[15].S) & (uint32)eMIOS_S_FLAG_MASK) )
2018 {
2019 /* Check that an event occurred on EMIOS channel 15 */
2020 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[15].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2021 {
2022 #if (defined GPT_EMIOS_1_CH_15_ISR_USED)
2023 Emios_Gpt_Ip_IrqHandler(1, 15);
2024 #endif
2025
2026 #if (defined ICU_EMIOS_1_CH_15_ISR_USED)
2027 Emios_Icu_Ip_IrqHandler(1, 15);
2028 #endif
2029
2030 #if (defined OCU_EMIOS_1_CH_15_ISR_USED)
2031 Emios_Ocu_Ip_IrqHandler(1, 15);
2032 #endif
2033
2034 #if (defined PWM_EMIOS_1_CH_15_ISR_USED)
2035 Emios_Pwm_Ip_IrqHandler(1, 15);
2036 #endif
2037
2038 }
2039 else
2040 {
2041 /* Do nothing - in case of spurious interrupts, return immediately */
2042 }
2043 }
2044 #endif
2045
2046 }
2047 #endif
2048 #if (\
2049 (defined GPT_EMIOS_1_CH_16_ISR_USED) ||\
2050 (defined GPT_EMIOS_1_CH_17_ISR_USED) ||\
2051 (defined GPT_EMIOS_1_CH_18_ISR_USED) ||\
2052 (defined GPT_EMIOS_1_CH_19_ISR_USED) ||\
2053 (defined ICU_EMIOS_1_CH_16_ISR_USED) ||\
2054 (defined ICU_EMIOS_1_CH_17_ISR_USED) ||\
2055 (defined ICU_EMIOS_1_CH_18_ISR_USED) ||\
2056 (defined ICU_EMIOS_1_CH_19_ISR_USED) ||\
2057 (defined OCU_EMIOS_1_CH_16_ISR_USED) ||\
2058 (defined OCU_EMIOS_1_CH_17_ISR_USED) ||\
2059 (defined OCU_EMIOS_1_CH_18_ISR_USED) ||\
2060 (defined OCU_EMIOS_1_CH_19_ISR_USED) ||\
2061 (defined PWM_EMIOS_1_CH_16_ISR_USED) ||\
2062 (defined PWM_EMIOS_1_CH_17_ISR_USED) ||\
2063 (defined PWM_EMIOS_1_CH_18_ISR_USED) ||\
2064 (defined PWM_EMIOS_1_CH_19_ISR_USED)\
2065 )
2066 /**
2067 * @brief Interrupt handler for Emios channels 16-19 for Emios instance 1
2068 * @details Process the interrupt of eMios channels 16-19
2069 *
2070 * @note This will be defined only if EMIOS channels 16, 17, 18, 19 are configured in GPT, ICU,
2071 * OCU or PWM mode.
2072 */
ISR(EMIOS1_1_IRQ)2073 ISR(EMIOS1_1_IRQ)
2074 {
2075 #if (defined EMIOS_1_CH_16_ISR_USED)
2076 /* Check that an event occurred on Emios channel 16 */
2077 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[16].S) & (uint32)eMIOS_S_FLAG_MASK) )
2078 {
2079 /* Check that an event occurred on EMIOS channel 16 */
2080 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[16].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2081 {
2082 #if (defined GPT_EMIOS_1_CH_16_ISR_USED)
2083 Emios_Gpt_Ip_IrqHandler(1, 16);
2084 #endif
2085
2086 #if (defined ICU_EMIOS_1_CH_16_ISR_USED)
2087 Emios_Icu_Ip_IrqHandler(1, 16);
2088 #endif
2089
2090 #if (defined OCU_EMIOS_1_CH_16_ISR_USED)
2091 Emios_Ocu_Ip_IrqHandler(1, 16);
2092 #endif
2093
2094 #if (defined PWM_EMIOS_1_CH_16_ISR_USED)
2095 Emios_Pwm_Ip_IrqHandler(1, 16);
2096 #endif
2097
2098 }
2099 else
2100 {
2101 /* Do nothing - in case of spurious interrupts, return immediately */
2102 }
2103 }
2104 #endif
2105
2106 #if (defined EMIOS_1_CH_17_ISR_USED)
2107 /* Check that an event occurred on Emios channel 17 */
2108 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[17].S) & (uint32)eMIOS_S_FLAG_MASK) )
2109 {
2110 /* Check that an event occurred on EMIOS channel 17 */
2111 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[17].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2112 {
2113 #if (defined GPT_EMIOS_1_CH_17_ISR_USED)
2114 Emios_Gpt_Ip_IrqHandler(1, 17);
2115 #endif
2116
2117 #if (defined ICU_EMIOS_1_CH_17_ISR_USED)
2118 Emios_Icu_Ip_IrqHandler(1, 17);
2119 #endif
2120
2121 #if (defined OCU_EMIOS_1_CH_17_ISR_USED)
2122 Emios_Ocu_Ip_IrqHandler(1, 17);
2123 #endif
2124
2125 #if (defined PWM_EMIOS_1_CH_17_ISR_USED)
2126 Emios_Pwm_Ip_IrqHandler(1, 17);
2127 #endif
2128
2129 }
2130 else
2131 {
2132 /* Do nothing - in case of spurious interrupts, return immediately */
2133 }
2134 }
2135 #endif
2136
2137 #if (defined EMIOS_1_CH_18_ISR_USED)
2138 /* Check that an event occurred on Emios channel 18 */
2139 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[18].S) & (uint32)eMIOS_S_FLAG_MASK) )
2140 {
2141 /* Check that an event occurred on EMIOS channel 18 */
2142 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[18].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2143 {
2144 #if (defined GPT_EMIOS_1_CH_18_ISR_USED)
2145 Emios_Gpt_Ip_IrqHandler(1, 18);
2146 #endif
2147
2148 #if (defined ICU_EMIOS_1_CH_18_ISR_USED)
2149 Emios_Icu_Ip_IrqHandler(1, 18);
2150 #endif
2151
2152 #if (defined OCU_EMIOS_1_CH_18_ISR_USED)
2153 Emios_Ocu_Ip_IrqHandler(1, 18);
2154 #endif
2155
2156 #if (defined PWM_EMIOS_1_CH_18_ISR_USED)
2157 Emios_Pwm_Ip_IrqHandler(1, 18);
2158 #endif
2159
2160 }
2161 else
2162 {
2163 /* Do nothing - in case of spurious interrupts, return immediately */
2164 }
2165 }
2166 #endif
2167
2168 #if (defined EMIOS_1_CH_19_ISR_USED)
2169 /* Check that an event occurred on Emios channel 19 */
2170 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[19].S) & (uint32)eMIOS_S_FLAG_MASK) )
2171 {
2172 /* Check that an event occurred on EMIOS channel 19 */
2173 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[19].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2174 {
2175 #if (defined GPT_EMIOS_1_CH_19_ISR_USED)
2176 Emios_Gpt_Ip_IrqHandler(1, 19);
2177 #endif
2178
2179 #if (defined ICU_EMIOS_1_CH_19_ISR_USED)
2180 Emios_Icu_Ip_IrqHandler(1, 19);
2181 #endif
2182
2183 #if (defined OCU_EMIOS_1_CH_19_ISR_USED)
2184 Emios_Ocu_Ip_IrqHandler(1, 19);
2185 #endif
2186
2187 #if (defined PWM_EMIOS_1_CH_19_ISR_USED)
2188 Emios_Pwm_Ip_IrqHandler(1, 19);
2189 #endif
2190
2191 }
2192 else
2193 {
2194 /* Do nothing - in case of spurious interrupts, return immediately */
2195 }
2196 }
2197 #endif
2198
2199 }
2200 #endif
2201 #if (\
2202 (defined GPT_EMIOS_1_CH_20_ISR_USED) ||\
2203 (defined GPT_EMIOS_1_CH_21_ISR_USED) ||\
2204 (defined GPT_EMIOS_1_CH_22_ISR_USED) ||\
2205 (defined GPT_EMIOS_1_CH_23_ISR_USED) ||\
2206 (defined ICU_EMIOS_1_CH_20_ISR_USED) ||\
2207 (defined ICU_EMIOS_1_CH_21_ISR_USED) ||\
2208 (defined ICU_EMIOS_1_CH_22_ISR_USED) ||\
2209 (defined ICU_EMIOS_1_CH_23_ISR_USED) ||\
2210 (defined OCU_EMIOS_1_CH_20_ISR_USED) ||\
2211 (defined OCU_EMIOS_1_CH_21_ISR_USED) ||\
2212 (defined OCU_EMIOS_1_CH_22_ISR_USED) ||\
2213 (defined OCU_EMIOS_1_CH_23_ISR_USED) ||\
2214 (defined PWM_EMIOS_1_CH_20_ISR_USED) ||\
2215 (defined PWM_EMIOS_1_CH_21_ISR_USED) ||\
2216 (defined PWM_EMIOS_1_CH_22_ISR_USED) ||\
2217 (defined PWM_EMIOS_1_CH_23_ISR_USED)\
2218 )
2219 /**
2220 * @brief Interrupt handler for Emios channels 20-23 for Emios instance 1
2221 * @details Process the interrupt of eMios channels 20-23
2222 *
2223 * @note This will be defined only if EMIOS channels 20, 21, 22, 23 are configured in GPT, ICU,
2224 * OCU or PWM mode.
2225 */
ISR(EMIOS1_0_IRQ)2226 ISR(EMIOS1_0_IRQ)
2227 {
2228 #if (defined EMIOS_1_CH_20_ISR_USED)
2229 /* Check that an event occurred on Emios channel 20 */
2230 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[20].S) & (uint32)eMIOS_S_FLAG_MASK) )
2231 {
2232 /* Check that an event occurred on EMIOS channel 20 */
2233 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[20].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2234 {
2235 #if (defined GPT_EMIOS_1_CH_20_ISR_USED)
2236 Emios_Gpt_Ip_IrqHandler(1, 20);
2237 #endif
2238
2239 #if (defined ICU_EMIOS_1_CH_20_ISR_USED)
2240 Emios_Icu_Ip_IrqHandler(1, 20);
2241 #endif
2242
2243 #if (defined OCU_EMIOS_1_CH_20_ISR_USED)
2244 Emios_Ocu_Ip_IrqHandler(1, 20);
2245 #endif
2246
2247 #if (defined PWM_EMIOS_1_CH_20_ISR_USED)
2248 Emios_Pwm_Ip_IrqHandler(1, 20);
2249 #endif
2250
2251 }
2252 else
2253 {
2254 /* Do nothing - in case of spurious interrupts, return immediately */
2255 }
2256 }
2257 #endif
2258
2259 #if (defined EMIOS_1_CH_21_ISR_USED)
2260 /* Check that an event occurred on Emios channel 21 */
2261 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[21].S) & (uint32)eMIOS_S_FLAG_MASK) )
2262 {
2263 /* Check that an event occurred on EMIOS channel 21 */
2264 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[21].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2265 {
2266 #if (defined GPT_EMIOS_1_CH_21_ISR_USED)
2267 Emios_Gpt_Ip_IrqHandler(1, 21);
2268 #endif
2269
2270 #if (defined ICU_EMIOS_1_CH_21_ISR_USED)
2271 Emios_Icu_Ip_IrqHandler(1, 21);
2272 #endif
2273
2274 #if (defined OCU_EMIOS_1_CH_21_ISR_USED)
2275 Emios_Ocu_Ip_IrqHandler(1, 21);
2276 #endif
2277
2278 #if (defined PWM_EMIOS_1_CH_21_ISR_USED)
2279 Emios_Pwm_Ip_IrqHandler(1, 21);
2280 #endif
2281
2282 }
2283 else
2284 {
2285 /* Do nothing - in case of spurious interrupts, return immediately */
2286 }
2287 }
2288 #endif
2289
2290 #if (defined EMIOS_1_CH_22_ISR_USED)
2291 /* Check that an event occurred on Emios channel 22 */
2292 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[22].S) & (uint32)eMIOS_S_FLAG_MASK) )
2293 {
2294 /* Check that an event occurred on EMIOS channel 22 */
2295 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[22].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2296 {
2297 #if (defined GPT_EMIOS_1_CH_22_ISR_USED)
2298 Emios_Gpt_Ip_IrqHandler(1, 22);
2299 #endif
2300
2301 #if (defined ICU_EMIOS_1_CH_22_ISR_USED)
2302 Emios_Icu_Ip_IrqHandler(1, 22);
2303 #endif
2304
2305 #if (defined OCU_EMIOS_1_CH_22_ISR_USED)
2306 Emios_Ocu_Ip_IrqHandler(1, 22);
2307 #endif
2308
2309 #if (defined PWM_EMIOS_1_CH_22_ISR_USED)
2310 Emios_Pwm_Ip_IrqHandler(1, 22);
2311 #endif
2312
2313 }
2314 else
2315 {
2316 /* Do nothing - in case of spurious interrupts, return immediately */
2317 }
2318 }
2319 #endif
2320
2321 #if (defined EMIOS_1_CH_23_ISR_USED)
2322 /* Check that an event occurred on Emios channel 23 */
2323 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[23].S) & (uint32)eMIOS_S_FLAG_MASK) )
2324 {
2325 /* Check that an event occurred on EMIOS channel 23 */
2326 if ( 0U != ((Emios_Ip_paxBase[1]->CH.UC[23].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2327 {
2328 #if (defined GPT_EMIOS_1_CH_23_ISR_USED)
2329 Emios_Gpt_Ip_IrqHandler(1, 23);
2330 #endif
2331
2332 #if (defined ICU_EMIOS_1_CH_23_ISR_USED)
2333 Emios_Icu_Ip_IrqHandler(1, 23);
2334 #endif
2335
2336 #if (defined OCU_EMIOS_1_CH_23_ISR_USED)
2337 Emios_Ocu_Ip_IrqHandler(1, 23);
2338 #endif
2339
2340 #if (defined PWM_EMIOS_1_CH_23_ISR_USED)
2341 Emios_Pwm_Ip_IrqHandler(1, 23);
2342 #endif
2343
2344 }
2345 else
2346 {
2347 /* Do nothing - in case of spurious interrupts, return immediately */
2348 }
2349 }
2350 #endif
2351
2352 }
2353 #endif
2354
2355 #if (\
2356 (defined GPT_EMIOS_2_CH_0_ISR_USED) ||\
2357 (defined GPT_EMIOS_2_CH_1_ISR_USED) ||\
2358 (defined GPT_EMIOS_2_CH_2_ISR_USED) ||\
2359 (defined GPT_EMIOS_2_CH_3_ISR_USED) ||\
2360 (defined ICU_EMIOS_2_CH_0_ISR_USED) ||\
2361 (defined ICU_EMIOS_2_CH_1_ISR_USED) ||\
2362 (defined ICU_EMIOS_2_CH_2_ISR_USED) ||\
2363 (defined ICU_EMIOS_2_CH_3_ISR_USED) ||\
2364 (defined OCU_EMIOS_2_CH_0_ISR_USED) ||\
2365 (defined OCU_EMIOS_2_CH_1_ISR_USED) ||\
2366 (defined OCU_EMIOS_2_CH_2_ISR_USED) ||\
2367 (defined OCU_EMIOS_2_CH_3_ISR_USED) ||\
2368 (defined PWM_EMIOS_2_CH_0_ISR_USED) ||\
2369 (defined PWM_EMIOS_2_CH_1_ISR_USED) ||\
2370 (defined PWM_EMIOS_2_CH_2_ISR_USED) ||\
2371 (defined PWM_EMIOS_2_CH_3_ISR_USED)\
2372 )
2373 /**
2374 * @brief Interrupt handler for Emios channels 0-3 for Emios instance 2
2375 * @details Process the interrupt of eMios channels 0-3
2376 *
2377 * @note This will be defined only if EMIOS channels 0, 1, 2, 3 are configured in GPT, ICU,
2378 * OCU or PWM mode.
2379 */
ISR(EMIOS2_5_IRQ)2380 ISR(EMIOS2_5_IRQ)
2381 {
2382 #if (defined EMIOS_2_CH_0_ISR_USED)
2383 /* Check that an event occurred on Emios channel 0 */
2384 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[0].S) & (uint32)eMIOS_S_FLAG_MASK) )
2385 {
2386 /* Check that an event occurred on EMIOS channel 0 */
2387 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[0].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2388 {
2389 #if (defined GPT_EMIOS_2_CH_0_ISR_USED)
2390 Emios_Gpt_Ip_IrqHandler(2, 0);
2391 #endif
2392
2393 #if (defined ICU_EMIOS_2_CH_0_ISR_USED)
2394 Emios_Icu_Ip_IrqHandler(2, 0);
2395 #endif
2396
2397 #if (defined OCU_EMIOS_2_CH_0_ISR_USED)
2398 Emios_Ocu_Ip_IrqHandler(2, 0);
2399 #endif
2400
2401 #if (defined PWM_EMIOS_2_CH_0_ISR_USED)
2402 Emios_Pwm_Ip_IrqHandler(2, 0);
2403 #endif
2404
2405 }
2406 else
2407 {
2408 /* Do nothing - in case of spurious interrupts, return immediately */
2409 }
2410 }
2411 #endif
2412
2413 #if (defined EMIOS_2_CH_1_ISR_USED)
2414 /* Check that an event occurred on Emios channel 1 */
2415 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[1].S) & (uint32)eMIOS_S_FLAG_MASK) )
2416 {
2417 /* Check that an event occurred on EMIOS channel 1 */
2418 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[1].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2419 {
2420 #if (defined GPT_EMIOS_2_CH_1_ISR_USED)
2421 Emios_Gpt_Ip_IrqHandler(2, 1);
2422 #endif
2423
2424 #if (defined ICU_EMIOS_2_CH_1_ISR_USED)
2425 Emios_Icu_Ip_IrqHandler(2, 1);
2426 #endif
2427
2428 #if (defined OCU_EMIOS_2_CH_1_ISR_USED)
2429 Emios_Ocu_Ip_IrqHandler(2, 1);
2430 #endif
2431
2432 #if (defined PWM_EMIOS_2_CH_1_ISR_USED)
2433 Emios_Pwm_Ip_IrqHandler(2, 1);
2434 #endif
2435
2436 }
2437 else
2438 {
2439 /* Do nothing - in case of spurious interrupts, return immediately */
2440 }
2441 }
2442 #endif
2443
2444 #if (defined EMIOS_2_CH_2_ISR_USED)
2445 /* Check that an event occurred on Emios channel 2 */
2446 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[2].S) & (uint32)eMIOS_S_FLAG_MASK) )
2447 {
2448 /* Check that an event occurred on EMIOS channel 2 */
2449 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[2].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2450 {
2451 #if (defined GPT_EMIOS_2_CH_2_ISR_USED)
2452 Emios_Gpt_Ip_IrqHandler(2, 2);
2453 #endif
2454
2455 #if (defined ICU_EMIOS_2_CH_2_ISR_USED)
2456 Emios_Icu_Ip_IrqHandler(2, 2);
2457 #endif
2458
2459 #if (defined OCU_EMIOS_2_CH_2_ISR_USED)
2460 Emios_Ocu_Ip_IrqHandler(2, 2);
2461 #endif
2462
2463 #if (defined PWM_EMIOS_2_CH_2_ISR_USED)
2464 Emios_Pwm_Ip_IrqHandler(2, 2);
2465 #endif
2466
2467 }
2468 else
2469 {
2470 /* Do nothing - in case of spurious interrupts, return immediately */
2471 }
2472 }
2473 #endif
2474
2475 #if (defined EMIOS_2_CH_3_ISR_USED)
2476 /* Check that an event occurred on Emios channel 3 */
2477 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[3].S) & (uint32)eMIOS_S_FLAG_MASK) )
2478 {
2479 /* Check that an event occurred on EMIOS channel 3 */
2480 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[3].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2481 {
2482 #if (defined GPT_EMIOS_2_CH_3_ISR_USED)
2483 Emios_Gpt_Ip_IrqHandler(2, 3);
2484 #endif
2485
2486 #if (defined ICU_EMIOS_2_CH_3_ISR_USED)
2487 Emios_Icu_Ip_IrqHandler(2, 3);
2488 #endif
2489
2490 #if (defined OCU_EMIOS_2_CH_3_ISR_USED)
2491 Emios_Ocu_Ip_IrqHandler(2, 3);
2492 #endif
2493
2494 #if (defined PWM_EMIOS_2_CH_3_ISR_USED)
2495 Emios_Pwm_Ip_IrqHandler(2, 3);
2496 #endif
2497
2498 }
2499 else
2500 {
2501 /* Do nothing - in case of spurious interrupts, return immediately */
2502 }
2503 }
2504 #endif
2505
2506 }
2507 #endif
2508 #if (\
2509 (defined GPT_EMIOS_2_CH_4_ISR_USED) ||\
2510 (defined GPT_EMIOS_2_CH_5_ISR_USED) ||\
2511 (defined GPT_EMIOS_2_CH_6_ISR_USED) ||\
2512 (defined GPT_EMIOS_2_CH_7_ISR_USED) ||\
2513 (defined ICU_EMIOS_2_CH_4_ISR_USED) ||\
2514 (defined ICU_EMIOS_2_CH_5_ISR_USED) ||\
2515 (defined ICU_EMIOS_2_CH_6_ISR_USED) ||\
2516 (defined ICU_EMIOS_2_CH_7_ISR_USED) ||\
2517 (defined OCU_EMIOS_2_CH_4_ISR_USED) ||\
2518 (defined OCU_EMIOS_2_CH_5_ISR_USED) ||\
2519 (defined OCU_EMIOS_2_CH_6_ISR_USED) ||\
2520 (defined OCU_EMIOS_2_CH_7_ISR_USED) ||\
2521 (defined PWM_EMIOS_2_CH_4_ISR_USED) ||\
2522 (defined PWM_EMIOS_2_CH_5_ISR_USED) ||\
2523 (defined PWM_EMIOS_2_CH_6_ISR_USED) ||\
2524 (defined PWM_EMIOS_2_CH_7_ISR_USED)\
2525 )
2526 /**
2527 * @brief Interrupt handler for Emios channels 4-7 for Emios instance 2
2528 * @details Process the interrupt of eMios channels 4-7
2529 *
2530 * @note This will be defined only if EMIOS channels 4, 5, 6, 7 are configured in GPT, ICU,
2531 * OCU or PWM mode.
2532 */
ISR(EMIOS2_4_IRQ)2533 ISR(EMIOS2_4_IRQ)
2534 {
2535 #if (defined EMIOS_2_CH_4_ISR_USED)
2536 /* Check that an event occurred on Emios channel 4 */
2537 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[4].S) & (uint32)eMIOS_S_FLAG_MASK) )
2538 {
2539 /* Check that an event occurred on EMIOS channel 4 */
2540 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[4].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2541 {
2542 #if (defined GPT_EMIOS_2_CH_4_ISR_USED)
2543 Emios_Gpt_Ip_IrqHandler(2, 4);
2544 #endif
2545
2546 #if (defined ICU_EMIOS_2_CH_4_ISR_USED)
2547 Emios_Icu_Ip_IrqHandler(2, 4);
2548 #endif
2549
2550 #if (defined OCU_EMIOS_2_CH_4_ISR_USED)
2551 Emios_Ocu_Ip_IrqHandler(2, 4);
2552 #endif
2553
2554 #if (defined PWM_EMIOS_2_CH_4_ISR_USED)
2555 Emios_Pwm_Ip_IrqHandler(2, 4);
2556 #endif
2557
2558 }
2559 else
2560 {
2561 /* Do nothing - in case of spurious interrupts, return immediately */
2562 }
2563 }
2564 #endif
2565
2566 #if (defined EMIOS_2_CH_5_ISR_USED)
2567 /* Check that an event occurred on Emios channel 5 */
2568 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[5].S) & (uint32)eMIOS_S_FLAG_MASK) )
2569 {
2570 /* Check that an event occurred on EMIOS channel 5 */
2571 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[5].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2572 {
2573 #if (defined GPT_EMIOS_2_CH_5_ISR_USED)
2574 Emios_Gpt_Ip_IrqHandler(2, 5);
2575 #endif
2576
2577 #if (defined ICU_EMIOS_2_CH_5_ISR_USED)
2578 Emios_Icu_Ip_IrqHandler(2, 5);
2579 #endif
2580
2581 #if (defined OCU_EMIOS_2_CH_5_ISR_USED)
2582 Emios_Ocu_Ip_IrqHandler(2, 5);
2583 #endif
2584
2585 #if (defined PWM_EMIOS_2_CH_5_ISR_USED)
2586 Emios_Pwm_Ip_IrqHandler(2, 5);
2587 #endif
2588
2589 }
2590 else
2591 {
2592 /* Do nothing - in case of spurious interrupts, return immediately */
2593 }
2594 }
2595 #endif
2596
2597 #if (defined EMIOS_2_CH_6_ISR_USED)
2598 /* Check that an event occurred on Emios channel 6 */
2599 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[6].S) & (uint32)eMIOS_S_FLAG_MASK) )
2600 {
2601 /* Check that an event occurred on EMIOS channel 6 */
2602 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[6].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2603 {
2604 #if (defined GPT_EMIOS_2_CH_6_ISR_USED)
2605 Emios_Gpt_Ip_IrqHandler(2, 6);
2606 #endif
2607
2608 #if (defined ICU_EMIOS_2_CH_6_ISR_USED)
2609 Emios_Icu_Ip_IrqHandler(2, 6);
2610 #endif
2611
2612 #if (defined OCU_EMIOS_2_CH_6_ISR_USED)
2613 Emios_Ocu_Ip_IrqHandler(2, 6);
2614 #endif
2615
2616 #if (defined PWM_EMIOS_2_CH_6_ISR_USED)
2617 Emios_Pwm_Ip_IrqHandler(2, 6);
2618 #endif
2619
2620 }
2621 else
2622 {
2623 /* Do nothing - in case of spurious interrupts, return immediately */
2624 }
2625 }
2626 #endif
2627
2628 #if (defined EMIOS_2_CH_7_ISR_USED)
2629 /* Check that an event occurred on Emios channel 7 */
2630 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[7].S) & (uint32)eMIOS_S_FLAG_MASK) )
2631 {
2632 /* Check that an event occurred on EMIOS channel 7 */
2633 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[7].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2634 {
2635 #if (defined GPT_EMIOS_2_CH_7_ISR_USED)
2636 Emios_Gpt_Ip_IrqHandler(2, 7);
2637 #endif
2638
2639 #if (defined ICU_EMIOS_2_CH_7_ISR_USED)
2640 Emios_Icu_Ip_IrqHandler(2, 7);
2641 #endif
2642
2643 #if (defined OCU_EMIOS_2_CH_7_ISR_USED)
2644 Emios_Ocu_Ip_IrqHandler(2, 7);
2645 #endif
2646
2647 #if (defined PWM_EMIOS_2_CH_7_ISR_USED)
2648 Emios_Pwm_Ip_IrqHandler(2, 7);
2649 #endif
2650
2651 }
2652 else
2653 {
2654 /* Do nothing - in case of spurious interrupts, return immediately */
2655 }
2656 }
2657 #endif
2658
2659 }
2660 #endif
2661 #if (\
2662 (defined GPT_EMIOS_2_CH_8_ISR_USED) ||\
2663 (defined GPT_EMIOS_2_CH_9_ISR_USED) ||\
2664 (defined GPT_EMIOS_2_CH_10_ISR_USED) ||\
2665 (defined GPT_EMIOS_2_CH_11_ISR_USED) ||\
2666 (defined ICU_EMIOS_2_CH_8_ISR_USED) ||\
2667 (defined ICU_EMIOS_2_CH_9_ISR_USED) ||\
2668 (defined ICU_EMIOS_2_CH_10_ISR_USED) ||\
2669 (defined ICU_EMIOS_2_CH_11_ISR_USED) ||\
2670 (defined OCU_EMIOS_2_CH_8_ISR_USED) ||\
2671 (defined OCU_EMIOS_2_CH_9_ISR_USED) ||\
2672 (defined OCU_EMIOS_2_CH_10_ISR_USED) ||\
2673 (defined OCU_EMIOS_2_CH_11_ISR_USED) ||\
2674 (defined PWM_EMIOS_2_CH_8_ISR_USED) ||\
2675 (defined PWM_EMIOS_2_CH_9_ISR_USED) ||\
2676 (defined PWM_EMIOS_2_CH_10_ISR_USED) ||\
2677 (defined PWM_EMIOS_2_CH_11_ISR_USED)\
2678 )
2679 /**
2680 * @brief Interrupt handler for Emios channels 8-11 for Emios instance 2
2681 * @details Process the interrupt of eMios channels 8-11
2682 *
2683 * @note This will be defined only if EMIOS channels 8, 9, 10, 11 are configured in GPT, ICU,
2684 * OCU or PWM mode.
2685 */
ISR(EMIOS2_3_IRQ)2686 ISR(EMIOS2_3_IRQ)
2687 {
2688 #if (defined EMIOS_2_CH_8_ISR_USED)
2689 /* Check that an event occurred on Emios channel 8 */
2690 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[8].S) & (uint32)eMIOS_S_FLAG_MASK) )
2691 {
2692 /* Check that an event occurred on EMIOS channel 8 */
2693 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[8].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2694 {
2695 #if (defined GPT_EMIOS_2_CH_8_ISR_USED)
2696 Emios_Gpt_Ip_IrqHandler(2, 8);
2697 #endif
2698
2699 #if (defined ICU_EMIOS_2_CH_8_ISR_USED)
2700 Emios_Icu_Ip_IrqHandler(2, 8);
2701 #endif
2702
2703 #if (defined OCU_EMIOS_2_CH_8_ISR_USED)
2704 Emios_Ocu_Ip_IrqHandler(2, 8);
2705 #endif
2706
2707 #if (defined PWM_EMIOS_2_CH_8_ISR_USED)
2708 Emios_Pwm_Ip_IrqHandler(2, 8);
2709 #endif
2710
2711 }
2712 else
2713 {
2714 /* Do nothing - in case of spurious interrupts, return immediately */
2715 }
2716 }
2717 #endif
2718
2719 #if (defined EMIOS_2_CH_9_ISR_USED)
2720 /* Check that an event occurred on Emios channel 9 */
2721 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[9].S) & (uint32)eMIOS_S_FLAG_MASK) )
2722 {
2723 /* Check that an event occurred on EMIOS channel 9 */
2724 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[9].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2725 {
2726 #if (defined GPT_EMIOS_2_CH_9_ISR_USED)
2727 Emios_Gpt_Ip_IrqHandler(2, 9);
2728 #endif
2729
2730 #if (defined ICU_EMIOS_2_CH_9_ISR_USED)
2731 Emios_Icu_Ip_IrqHandler(2, 9);
2732 #endif
2733
2734 #if (defined OCU_EMIOS_2_CH_9_ISR_USED)
2735 Emios_Ocu_Ip_IrqHandler(2, 9);
2736 #endif
2737
2738 #if (defined PWM_EMIOS_2_CH_9_ISR_USED)
2739 Emios_Pwm_Ip_IrqHandler(2, 9);
2740 #endif
2741
2742 }
2743 else
2744 {
2745 /* Do nothing - in case of spurious interrupts, return immediately */
2746 }
2747 }
2748 #endif
2749
2750 #if (defined EMIOS_2_CH_10_ISR_USED)
2751 /* Check that an event occurred on Emios channel 10 */
2752 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[10].S) & (uint32)eMIOS_S_FLAG_MASK) )
2753 {
2754 /* Check that an event occurred on EMIOS channel 10 */
2755 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[10].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2756 {
2757 #if (defined GPT_EMIOS_2_CH_10_ISR_USED)
2758 Emios_Gpt_Ip_IrqHandler(2, 10);
2759 #endif
2760
2761 #if (defined ICU_EMIOS_2_CH_10_ISR_USED)
2762 Emios_Icu_Ip_IrqHandler(2, 10);
2763 #endif
2764
2765 #if (defined OCU_EMIOS_2_CH_10_ISR_USED)
2766 Emios_Ocu_Ip_IrqHandler(2, 10);
2767 #endif
2768
2769 #if (defined PWM_EMIOS_2_CH_10_ISR_USED)
2770 Emios_Pwm_Ip_IrqHandler(2, 10);
2771 #endif
2772
2773 }
2774 else
2775 {
2776 /* Do nothing - in case of spurious interrupts, return immediately */
2777 }
2778 }
2779 #endif
2780
2781 #if (defined EMIOS_2_CH_11_ISR_USED)
2782 /* Check that an event occurred on Emios channel 11 */
2783 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[11].S) & (uint32)eMIOS_S_FLAG_MASK) )
2784 {
2785 /* Check that an event occurred on EMIOS channel 11 */
2786 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[11].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2787 {
2788 #if (defined GPT_EMIOS_2_CH_11_ISR_USED)
2789 Emios_Gpt_Ip_IrqHandler(2, 11);
2790 #endif
2791
2792 #if (defined ICU_EMIOS_2_CH_11_ISR_USED)
2793 Emios_Icu_Ip_IrqHandler(2, 11);
2794 #endif
2795
2796 #if (defined OCU_EMIOS_2_CH_11_ISR_USED)
2797 Emios_Ocu_Ip_IrqHandler(2, 11);
2798 #endif
2799
2800 #if (defined PWM_EMIOS_2_CH_11_ISR_USED)
2801 Emios_Pwm_Ip_IrqHandler(2, 11);
2802 #endif
2803
2804 }
2805 else
2806 {
2807 /* Do nothing - in case of spurious interrupts, return immediately */
2808 }
2809 }
2810 #endif
2811
2812 }
2813 #endif
2814 #if (\
2815 (defined GPT_EMIOS_2_CH_12_ISR_USED) ||\
2816 (defined GPT_EMIOS_2_CH_13_ISR_USED) ||\
2817 (defined GPT_EMIOS_2_CH_14_ISR_USED) ||\
2818 (defined GPT_EMIOS_2_CH_15_ISR_USED) ||\
2819 (defined ICU_EMIOS_2_CH_12_ISR_USED) ||\
2820 (defined ICU_EMIOS_2_CH_13_ISR_USED) ||\
2821 (defined ICU_EMIOS_2_CH_14_ISR_USED) ||\
2822 (defined ICU_EMIOS_2_CH_15_ISR_USED) ||\
2823 (defined OCU_EMIOS_2_CH_12_ISR_USED) ||\
2824 (defined OCU_EMIOS_2_CH_13_ISR_USED) ||\
2825 (defined OCU_EMIOS_2_CH_14_ISR_USED) ||\
2826 (defined OCU_EMIOS_2_CH_15_ISR_USED) ||\
2827 (defined PWM_EMIOS_2_CH_12_ISR_USED) ||\
2828 (defined PWM_EMIOS_2_CH_13_ISR_USED) ||\
2829 (defined PWM_EMIOS_2_CH_14_ISR_USED) ||\
2830 (defined PWM_EMIOS_2_CH_15_ISR_USED)\
2831 )
2832 /**
2833 * @brief Interrupt handler for Emios channels 12-15 for Emios instance 2
2834 * @details Process the interrupt of eMios channels 12-15
2835 *
2836 * @note This will be defined only if EMIOS channels 12, 13, 14, 15 are configured in GPT, ICU,
2837 * OCU or PWM mode.
2838 */
ISR(EMIOS2_2_IRQ)2839 ISR(EMIOS2_2_IRQ)
2840 {
2841 #if (defined EMIOS_2_CH_12_ISR_USED)
2842 /* Check that an event occurred on Emios channel 12 */
2843 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[12].S) & (uint32)eMIOS_S_FLAG_MASK) )
2844 {
2845 /* Check that an event occurred on EMIOS channel 12 */
2846 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[12].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2847 {
2848 #if (defined GPT_EMIOS_2_CH_12_ISR_USED)
2849 Emios_Gpt_Ip_IrqHandler(2, 12);
2850 #endif
2851
2852 #if (defined ICU_EMIOS_2_CH_12_ISR_USED)
2853 Emios_Icu_Ip_IrqHandler(2, 12);
2854 #endif
2855
2856 #if (defined OCU_EMIOS_2_CH_12_ISR_USED)
2857 Emios_Ocu_Ip_IrqHandler(2, 12);
2858 #endif
2859
2860 #if (defined PWM_EMIOS_2_CH_12_ISR_USED)
2861 Emios_Pwm_Ip_IrqHandler(2, 12);
2862 #endif
2863
2864 }
2865 else
2866 {
2867 /* Do nothing - in case of spurious interrupts, return immediately */
2868 }
2869 }
2870 #endif
2871
2872 #if (defined EMIOS_2_CH_13_ISR_USED)
2873 /* Check that an event occurred on Emios channel 13 */
2874 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[13].S) & (uint32)eMIOS_S_FLAG_MASK) )
2875 {
2876 /* Check that an event occurred on EMIOS channel 13 */
2877 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[13].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2878 {
2879 #if (defined GPT_EMIOS_2_CH_13_ISR_USED)
2880 Emios_Gpt_Ip_IrqHandler(2, 13);
2881 #endif
2882
2883 #if (defined ICU_EMIOS_2_CH_13_ISR_USED)
2884 Emios_Icu_Ip_IrqHandler(2, 13);
2885 #endif
2886
2887 #if (defined OCU_EMIOS_2_CH_13_ISR_USED)
2888 Emios_Ocu_Ip_IrqHandler(2, 13);
2889 #endif
2890
2891 #if (defined PWM_EMIOS_2_CH_13_ISR_USED)
2892 Emios_Pwm_Ip_IrqHandler(2, 13);
2893 #endif
2894
2895 }
2896 else
2897 {
2898 /* Do nothing - in case of spurious interrupts, return immediately */
2899 }
2900 }
2901 #endif
2902
2903 #if (defined EMIOS_2_CH_14_ISR_USED)
2904 /* Check that an event occurred on Emios channel 14 */
2905 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[14].S) & (uint32)eMIOS_S_FLAG_MASK) )
2906 {
2907 /* Check that an event occurred on EMIOS channel 14 */
2908 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[14].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2909 {
2910 #if (defined GPT_EMIOS_2_CH_14_ISR_USED)
2911 Emios_Gpt_Ip_IrqHandler(2, 14);
2912 #endif
2913
2914 #if (defined ICU_EMIOS_2_CH_14_ISR_USED)
2915 Emios_Icu_Ip_IrqHandler(2, 14);
2916 #endif
2917
2918 #if (defined OCU_EMIOS_2_CH_14_ISR_USED)
2919 Emios_Ocu_Ip_IrqHandler(2, 14);
2920 #endif
2921
2922 #if (defined PWM_EMIOS_2_CH_14_ISR_USED)
2923 Emios_Pwm_Ip_IrqHandler(2, 14);
2924 #endif
2925
2926 }
2927 else
2928 {
2929 /* Do nothing - in case of spurious interrupts, return immediately */
2930 }
2931 }
2932 #endif
2933
2934 #if (defined EMIOS_2_CH_15_ISR_USED)
2935 /* Check that an event occurred on Emios channel 15 */
2936 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[15].S) & (uint32)eMIOS_S_FLAG_MASK) )
2937 {
2938 /* Check that an event occurred on EMIOS channel 15 */
2939 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[15].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
2940 {
2941 #if (defined GPT_EMIOS_2_CH_15_ISR_USED)
2942 Emios_Gpt_Ip_IrqHandler(2, 15);
2943 #endif
2944
2945 #if (defined ICU_EMIOS_2_CH_15_ISR_USED)
2946 Emios_Icu_Ip_IrqHandler(2, 15);
2947 #endif
2948
2949 #if (defined OCU_EMIOS_2_CH_15_ISR_USED)
2950 Emios_Ocu_Ip_IrqHandler(2, 15);
2951 #endif
2952
2953 #if (defined PWM_EMIOS_2_CH_15_ISR_USED)
2954 Emios_Pwm_Ip_IrqHandler(2, 15);
2955 #endif
2956
2957 }
2958 else
2959 {
2960 /* Do nothing - in case of spurious interrupts, return immediately */
2961 }
2962 }
2963 #endif
2964
2965 }
2966 #endif
2967 #if (\
2968 (defined GPT_EMIOS_2_CH_16_ISR_USED) ||\
2969 (defined GPT_EMIOS_2_CH_17_ISR_USED) ||\
2970 (defined GPT_EMIOS_2_CH_18_ISR_USED) ||\
2971 (defined GPT_EMIOS_2_CH_19_ISR_USED) ||\
2972 (defined ICU_EMIOS_2_CH_16_ISR_USED) ||\
2973 (defined ICU_EMIOS_2_CH_17_ISR_USED) ||\
2974 (defined ICU_EMIOS_2_CH_18_ISR_USED) ||\
2975 (defined ICU_EMIOS_2_CH_19_ISR_USED) ||\
2976 (defined OCU_EMIOS_2_CH_16_ISR_USED) ||\
2977 (defined OCU_EMIOS_2_CH_17_ISR_USED) ||\
2978 (defined OCU_EMIOS_2_CH_18_ISR_USED) ||\
2979 (defined OCU_EMIOS_2_CH_19_ISR_USED) ||\
2980 (defined PWM_EMIOS_2_CH_16_ISR_USED) ||\
2981 (defined PWM_EMIOS_2_CH_17_ISR_USED) ||\
2982 (defined PWM_EMIOS_2_CH_18_ISR_USED) ||\
2983 (defined PWM_EMIOS_2_CH_19_ISR_USED)\
2984 )
2985 /**
2986 * @brief Interrupt handler for Emios channels 16-19 for Emios instance 2
2987 * @details Process the interrupt of eMios channels 16-19
2988 *
2989 * @note This will be defined only if EMIOS channels 16, 17, 18, 19 are configured in GPT, ICU,
2990 * OCU or PWM mode.
2991 */
ISR(EMIOS2_1_IRQ)2992 ISR(EMIOS2_1_IRQ)
2993 {
2994 #if (defined EMIOS_2_CH_16_ISR_USED)
2995 /* Check that an event occurred on Emios channel 16 */
2996 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[16].S) & (uint32)eMIOS_S_FLAG_MASK) )
2997 {
2998 /* Check that an event occurred on EMIOS channel 16 */
2999 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[16].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
3000 {
3001 #if (defined GPT_EMIOS_2_CH_16_ISR_USED)
3002 Emios_Gpt_Ip_IrqHandler(2, 16);
3003 #endif
3004
3005 #if (defined ICU_EMIOS_2_CH_16_ISR_USED)
3006 Emios_Icu_Ip_IrqHandler(2, 16);
3007 #endif
3008
3009 #if (defined OCU_EMIOS_2_CH_16_ISR_USED)
3010 Emios_Ocu_Ip_IrqHandler(2, 16);
3011 #endif
3012
3013 #if (defined PWM_EMIOS_2_CH_16_ISR_USED)
3014 Emios_Pwm_Ip_IrqHandler(2, 16);
3015 #endif
3016
3017 }
3018 else
3019 {
3020 /* Do nothing - in case of spurious interrupts, return immediately */
3021 }
3022 }
3023 #endif
3024
3025 #if (defined EMIOS_2_CH_17_ISR_USED)
3026 /* Check that an event occurred on Emios channel 17 */
3027 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[17].S) & (uint32)eMIOS_S_FLAG_MASK) )
3028 {
3029 /* Check that an event occurred on EMIOS channel 17 */
3030 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[17].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
3031 {
3032 #if (defined GPT_EMIOS_2_CH_17_ISR_USED)
3033 Emios_Gpt_Ip_IrqHandler(2, 17);
3034 #endif
3035
3036 #if (defined ICU_EMIOS_2_CH_17_ISR_USED)
3037 Emios_Icu_Ip_IrqHandler(2, 17);
3038 #endif
3039
3040 #if (defined OCU_EMIOS_2_CH_17_ISR_USED)
3041 Emios_Ocu_Ip_IrqHandler(2, 17);
3042 #endif
3043
3044 #if (defined PWM_EMIOS_2_CH_17_ISR_USED)
3045 Emios_Pwm_Ip_IrqHandler(2, 17);
3046 #endif
3047
3048 }
3049 else
3050 {
3051 /* Do nothing - in case of spurious interrupts, return immediately */
3052 }
3053 }
3054 #endif
3055
3056 #if (defined EMIOS_2_CH_18_ISR_USED)
3057 /* Check that an event occurred on Emios channel 18 */
3058 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[18].S) & (uint32)eMIOS_S_FLAG_MASK) )
3059 {
3060 /* Check that an event occurred on EMIOS channel 18 */
3061 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[18].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
3062 {
3063 #if (defined GPT_EMIOS_2_CH_18_ISR_USED)
3064 Emios_Gpt_Ip_IrqHandler(2, 18);
3065 #endif
3066
3067 #if (defined ICU_EMIOS_2_CH_18_ISR_USED)
3068 Emios_Icu_Ip_IrqHandler(2, 18);
3069 #endif
3070
3071 #if (defined OCU_EMIOS_2_CH_18_ISR_USED)
3072 Emios_Ocu_Ip_IrqHandler(2, 18);
3073 #endif
3074
3075 #if (defined PWM_EMIOS_2_CH_18_ISR_USED)
3076 Emios_Pwm_Ip_IrqHandler(2, 18);
3077 #endif
3078
3079 }
3080 else
3081 {
3082 /* Do nothing - in case of spurious interrupts, return immediately */
3083 }
3084 }
3085 #endif
3086
3087 #if (defined EMIOS_2_CH_19_ISR_USED)
3088 /* Check that an event occurred on Emios channel 19 */
3089 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[19].S) & (uint32)eMIOS_S_FLAG_MASK) )
3090 {
3091 /* Check that an event occurred on EMIOS channel 19 */
3092 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[19].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
3093 {
3094 #if (defined GPT_EMIOS_2_CH_19_ISR_USED)
3095 Emios_Gpt_Ip_IrqHandler(2, 19);
3096 #endif
3097
3098 #if (defined ICU_EMIOS_2_CH_19_ISR_USED)
3099 Emios_Icu_Ip_IrqHandler(2, 19);
3100 #endif
3101
3102 #if (defined OCU_EMIOS_2_CH_19_ISR_USED)
3103 Emios_Ocu_Ip_IrqHandler(2, 19);
3104 #endif
3105
3106 #if (defined PWM_EMIOS_2_CH_19_ISR_USED)
3107 Emios_Pwm_Ip_IrqHandler(2, 19);
3108 #endif
3109
3110 }
3111 else
3112 {
3113 /* Do nothing - in case of spurious interrupts, return immediately */
3114 }
3115 }
3116 #endif
3117
3118 }
3119 #endif
3120 #if (\
3121 (defined GPT_EMIOS_2_CH_20_ISR_USED) ||\
3122 (defined GPT_EMIOS_2_CH_21_ISR_USED) ||\
3123 (defined GPT_EMIOS_2_CH_22_ISR_USED) ||\
3124 (defined GPT_EMIOS_2_CH_23_ISR_USED) ||\
3125 (defined ICU_EMIOS_2_CH_20_ISR_USED) ||\
3126 (defined ICU_EMIOS_2_CH_21_ISR_USED) ||\
3127 (defined ICU_EMIOS_2_CH_22_ISR_USED) ||\
3128 (defined ICU_EMIOS_2_CH_23_ISR_USED) ||\
3129 (defined OCU_EMIOS_2_CH_20_ISR_USED) ||\
3130 (defined OCU_EMIOS_2_CH_21_ISR_USED) ||\
3131 (defined OCU_EMIOS_2_CH_22_ISR_USED) ||\
3132 (defined OCU_EMIOS_2_CH_23_ISR_USED) ||\
3133 (defined PWM_EMIOS_2_CH_20_ISR_USED) ||\
3134 (defined PWM_EMIOS_2_CH_21_ISR_USED) ||\
3135 (defined PWM_EMIOS_2_CH_22_ISR_USED) ||\
3136 (defined PWM_EMIOS_2_CH_23_ISR_USED)\
3137 )
3138 /**
3139 * @brief Interrupt handler for Emios channels 20-23 for Emios instance 2
3140 * @details Process the interrupt of eMios channels 20-23
3141 *
3142 * @note This will be defined only if EMIOS channels 20, 21, 22, 23 are configured in GPT, ICU,
3143 * OCU or PWM mode.
3144 */
ISR(EMIOS2_0_IRQ)3145 ISR(EMIOS2_0_IRQ)
3146 {
3147 #if (defined EMIOS_2_CH_20_ISR_USED)
3148 /* Check that an event occurred on Emios channel 20 */
3149 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[20].S) & (uint32)eMIOS_S_FLAG_MASK) )
3150 {
3151 /* Check that an event occurred on EMIOS channel 20 */
3152 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[20].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
3153 {
3154 #if (defined GPT_EMIOS_2_CH_20_ISR_USED)
3155 Emios_Gpt_Ip_IrqHandler(2, 20);
3156 #endif
3157
3158 #if (defined ICU_EMIOS_2_CH_20_ISR_USED)
3159 Emios_Icu_Ip_IrqHandler(2, 20);
3160 #endif
3161
3162 #if (defined OCU_EMIOS_2_CH_20_ISR_USED)
3163 Emios_Ocu_Ip_IrqHandler(2, 20);
3164 #endif
3165
3166 #if (defined PWM_EMIOS_2_CH_20_ISR_USED)
3167 Emios_Pwm_Ip_IrqHandler(2, 20);
3168 #endif
3169
3170 }
3171 else
3172 {
3173 /* Do nothing - in case of spurious interrupts, return immediately */
3174 }
3175 }
3176 #endif
3177
3178 #if (defined EMIOS_2_CH_21_ISR_USED)
3179 /* Check that an event occurred on Emios channel 21 */
3180 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[21].S) & (uint32)eMIOS_S_FLAG_MASK) )
3181 {
3182 /* Check that an event occurred on EMIOS channel 21 */
3183 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[21].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
3184 {
3185 #if (defined GPT_EMIOS_2_CH_21_ISR_USED)
3186 Emios_Gpt_Ip_IrqHandler(2, 21);
3187 #endif
3188
3189 #if (defined ICU_EMIOS_2_CH_21_ISR_USED)
3190 Emios_Icu_Ip_IrqHandler(2, 21);
3191 #endif
3192
3193 #if (defined OCU_EMIOS_2_CH_21_ISR_USED)
3194 Emios_Ocu_Ip_IrqHandler(2, 21);
3195 #endif
3196
3197 #if (defined PWM_EMIOS_2_CH_21_ISR_USED)
3198 Emios_Pwm_Ip_IrqHandler(2, 21);
3199 #endif
3200
3201 }
3202 else
3203 {
3204 /* Do nothing - in case of spurious interrupts, return immediately */
3205 }
3206 }
3207 #endif
3208
3209 #if (defined EMIOS_2_CH_22_ISR_USED)
3210 /* Check that an event occurred on Emios channel 22 */
3211 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[22].S) & (uint32)eMIOS_S_FLAG_MASK) )
3212 {
3213 /* Check that an event occurred on EMIOS channel 22 */
3214 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[22].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
3215 {
3216 #if (defined GPT_EMIOS_2_CH_22_ISR_USED)
3217 Emios_Gpt_Ip_IrqHandler(2, 22);
3218 #endif
3219
3220 #if (defined ICU_EMIOS_2_CH_22_ISR_USED)
3221 Emios_Icu_Ip_IrqHandler(2, 22);
3222 #endif
3223
3224 #if (defined OCU_EMIOS_2_CH_22_ISR_USED)
3225 Emios_Ocu_Ip_IrqHandler(2, 22);
3226 #endif
3227
3228 #if (defined PWM_EMIOS_2_CH_22_ISR_USED)
3229 Emios_Pwm_Ip_IrqHandler(2, 22);
3230 #endif
3231
3232 }
3233 else
3234 {
3235 /* Do nothing - in case of spurious interrupts, return immediately */
3236 }
3237 }
3238 #endif
3239
3240 #if (defined EMIOS_2_CH_23_ISR_USED)
3241 /* Check that an event occurred on Emios channel 23 */
3242 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[23].S) & (uint32)eMIOS_S_FLAG_MASK) )
3243 {
3244 /* Check that an event occurred on EMIOS channel 23 */
3245 if ( 0U != ((Emios_Ip_paxBase[2]->CH.UC[23].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))) )
3246 {
3247 #if (defined GPT_EMIOS_2_CH_23_ISR_USED)
3248 Emios_Gpt_Ip_IrqHandler(2, 23);
3249 #endif
3250
3251 #if (defined ICU_EMIOS_2_CH_23_ISR_USED)
3252 Emios_Icu_Ip_IrqHandler(2, 23);
3253 #endif
3254
3255 #if (defined OCU_EMIOS_2_CH_23_ISR_USED)
3256 Emios_Ocu_Ip_IrqHandler(2, 23);
3257 #endif
3258
3259 #if (defined PWM_EMIOS_2_CH_23_ISR_USED)
3260 Emios_Pwm_Ip_IrqHandler(2, 23);
3261 #endif
3262
3263 }
3264 else
3265 {
3266 /* Do nothing - in case of spurious interrupts, return immediately */
3267 }
3268 }
3269 #endif
3270
3271 }
3272 #endif
3273
3274
3275 #define MCL_STOP_SEC_CODE
3276 #include "Mcl_MemMap.h"
3277
3278 #ifdef __cplusplus
3279 }
3280 #endif
3281
3282 /** @} */
3283
