1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Emios_Mcl_Ip.c
9 *
10 * @version 3.0.0
11 *
12 * @brief AUTOSAR Mcl - Emios Common driver source file.
13 * @details
14 *
15 * @addtogroup EMIOS_IP_DRIVER EMIOS IP Driver
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Emios_Mcl_Ip.h"
30
31 /*==================================================================================================
32 * SOURCE FILE VERSION INFORMATION
33 ==================================================================================================*/
34 #define EMIOS_MCL_IP_VENDOR_ID_C 43
35 #define EMIOS_MCL_IP_AR_RELEASE_MAJOR_VERSION_C 4
36 #define EMIOS_MCL_IP_AR_RELEASE_MINOR_VERSION_C 7
37 #define EMIOS_MCL_IP_AR_RELEASE_REVISION_VERSION_C 0
38 #define EMIOS_MCL_IP_SW_MAJOR_VERSION_C 3
39 #define EMIOS_MCL_IP_SW_MINOR_VERSION_C 0
40 #define EMIOS_MCL_IP_SW_PATCH_VERSION_C 0
41 /*==================================================================================================
42 * FILE VERSION CHECKS
43 ==================================================================================================*/
44 #if (EMIOS_MCL_IP_VENDOR_ID_C != EMIOS_MCL_IP_VENDOR_ID)
45 #error "Emios_Mcl_Ip.c and Emios_Mcl_Ip.h have different vendor ids"
46 #endif
47
48 /* Check if source file and Emios_Mcl_Ip.h file are of the same Autosar version */
49 #if ((EMIOS_MCL_IP_AR_RELEASE_MAJOR_VERSION_C != EMIOS_MCL_IP_AR_RELEASE_MAJOR_VERSION) || \
50 (EMIOS_MCL_IP_AR_RELEASE_MINOR_VERSION_C != EMIOS_MCL_IP_AR_RELEASE_MINOR_VERSION) || \
51 (EMIOS_MCL_IP_AR_RELEASE_REVISION_VERSION_C != EMIOS_MCL_IP_AR_RELEASE_REVISION_VERSION))
52 #error "AutoSar Version Numbers of Emios_Mcl_Ip.c and Emios_Mcl_Ip.h are different"
53 #endif
54
55 /* Check if source file and Emios_Mcl_Ip.h file are of the same Software version */
56 #if ((EMIOS_MCL_IP_SW_MAJOR_VERSION_C != EMIOS_MCL_IP_SW_MAJOR_VERSION) || \
57 (EMIOS_MCL_IP_SW_MINOR_VERSION_C != EMIOS_MCL_IP_SW_MINOR_VERSION) || \
58 (EMIOS_MCL_IP_SW_PATCH_VERSION_C != EMIOS_MCL_IP_SW_PATCH_VERSION))
59 #error "Software Version Numbers of Emios_Mcl_Ip.c and Emios_Mcl_Ip.h are different"
60 #endif
61 /*==================================================================================================
62 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
63 ==================================================================================================*/
64
65 /*==================================================================================================
66 * LOCAL MACROS
67 ==================================================================================================*/
68
69 /*==================================================================================================
70 * LOCAL CONSTANTS
71 ==================================================================================================*/
72
73 /*==================================================================================================
74 * LOCAL VARIABLES
75 ==================================================================================================*/
76 #define MCL_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
77 #include "Mcl_MemMap.h"
78
79 eMIOS_Type *const Emios_Ip_paxBase[eMIOS_INSTANCE_COUNT] = IP_eMIOS_BASE_PTRS;
80
81 #define MCL_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
82 #include "Mcl_MemMap.h"
83
84 #if (EMIOS_IP_MULTICORE_IS_AVAILABLE == STD_ON)
85
86 #define MCL_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
87 #include "Mcl_MemMap.h"
88
89 static Emios_Ip_InstStateType Emios_Ip_axIpIsInitialized[eMIOS_INSTANCE_COUNT] =
90 {
91 {(boolean)FALSE, (uint8)255}
92 };
93
94 #define MCL_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
95 #include "Mcl_MemMap.h"
96
97 #else
98
99 #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
100 #include "Mcl_MemMap.h"
101
102 VAR_SEC_NOCACHE(Emios_Ip_axIpIsInitialized) static Emios_Ip_InstStateType Emios_Ip_axIpIsInitialized[eMIOS_INSTANCE_COUNT];
103
104 #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
105 #include "Mcl_MemMap.h"
106
107 #endif
108
109
110 #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
111 #include "Mcl_MemMap.h"
112
113 VAR_SEC_NOCACHE(Emios_Ip_axChState) static Emios_Ip_ChStateType Emios_Ip_axChState[eMIOS_INSTANCE_COUNT][eMIOS_CH_UC_UC_COUNT];
114
115 #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
116 #include "Mcl_MemMap.h"
117
118 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
119 #define MCL_START_SEC_VAR_CLEARED_32
120 #include "Mcl_MemMap.h"
121
122 /* Array to store the period master bus */
123 static uint32 Emios_Ip_ChPeriodMasterBus[eMIOS_INSTANCE_COUNT][eMIOS_CH_UC_UC_COUNT];
124
125 #define MCL_STOP_SEC_VAR_CLEARED_32
126 #include "Mcl_MemMap.h"
127 #else
128 #define MCL_START_SEC_VAR_CLEARED_16
129 #include "Mcl_MemMap.h"
130
131 /* Array to store the period master bus */
132 static uint16 Emios_Ip_ChPeriodMasterBus[eMIOS_INSTANCE_COUNT][eMIOS_CH_UC_UC_COUNT];
133
134 #define MCL_STOP_SEC_VAR_CLEARED_16
135 #include "Mcl_MemMap.h"
136 #endif
137
138 /*==================================================================================================
139 * GLOBAL CONSTANTS
140 ==================================================================================================*/
141
142 /*==================================================================================================
143 * GLOBAL VARIABLES
144 ==================================================================================================*/
145
146 /*==================================================================================================
147 * LOCAL FUNCTION PROTOTYPES
148 ==================================================================================================*/
149
150 /*==================================================================================================
151 * LOCAL FUNCTIONS
152 ==================================================================================================*/
153
154 /*==================================================================================================
155 * GLOBAL FUNCTIONS
156 ==================================================================================================*/
157 #define MCL_START_SEC_CODE
158 #include "Mcl_MemMap.h"
159
160 /** @implements Emios_Mcl_Ip_Init_Activity */
Emios_Mcl_Ip_Init(uint8 Instance,const Emios_Mcl_Ip_ConfigType * const ConfigPtr)161 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Init(uint8 Instance, const Emios_Mcl_Ip_ConfigType* const ConfigPtr)
162 {
163 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
164 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
165 DevAssert(ConfigPtr != NULL_PTR);
166 #endif
167
168 uint8 CurrentChannel;
169 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
170 Emios_Ip_CommonStatusType Status = EMIOS_IP_COMMON_STATUS_SUCCESS;
171
172 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
173 uint8 coreID = (uint8)OsIf_GetCoreID();
174 if ( MULTICORE_INIT_CORE == coreID )
175 {
176 #endif /* STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE */
177
178 if (Emios_Ip_axIpIsInitialized[Instance].instanceInitState == TRUE)
179 {
180 Status = EMIOS_IP_COMMON_STATUS_FAIL;
181 }
182 else
183 {
184 /* Initialization of EMIOS instance specific parameters. */
185 Base->MCR &= ~eMIOS_MCR_GPREN_MASK;
186 Base->MCR = eMIOS_MCR_GPRE(ConfigPtr->emiosGlobalConfig->clkDivVal) | eMIOS_MCR_FRZ(((uint32)ConfigPtr->emiosGlobalConfig->allowDebugMode)) | \
187 eMIOS_MCR_GTBE(ConfigPtr->emiosGlobalConfig->enableGlobalTimeBase);
188
189 /* Initialization of EMIOS channel specific parameters. */
190 for (CurrentChannel = 0; CurrentChannel < ConfigPtr->channelsNumber; CurrentChannel++)
191 {
192 if ((*ConfigPtr->masterBusConfig)[CurrentChannel].allowDebugMode)
193 {
194 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_FREN_MASK;
195 }
196
197 /* Set Cn UCPRE to divider. */
198 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C2 |= eMIOS_C2_UCEXTPRE((*ConfigPtr->masterBusConfig)[CurrentChannel].masterBusPrescaler);
199
200 switch ((*ConfigPtr->masterBusConfig)[CurrentChannel].masterMode)
201 {
202 case EMIOS_IP_MC_UP_COUNTER_START:
203 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
204 break;
205 case EMIOS_IP_MC_UP_COUNTER_END:
206 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
207 break;
208 case EMIOS_IP_MC_UP_DOWN_COUNTER:
209 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].B = 0;
210 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
211 break;
212 case EMIOS_IP_MCB_UP_COUNTER:
213 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
214 break;
215 case EMIOS_IP_MCB_UP_DOWN_COUNTER:
216 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].A = (*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
217 break;
218 default:
219 /* Do nothing. */
220 break;
221 }
222
223 /* Write CNT register with start offset value. */
224 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].CNT = (*ConfigPtr->masterBusConfig)[CurrentChannel].offsetStartValue;
225
226 /* Set mode Cn_MODE = mode. */
227 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_MODE((*ConfigPtr->masterBusConfig)[CurrentChannel].masterMode);
228
229 Base->CH.UC[(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].C |= eMIOS_C_UCPREN(1U);
230
231 /* Save current state of channel. */
232 Emios_Ip_axChState[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].counterMode = (*ConfigPtr->masterBusConfig)[CurrentChannel].masterMode;
233 Emios_Ip_axChState[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel].channelInitState = TRUE;
234 /* Save the period of master bus channel. */
235 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
236 Emios_Ip_ChPeriodMasterBus[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel] = (uint32)(*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
237 #else
238 Emios_Ip_ChPeriodMasterBus[Instance][(*ConfigPtr->masterBusConfig)[CurrentChannel].hwChannel] = (uint16)(*ConfigPtr->masterBusConfig)[CurrentChannel].defaultPeriod;
239 #endif
240 }
241
242 /* Save current state of the instance. */
243 Emios_Ip_axIpIsInitialized[Instance].instanceInitState = TRUE;
244 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
245 Emios_Ip_axIpIsInitialized[Instance].runCore = ConfigPtr->instanceCoreNumber;
246 #endif
247 }
248
249 Base->MCR |= eMIOS_MCR_GPREN_MASK;
250
251 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
252 }
253 else
254 {
255 Status = EMIOS_IP_COMMON_STATUS_WRONG_CORE;
256 }
257 #endif /* STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE */
258
259 return Status;
260 }
261
262 /** @implements Emios_Mcl_Ip_EnableChannel_Activity */
Emios_Mcl_Ip_EnableChannel(uint8 Instance,uint8 HwChannel)263 void Emios_Mcl_Ip_EnableChannel(uint8 Instance, uint8 HwChannel)
264 {
265 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
266 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
267 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT);
268 #endif
269
270 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
271 Base->UCDIS &= ~(uint32)((uint32)1 << ((uint32)HwChannel));
272 }
273
274 /** @implements Emios_Mcl_Ip_DisableChannel_Activity */
Emios_Mcl_Ip_DisableChannel(uint8 Instance,uint8 HwChannel)275 void Emios_Mcl_Ip_DisableChannel(uint8 Instance, uint8 HwChannel)
276 {
277 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
278 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
279 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT);
280 #endif
281
282 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
283 Base->UCDIS |= (uint32)((uint32)1 << ((uint32)HwChannel));
284 }
285
286 /** @implements Emios_Mcl_Ip_ComparatorTransferEnable_Activity */
Emios_Mcl_Ip_ComparatorTransferEnable(uint8 Instance,uint32 ChannelMask)287 void Emios_Mcl_Ip_ComparatorTransferEnable(uint8 Instance, uint32 ChannelMask)
288 {
289 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
290 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
291 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL);
292 #endif
293
294 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
295 /* Update enable. */
296 Base->OUDIS &= ~(ChannelMask);
297 }
298
299 /** @implements Emios_Mcl_Ip_ComparatorTransferDisable_Activity */
Emios_Mcl_Ip_ComparatorTransferDisable(uint8 Instance,uint32 ChannelMask)300 void Emios_Mcl_Ip_ComparatorTransferDisable(uint8 Instance, uint32 ChannelMask)
301 {
302 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
303 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
304 DevAssert(ChannelMask < EMIOS_CHANNELMASK_MAXVAL);
305 #endif
306
307 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
308 /* Disable channel output. */
309 Base->OUDIS |= ChannelMask;
310 }
311
312 /** @implements Emios_Mcl_Ip_Deinit_Activity */
Emios_Mcl_Ip_Deinit(uint8 Instance)313 Emios_Ip_CommonStatusType Emios_Mcl_Ip_Deinit(uint8 Instance)
314 {
315 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
316 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
317 #endif
318
319 uint8 CurrentChannel;
320 Emios_Ip_CommonStatusType Status = EMIOS_IP_COMMON_STATUS_SUCCESS;
321 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
322
323 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
324 uint8 coreID = (uint8)OsIf_GetCoreID();
325 if ( MULTICORE_INIT_CORE == coreID )
326 {
327 #endif /* STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE */
328 if (Emios_Ip_axIpIsInitialized[Instance].instanceInitState == FALSE)
329 {
330 Status = EMIOS_IP_COMMON_STATUS_FAIL;
331 }
332 else
333 {
334 Base->MCR &= ~eMIOS_MCR_GPREN_MASK;
335 Base->MCR = eMIOS_MCR_GPRE(0U) | eMIOS_MCR_FRZ(0U) | eMIOS_MCR_GTBE(0U);
336
337 for (CurrentChannel = 0; CurrentChannel < eMIOS_CH_UC_UC_COUNT; CurrentChannel++)
338 {
339 if(Emios_Ip_axChState[Instance][CurrentChannel].channelInitState == TRUE)
340 {
341 /* Disable channel pre-scaler (reset default) */
342 Emios_Ip_paxBase[Instance]->CH.UC[CurrentChannel].C = 0U;
343 /* Reset An and Bn registers */
344 Emios_Ip_paxBase[Instance]->CH.UC[CurrentChannel].A = 0UL;
345 Emios_Ip_paxBase[Instance]->CH.UC[CurrentChannel].B = 0UL;
346
347 Emios_Ip_paxBase[Instance]->UCDIS |= (uint32)((uint32)0 << ((uint32)CurrentChannel));
348 /* Clear the period of master bus channel. */
349 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
350 Emios_Ip_ChPeriodMasterBus[Instance][CurrentChannel] = (uint32)0U;
351 #else
352 Emios_Ip_ChPeriodMasterBus[Instance][CurrentChannel] = (uint16)0U;
353 #endif
354 Emios_Ip_axChState[Instance][CurrentChannel].channelInitState = FALSE;
355 }
356 }
357 Emios_Ip_axIpIsInitialized[Instance].instanceInitState = FALSE;
358 }
359 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
360 }
361 else
362 {
363 Status = EMIOS_IP_COMMON_STATUS_WRONG_CORE;
364 }
365 #endif /* STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE */
366
367 return Status;
368 }
369
370 /** @implements Emios_Mcl_Ip_SetReloadInterval_Activity */
Emios_Mcl_Ip_SetReloadInterval(uint8 HwInstance,uint8 HwChannel,uint8 Interval)371 void Emios_Mcl_Ip_SetReloadInterval(uint8 HwInstance, uint8 HwChannel, uint8 Interval)
372 {
373 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
374 DevAssert((uint8)31 > Interval);
375 DevAssert(HwInstance < eMIOS_INSTANCE_COUNT);
376 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT);
377 #endif
378 /* Specifies the delay interval, in counter bus reload events, between each assertion
379 * of AS1-BS1 reload in MC and MCB modes. */
380 Emios_Ip_paxBase[HwInstance]->CH.UC[HwChannel].C2 = eMIOS_C2_UCRELDEL_INT(Interval);
381 }
382
383 /** @implements Emios_Mcl_Ip_ValidateChannel_Activity */
Emios_Mcl_Ip_ValidateChannel(uint8 HwInstance,uint8 HwChannel)384 boolean Emios_Mcl_Ip_ValidateChannel(uint8 HwInstance, uint8 HwChannel)
385 {
386 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
387 /* Check input parameter*/
388 DevAssert(HwInstance < eMIOS_INSTANCE_COUNT);
389 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT);
390 #endif
391 boolean Valid = FALSE;
392
393 if (TRUE == Emios_Ip_axChState[HwInstance][HwChannel].channelInitState)
394 {
395 Valid = TRUE;
396 }
397 return Valid;
398 }
399
400 /** @implements Emios_Mcl_Ip_SetCounterBusPeriod_Activity */
Emios_Mcl_Ip_SetCounterBusPeriod(uint8 HwInstance,uint8 HwChannel,uint32 Period)401 Emios_Ip_CommonStatusType Emios_Mcl_Ip_SetCounterBusPeriod(uint8 HwInstance, uint8 HwChannel, uint32 Period)
402 {
403 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
404 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
405 DevAssert((uint32)16777215 > Period);
406 #else
407 DevAssert((uint32)65535 > Period);
408 #endif
409 DevAssert(HwInstance < eMIOS_INSTANCE_COUNT);
410 DevAssert(HwChannel < eMIOS_CH_UC_UC_COUNT);
411 #endif
412 Emios_Ip_CommonStatusType Status = EMIOS_IP_COMMON_STATUS_FAIL;
413
414 if (( (Emios_Ip_axChState[HwInstance][HwChannel].counterMode == EMIOS_IP_MCB_UP_COUNTER) || \
415 (Emios_Ip_axChState[HwInstance][HwChannel].counterMode == EMIOS_IP_MCB_UP_DOWN_COUNTER) ) && \
416 (Period < 1U) )
417 {
418 Status = EMIOS_IP_COMMON_STATUS_FAIL;
419 }
420 else
421 {
422 Emios_Ip_paxBase[HwInstance]->CH.UC[HwChannel].A = Period;
423 /* Store the new period */
424 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
425 Emios_Ip_ChPeriodMasterBus[HwInstance][HwChannel] = Period;
426 #else
427 Emios_Ip_ChPeriodMasterBus[HwInstance][HwChannel] = (uint16)Period;
428 #endif
429 Status = EMIOS_IP_COMMON_STATUS_SUCCESS;
430 }
431 return Status;
432 }
433
434
435 /** @implements Emios_Mcl_Ip_GetCounterBusPeriod_Activity */
436 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance,uint8 Channel)437 uint32 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel)
438 #else
439 uint16 Emios_Mcl_Ip_GetCounterBusPeriod(uint8 Instance, uint8 Channel)
440 #endif
441 {
442 #if (EMIOS_MCL_IP_DEV_ERROR_DETECT == STD_ON)
443 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
444 DevAssert(Channel < eMIOS_CH_UC_UC_COUNT);
445 #endif
446 /* Get period of counter bus channels. */
447 #if (STD_ON == EMIOS_MCL_IP_24BITS_TIMER_WIDTH)
448 uint32 PeriodCounterBus = Emios_Ip_ChPeriodMasterBus[Instance][Channel];
449 #else
450 uint16 PeriodCounterBus = Emios_Ip_ChPeriodMasterBus[Instance][Channel];
451 #endif
452
453 return PeriodCounterBus;
454 }
455
456 #if (STD_ON == EMIOS_IP_MULTICORE_IS_AVAILABLE)
457 /** @implements Emios_Mcl_Ip_ValidateMultiCoreInit_Activity */
Emios_Mcl_Ip_ValidateMultiCoreInit(uint8 HwInstance)458 boolean Emios_Mcl_Ip_ValidateMultiCoreInit(uint8 HwInstance)
459 {
460 boolean Valid = FALSE;
461 uint8 CoreId = (uint8)OsIf_GetCoreID();
462
463 if (Emios_Ip_axIpIsInitialized[HwInstance].runCore == CoreId)
464 {
465 Valid = TRUE;
466 }
467
468 return Valid;
469 }
470 #endif
471
Emios_Mcl_Ip_ConfigureGlobalTimebase(uint8 Instance,uint8 Value)472 void Emios_Mcl_Ip_ConfigureGlobalTimebase(uint8 Instance, uint8 Value)
473 {
474 #if (STD_ON == EMIOS_MCL_IP_DEV_ERROR_DETECT)
475 DevAssert(Instance < eMIOS_INSTANCE_COUNT);
476 DevAssert(((uint8)STD_ON == Value)||((uint8)STD_OFF == Value));
477 #endif
478
479 eMIOS_Type* Base = Emios_Ip_paxBase[Instance];
480 /* Configure GTBE bit. */
481 if ((uint8)STD_ON == Value)
482 {
483 Base->MCR |= eMIOS_MCR_GTBE_MASK;
484 }
485 else
486 {
487 Base->MCR &= (~eMIOS_MCR_GTBE_MASK);
488 }
489 }
490
491 #define MCL_STOP_SEC_CODE
492 #include "Mcl_MemMap.h"
493
494 #ifdef __cplusplus
495 }
496 #endif
497
498 /** @} */
499
