Home
last modified time | relevance | path

Searched refs:MCG_C11_PLLREFSEL1_VAL (Results 1 – 25 of 33) sorted by relevance

12

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV11Z7/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z1287/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z7/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW41Z4/drivers/
Dfsl_clock.c109 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM14ZA5/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
416 return *pllExtClkFreq[MCG_C11_PLLREFSEL1_VAL]; in CLOCK_GetPll1RefFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM33ZA5/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
416 return *pllExtClkFreq[MCG_C11_PLLREFSEL1_VAL]; in CLOCK_GetPll1RefFreq()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK02F12810/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12810/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F12810/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV30F12810/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL25Z4/drivers/
Dfsl_clock.c81 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW24D5/drivers/
Dfsl_clock.c81 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW22D5/drivers/
Dfsl_clock.c81 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM34Z7/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F25612/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV58F24/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F51212/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV56F24/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK24F12/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK63F12/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK64F12/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK80F25615/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK82F25615/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/drivers/
Dfsl_clock.c63 #define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) macro

12