1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_EMAC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_EMAC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_EMAC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_EMAC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EMAC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EMAC_Peripheral_Access_Layer EMAC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EMAC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t MAC_CONFIGURATION; /**< MAC Configuration, offset: 0x0 */ 74 __IO uint32_t MAC_EXT_CONFIGURATION; /**< MAC Extended Configuration, offset: 0x4 */ 75 __IO uint32_t MAC_PACKET_FILTER; /**< MAC Packet Filter, offset: 0x8 */ 76 __IO uint32_t MAC_WATCHDOG_TIMEOUT; /**< MAC Watchdog Timeout, offset: 0xC */ 77 __IO uint32_t MAC_HASH_TABLE_REG0; /**< MAC Hash Table First 32 Bits, offset: 0x10 */ 78 __IO uint32_t MAC_HASH_TABLE_REG1; /**< MAC Hash Table Second 32 Bits, offset: 0x14 */ 79 uint8_t RESERVED_0[56]; 80 union { /* offset: 0x50 */ 81 __IO uint32_t MAC_VLAN_TAG_CTRL; /**< MAC VLAN Tag Control, offset: 0x50 */ 82 __IO uint32_t MAC_VLAN_TAG; /**< MAC VLAN Tag, offset: 0x50 */ 83 } MAC_VLAN; 84 union { /* offset: 0x54 */ 85 __IO uint32_t MAC_VLAN_TAG_DATA; /**< MAC VLAN Tag Data, offset: 0x54 */ 86 __IO uint32_t MAC_VLAN_TAG_FILTER0; /**< MAC VLAN Tag Filter 0, offset: 0x54 */ 87 __IO uint32_t MAC_VLAN_TAG_FILTER1; /**< MAC VLAN Tag Filter 1, offset: 0x54 */ 88 __IO uint32_t MAC_VLAN_TAG_FILTER2; /**< MAC VLAN Tag Filter 2, offset: 0x54 */ 89 __IO uint32_t MAC_VLAN_TAG_FILTER3; /**< MAC VLAN Tag Filter 3, offset: 0x54 */ 90 } MAC_VLAN_TAG; 91 __IO uint32_t MAC_VLAN_HASH_TABLE; /**< MAC VLAN Hash Table, offset: 0x58 */ 92 uint8_t RESERVED_1[4]; 93 union { /* offset: 0x60 */ 94 __IO uint32_t MAC_VLAN_INCL0; /**< MAC VLAN Inclusion 0, offset: 0x60 */ 95 __IO uint32_t MAC_VLAN_INCL1; /**< MAC VLAN Inclusion 1, offset: 0x60 */ 96 __IO uint32_t MAC_VLAN_INCL2; /**< MAC VLAN Inclusion 2, offset: 0x60 */ 97 __IO uint32_t MAC_VLAN_INCL3; /**< MAC VLAN Inclusion 3, offset: 0x60 */ 98 __IO uint32_t MAC_VLAN_INCL4; /**< MAC VLAN Inclusion 4, offset: 0x60 */ 99 __IO uint32_t MAC_VLAN_INCL5; /**< MAC VLAN Inclusion 5, offset: 0x60 */ 100 __IO uint32_t MAC_VLAN_INCL6; /**< MAC VLAN Inclusion 6, offset: 0x60 */ 101 __IO uint32_t MAC_VLAN_INCL7; /**< MAC VLAN Inclusion 7, offset: 0x60 */ 102 __IO uint32_t MAC_VLAN_INCL; /**< MAC VLAN Inclusion Or Replacement, offset: 0x60 */ 103 } MAC_VLAN_INCL; 104 __IO uint32_t MAC_INNER_VLAN_INCL; /**< Inner VLAN Tag Inclusion Or Replacement, offset: 0x64 */ 105 uint8_t RESERVED_2[8]; 106 __IO uint32_t MAC_Q0_TX_FLOW_CTRL; /**< MAC Q0 Tx Flow Control, offset: 0x70 */ 107 uint8_t RESERVED_3[28]; 108 __IO uint32_t MAC_RX_FLOW_CTRL; /**< MAC Receive Flow Control, offset: 0x90 */ 109 __IO uint32_t MAC_RXQ_CTRL4; /**< MAC RxQ Control 4, offset: 0x94 */ 110 uint8_t RESERVED_4[8]; 111 __IO uint32_t MAC_RXQ_CTRL0; /**< MAC RxQ Control 0, offset: 0xA0 */ 112 __IO uint32_t MAC_RXQ_CTRL1; /**< Receive Queue Control 1, offset: 0xA4 */ 113 __IO uint32_t MAC_RXQ_CTRL2; /**< MAC RxQ Control 2, offset: 0xA8 */ 114 uint8_t RESERVED_5[4]; 115 __I uint32_t MAC_INTERRUPT_STATUS; /**< MAC Interrupt Status, offset: 0xB0 */ 116 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< MAC Interrupt Enable, offset: 0xB4 */ 117 __I uint32_t MAC_RX_TX_STATUS; /**< MAC Rx Transmit Status, offset: 0xB8 */ 118 uint8_t RESERVED_6[84]; 119 __I uint32_t MAC_VERSION; /**< MAC Version, offset: 0x110 */ 120 __I uint32_t MAC_DEBUG; /**< MAC Debug, offset: 0x114 */ 121 uint8_t RESERVED_7[4]; 122 __I uint32_t MAC_HW_FEATURE0; /**< MAC Hardware Feature 0, offset: 0x11C */ 123 __I uint32_t MAC_HW_FEATURE1; /**< MAC Hardware Feature 1, offset: 0x120 */ 124 __I uint32_t MAC_HW_FEATURE2; /**< MAC Hardware Feature 2, offset: 0x124 */ 125 __I uint32_t MAC_HW_FEATURE3; /**< MAC Hardware Feature 3, offset: 0x128 */ 126 uint8_t RESERVED_8[20]; 127 __I uint32_t MAC_DPP_FSM_INTERRUPT_STATUS; /**< MAC DPP FSM Interrupt Status, offset: 0x140 */ 128 uint8_t RESERVED_9[4]; 129 __IO uint32_t MAC_FSM_CONTROL; /**< MAC FSM Control, offset: 0x148 */ 130 __IO uint32_t MAC_FSM_ACT_TIMER; /**< MAC FSM ACT Timer, offset: 0x14C */ 131 __IO uint32_t SCS_REG1; /**< SCS_REG 1, offset: 0x150 */ 132 uint8_t RESERVED_10[172]; 133 __IO uint32_t MAC_MDIO_ADDRESS; /**< MAC MDIO Address, offset: 0x200 */ 134 __IO uint32_t MAC_MDIO_DATA; /**< MAC MDIO Data, offset: 0x204 */ 135 uint8_t RESERVED_11[40]; 136 __IO uint32_t MAC_CSR_SW_CTRL; /**< MAC CSR Software Control, offset: 0x230 */ 137 __IO uint32_t MAC_FPE_CTRL_STS; /**< MAC FPE Control STS, offset: 0x234 */ 138 uint8_t RESERVED_12[8]; 139 __I uint32_t MAC_PRESN_TIME_NS; /**< MAC Presentation Time, offset: 0x240 */ 140 __IO uint32_t MAC_PRESN_TIME_UPDT; /**< MAC Presentation Time Update, offset: 0x244 */ 141 uint8_t RESERVED_13[184]; 142 __IO uint32_t MAC_ADDRESS0_HIGH; /**< MAC Address 0 High, offset: 0x300 */ 143 __IO uint32_t MAC_ADDRESS0_LOW; /**< MAC Address 0 Low, offset: 0x304 */ 144 __IO uint32_t MAC_ADDRESS1_HIGH; /**< MAC Address 1 High, offset: 0x308 */ 145 __IO uint32_t MAC_ADDRESS1_LOW; /**< MAC Address 1 Low, offset: 0x30C */ 146 __IO uint32_t MAC_ADDRESS2_HIGH; /**< MAC Address 2 High, offset: 0x310 */ 147 __IO uint32_t MAC_ADDRESS2_LOW; /**< MAC Address 2 Low, offset: 0x314 */ 148 uint8_t RESERVED_14[1000]; 149 __IO uint32_t MMC_CONTROL; /**< MMC Control, offset: 0x700 */ 150 __I uint32_t MMC_RX_INTERRUPT; /**< MMC Receive Interrupt, offset: 0x704 */ 151 __I uint32_t MMC_TX_INTERRUPT; /**< MMC Transmit Interrupt, offset: 0x708 */ 152 __IO uint32_t MMC_RX_INTERRUPT_MASK; /**< MMC Receive Interrupt Mask, offset: 0x70C */ 153 __IO uint32_t MMC_TX_INTERRUPT_MASK; /**< MMC Transmit Interrupt Mask, offset: 0x710 */ 154 __I uint32_t TX_OCTET_COUNT_GOOD_BAD; /**< Transmit Octet Count Good Bad, offset: 0x714 */ 155 __I uint32_t TX_PACKET_COUNT_GOOD_BAD; /**< Transmit Packet Count Good Bad, offset: 0x718 */ 156 __I uint32_t TX_BROADCAST_PACKETS_GOOD; /**< Transmit Broadcast Packets Good, offset: 0x71C */ 157 __I uint32_t TX_MULTICAST_PACKETS_GOOD; /**< Transmit Multicast Packets Good, offset: 0x720 */ 158 __I uint32_t TX_64OCTETS_PACKETS_GOOD_BAD; /**< Transmit 64-Octet Packets Good Bad, offset: 0x724 */ 159 __I uint32_t TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Transmit 65 To 127 Octet Packets Good Bad, offset: 0x728 */ 160 __I uint32_t TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Transmit 128 To 255 Octet Packets Good Bad, offset: 0x72C */ 161 __I uint32_t TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Transmit 256 To 511 Octet Packets Good Bad, offset: 0x730 */ 162 __I uint32_t TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Transmit 512 To 1023 Octet Packets Good Bad, offset: 0x734 */ 163 __I uint32_t TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Transmit 1024 To Max Octet Packets Good Bad, offset: 0x738 */ 164 __I uint32_t TX_UNICAST_PACKETS_GOOD_BAD; /**< Transmit Unicast Packets Good Bad, offset: 0x73C */ 165 __I uint32_t TX_MULTICAST_PACKETS_GOOD_BAD; /**< Transmit Multicast Packets Good Bad, offset: 0x740 */ 166 __I uint32_t TX_BROADCAST_PACKETS_GOOD_BAD; /**< Transmit Broadcast Packets Good Bad, offset: 0x744 */ 167 __I uint32_t TX_UNDERFLOW_ERROR_PACKETS; /**< Transmit Underflow Error Packets, offset: 0x748 */ 168 __I uint32_t TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Transmit Single Collision Good Packets, offset: 0x74C */ 169 __I uint32_t TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Transmit Multiple Collision Good Packets, offset: 0x750 */ 170 __I uint32_t TX_DEFERRED_PACKETS; /**< Transmit Deferred Packets, offset: 0x754 */ 171 __I uint32_t TX_LATE_COLLISION_PACKETS; /**< Transmit Late Collision Packets, offset: 0x758 */ 172 __I uint32_t TX_EXCESSIVE_COLLISION_PACKETS; /**< Transmit Excessive Collision Packets, offset: 0x75C */ 173 __I uint32_t TX_CARRIER_ERROR_PACKETS; /**< Transmit Carrier Error Packets, offset: 0x760 */ 174 __I uint32_t TX_OCTET_COUNT_GOOD; /**< Transmit Octet Count Good, offset: 0x764 */ 175 __I uint32_t TX_PACKET_COUNT_GOOD; /**< Transmit Packet Count Good, offset: 0x768 */ 176 __I uint32_t TX_EXCESSIVE_DEFERRAL_ERROR; /**< Transmit Excessive Deferral Error, offset: 0x76C */ 177 __I uint32_t TX_PAUSE_PACKETS; /**< Transmit Pause Packets, offset: 0x770 */ 178 __I uint32_t TX_VLAN_PACKETS_GOOD; /**< Transmit VLAN Packets Good, offset: 0x774 */ 179 __I uint32_t TX_OSIZE_PACKETS_GOOD; /**< Transmit O Size Packets Good, offset: 0x778 */ 180 uint8_t RESERVED_15[4]; 181 __I uint32_t RX_PACKETS_COUNT_GOOD_BAD; /**< Receive Packets Count Good Bad, offset: 0x780 */ 182 __I uint32_t RX_OCTET_COUNT_GOOD_BAD; /**< Receive Octet Count Good Bad, offset: 0x784 */ 183 __I uint32_t RX_OCTET_COUNT_GOOD; /**< Receive Octet Count Good, offset: 0x788 */ 184 __I uint32_t RX_BROADCAST_PACKETS_GOOD; /**< Receive Broadcast Packets Good, offset: 0x78C */ 185 __I uint32_t RX_MULTICAST_PACKETS_GOOD; /**< Receive Multicast Packets Good, offset: 0x790 */ 186 __I uint32_t RX_CRC_ERROR_PACKETS; /**< Receive CRC Error Packets, offset: 0x794 */ 187 __I uint32_t RX_ALIGNMENT_ERROR_PACKETS; /**< Receive Alignment Error Packets, offset: 0x798 */ 188 __I uint32_t RX_RUNT_ERROR_PACKETS; /**< Receive Runt Error Packets, offset: 0x79C */ 189 __I uint32_t RX_JABBER_ERROR_PACKETS; /**< Receive Jabber Error Packets, offset: 0x7A0 */ 190 __I uint32_t RX_UNDERSIZE_PACKETS_GOOD; /**< Receive Undersize Packets Good, offset: 0x7A4 */ 191 __I uint32_t RX_OVERSIZE_PACKETS_GOOD; /**< Receive Oversize Packets Good, offset: 0x7A8 */ 192 __I uint32_t RX_64OCTETS_PACKETS_GOOD_BAD; /**< Receive 64 Octets Packets Good Bad, offset: 0x7AC */ 193 __I uint32_t RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Receive 65-127 Octets Packets Good Bad, offset: 0x7B0 */ 194 __I uint32_t RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Receive 128-255 Octets Packets Good Bad, offset: 0x7B4 */ 195 __I uint32_t RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Receive 256-511 Octets Packets Good Bad, offset: 0x7B8 */ 196 __I uint32_t RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Receive 512-1023 Octets Packets Good Bad, offset: 0x7BC */ 197 __I uint32_t RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Receive 1024 To Max Octets Good Bad, offset: 0x7C0 */ 198 __I uint32_t RX_UNICAST_PACKETS_GOOD; /**< Receive Unicast Packets Good, offset: 0x7C4 */ 199 __I uint32_t RX_LENGTH_ERROR_PACKETS; /**< Receive Length Error Packets, offset: 0x7C8 */ 200 __I uint32_t RX_OUT_OF_RANGE_TYPE_PACKETS; /**< Receive Out of Range Type Packet, offset: 0x7CC */ 201 __I uint32_t RX_PAUSE_PACKETS; /**< Receive Pause Packets, offset: 0x7D0 */ 202 __I uint32_t RX_FIFO_OVERFLOW_PACKETS; /**< Receive FIFO Overflow Packets, offset: 0x7D4 */ 203 __I uint32_t RX_VLAN_PACKETS_GOOD_BAD; /**< Receive VLAN Packets Good Bad, offset: 0x7D8 */ 204 __I uint32_t RX_WATCHDOG_ERROR_PACKETS; /**< Receive Watchdog Error Packets, offset: 0x7DC */ 205 __I uint32_t RX_RECEIVE_ERROR_PACKETS; /**< Receive Receive Error Packets, offset: 0x7E0 */ 206 __I uint32_t RX_CONTROL_PACKETS_GOOD; /**< Receive Control Packets Good, offset: 0x7E4 */ 207 uint8_t RESERVED_16[184]; 208 __I uint32_t MMC_FPE_TX_INTERRUPT; /**< MMC Transmit FPE Fragment Counter Interrupt Status, offset: 0x8A0 */ 209 __IO uint32_t MMC_FPE_TX_INTERRUPT_MASK; /**< MMC FPE Transmit Interrupt Mask, offset: 0x8A4 */ 210 __I uint32_t MMC_TX_FPE_FRAGMENT_CNTR; /**< Transmit FPE Fragment Counter, offset: 0x8A8 */ 211 __I uint32_t MMC_TX_HOLD_REQ_CNTR; /**< Transmit Hold Request Counter, offset: 0x8AC */ 212 uint8_t RESERVED_17[16]; 213 __I uint32_t MMC_FPE_RX_INTERRUPT; /**< MMC Receive Packet Assembly Error Counter Interrupt Status, offset: 0x8C0 */ 214 __IO uint32_t MMC_FPE_RX_INTERRUPT_MASK; /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */ 215 __I uint32_t MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Assembly Error Counter, offset: 0x8C8 */ 216 __I uint32_t MMC_RX_PACKET_SMD_ERR_CNTR; /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */ 217 __I uint32_t MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Assembly OK Counter, offset: 0x8D0 */ 218 __I uint32_t MMC_RX_FPE_FRAGMENT_CNTR; /**< MMC Receive FPE Fragment Counter, offset: 0x8D4 */ 219 uint8_t RESERVED_18[40]; 220 __IO uint32_t MAC_L3_L4_CONTROL0; /**< MAC Layer 3 Layer 4 Control 0, offset: 0x900 */ 221 __IO uint32_t MAC_LAYER4_ADDRESS0; /**< MAC Layer 4 Address 0, offset: 0x904 */ 222 uint8_t RESERVED_19[8]; 223 __IO uint32_t MAC_LAYER3_ADDR0_REG0; /**< MAC Layer 3 Address 0 Reg 0, offset: 0x910 */ 224 __IO uint32_t MAC_LAYER3_ADDR1_REG0; /**< MAC Layer 3 Address 1 Reg 0, offset: 0x914 */ 225 __IO uint32_t MAC_LAYER3_ADDR2_REG0; /**< MAC Layer 3 Address 2 Reg 0, offset: 0x918 */ 226 __IO uint32_t MAC_LAYER3_ADDR3_REG0; /**< MAC Layer 3 Address 3 Reg 0, offset: 0x91C */ 227 uint8_t RESERVED_20[16]; 228 __IO uint32_t MAC_L3_L4_CONTROL1; /**< MAC L3 L4 Control 1, offset: 0x930 */ 229 __IO uint32_t MAC_LAYER4_ADDRESS1; /**< MAC Layer 4 Address 1, offset: 0x934 */ 230 uint8_t RESERVED_21[8]; 231 __IO uint32_t MAC_LAYER3_ADDR0_REG1; /**< MAC Layer 3 Address 0 Reg 1, offset: 0x940 */ 232 __IO uint32_t MAC_LAYER3_ADDR1_REG1; /**< MAC Layer 3 Address 1 Reg 1, offset: 0x944 */ 233 __IO uint32_t MAC_LAYER3_ADDR2_REG1; /**< MAC Layer 3 Address 2 Reg 1, offset: 0x948 */ 234 __IO uint32_t MAC_LAYER3_ADDR3_REG1; /**< MAC Layer 3 Address 3 Reg 1, offset: 0x94C */ 235 uint8_t RESERVED_22[16]; 236 __IO uint32_t MAC_L3_L4_CONTROL2; /**< MAC L3 L4 Control 2, offset: 0x960 */ 237 __IO uint32_t MAC_LAYER4_ADDRESS2; /**< MAC Layer 4 Address 2, offset: 0x964 */ 238 uint8_t RESERVED_23[8]; 239 __IO uint32_t MAC_LAYER3_ADDR0_REG2; /**< MAC Layer 3 Address 0 Reg 2, offset: 0x970 */ 240 __IO uint32_t MAC_LAYER3_ADDR1_REG2; /**< MAC Layer 3 Address 1 Reg 2, offset: 0x974 */ 241 __IO uint32_t MAC_LAYER3_ADDR2_REG2; /**< MAC Layer 3 Address 2 Reg 2, offset: 0x978 */ 242 __IO uint32_t MAC_LAYER3_ADDR3_REG2; /**< MAC Layer 3 Address 3 Reg 2, offset: 0x97C */ 243 uint8_t RESERVED_24[16]; 244 __IO uint32_t MAC_L3_L4_CONTROL3; /**< MAC L3 L4 Control 3, offset: 0x990 */ 245 __IO uint32_t MAC_LAYER4_ADDRESS3; /**< MAC Layer 4 Address 3, offset: 0x994 */ 246 uint8_t RESERVED_25[8]; 247 __IO uint32_t MAC_LAYER3_ADDR0_REG3; /**< MAC Layer 3 Address 0 Reg 3, offset: 0x9A0 */ 248 __IO uint32_t MAC_LAYER3_ADDR1_REG3; /**< MAC Layer 3 Address 1 Reg 3, offset: 0x9A4 */ 249 __IO uint32_t MAC_LAYER3_ADDR2_REG3; /**< MAC Layer 3 Address 2 Reg 3, offset: 0x9A8 */ 250 __IO uint32_t MAC_LAYER3_ADDR3_REG3; /**< MAC Layer 3 Address 3 Reg 3, offset: 0x9AC */ 251 uint8_t RESERVED_26[336]; 252 __IO uint32_t MAC_TIMESTAMP_CONTROL; /**< MAC Timestamp Control, offset: 0xB00 */ 253 __IO uint32_t MAC_SUB_SECOND_INCREMENT; /**< MAC Sub Second Increment, offset: 0xB04 */ 254 __I uint32_t MAC_SYSTEM_TIME_SECONDS; /**< MAC System Time In Seconds, offset: 0xB08 */ 255 __I uint32_t MAC_SYSTEM_TIME_NANOSECONDS; /**< MAC System Time In Nanoseconds, offset: 0xB0C */ 256 __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE; /**< MAC System Time Seconds Update, offset: 0xB10 */ 257 __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< MAC System Time Nanoseconds Update, offset: 0xB14 */ 258 __IO uint32_t MAC_TIMESTAMP_ADDEND; /**< MAC Timestamp Addend, offset: 0xB18 */ 259 __IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< MAC System Time Higher Word In Seconds, offset: 0xB1C */ 260 __I uint32_t MAC_TIMESTAMP_STATUS; /**< MAC Timestamp Status, offset: 0xB20 */ 261 uint8_t RESERVED_27[12]; 262 __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< MAC Transmit Timestamp Status In Nanoseconds, offset: 0xB30 */ 263 __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< MAC Transmit Timestamp Status In Seconds, offset: 0xB34 */ 264 uint8_t RESERVED_28[24]; 265 __IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR; /**< MAC Timestamp Ingress Asymmetry Correction, offset: 0xB50 */ 266 __IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR; /**< MAC Timestamp Egress Asymmetry Correction, offset: 0xB54 */ 267 __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< MAC Timestamp Ingress Correction In Nanoseconds, offset: 0xB58 */ 268 __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< MAC Timestamp Egress Correction In Nanoseconds, offset: 0xB5C */ 269 __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< MAC Timestamp Ingress Correction In Subnanoseconds, offset: 0xB60 */ 270 __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< MAC Timestamp Engress Correction In Subnanoseconds, offset: 0xB64 */ 271 __I uint32_t MAC_TIMESTAMP_INGRESS_LATENCY; /**< MAC Timestamp Ingress Latency, offset: 0xB68 */ 272 __I uint32_t MAC_TIMESTAMP_EGRESS_LATENCY; /**< MAC Timestamp Egress Latecy, offset: 0xB6C */ 273 __IO uint32_t MAC_PPS_CONTROL; /**< MAC PPS Control, offset: 0xB70 */ 274 uint8_t RESERVED_29[12]; 275 __IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS; /**< MAC PPS0 Target Time In Seconds, offset: 0xB80 */ 276 __IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS; /**< MAC PPS0 Target Time In Nanoseconds, offset: 0xB84 */ 277 __IO uint32_t MAC_PPS0_INTERVAL; /**< MAC PPS0 Interval, offset: 0xB88 */ 278 __IO uint32_t MAC_PPS0_WIDTH; /**< MAC PPS0 Width, offset: 0xB8C */ 279 __IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS; /**< MAC PPS1 Target Time In Seconds, offset: 0xB90 */ 280 __IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS; /**< MAC PPS1 Target Time In Nanoseconds, offset: 0xB94 */ 281 __IO uint32_t MAC_PPS1_INTERVAL; /**< MAC PPS1 Interval, offset: 0xB98 */ 282 __IO uint32_t MAC_PPS1_WIDTH; /**< MAC PPS1 Width, offset: 0xB9C */ 283 __IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS; /**< MAC PPS2 Taget Time In Seconds, offset: 0xBA0 */ 284 __IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS; /**< MAC PPS2 Target Time In Nanoseconds, offset: 0xBA4 */ 285 __IO uint32_t MAC_PPS2_INTERVAL; /**< MAC PPS2 Interval, offset: 0xBA8 */ 286 __IO uint32_t MAC_PPS2_WIDTH; /**< MAC PPS2 Width, offset: 0xBAC */ 287 __IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS; /**< MAC PPS3 Target Time In Seconds, offset: 0xBB0 */ 288 __IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS; /**< MAC PPS3 Target Time In Nanoseconds, offset: 0xBB4 */ 289 __IO uint32_t MAC_PPS3_INTERVAL; /**< MAC PPS3 Interval, offset: 0xBB8 */ 290 __IO uint32_t MAC_PPS3_WIDTH; /**< MAC PPS3 Width, offset: 0xBBC */ 291 uint8_t RESERVED_30[64]; 292 __IO uint32_t MTL_OPERATION_MODE; /**< MTL Operation Mode, offset: 0xC00 */ 293 uint8_t RESERVED_31[4]; 294 __IO uint32_t MTL_DBG_CTL; /**< MTL Debug Control, offset: 0xC08 */ 295 __IO uint32_t MTL_DBG_STS; /**< MTL Debug Status, offset: 0xC0C */ 296 __IO uint32_t MTL_FIFO_DEBUG_DATA; /**< MTL FIFO Debug Data, offset: 0xC10 */ 297 uint8_t RESERVED_32[12]; 298 __I uint32_t MTL_INTERRUPT_STATUS; /**< MTL Interrupt Status, offset: 0xC20 */ 299 uint8_t RESERVED_33[12]; 300 __IO uint32_t MTL_RXQ_DMA_MAP0; /**< MTL Receive Queue DMA Map 0, offset: 0xC30 */ 301 uint8_t RESERVED_34[12]; 302 __IO uint32_t MTL_TBS_CTRL; /**< MTL TBS Control, offset: 0xC40 */ 303 uint8_t RESERVED_35[12]; 304 __IO uint32_t MTL_EST_CONTROL; /**< MTL EST Control, offset: 0xC50 */ 305 uint8_t RESERVED_36[4]; 306 __IO uint32_t MTL_EST_STATUS; /**< MTL EST Status, offset: 0xC58 */ 307 uint8_t RESERVED_37[4]; 308 __IO uint32_t MTL_EST_SCH_ERROR; /**< MTL EST Scheduling Error, offset: 0xC60 */ 309 __IO uint32_t MTL_EST_FRM_SIZE_ERROR; /**< MTL EST Frame Size Error, offset: 0xC64 */ 310 __I uint32_t MTL_EST_FRM_SIZE_CAPTURE; /**< MTL EST Frame Size Capture, offset: 0xC68 */ 311 uint8_t RESERVED_38[4]; 312 __IO uint32_t MTL_EST_INTR_ENABLE; /**< MTL EST Interrupt Enable, offset: 0xC70 */ 313 uint8_t RESERVED_39[12]; 314 __IO uint32_t MTL_EST_GCL_CONTROL; /**< MTL EST GCL Control, offset: 0xC80 */ 315 __IO uint32_t MTL_EST_GCL_DATA; /**< MTL EST GCL Data, offset: 0xC84 */ 316 uint8_t RESERVED_40[8]; 317 __IO uint32_t MTL_FPE_CTRL_STS; /**< MTL FPE Control Status, offset: 0xC90 */ 318 __IO uint32_t MTL_FPE_ADVANCE; /**< MTL FPE Advance, offset: 0xC94 */ 319 uint8_t RESERVED_41[8]; 320 __IO uint32_t MTL_RXP_CONTROL_STATUS; /**< MTL Rx Parser Control Status, offset: 0xCA0 */ 321 __IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS; /**< MTL Rx Parser Interrupt Control Status, offset: 0xCA4 */ 322 __I uint32_t MTL_RXP_DROP_CNT; /**< MTL Rx Parser Drop Count, offset: 0xCA8 */ 323 __I uint32_t MTL_RXP_ERROR_CNT; /**< MTL Rx Parser Error Count, offset: 0xCAC */ 324 __IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< MTL Rx Parser Indirect Access Control Status, offset: 0xCB0 */ 325 __I uint32_t MTL_RXP_INDIRECT_ACC_DATA; /**< MTL Rx Parser Indirect Access Data, offset: 0xCB4 */ 326 uint8_t RESERVED_42[8]; 327 __IO uint32_t MTL_ECC_CONTROL; /**< MTL ECC Control, offset: 0xCC0 */ 328 __I uint32_t MTL_SAFETY_INTERRUPT_STATUS; /**< MTL Safety Interript Status, offset: 0xCC4 */ 329 __IO uint32_t MTL_ECC_INTERRUPT_ENABLE; /**< MTL ECC Interrupt Enable, offset: 0xCC8 */ 330 __IO uint32_t MTL_ECC_INTERRUPT_STATUS; /**< MTL ECC Interrupt Status, offset: 0xCCC */ 331 __IO uint32_t MTL_ECC_ERR_STS_RCTL; /**< MTL ECC Error Status, offset: 0xCD0 */ 332 __I uint32_t MTL_ECC_ERR_ADDR_STATUS; /**< MTL ECC Error Adress Status, offset: 0xCD4 */ 333 __I uint32_t MTL_ECC_ERR_CNTR_STATUS; /**< MTL ECC Error Control Status, offset: 0xCD8 */ 334 uint8_t RESERVED_43[4]; 335 __IO uint32_t MTL_DPP_CONTROL; /**< MTL DPP Control, offset: 0xCE0 */ 336 uint8_t RESERVED_44[28]; 337 __IO uint32_t MTL_TXQ0_OPERATION_MODE; /**< MTL Tx Queue 0 Operation Mode, offset: 0xD00 */ 338 __I uint32_t MTL_TXQ0_UNDERFLOW; /**< MTL Tx Queue 0 Underflow, offset: 0xD04 */ 339 __I uint32_t MTL_TXQ0_DEBUG; /**< MTL Tx Queue 0 Debug, offset: 0xD08 */ 340 uint8_t RESERVED_45[8]; 341 __I uint32_t MTL_TXQ0_ETS_STATUS; /**< MTL Tx Queue 0 ETS Status, offset: 0xD14 */ 342 __IO uint32_t MTL_TXQ0_QUANTUM_WEIGHT; /**< MTL Tx Queue Quantum Weight, offset: 0xD18 */ 343 uint8_t RESERVED_46[16]; 344 __IO uint32_t MTL_Q0_INTERRUPT_CONTROL_STATUS; /**< MTL Queue 0 Interrupt Control Status, offset: 0xD2C */ 345 __IO uint32_t MTL_RXQ0_OPERATION_MODE; /**< MTL Rx Queue 0 Operation Mode, offset: 0xD30 */ 346 __I uint32_t MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT; /**< MTL Rx Queue Missed Packet Overflow Count, offset: 0xD34 */ 347 __I uint32_t MTL_RXQ0_DEBUG; /**< MTL Rx Queue 0 Debug, offset: 0xD38 */ 348 __IO uint32_t MTL_RXQ0_CONTROL; /**< MTL Rx Queue 0 Control 0, offset: 0xD3C */ 349 __IO uint32_t MTL_TXQ1_OPERATION_MODE; /**< MTL Tx Queue 1 Operation Mode, offset: 0xD40 */ 350 __I uint32_t MTL_TXQ1_UNDERFLOW; /**< MTL Tx Queue 1 Underflow, offset: 0xD44 */ 351 __I uint32_t MTL_TXQ1_DEBUG; /**< MTL Tx Queue 1 Debug, offset: 0xD48 */ 352 uint8_t RESERVED_47[4]; 353 __IO uint32_t MTL_TXQ1_ETS_CONTROL; /**< MTL Tx Queue 1 ETS Control, offset: 0xD50 */ 354 __I uint32_t MTL_TXQ1_ETS_STATUS; /**< MTL Tx Queue 1 ETS Status, offset: 0xD54 */ 355 __IO uint32_t MTL_TXQ1_QUANTUM_WEIGHT; /**< MTL Tx Queue 1 Quantum Weight, offset: 0xD58 */ 356 __IO uint32_t MTL_TXQ1_SENDSLOPECREDIT; /**< MTL Tx Queue 1 Sendslope Credit, offset: 0xD5C */ 357 __IO uint32_t MTL_TXQ1_HICREDIT; /**< MTL Tx Queue 1 HiCredit, offset: 0xD60 */ 358 __IO uint32_t MTL_TXQ1_LOCREDIT; /**< MTL Tx Queue 1 LoCredit, offset: 0xD64 */ 359 uint8_t RESERVED_48[4]; 360 __IO uint32_t MTL_Q1_INTERRUPT_CONTROL_STATUS; /**< MTL Queue 1 Interrupt Control Status, offset: 0xD6C */ 361 __IO uint32_t MTL_RXQ1_OPERATION_MODE; /**< MTL Rx Queue 1 Operation Mode, offset: 0xD70 */ 362 __I uint32_t MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT; /**< MTL Rx Queue 1 Missed Packet Overflow Counter, offset: 0xD74 */ 363 __I uint32_t MTL_RXQ1_DEBUG; /**< MTL Rx Queue 1 Debug, offset: 0xD78 */ 364 __IO uint32_t MTL_RXQ1_CONTROL; /**< MTL Rx Queue 1 Control, offset: 0xD7C */ 365 uint8_t RESERVED_49[640]; 366 __IO uint32_t DMA_MODE; /**< DMA Mode, offset: 0x1000 */ 367 __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus Mode, offset: 0x1004 */ 368 __I uint32_t DMA_INTERRUPT_STATUS; /**< DMA Interrupt Status, offset: 0x1008 */ 369 __I uint32_t DMA_DEBUG_STATUS0; /**< DMA Debug Status 0, offset: 0x100C */ 370 uint8_t RESERVED_50[64]; 371 __IO uint32_t DMA_TBS_CTRL; /**< DMA TBS Control, offset: 0x1050 */ 372 uint8_t RESERVED_51[44]; 373 __I uint32_t DMA_SAFETY_INTERRUPT_STATUS; /**< DMA Safety Interrupt Status, offset: 0x1080 */ 374 uint8_t RESERVED_52[124]; 375 __IO uint32_t DMA_CH0_CONTROL; /**< DMA Channel 0 Control, offset: 0x1100 */ 376 __IO uint32_t DMA_CH0_TX_CONTROL; /**< DMA Channel Tx Control, offset: 0x1104 */ 377 __IO uint32_t DMA_CH0_RX_CONTROL; /**< DMA Channel Rx Control, offset: 0x1108 */ 378 uint8_t RESERVED_53[8]; 379 __IO uint32_t DMA_CH0_TXDESC_LIST_ADDRESS; /**< DMA Channel 0 Tx Descriptor List Address, offset: 0x1114 */ 380 uint8_t RESERVED_54[4]; 381 __IO uint32_t DMA_CH0_RXDESC_LIST_ADDRESS; /**< DMA Channel 0 Rx Descriptor List Address, offset: 0x111C */ 382 __IO uint32_t DMA_CH0_TXDESC_TAIL_POINTER; /**< DMA Channel 0 Tx Descriptor Tail Pointer, offset: 0x1120 */ 383 uint8_t RESERVED_55[4]; 384 __IO uint32_t DMA_CH0_RXDESC_TAIL_POINTER; /**< DMA Channeli 0 Rx Descriptor List Pointer, offset: 0x1128 */ 385 __IO uint32_t DMA_CH0_TXDESC_RING_LENGTH; /**< DMA Channel 0 Tx Descriptor Ring Length, offset: 0x112C */ 386 __IO uint32_t DMA_CH0_RXDESC_RING_LENGTH; /**< DMA Channel 0 Rx Descriptor Ring Length, offset: 0x1130 */ 387 __IO uint32_t DMA_CH0_INTERRUPT_ENABLE; /**< DMA Channel 0 Interrupt Enable, offset: 0x1134 */ 388 __IO uint32_t DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER; /**< DMA Channel 0 Rx Interrupt Watchdog Timer, offset: 0x1138 */ 389 __IO uint32_t DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS; /**< DMA Channel 0 Slot Function Control Status, offset: 0x113C */ 390 uint8_t RESERVED_56[4]; 391 __I uint32_t DMA_CH0_CURRENT_APP_TXDESC; /**< DMA Channel 0 Current Application Transmit Descriptor, offset: 0x1144 */ 392 uint8_t RESERVED_57[4]; 393 __I uint32_t DMA_CH0_CURRENT_APP_RXDESC; /**< DMA Channel 0 Current Application Receive Descriptor, offset: 0x114C */ 394 uint8_t RESERVED_58[4]; 395 __I uint32_t DMA_CH0_CURRENT_APP_TXBUFFER; /**< DMA Channel 0 Current Application Transmit Descriptor, offset: 0x1154 */ 396 uint8_t RESERVED_59[4]; 397 __I uint32_t DMA_CH0_CURRENT_APP_RXBUFFER; /**< DMA Channel 0 Current Application Receive Buffer, offset: 0x115C */ 398 __IO uint32_t DMA_CH0_STATUS; /**< DMA Channel 0 Status, offset: 0x1160 */ 399 __I uint32_t DMA_CH0_MISS_FRAME_CNT; /**< DMA Channel 0 Miss Frame Counter, offset: 0x1164 */ 400 __I uint32_t DMA_CH0_RXP_ACCEPT_CNT; /**< DMA Channel 0 Rx Parser Accept Count, offset: 0x1168 */ 401 __I uint32_t DMA_CH0_RX_ERI_CNT; /**< DMA Channel 0 Rx ERI Count, offset: 0x116C */ 402 uint8_t RESERVED_60[16]; 403 __IO uint32_t DMA_CH1_CONTROL; /**< DMA Channel 1 Control, offset: 0x1180 */ 404 __IO uint32_t DMA_CH1_TX_CONTROL; /**< DMA Channel 1 Tx Control, offset: 0x1184 */ 405 __IO uint32_t DMA_CH1_RX_CONTROL; /**< DMA Channel 1 Rx Control, offset: 0x1188 */ 406 uint8_t RESERVED_61[8]; 407 __IO uint32_t DMA_CH1_TXDESC_LIST_ADDRESS; /**< DMA Channel 1 Tx Descriptor List Address, offset: 0x1194 */ 408 uint8_t RESERVED_62[4]; 409 __IO uint32_t DMA_CH1_RXDESC_LIST_ADDRESS; /**< DMA Channel 1 Rx Descriptor List Address, offset: 0x119C */ 410 __IO uint32_t DMA_CH1_TXDESC_TAIL_POINTER; /**< DMA Channel 1 Tx Descriptor Tail Pointer, offset: 0x11A0 */ 411 uint8_t RESERVED_63[4]; 412 __IO uint32_t DMA_CH1_RXDESC_TAIL_POINTER; /**< DMA Channel 1 Rx Descriptor Tail Pointer, offset: 0x11A8 */ 413 __IO uint32_t DMA_CH1_TXDESC_RING_LENGTH; /**< DMA Channel 1 Tx Descriptor Ring Length, offset: 0x11AC */ 414 __IO uint32_t DMA_CH1_RXDESC_RING_LENGTH; /**< DMA Channel 1 Rx Descriptor Ring Length, offset: 0x11B0 */ 415 __IO uint32_t DMA_CH1_INTERRUPT_ENABLE; /**< DMA Channel 1 Interrupt Enable, offset: 0x11B4 */ 416 __IO uint32_t DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER; /**< DMA Channel 1 Rx Interrupt Watchdog Timer, offset: 0x11B8 */ 417 __IO uint32_t DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS; /**< DMA Channel 1 Slot Function Control Status, offset: 0x11BC */ 418 uint8_t RESERVED_64[4]; 419 __I uint32_t DMA_CH1_CURRENT_APP_TXDESC; /**< DMA Channel 1 Current Application Transmit Descriptor, offset: 0x11C4 */ 420 uint8_t RESERVED_65[4]; 421 __I uint32_t DMA_CH1_CURRENT_APP_RXDESC; /**< DMA Channel 1 Current Application Receive Descriptor, offset: 0x11CC */ 422 uint8_t RESERVED_66[4]; 423 __I uint32_t DMA_CH1_CURRENT_APP_TXBUFFER; /**< DMA Channel 1 Current Application Transmit Buffer, offset: 0x11D4 */ 424 uint8_t RESERVED_67[4]; 425 __I uint32_t DMA_CH1_CURRENT_APP_RXBUFFER; /**< DMA Channel 1 Current Application Receive Buffer, offset: 0x11DC */ 426 __IO uint32_t DMA_CH1_STATUS; /**< DMA Channel 1 Status, offset: 0x11E0 */ 427 __I uint32_t DMA_CH1_MISS_FRAME_CNT; /**< DMA Channel 1 Miss Frame Counter, offset: 0x11E4 */ 428 __I uint32_t DMA_CH1_RXP_ACCEPT_CNT; /**< DMA Channel 1 Rx Parser Accept Count, offset: 0x11E8 */ 429 __I uint32_t DMA_CH1_RX_ERI_CNT; /**< DMA Channel 1 Rx ERI Count, offset: 0x11EC */ 430 } EMAC_Type, *EMAC_MemMapPtr; 431 432 /** Number of instances of the EMAC module. */ 433 #define EMAC_INSTANCE_COUNT (1u) 434 435 /* EMAC - Peripheral instance base addresses */ 436 /** Peripheral EMAC base address */ 437 #define IP_EMAC_BASE (0x40480000u) 438 /** Peripheral EMAC base pointer */ 439 #define IP_EMAC ((EMAC_Type *)IP_EMAC_BASE) 440 /** Array initializer of EMAC peripheral base addresses */ 441 #define IP_EMAC_BASE_ADDRS { IP_EMAC_BASE } 442 /** Array initializer of EMAC peripheral base pointers */ 443 #define IP_EMAC_BASE_PTRS { IP_EMAC } 444 445 /* ---------------------------------------------------------------------------- 446 -- EMAC Register Masks 447 ---------------------------------------------------------------------------- */ 448 449 /*! 450 * @addtogroup EMAC_Register_Masks EMAC Register Masks 451 * @{ 452 */ 453 454 /*! @name MAC_CONFIGURATION - MAC Configuration */ 455 /*! @{ */ 456 457 #define EMAC_MAC_CONFIGURATION_RE_MASK (0x1U) 458 #define EMAC_MAC_CONFIGURATION_RE_SHIFT (0U) 459 #define EMAC_MAC_CONFIGURATION_RE_WIDTH (1U) 460 #define EMAC_MAC_CONFIGURATION_RE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_RE_SHIFT)) & EMAC_MAC_CONFIGURATION_RE_MASK) 461 462 #define EMAC_MAC_CONFIGURATION_TE_MASK (0x2U) 463 #define EMAC_MAC_CONFIGURATION_TE_SHIFT (1U) 464 #define EMAC_MAC_CONFIGURATION_TE_WIDTH (1U) 465 #define EMAC_MAC_CONFIGURATION_TE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_TE_SHIFT)) & EMAC_MAC_CONFIGURATION_TE_MASK) 466 467 #define EMAC_MAC_CONFIGURATION_PRELEN_MASK (0xCU) 468 #define EMAC_MAC_CONFIGURATION_PRELEN_SHIFT (2U) 469 #define EMAC_MAC_CONFIGURATION_PRELEN_WIDTH (2U) 470 #define EMAC_MAC_CONFIGURATION_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT)) & EMAC_MAC_CONFIGURATION_PRELEN_MASK) 471 472 #define EMAC_MAC_CONFIGURATION_DC_MASK (0x10U) 473 #define EMAC_MAC_CONFIGURATION_DC_SHIFT (4U) 474 #define EMAC_MAC_CONFIGURATION_DC_WIDTH (1U) 475 #define EMAC_MAC_CONFIGURATION_DC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_DC_SHIFT)) & EMAC_MAC_CONFIGURATION_DC_MASK) 476 477 #define EMAC_MAC_CONFIGURATION_BL_MASK (0x60U) 478 #define EMAC_MAC_CONFIGURATION_BL_SHIFT (5U) 479 #define EMAC_MAC_CONFIGURATION_BL_WIDTH (2U) 480 #define EMAC_MAC_CONFIGURATION_BL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_BL_SHIFT)) & EMAC_MAC_CONFIGURATION_BL_MASK) 481 482 #define EMAC_MAC_CONFIGURATION_DR_MASK (0x100U) 483 #define EMAC_MAC_CONFIGURATION_DR_SHIFT (8U) 484 #define EMAC_MAC_CONFIGURATION_DR_WIDTH (1U) 485 #define EMAC_MAC_CONFIGURATION_DR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_DR_SHIFT)) & EMAC_MAC_CONFIGURATION_DR_MASK) 486 487 #define EMAC_MAC_CONFIGURATION_DCRS_MASK (0x200U) 488 #define EMAC_MAC_CONFIGURATION_DCRS_SHIFT (9U) 489 #define EMAC_MAC_CONFIGURATION_DCRS_WIDTH (1U) 490 #define EMAC_MAC_CONFIGURATION_DCRS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_DCRS_SHIFT)) & EMAC_MAC_CONFIGURATION_DCRS_MASK) 491 492 #define EMAC_MAC_CONFIGURATION_DO_MASK (0x400U) 493 #define EMAC_MAC_CONFIGURATION_DO_SHIFT (10U) 494 #define EMAC_MAC_CONFIGURATION_DO_WIDTH (1U) 495 #define EMAC_MAC_CONFIGURATION_DO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_DO_SHIFT)) & EMAC_MAC_CONFIGURATION_DO_MASK) 496 497 #define EMAC_MAC_CONFIGURATION_ECRSFD_MASK (0x800U) 498 #define EMAC_MAC_CONFIGURATION_ECRSFD_SHIFT (11U) 499 #define EMAC_MAC_CONFIGURATION_ECRSFD_WIDTH (1U) 500 #define EMAC_MAC_CONFIGURATION_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_ECRSFD_SHIFT)) & EMAC_MAC_CONFIGURATION_ECRSFD_MASK) 501 502 #define EMAC_MAC_CONFIGURATION_LM_MASK (0x1000U) 503 #define EMAC_MAC_CONFIGURATION_LM_SHIFT (12U) 504 #define EMAC_MAC_CONFIGURATION_LM_WIDTH (1U) 505 #define EMAC_MAC_CONFIGURATION_LM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_LM_SHIFT)) & EMAC_MAC_CONFIGURATION_LM_MASK) 506 507 #define EMAC_MAC_CONFIGURATION_DM_MASK (0x2000U) 508 #define EMAC_MAC_CONFIGURATION_DM_SHIFT (13U) 509 #define EMAC_MAC_CONFIGURATION_DM_WIDTH (1U) 510 #define EMAC_MAC_CONFIGURATION_DM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_DM_SHIFT)) & EMAC_MAC_CONFIGURATION_DM_MASK) 511 512 #define EMAC_MAC_CONFIGURATION_FES_MASK (0x4000U) 513 #define EMAC_MAC_CONFIGURATION_FES_SHIFT (14U) 514 #define EMAC_MAC_CONFIGURATION_FES_WIDTH (1U) 515 #define EMAC_MAC_CONFIGURATION_FES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_FES_SHIFT)) & EMAC_MAC_CONFIGURATION_FES_MASK) 516 517 #define EMAC_MAC_CONFIGURATION_PS_MASK (0x8000U) 518 #define EMAC_MAC_CONFIGURATION_PS_SHIFT (15U) 519 #define EMAC_MAC_CONFIGURATION_PS_WIDTH (1U) 520 #define EMAC_MAC_CONFIGURATION_PS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_PS_SHIFT)) & EMAC_MAC_CONFIGURATION_PS_MASK) 521 522 #define EMAC_MAC_CONFIGURATION_JE_MASK (0x10000U) 523 #define EMAC_MAC_CONFIGURATION_JE_SHIFT (16U) 524 #define EMAC_MAC_CONFIGURATION_JE_WIDTH (1U) 525 #define EMAC_MAC_CONFIGURATION_JE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_JE_SHIFT)) & EMAC_MAC_CONFIGURATION_JE_MASK) 526 527 #define EMAC_MAC_CONFIGURATION_JD_MASK (0x20000U) 528 #define EMAC_MAC_CONFIGURATION_JD_SHIFT (17U) 529 #define EMAC_MAC_CONFIGURATION_JD_WIDTH (1U) 530 #define EMAC_MAC_CONFIGURATION_JD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_JD_SHIFT)) & EMAC_MAC_CONFIGURATION_JD_MASK) 531 532 #define EMAC_MAC_CONFIGURATION_WD_MASK (0x80000U) 533 #define EMAC_MAC_CONFIGURATION_WD_SHIFT (19U) 534 #define EMAC_MAC_CONFIGURATION_WD_WIDTH (1U) 535 #define EMAC_MAC_CONFIGURATION_WD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_WD_SHIFT)) & EMAC_MAC_CONFIGURATION_WD_MASK) 536 537 #define EMAC_MAC_CONFIGURATION_ACS_MASK (0x100000U) 538 #define EMAC_MAC_CONFIGURATION_ACS_SHIFT (20U) 539 #define EMAC_MAC_CONFIGURATION_ACS_WIDTH (1U) 540 #define EMAC_MAC_CONFIGURATION_ACS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_ACS_SHIFT)) & EMAC_MAC_CONFIGURATION_ACS_MASK) 541 542 #define EMAC_MAC_CONFIGURATION_CST_MASK (0x200000U) 543 #define EMAC_MAC_CONFIGURATION_CST_SHIFT (21U) 544 #define EMAC_MAC_CONFIGURATION_CST_WIDTH (1U) 545 #define EMAC_MAC_CONFIGURATION_CST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_CST_SHIFT)) & EMAC_MAC_CONFIGURATION_CST_MASK) 546 547 #define EMAC_MAC_CONFIGURATION_S2KP_MASK (0x400000U) 548 #define EMAC_MAC_CONFIGURATION_S2KP_SHIFT (22U) 549 #define EMAC_MAC_CONFIGURATION_S2KP_WIDTH (1U) 550 #define EMAC_MAC_CONFIGURATION_S2KP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_S2KP_SHIFT)) & EMAC_MAC_CONFIGURATION_S2KP_MASK) 551 552 #define EMAC_MAC_CONFIGURATION_GPSLCE_MASK (0x800000U) 553 #define EMAC_MAC_CONFIGURATION_GPSLCE_SHIFT (23U) 554 #define EMAC_MAC_CONFIGURATION_GPSLCE_WIDTH (1U) 555 #define EMAC_MAC_CONFIGURATION_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_GPSLCE_SHIFT)) & EMAC_MAC_CONFIGURATION_GPSLCE_MASK) 556 557 #define EMAC_MAC_CONFIGURATION_IPG_MASK (0x7000000U) 558 #define EMAC_MAC_CONFIGURATION_IPG_SHIFT (24U) 559 #define EMAC_MAC_CONFIGURATION_IPG_WIDTH (3U) 560 #define EMAC_MAC_CONFIGURATION_IPG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_IPG_SHIFT)) & EMAC_MAC_CONFIGURATION_IPG_MASK) 561 562 #define EMAC_MAC_CONFIGURATION_IPC_MASK (0x8000000U) 563 #define EMAC_MAC_CONFIGURATION_IPC_SHIFT (27U) 564 #define EMAC_MAC_CONFIGURATION_IPC_WIDTH (1U) 565 #define EMAC_MAC_CONFIGURATION_IPC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_IPC_SHIFT)) & EMAC_MAC_CONFIGURATION_IPC_MASK) 566 567 #define EMAC_MAC_CONFIGURATION_SARC_MASK (0x70000000U) 568 #define EMAC_MAC_CONFIGURATION_SARC_SHIFT (28U) 569 #define EMAC_MAC_CONFIGURATION_SARC_WIDTH (3U) 570 #define EMAC_MAC_CONFIGURATION_SARC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CONFIGURATION_SARC_SHIFT)) & EMAC_MAC_CONFIGURATION_SARC_MASK) 571 /*! @} */ 572 573 /*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration */ 574 /*! @{ */ 575 576 #define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU) 577 #define EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U) 578 #define EMAC_MAC_EXT_CONFIGURATION_GPSL_WIDTH (14U) 579 #define EMAC_MAC_EXT_CONFIGURATION_GPSL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK) 580 581 #define EMAC_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U) 582 #define EMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U) 583 #define EMAC_MAC_EXT_CONFIGURATION_DCRCC_WIDTH (1U) 584 #define EMAC_MAC_EXT_CONFIGURATION_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & EMAC_MAC_EXT_CONFIGURATION_DCRCC_MASK) 585 586 #define EMAC_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U) 587 #define EMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U) 588 #define EMAC_MAC_EXT_CONFIGURATION_SPEN_WIDTH (1U) 589 #define EMAC_MAC_EXT_CONFIGURATION_SPEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & EMAC_MAC_EXT_CONFIGURATION_SPEN_MASK) 590 591 #define EMAC_MAC_EXT_CONFIGURATION_USP_MASK (0x40000U) 592 #define EMAC_MAC_EXT_CONFIGURATION_USP_SHIFT (18U) 593 #define EMAC_MAC_EXT_CONFIGURATION_USP_WIDTH (1U) 594 #define EMAC_MAC_EXT_CONFIGURATION_USP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_EXT_CONFIGURATION_USP_SHIFT)) & EMAC_MAC_EXT_CONFIGURATION_USP_MASK) 595 596 #define EMAC_MAC_EXT_CONFIGURATION_PDC_MASK (0x80000U) 597 #define EMAC_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U) 598 #define EMAC_MAC_EXT_CONFIGURATION_PDC_WIDTH (1U) 599 #define EMAC_MAC_EXT_CONFIGURATION_PDC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & EMAC_MAC_EXT_CONFIGURATION_PDC_MASK) 600 601 #define EMAC_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U) 602 #define EMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U) 603 #define EMAC_MAC_EXT_CONFIGURATION_EIPGEN_WIDTH (1U) 604 #define EMAC_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & EMAC_MAC_EXT_CONFIGURATION_EIPGEN_MASK) 605 606 #define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U) 607 #define EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U) 608 #define EMAC_MAC_EXT_CONFIGURATION_EIPG_WIDTH (5U) 609 #define EMAC_MAC_EXT_CONFIGURATION_EIPG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK) 610 /*! @} */ 611 612 /*! @name MAC_PACKET_FILTER - MAC Packet Filter */ 613 /*! @{ */ 614 615 #define EMAC_MAC_PACKET_FILTER_PR_MASK (0x1U) 616 #define EMAC_MAC_PACKET_FILTER_PR_SHIFT (0U) 617 #define EMAC_MAC_PACKET_FILTER_PR_WIDTH (1U) 618 #define EMAC_MAC_PACKET_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_PR_SHIFT)) & EMAC_MAC_PACKET_FILTER_PR_MASK) 619 620 #define EMAC_MAC_PACKET_FILTER_HUC_MASK (0x2U) 621 #define EMAC_MAC_PACKET_FILTER_HUC_SHIFT (1U) 622 #define EMAC_MAC_PACKET_FILTER_HUC_WIDTH (1U) 623 #define EMAC_MAC_PACKET_FILTER_HUC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_HUC_SHIFT)) & EMAC_MAC_PACKET_FILTER_HUC_MASK) 624 625 #define EMAC_MAC_PACKET_FILTER_HMC_MASK (0x4U) 626 #define EMAC_MAC_PACKET_FILTER_HMC_SHIFT (2U) 627 #define EMAC_MAC_PACKET_FILTER_HMC_WIDTH (1U) 628 #define EMAC_MAC_PACKET_FILTER_HMC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_HMC_SHIFT)) & EMAC_MAC_PACKET_FILTER_HMC_MASK) 629 630 #define EMAC_MAC_PACKET_FILTER_DAIF_MASK (0x8U) 631 #define EMAC_MAC_PACKET_FILTER_DAIF_SHIFT (3U) 632 #define EMAC_MAC_PACKET_FILTER_DAIF_WIDTH (1U) 633 #define EMAC_MAC_PACKET_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_DAIF_SHIFT)) & EMAC_MAC_PACKET_FILTER_DAIF_MASK) 634 635 #define EMAC_MAC_PACKET_FILTER_PM_MASK (0x10U) 636 #define EMAC_MAC_PACKET_FILTER_PM_SHIFT (4U) 637 #define EMAC_MAC_PACKET_FILTER_PM_WIDTH (1U) 638 #define EMAC_MAC_PACKET_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_PM_SHIFT)) & EMAC_MAC_PACKET_FILTER_PM_MASK) 639 640 #define EMAC_MAC_PACKET_FILTER_DBF_MASK (0x20U) 641 #define EMAC_MAC_PACKET_FILTER_DBF_SHIFT (5U) 642 #define EMAC_MAC_PACKET_FILTER_DBF_WIDTH (1U) 643 #define EMAC_MAC_PACKET_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_DBF_SHIFT)) & EMAC_MAC_PACKET_FILTER_DBF_MASK) 644 645 #define EMAC_MAC_PACKET_FILTER_PCF_MASK (0xC0U) 646 #define EMAC_MAC_PACKET_FILTER_PCF_SHIFT (6U) 647 #define EMAC_MAC_PACKET_FILTER_PCF_WIDTH (2U) 648 #define EMAC_MAC_PACKET_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_PCF_SHIFT)) & EMAC_MAC_PACKET_FILTER_PCF_MASK) 649 650 #define EMAC_MAC_PACKET_FILTER_SAIF_MASK (0x100U) 651 #define EMAC_MAC_PACKET_FILTER_SAIF_SHIFT (8U) 652 #define EMAC_MAC_PACKET_FILTER_SAIF_WIDTH (1U) 653 #define EMAC_MAC_PACKET_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_SAIF_SHIFT)) & EMAC_MAC_PACKET_FILTER_SAIF_MASK) 654 655 #define EMAC_MAC_PACKET_FILTER_SAF_MASK (0x200U) 656 #define EMAC_MAC_PACKET_FILTER_SAF_SHIFT (9U) 657 #define EMAC_MAC_PACKET_FILTER_SAF_WIDTH (1U) 658 #define EMAC_MAC_PACKET_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_SAF_SHIFT)) & EMAC_MAC_PACKET_FILTER_SAF_MASK) 659 660 #define EMAC_MAC_PACKET_FILTER_HPF_MASK (0x400U) 661 #define EMAC_MAC_PACKET_FILTER_HPF_SHIFT (10U) 662 #define EMAC_MAC_PACKET_FILTER_HPF_WIDTH (1U) 663 #define EMAC_MAC_PACKET_FILTER_HPF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_HPF_SHIFT)) & EMAC_MAC_PACKET_FILTER_HPF_MASK) 664 665 #define EMAC_MAC_PACKET_FILTER_VTFE_MASK (0x10000U) 666 #define EMAC_MAC_PACKET_FILTER_VTFE_SHIFT (16U) 667 #define EMAC_MAC_PACKET_FILTER_VTFE_WIDTH (1U) 668 #define EMAC_MAC_PACKET_FILTER_VTFE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_VTFE_SHIFT)) & EMAC_MAC_PACKET_FILTER_VTFE_MASK) 669 670 #define EMAC_MAC_PACKET_FILTER_IPFE_MASK (0x100000U) 671 #define EMAC_MAC_PACKET_FILTER_IPFE_SHIFT (20U) 672 #define EMAC_MAC_PACKET_FILTER_IPFE_WIDTH (1U) 673 #define EMAC_MAC_PACKET_FILTER_IPFE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_IPFE_SHIFT)) & EMAC_MAC_PACKET_FILTER_IPFE_MASK) 674 675 #define EMAC_MAC_PACKET_FILTER_DNTU_MASK (0x200000U) 676 #define EMAC_MAC_PACKET_FILTER_DNTU_SHIFT (21U) 677 #define EMAC_MAC_PACKET_FILTER_DNTU_WIDTH (1U) 678 #define EMAC_MAC_PACKET_FILTER_DNTU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_DNTU_SHIFT)) & EMAC_MAC_PACKET_FILTER_DNTU_MASK) 679 680 #define EMAC_MAC_PACKET_FILTER_RA_MASK (0x80000000U) 681 #define EMAC_MAC_PACKET_FILTER_RA_SHIFT (31U) 682 #define EMAC_MAC_PACKET_FILTER_RA_WIDTH (1U) 683 #define EMAC_MAC_PACKET_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PACKET_FILTER_RA_SHIFT)) & EMAC_MAC_PACKET_FILTER_RA_MASK) 684 /*! @} */ 685 686 /*! @name MAC_WATCHDOG_TIMEOUT - MAC Watchdog Timeout */ 687 /*! @{ */ 688 689 #define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU) 690 #define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U) 691 #define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_WIDTH (4U) 692 #define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK) 693 694 #define EMAC_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x100U) 695 #define EMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U) 696 #define EMAC_MAC_WATCHDOG_TIMEOUT_PWE_WIDTH (1U) 697 #define EMAC_MAC_WATCHDOG_TIMEOUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & EMAC_MAC_WATCHDOG_TIMEOUT_PWE_MASK) 698 /*! @} */ 699 700 /*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table First 32 Bits */ 701 /*! @{ */ 702 703 #define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU) 704 #define EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U) 705 #define EMAC_MAC_HASH_TABLE_REG0_HT31T0_WIDTH (32U) 706 #define EMAC_MAC_HASH_TABLE_REG0_HT31T0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK) 707 /*! @} */ 708 709 /*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Second 32 Bits */ 710 /*! @{ */ 711 712 #define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU) 713 #define EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U) 714 #define EMAC_MAC_HASH_TABLE_REG1_HT63T32_WIDTH (32U) 715 #define EMAC_MAC_HASH_TABLE_REG1_HT63T32(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK) 716 /*! @} */ 717 718 /*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */ 719 /*! @{ */ 720 721 #define EMAC_MAC_VLAN_TAG_CTRL_OB_MASK (0x1U) 722 #define EMAC_MAC_VLAN_TAG_CTRL_OB_SHIFT (0U) 723 #define EMAC_MAC_VLAN_TAG_CTRL_OB_WIDTH (1U) 724 #define EMAC_MAC_VLAN_TAG_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_OB_MASK) 725 726 #define EMAC_MAC_VLAN_TAG_CTRL_CT_MASK (0x2U) 727 #define EMAC_MAC_VLAN_TAG_CTRL_CT_SHIFT (1U) 728 #define EMAC_MAC_VLAN_TAG_CTRL_CT_WIDTH (1U) 729 #define EMAC_MAC_VLAN_TAG_CTRL_CT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_CT_MASK) 730 731 #define EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK (0xCU) 732 #define EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2U) 733 #define EMAC_MAC_VLAN_TAG_CTRL_OFS_WIDTH (2U) 734 #define EMAC_MAC_VLAN_TAG_CTRL_OFS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK) 735 736 #define EMAC_MAC_VLAN_TAG_CTRL_ETV_MASK (0x10000U) 737 #define EMAC_MAC_VLAN_TAG_CTRL_ETV_SHIFT (16U) 738 #define EMAC_MAC_VLAN_TAG_CTRL_ETV_WIDTH (1U) 739 #define EMAC_MAC_VLAN_TAG_CTRL_ETV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_ETV_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_ETV_MASK) 740 741 #define EMAC_MAC_VLAN_TAG_CTRL_VTIM_MASK (0x20000U) 742 #define EMAC_MAC_VLAN_TAG_CTRL_VTIM_SHIFT (17U) 743 #define EMAC_MAC_VLAN_TAG_CTRL_VTIM_WIDTH (1U) 744 #define EMAC_MAC_VLAN_TAG_CTRL_VTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_VTIM_MASK) 745 746 #define EMAC_MAC_VLAN_TAG_CTRL_ESVL_MASK (0x40000U) 747 #define EMAC_MAC_VLAN_TAG_CTRL_ESVL_SHIFT (18U) 748 #define EMAC_MAC_VLAN_TAG_CTRL_ESVL_WIDTH (1U) 749 #define EMAC_MAC_VLAN_TAG_CTRL_ESVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_ESVL_MASK) 750 751 #define EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_MASK (0x80000U) 752 #define EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT (19U) 753 #define EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_WIDTH (1U) 754 #define EMAC_MAC_VLAN_TAG_CTRL_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_MASK) 755 756 #define EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_MASK (0x100000U) 757 #define EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT (20U) 758 #define EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_WIDTH (1U) 759 #define EMAC_MAC_VLAN_TAG_CTRL_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_MASK) 760 761 #define EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x600000U) 762 #define EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21U) 763 #define EMAC_MAC_VLAN_TAG_CTRL_EVLS_WIDTH (2U) 764 #define EMAC_MAC_VLAN_TAG_CTRL_EVLS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK) 765 766 #define EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_MASK (0x1000000U) 767 #define EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT (24U) 768 #define EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_WIDTH (1U) 769 #define EMAC_MAC_VLAN_TAG_CTRL_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_MASK) 770 771 #define EMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK (0x2000000U) 772 #define EMAC_MAC_VLAN_TAG_CTRL_VTHM_SHIFT (25U) 773 #define EMAC_MAC_VLAN_TAG_CTRL_VTHM_WIDTH (1U) 774 #define EMAC_MAC_VLAN_TAG_CTRL_VTHM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK) 775 776 #define EMAC_MAC_VLAN_TAG_CTRL_EDVLP_MASK (0x4000000U) 777 #define EMAC_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT (26U) 778 #define EMAC_MAC_VLAN_TAG_CTRL_EDVLP_WIDTH (1U) 779 #define EMAC_MAC_VLAN_TAG_CTRL_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_EDVLP_MASK) 780 781 #define EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_MASK (0x8000000U) 782 #define EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT (27U) 783 #define EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_WIDTH (1U) 784 #define EMAC_MAC_VLAN_TAG_CTRL_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_MASK) 785 786 #define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x30000000U) 787 #define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28U) 788 #define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_WIDTH (2U) 789 #define EMAC_MAC_VLAN_TAG_CTRL_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK) 790 791 #define EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK (0x80000000U) 792 #define EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U) 793 #define EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_WIDTH (1U) 794 #define EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK) 795 /*! @} */ 796 797 /*! @name MAC_VLAN_TAG - MAC VLAN Tag */ 798 /*! @{ */ 799 800 #define EMAC_MAC_VLAN_TAG_VL_MASK (0xFFFFU) 801 #define EMAC_MAC_VLAN_TAG_VL_SHIFT (0U) 802 #define EMAC_MAC_VLAN_TAG_VL_WIDTH (16U) 803 #define EMAC_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_VL_SHIFT)) & EMAC_MAC_VLAN_TAG_VL_MASK) 804 805 #define EMAC_MAC_VLAN_TAG_ETV_MASK (0x10000U) 806 #define EMAC_MAC_VLAN_TAG_ETV_SHIFT (16U) 807 #define EMAC_MAC_VLAN_TAG_ETV_WIDTH (1U) 808 #define EMAC_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_ETV_SHIFT)) & EMAC_MAC_VLAN_TAG_ETV_MASK) 809 810 #define EMAC_MAC_VLAN_TAG_VTIM_MASK (0x20000U) 811 #define EMAC_MAC_VLAN_TAG_VTIM_SHIFT (17U) 812 #define EMAC_MAC_VLAN_TAG_VTIM_WIDTH (1U) 813 #define EMAC_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_VTIM_SHIFT)) & EMAC_MAC_VLAN_TAG_VTIM_MASK) 814 815 #define EMAC_MAC_VLAN_TAG_ESVL_MASK (0x40000U) 816 #define EMAC_MAC_VLAN_TAG_ESVL_SHIFT (18U) 817 #define EMAC_MAC_VLAN_TAG_ESVL_WIDTH (1U) 818 #define EMAC_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_ESVL_SHIFT)) & EMAC_MAC_VLAN_TAG_ESVL_MASK) 819 820 #define EMAC_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U) 821 #define EMAC_MAC_VLAN_TAG_ERSVLM_SHIFT (19U) 822 #define EMAC_MAC_VLAN_TAG_ERSVLM_WIDTH (1U) 823 #define EMAC_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_ERSVLM_SHIFT)) & EMAC_MAC_VLAN_TAG_ERSVLM_MASK) 824 825 #define EMAC_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U) 826 #define EMAC_MAC_VLAN_TAG_DOVLTC_SHIFT (20U) 827 #define EMAC_MAC_VLAN_TAG_DOVLTC_WIDTH (1U) 828 #define EMAC_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DOVLTC_SHIFT)) & EMAC_MAC_VLAN_TAG_DOVLTC_MASK) 829 830 #define EMAC_MAC_VLAN_TAG_EVLS_MASK (0x600000U) 831 #define EMAC_MAC_VLAN_TAG_EVLS_SHIFT (21U) 832 #define EMAC_MAC_VLAN_TAG_EVLS_WIDTH (2U) 833 #define EMAC_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_EVLS_SHIFT)) & EMAC_MAC_VLAN_TAG_EVLS_MASK) 834 835 #define EMAC_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U) 836 #define EMAC_MAC_VLAN_TAG_EVLRXS_SHIFT (24U) 837 #define EMAC_MAC_VLAN_TAG_EVLRXS_WIDTH (1U) 838 #define EMAC_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_EVLRXS_SHIFT)) & EMAC_MAC_VLAN_TAG_EVLRXS_MASK) 839 840 #define EMAC_MAC_VLAN_TAG_VTHM_MASK (0x2000000U) 841 #define EMAC_MAC_VLAN_TAG_VTHM_SHIFT (25U) 842 #define EMAC_MAC_VLAN_TAG_VTHM_WIDTH (1U) 843 #define EMAC_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_VTHM_SHIFT)) & EMAC_MAC_VLAN_TAG_VTHM_MASK) 844 845 #define EMAC_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U) 846 #define EMAC_MAC_VLAN_TAG_EDVLP_SHIFT (26U) 847 #define EMAC_MAC_VLAN_TAG_EDVLP_WIDTH (1U) 848 #define EMAC_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_EDVLP_SHIFT)) & EMAC_MAC_VLAN_TAG_EDVLP_MASK) 849 850 #define EMAC_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U) 851 #define EMAC_MAC_VLAN_TAG_ERIVLT_SHIFT (27U) 852 #define EMAC_MAC_VLAN_TAG_ERIVLT_WIDTH (1U) 853 #define EMAC_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_ERIVLT_SHIFT)) & EMAC_MAC_VLAN_TAG_ERIVLT_MASK) 854 855 #define EMAC_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U) 856 #define EMAC_MAC_VLAN_TAG_EIVLS_SHIFT (28U) 857 #define EMAC_MAC_VLAN_TAG_EIVLS_WIDTH (2U) 858 #define EMAC_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT)) & EMAC_MAC_VLAN_TAG_EIVLS_MASK) 859 860 #define EMAC_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U) 861 #define EMAC_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U) 862 #define EMAC_MAC_VLAN_TAG_EIVLRXS_WIDTH (1U) 863 #define EMAC_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & EMAC_MAC_VLAN_TAG_EIVLRXS_MASK) 864 /*! @} */ 865 866 /*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */ 867 /*! @{ */ 868 869 #define EMAC_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFFU) 870 #define EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT (0U) 871 #define EMAC_MAC_VLAN_TAG_DATA_VID_WIDTH (16U) 872 #define EMAC_MAC_VLAN_TAG_DATA_VID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT)) & EMAC_MAC_VLAN_TAG_DATA_VID_MASK) 873 874 #define EMAC_MAC_VLAN_TAG_DATA_VEN_MASK (0x10000U) 875 #define EMAC_MAC_VLAN_TAG_DATA_VEN_SHIFT (16U) 876 #define EMAC_MAC_VLAN_TAG_DATA_VEN_WIDTH (1U) 877 #define EMAC_MAC_VLAN_TAG_DATA_VEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & EMAC_MAC_VLAN_TAG_DATA_VEN_MASK) 878 879 #define EMAC_MAC_VLAN_TAG_DATA_ETV_MASK (0x20000U) 880 #define EMAC_MAC_VLAN_TAG_DATA_ETV_SHIFT (17U) 881 #define EMAC_MAC_VLAN_TAG_DATA_ETV_WIDTH (1U) 882 #define EMAC_MAC_VLAN_TAG_DATA_ETV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & EMAC_MAC_VLAN_TAG_DATA_ETV_MASK) 883 884 #define EMAC_MAC_VLAN_TAG_DATA_DOVLTC_MASK (0x40000U) 885 #define EMAC_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT (18U) 886 #define EMAC_MAC_VLAN_TAG_DATA_DOVLTC_WIDTH (1U) 887 #define EMAC_MAC_VLAN_TAG_DATA_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & EMAC_MAC_VLAN_TAG_DATA_DOVLTC_MASK) 888 889 #define EMAC_MAC_VLAN_TAG_DATA_ERSVLM_MASK (0x80000U) 890 #define EMAC_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT (19U) 891 #define EMAC_MAC_VLAN_TAG_DATA_ERSVLM_WIDTH (1U) 892 #define EMAC_MAC_VLAN_TAG_DATA_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & EMAC_MAC_VLAN_TAG_DATA_ERSVLM_MASK) 893 894 #define EMAC_MAC_VLAN_TAG_DATA_ERIVLT_MASK (0x100000U) 895 #define EMAC_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT (20U) 896 #define EMAC_MAC_VLAN_TAG_DATA_ERIVLT_WIDTH (1U) 897 #define EMAC_MAC_VLAN_TAG_DATA_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & EMAC_MAC_VLAN_TAG_DATA_ERIVLT_MASK) 898 899 #define EMAC_MAC_VLAN_TAG_DATA_DMACHEN_MASK (0x1000000U) 900 #define EMAC_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U) 901 #define EMAC_MAC_VLAN_TAG_DATA_DMACHEN_WIDTH (1U) 902 #define EMAC_MAC_VLAN_TAG_DATA_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & EMAC_MAC_VLAN_TAG_DATA_DMACHEN_MASK) 903 904 #define EMAC_MAC_VLAN_TAG_DATA_DMACHN_MASK (0x2000000U) 905 #define EMAC_MAC_VLAN_TAG_DATA_DMACHN_SHIFT (25U) 906 #define EMAC_MAC_VLAN_TAG_DATA_DMACHN_WIDTH (1U) 907 #define EMAC_MAC_VLAN_TAG_DATA_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & EMAC_MAC_VLAN_TAG_DATA_DMACHN_MASK) 908 /*! @} */ 909 910 /*! @name MAC_VLAN_TAG_FILTER0 - MAC VLAN Tag Filter 0 */ 911 /*! @{ */ 912 913 #define EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK (0xFFFFU) 914 #define EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT (0U) 915 #define EMAC_MAC_VLAN_TAG_FILTER0_VID_WIDTH (16U) 916 #define EMAC_MAC_VLAN_TAG_FILTER0_VID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK) 917 918 #define EMAC_MAC_VLAN_TAG_FILTER0_VEN_MASK (0x10000U) 919 #define EMAC_MAC_VLAN_TAG_FILTER0_VEN_SHIFT (16U) 920 #define EMAC_MAC_VLAN_TAG_FILTER0_VEN_WIDTH (1U) 921 #define EMAC_MAC_VLAN_TAG_FILTER0_VEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER0_VEN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER0_VEN_MASK) 922 923 #define EMAC_MAC_VLAN_TAG_FILTER0_ETV_MASK (0x20000U) 924 #define EMAC_MAC_VLAN_TAG_FILTER0_ETV_SHIFT (17U) 925 #define EMAC_MAC_VLAN_TAG_FILTER0_ETV_WIDTH (1U) 926 #define EMAC_MAC_VLAN_TAG_FILTER0_ETV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER0_ETV_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER0_ETV_MASK) 927 928 #define EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC_MASK (0x40000U) 929 #define EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC_SHIFT (18U) 930 #define EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC_WIDTH (1U) 931 #define EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC_MASK) 932 933 #define EMAC_MAC_VLAN_TAG_FILTER0_ERSVLM_MASK (0x80000U) 934 #define EMAC_MAC_VLAN_TAG_FILTER0_ERSVLM_SHIFT (19U) 935 #define EMAC_MAC_VLAN_TAG_FILTER0_ERSVLM_WIDTH (1U) 936 #define EMAC_MAC_VLAN_TAG_FILTER0_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER0_ERSVLM_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER0_ERSVLM_MASK) 937 938 #define EMAC_MAC_VLAN_TAG_FILTER0_ERIVLT_MASK (0x100000U) 939 #define EMAC_MAC_VLAN_TAG_FILTER0_ERIVLT_SHIFT (20U) 940 #define EMAC_MAC_VLAN_TAG_FILTER0_ERIVLT_WIDTH (1U) 941 #define EMAC_MAC_VLAN_TAG_FILTER0_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER0_ERIVLT_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER0_ERIVLT_MASK) 942 943 #define EMAC_MAC_VLAN_TAG_FILTER0_DMACHEN_MASK (0x1000000U) 944 #define EMAC_MAC_VLAN_TAG_FILTER0_DMACHEN_SHIFT (24U) 945 #define EMAC_MAC_VLAN_TAG_FILTER0_DMACHEN_WIDTH (1U) 946 #define EMAC_MAC_VLAN_TAG_FILTER0_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER0_DMACHEN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER0_DMACHEN_MASK) 947 948 #define EMAC_MAC_VLAN_TAG_FILTER0_DMACHN_MASK (0x2000000U) 949 #define EMAC_MAC_VLAN_TAG_FILTER0_DMACHN_SHIFT (25U) 950 #define EMAC_MAC_VLAN_TAG_FILTER0_DMACHN_WIDTH (1U) 951 #define EMAC_MAC_VLAN_TAG_FILTER0_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER0_DMACHN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER0_DMACHN_MASK) 952 /*! @} */ 953 954 /*! @name MAC_VLAN_TAG_FILTER1 - MAC VLAN Tag Filter 1 */ 955 /*! @{ */ 956 957 #define EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK (0xFFFFU) 958 #define EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT (0U) 959 #define EMAC_MAC_VLAN_TAG_FILTER1_VID_WIDTH (16U) 960 #define EMAC_MAC_VLAN_TAG_FILTER1_VID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK) 961 962 #define EMAC_MAC_VLAN_TAG_FILTER1_VEN_MASK (0x10000U) 963 #define EMAC_MAC_VLAN_TAG_FILTER1_VEN_SHIFT (16U) 964 #define EMAC_MAC_VLAN_TAG_FILTER1_VEN_WIDTH (1U) 965 #define EMAC_MAC_VLAN_TAG_FILTER1_VEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER1_VEN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER1_VEN_MASK) 966 967 #define EMAC_MAC_VLAN_TAG_FILTER1_ETV_MASK (0x20000U) 968 #define EMAC_MAC_VLAN_TAG_FILTER1_ETV_SHIFT (17U) 969 #define EMAC_MAC_VLAN_TAG_FILTER1_ETV_WIDTH (1U) 970 #define EMAC_MAC_VLAN_TAG_FILTER1_ETV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER1_ETV_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER1_ETV_MASK) 971 972 #define EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC_MASK (0x40000U) 973 #define EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC_SHIFT (18U) 974 #define EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC_WIDTH (1U) 975 #define EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC_MASK) 976 977 #define EMAC_MAC_VLAN_TAG_FILTER1_ERSVLM_MASK (0x80000U) 978 #define EMAC_MAC_VLAN_TAG_FILTER1_ERSVLM_SHIFT (19U) 979 #define EMAC_MAC_VLAN_TAG_FILTER1_ERSVLM_WIDTH (1U) 980 #define EMAC_MAC_VLAN_TAG_FILTER1_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER1_ERSVLM_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER1_ERSVLM_MASK) 981 982 #define EMAC_MAC_VLAN_TAG_FILTER1_ERIVLT_MASK (0x100000U) 983 #define EMAC_MAC_VLAN_TAG_FILTER1_ERIVLT_SHIFT (20U) 984 #define EMAC_MAC_VLAN_TAG_FILTER1_ERIVLT_WIDTH (1U) 985 #define EMAC_MAC_VLAN_TAG_FILTER1_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER1_ERIVLT_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER1_ERIVLT_MASK) 986 987 #define EMAC_MAC_VLAN_TAG_FILTER1_DMACHEN_MASK (0x1000000U) 988 #define EMAC_MAC_VLAN_TAG_FILTER1_DMACHEN_SHIFT (24U) 989 #define EMAC_MAC_VLAN_TAG_FILTER1_DMACHEN_WIDTH (1U) 990 #define EMAC_MAC_VLAN_TAG_FILTER1_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER1_DMACHEN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER1_DMACHEN_MASK) 991 992 #define EMAC_MAC_VLAN_TAG_FILTER1_DMACHN_MASK (0x2000000U) 993 #define EMAC_MAC_VLAN_TAG_FILTER1_DMACHN_SHIFT (25U) 994 #define EMAC_MAC_VLAN_TAG_FILTER1_DMACHN_WIDTH (1U) 995 #define EMAC_MAC_VLAN_TAG_FILTER1_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER1_DMACHN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER1_DMACHN_MASK) 996 /*! @} */ 997 998 /*! @name MAC_VLAN_TAG_FILTER2 - MAC VLAN Tag Filter 2 */ 999 /*! @{ */ 1000 1001 #define EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK (0xFFFFU) 1002 #define EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT (0U) 1003 #define EMAC_MAC_VLAN_TAG_FILTER2_VID_WIDTH (16U) 1004 #define EMAC_MAC_VLAN_TAG_FILTER2_VID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK) 1005 1006 #define EMAC_MAC_VLAN_TAG_FILTER2_VEN_MASK (0x10000U) 1007 #define EMAC_MAC_VLAN_TAG_FILTER2_VEN_SHIFT (16U) 1008 #define EMAC_MAC_VLAN_TAG_FILTER2_VEN_WIDTH (1U) 1009 #define EMAC_MAC_VLAN_TAG_FILTER2_VEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER2_VEN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER2_VEN_MASK) 1010 1011 #define EMAC_MAC_VLAN_TAG_FILTER2_ETV_MASK (0x20000U) 1012 #define EMAC_MAC_VLAN_TAG_FILTER2_ETV_SHIFT (17U) 1013 #define EMAC_MAC_VLAN_TAG_FILTER2_ETV_WIDTH (1U) 1014 #define EMAC_MAC_VLAN_TAG_FILTER2_ETV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER2_ETV_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER2_ETV_MASK) 1015 1016 #define EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC_MASK (0x40000U) 1017 #define EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC_SHIFT (18U) 1018 #define EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC_WIDTH (1U) 1019 #define EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC_MASK) 1020 1021 #define EMAC_MAC_VLAN_TAG_FILTER2_ERSVLM_MASK (0x80000U) 1022 #define EMAC_MAC_VLAN_TAG_FILTER2_ERSVLM_SHIFT (19U) 1023 #define EMAC_MAC_VLAN_TAG_FILTER2_ERSVLM_WIDTH (1U) 1024 #define EMAC_MAC_VLAN_TAG_FILTER2_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER2_ERSVLM_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER2_ERSVLM_MASK) 1025 1026 #define EMAC_MAC_VLAN_TAG_FILTER2_ERIVLT_MASK (0x100000U) 1027 #define EMAC_MAC_VLAN_TAG_FILTER2_ERIVLT_SHIFT (20U) 1028 #define EMAC_MAC_VLAN_TAG_FILTER2_ERIVLT_WIDTH (1U) 1029 #define EMAC_MAC_VLAN_TAG_FILTER2_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER2_ERIVLT_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER2_ERIVLT_MASK) 1030 1031 #define EMAC_MAC_VLAN_TAG_FILTER2_DMACHEN_MASK (0x1000000U) 1032 #define EMAC_MAC_VLAN_TAG_FILTER2_DMACHEN_SHIFT (24U) 1033 #define EMAC_MAC_VLAN_TAG_FILTER2_DMACHEN_WIDTH (1U) 1034 #define EMAC_MAC_VLAN_TAG_FILTER2_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER2_DMACHEN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER2_DMACHEN_MASK) 1035 1036 #define EMAC_MAC_VLAN_TAG_FILTER2_DMACHN_MASK (0x2000000U) 1037 #define EMAC_MAC_VLAN_TAG_FILTER2_DMACHN_SHIFT (25U) 1038 #define EMAC_MAC_VLAN_TAG_FILTER2_DMACHN_WIDTH (1U) 1039 #define EMAC_MAC_VLAN_TAG_FILTER2_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER2_DMACHN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER2_DMACHN_MASK) 1040 /*! @} */ 1041 1042 /*! @name MAC_VLAN_TAG_FILTER3 - MAC VLAN Tag Filter 3 */ 1043 /*! @{ */ 1044 1045 #define EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK (0xFFFFU) 1046 #define EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT (0U) 1047 #define EMAC_MAC_VLAN_TAG_FILTER3_VID_WIDTH (16U) 1048 #define EMAC_MAC_VLAN_TAG_FILTER3_VID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK) 1049 1050 #define EMAC_MAC_VLAN_TAG_FILTER3_VEN_MASK (0x10000U) 1051 #define EMAC_MAC_VLAN_TAG_FILTER3_VEN_SHIFT (16U) 1052 #define EMAC_MAC_VLAN_TAG_FILTER3_VEN_WIDTH (1U) 1053 #define EMAC_MAC_VLAN_TAG_FILTER3_VEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER3_VEN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER3_VEN_MASK) 1054 1055 #define EMAC_MAC_VLAN_TAG_FILTER3_ETV_MASK (0x20000U) 1056 #define EMAC_MAC_VLAN_TAG_FILTER3_ETV_SHIFT (17U) 1057 #define EMAC_MAC_VLAN_TAG_FILTER3_ETV_WIDTH (1U) 1058 #define EMAC_MAC_VLAN_TAG_FILTER3_ETV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER3_ETV_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER3_ETV_MASK) 1059 1060 #define EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC_MASK (0x40000U) 1061 #define EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC_SHIFT (18U) 1062 #define EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC_WIDTH (1U) 1063 #define EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC_MASK) 1064 1065 #define EMAC_MAC_VLAN_TAG_FILTER3_ERSVLM_MASK (0x80000U) 1066 #define EMAC_MAC_VLAN_TAG_FILTER3_ERSVLM_SHIFT (19U) 1067 #define EMAC_MAC_VLAN_TAG_FILTER3_ERSVLM_WIDTH (1U) 1068 #define EMAC_MAC_VLAN_TAG_FILTER3_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER3_ERSVLM_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER3_ERSVLM_MASK) 1069 1070 #define EMAC_MAC_VLAN_TAG_FILTER3_ERIVLT_MASK (0x100000U) 1071 #define EMAC_MAC_VLAN_TAG_FILTER3_ERIVLT_SHIFT (20U) 1072 #define EMAC_MAC_VLAN_TAG_FILTER3_ERIVLT_WIDTH (1U) 1073 #define EMAC_MAC_VLAN_TAG_FILTER3_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER3_ERIVLT_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER3_ERIVLT_MASK) 1074 1075 #define EMAC_MAC_VLAN_TAG_FILTER3_DMACHEN_MASK (0x1000000U) 1076 #define EMAC_MAC_VLAN_TAG_FILTER3_DMACHEN_SHIFT (24U) 1077 #define EMAC_MAC_VLAN_TAG_FILTER3_DMACHEN_WIDTH (1U) 1078 #define EMAC_MAC_VLAN_TAG_FILTER3_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER3_DMACHEN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER3_DMACHEN_MASK) 1079 1080 #define EMAC_MAC_VLAN_TAG_FILTER3_DMACHN_MASK (0x2000000U) 1081 #define EMAC_MAC_VLAN_TAG_FILTER3_DMACHN_SHIFT (25U) 1082 #define EMAC_MAC_VLAN_TAG_FILTER3_DMACHN_WIDTH (1U) 1083 #define EMAC_MAC_VLAN_TAG_FILTER3_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_TAG_FILTER3_DMACHN_SHIFT)) & EMAC_MAC_VLAN_TAG_FILTER3_DMACHN_MASK) 1084 /*! @} */ 1085 1086 /*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */ 1087 /*! @{ */ 1088 1089 #define EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFFU) 1090 #define EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0U) 1091 #define EMAC_MAC_VLAN_HASH_TABLE_VLHT_WIDTH (16U) 1092 #define EMAC_MAC_VLAN_HASH_TABLE_VLHT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK) 1093 /*! @} */ 1094 1095 /*! @name MAC_VLAN_INCL0 - MAC VLAN Inclusion 0 */ 1096 /*! @{ */ 1097 1098 #define EMAC_MAC_VLAN_INCL0_VLT_MASK (0xFFFFU) 1099 #define EMAC_MAC_VLAN_INCL0_VLT_SHIFT (0U) 1100 #define EMAC_MAC_VLAN_INCL0_VLT_WIDTH (16U) 1101 #define EMAC_MAC_VLAN_INCL0_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL0_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL0_VLT_MASK) 1102 1103 #define EMAC_MAC_VLAN_INCL0_CSVL_MASK (0x80000U) 1104 #define EMAC_MAC_VLAN_INCL0_CSVL_SHIFT (19U) 1105 #define EMAC_MAC_VLAN_INCL0_CSVL_WIDTH (1U) 1106 #define EMAC_MAC_VLAN_INCL0_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL0_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL0_CSVL_MASK) 1107 /*! @} */ 1108 1109 /*! @name MAC_VLAN_INCL1 - MAC VLAN Inclusion 1 */ 1110 /*! @{ */ 1111 1112 #define EMAC_MAC_VLAN_INCL1_VLT_MASK (0xFFFFU) 1113 #define EMAC_MAC_VLAN_INCL1_VLT_SHIFT (0U) 1114 #define EMAC_MAC_VLAN_INCL1_VLT_WIDTH (16U) 1115 #define EMAC_MAC_VLAN_INCL1_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL1_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL1_VLT_MASK) 1116 1117 #define EMAC_MAC_VLAN_INCL1_CSVL_MASK (0x80000U) 1118 #define EMAC_MAC_VLAN_INCL1_CSVL_SHIFT (19U) 1119 #define EMAC_MAC_VLAN_INCL1_CSVL_WIDTH (1U) 1120 #define EMAC_MAC_VLAN_INCL1_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL1_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL1_CSVL_MASK) 1121 /*! @} */ 1122 1123 /*! @name MAC_VLAN_INCL2 - MAC VLAN Inclusion 2 */ 1124 /*! @{ */ 1125 1126 #define EMAC_MAC_VLAN_INCL2_VLT_MASK (0xFFFFU) 1127 #define EMAC_MAC_VLAN_INCL2_VLT_SHIFT (0U) 1128 #define EMAC_MAC_VLAN_INCL2_VLT_WIDTH (16U) 1129 #define EMAC_MAC_VLAN_INCL2_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL2_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL2_VLT_MASK) 1130 1131 #define EMAC_MAC_VLAN_INCL2_CSVL_MASK (0x80000U) 1132 #define EMAC_MAC_VLAN_INCL2_CSVL_SHIFT (19U) 1133 #define EMAC_MAC_VLAN_INCL2_CSVL_WIDTH (1U) 1134 #define EMAC_MAC_VLAN_INCL2_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL2_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL2_CSVL_MASK) 1135 /*! @} */ 1136 1137 /*! @name MAC_VLAN_INCL3 - MAC VLAN Inclusion 3 */ 1138 /*! @{ */ 1139 1140 #define EMAC_MAC_VLAN_INCL3_VLT_MASK (0xFFFFU) 1141 #define EMAC_MAC_VLAN_INCL3_VLT_SHIFT (0U) 1142 #define EMAC_MAC_VLAN_INCL3_VLT_WIDTH (16U) 1143 #define EMAC_MAC_VLAN_INCL3_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL3_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL3_VLT_MASK) 1144 1145 #define EMAC_MAC_VLAN_INCL3_CSVL_MASK (0x80000U) 1146 #define EMAC_MAC_VLAN_INCL3_CSVL_SHIFT (19U) 1147 #define EMAC_MAC_VLAN_INCL3_CSVL_WIDTH (1U) 1148 #define EMAC_MAC_VLAN_INCL3_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL3_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL3_CSVL_MASK) 1149 /*! @} */ 1150 1151 /*! @name MAC_VLAN_INCL4 - MAC VLAN Inclusion 4 */ 1152 /*! @{ */ 1153 1154 #define EMAC_MAC_VLAN_INCL4_VLT_MASK (0xFFFFU) 1155 #define EMAC_MAC_VLAN_INCL4_VLT_SHIFT (0U) 1156 #define EMAC_MAC_VLAN_INCL4_VLT_WIDTH (16U) 1157 #define EMAC_MAC_VLAN_INCL4_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL4_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL4_VLT_MASK) 1158 1159 #define EMAC_MAC_VLAN_INCL4_CSVL_MASK (0x80000U) 1160 #define EMAC_MAC_VLAN_INCL4_CSVL_SHIFT (19U) 1161 #define EMAC_MAC_VLAN_INCL4_CSVL_WIDTH (1U) 1162 #define EMAC_MAC_VLAN_INCL4_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL4_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL4_CSVL_MASK) 1163 /*! @} */ 1164 1165 /*! @name MAC_VLAN_INCL5 - MAC VLAN Inclusion 5 */ 1166 /*! @{ */ 1167 1168 #define EMAC_MAC_VLAN_INCL5_VLT_MASK (0xFFFFU) 1169 #define EMAC_MAC_VLAN_INCL5_VLT_SHIFT (0U) 1170 #define EMAC_MAC_VLAN_INCL5_VLT_WIDTH (16U) 1171 #define EMAC_MAC_VLAN_INCL5_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL5_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL5_VLT_MASK) 1172 1173 #define EMAC_MAC_VLAN_INCL5_CSVL_MASK (0x80000U) 1174 #define EMAC_MAC_VLAN_INCL5_CSVL_SHIFT (19U) 1175 #define EMAC_MAC_VLAN_INCL5_CSVL_WIDTH (1U) 1176 #define EMAC_MAC_VLAN_INCL5_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL5_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL5_CSVL_MASK) 1177 /*! @} */ 1178 1179 /*! @name MAC_VLAN_INCL6 - MAC VLAN Inclusion 6 */ 1180 /*! @{ */ 1181 1182 #define EMAC_MAC_VLAN_INCL6_VLT_MASK (0xFFFFU) 1183 #define EMAC_MAC_VLAN_INCL6_VLT_SHIFT (0U) 1184 #define EMAC_MAC_VLAN_INCL6_VLT_WIDTH (16U) 1185 #define EMAC_MAC_VLAN_INCL6_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL6_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL6_VLT_MASK) 1186 1187 #define EMAC_MAC_VLAN_INCL6_CSVL_MASK (0x80000U) 1188 #define EMAC_MAC_VLAN_INCL6_CSVL_SHIFT (19U) 1189 #define EMAC_MAC_VLAN_INCL6_CSVL_WIDTH (1U) 1190 #define EMAC_MAC_VLAN_INCL6_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL6_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL6_CSVL_MASK) 1191 /*! @} */ 1192 1193 /*! @name MAC_VLAN_INCL7 - MAC VLAN Inclusion 7 */ 1194 /*! @{ */ 1195 1196 #define EMAC_MAC_VLAN_INCL7_VLT_MASK (0xFFFFU) 1197 #define EMAC_MAC_VLAN_INCL7_VLT_SHIFT (0U) 1198 #define EMAC_MAC_VLAN_INCL7_VLT_WIDTH (16U) 1199 #define EMAC_MAC_VLAN_INCL7_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL7_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL7_VLT_MASK) 1200 1201 #define EMAC_MAC_VLAN_INCL7_CSVL_MASK (0x80000U) 1202 #define EMAC_MAC_VLAN_INCL7_CSVL_SHIFT (19U) 1203 #define EMAC_MAC_VLAN_INCL7_CSVL_WIDTH (1U) 1204 #define EMAC_MAC_VLAN_INCL7_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL7_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL7_CSVL_MASK) 1205 /*! @} */ 1206 1207 /*! @name MAC_VLAN_INCL - MAC VLAN Inclusion Or Replacement */ 1208 /*! @{ */ 1209 1210 #define EMAC_MAC_VLAN_INCL_VLT_MASK (0xFFFFU) 1211 #define EMAC_MAC_VLAN_INCL_VLT_SHIFT (0U) 1212 #define EMAC_MAC_VLAN_INCL_VLT_WIDTH (16U) 1213 #define EMAC_MAC_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_VLT_SHIFT)) & EMAC_MAC_VLAN_INCL_VLT_MASK) 1214 1215 #define EMAC_MAC_VLAN_INCL_VLC_MASK (0x30000U) 1216 #define EMAC_MAC_VLAN_INCL_VLC_SHIFT (16U) 1217 #define EMAC_MAC_VLAN_INCL_VLC_WIDTH (2U) 1218 #define EMAC_MAC_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_VLC_SHIFT)) & EMAC_MAC_VLAN_INCL_VLC_MASK) 1219 1220 #define EMAC_MAC_VLAN_INCL_VLP_MASK (0x40000U) 1221 #define EMAC_MAC_VLAN_INCL_VLP_SHIFT (18U) 1222 #define EMAC_MAC_VLAN_INCL_VLP_WIDTH (1U) 1223 #define EMAC_MAC_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_VLP_SHIFT)) & EMAC_MAC_VLAN_INCL_VLP_MASK) 1224 1225 #define EMAC_MAC_VLAN_INCL_CSVL_MASK (0x80000U) 1226 #define EMAC_MAC_VLAN_INCL_CSVL_SHIFT (19U) 1227 #define EMAC_MAC_VLAN_INCL_CSVL_WIDTH (1U) 1228 #define EMAC_MAC_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_CSVL_SHIFT)) & EMAC_MAC_VLAN_INCL_CSVL_MASK) 1229 1230 #define EMAC_MAC_VLAN_INCL_VLTI_MASK (0x100000U) 1231 #define EMAC_MAC_VLAN_INCL_VLTI_SHIFT (20U) 1232 #define EMAC_MAC_VLAN_INCL_VLTI_WIDTH (1U) 1233 #define EMAC_MAC_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_VLTI_SHIFT)) & EMAC_MAC_VLAN_INCL_VLTI_MASK) 1234 1235 #define EMAC_MAC_VLAN_INCL_CBTI_MASK (0x200000U) 1236 #define EMAC_MAC_VLAN_INCL_CBTI_SHIFT (21U) 1237 #define EMAC_MAC_VLAN_INCL_CBTI_WIDTH (1U) 1238 #define EMAC_MAC_VLAN_INCL_CBTI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_CBTI_SHIFT)) & EMAC_MAC_VLAN_INCL_CBTI_MASK) 1239 1240 #define EMAC_MAC_VLAN_INCL_ADDR_MASK (0x1000000U) 1241 #define EMAC_MAC_VLAN_INCL_ADDR_SHIFT (24U) 1242 #define EMAC_MAC_VLAN_INCL_ADDR_WIDTH (1U) 1243 #define EMAC_MAC_VLAN_INCL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_ADDR_SHIFT)) & EMAC_MAC_VLAN_INCL_ADDR_MASK) 1244 1245 #define EMAC_MAC_VLAN_INCL_RDWR_MASK (0x40000000U) 1246 #define EMAC_MAC_VLAN_INCL_RDWR_SHIFT (30U) 1247 #define EMAC_MAC_VLAN_INCL_RDWR_WIDTH (1U) 1248 #define EMAC_MAC_VLAN_INCL_RDWR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_RDWR_SHIFT)) & EMAC_MAC_VLAN_INCL_RDWR_MASK) 1249 1250 #define EMAC_MAC_VLAN_INCL_BUSY_MASK (0x80000000U) 1251 #define EMAC_MAC_VLAN_INCL_BUSY_SHIFT (31U) 1252 #define EMAC_MAC_VLAN_INCL_BUSY_WIDTH (1U) 1253 #define EMAC_MAC_VLAN_INCL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VLAN_INCL_BUSY_SHIFT)) & EMAC_MAC_VLAN_INCL_BUSY_MASK) 1254 /*! @} */ 1255 1256 /*! @name MAC_INNER_VLAN_INCL - Inner VLAN Tag Inclusion Or Replacement */ 1257 /*! @{ */ 1258 1259 #define EMAC_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFFU) 1260 #define EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT (0U) 1261 #define EMAC_MAC_INNER_VLAN_INCL_VLT_WIDTH (16U) 1262 #define EMAC_MAC_INNER_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & EMAC_MAC_INNER_VLAN_INCL_VLT_MASK) 1263 1264 #define EMAC_MAC_INNER_VLAN_INCL_VLC_MASK (0x30000U) 1265 #define EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT (16U) 1266 #define EMAC_MAC_INNER_VLAN_INCL_VLC_WIDTH (2U) 1267 #define EMAC_MAC_INNER_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & EMAC_MAC_INNER_VLAN_INCL_VLC_MASK) 1268 1269 #define EMAC_MAC_INNER_VLAN_INCL_VLP_MASK (0x40000U) 1270 #define EMAC_MAC_INNER_VLAN_INCL_VLP_SHIFT (18U) 1271 #define EMAC_MAC_INNER_VLAN_INCL_VLP_WIDTH (1U) 1272 #define EMAC_MAC_INNER_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & EMAC_MAC_INNER_VLAN_INCL_VLP_MASK) 1273 1274 #define EMAC_MAC_INNER_VLAN_INCL_CSVL_MASK (0x80000U) 1275 #define EMAC_MAC_INNER_VLAN_INCL_CSVL_SHIFT (19U) 1276 #define EMAC_MAC_INNER_VLAN_INCL_CSVL_WIDTH (1U) 1277 #define EMAC_MAC_INNER_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & EMAC_MAC_INNER_VLAN_INCL_CSVL_MASK) 1278 1279 #define EMAC_MAC_INNER_VLAN_INCL_VLTI_MASK (0x100000U) 1280 #define EMAC_MAC_INNER_VLAN_INCL_VLTI_SHIFT (20U) 1281 #define EMAC_MAC_INNER_VLAN_INCL_VLTI_WIDTH (1U) 1282 #define EMAC_MAC_INNER_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & EMAC_MAC_INNER_VLAN_INCL_VLTI_MASK) 1283 /*! @} */ 1284 1285 /*! @name MAC_Q0_TX_FLOW_CTRL - MAC Q0 Tx Flow Control */ 1286 /*! @{ */ 1287 1288 #define EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK (0x1U) 1289 #define EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT (0U) 1290 #define EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_WIDTH (1U) 1291 #define EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK) 1292 1293 #define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK (0x2U) 1294 #define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT (1U) 1295 #define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_WIDTH (1U) 1296 #define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK) 1297 1298 #define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK (0x70U) 1299 #define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT (4U) 1300 #define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_WIDTH (3U) 1301 #define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK) 1302 1303 #define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK (0x80U) 1304 #define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT (7U) 1305 #define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_WIDTH (1U) 1306 #define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK) 1307 1308 #define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFF0000U) 1309 #define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16U) 1310 #define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_WIDTH (16U) 1311 #define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT)) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK) 1312 /*! @} */ 1313 1314 /*! @name MAC_RX_FLOW_CTRL - MAC Receive Flow Control */ 1315 /*! @{ */ 1316 1317 #define EMAC_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) 1318 #define EMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) 1319 #define EMAC_MAC_RX_FLOW_CTRL_RFE_WIDTH (1U) 1320 #define EMAC_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & EMAC_MAC_RX_FLOW_CTRL_RFE_MASK) 1321 1322 #define EMAC_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) 1323 #define EMAC_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) 1324 #define EMAC_MAC_RX_FLOW_CTRL_UP_WIDTH (1U) 1325 #define EMAC_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_FLOW_CTRL_UP_SHIFT)) & EMAC_MAC_RX_FLOW_CTRL_UP_MASK) 1326 /*! @} */ 1327 1328 /*! @name MAC_RXQ_CTRL4 - MAC RxQ Control 4 */ 1329 /*! @{ */ 1330 1331 #define EMAC_MAC_RXQ_CTRL4_UFFQE_MASK (0x1U) 1332 #define EMAC_MAC_RXQ_CTRL4_UFFQE_SHIFT (0U) 1333 #define EMAC_MAC_RXQ_CTRL4_UFFQE_WIDTH (1U) 1334 #define EMAC_MAC_RXQ_CTRL4_UFFQE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & EMAC_MAC_RXQ_CTRL4_UFFQE_MASK) 1335 1336 #define EMAC_MAC_RXQ_CTRL4_UFFQ_MASK (0x2U) 1337 #define EMAC_MAC_RXQ_CTRL4_UFFQ_SHIFT (1U) 1338 #define EMAC_MAC_RXQ_CTRL4_UFFQ_WIDTH (1U) 1339 #define EMAC_MAC_RXQ_CTRL4_UFFQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & EMAC_MAC_RXQ_CTRL4_UFFQ_MASK) 1340 1341 #define EMAC_MAC_RXQ_CTRL4_MFFQE_MASK (0x100U) 1342 #define EMAC_MAC_RXQ_CTRL4_MFFQE_SHIFT (8U) 1343 #define EMAC_MAC_RXQ_CTRL4_MFFQE_WIDTH (1U) 1344 #define EMAC_MAC_RXQ_CTRL4_MFFQE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & EMAC_MAC_RXQ_CTRL4_MFFQE_MASK) 1345 1346 #define EMAC_MAC_RXQ_CTRL4_MFFQ_MASK (0x200U) 1347 #define EMAC_MAC_RXQ_CTRL4_MFFQ_SHIFT (9U) 1348 #define EMAC_MAC_RXQ_CTRL4_MFFQ_WIDTH (1U) 1349 #define EMAC_MAC_RXQ_CTRL4_MFFQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & EMAC_MAC_RXQ_CTRL4_MFFQ_MASK) 1350 1351 #define EMAC_MAC_RXQ_CTRL4_VFFQE_MASK (0x10000U) 1352 #define EMAC_MAC_RXQ_CTRL4_VFFQE_SHIFT (16U) 1353 #define EMAC_MAC_RXQ_CTRL4_VFFQE_WIDTH (1U) 1354 #define EMAC_MAC_RXQ_CTRL4_VFFQE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & EMAC_MAC_RXQ_CTRL4_VFFQE_MASK) 1355 1356 #define EMAC_MAC_RXQ_CTRL4_VFFQ_MASK (0x20000U) 1357 #define EMAC_MAC_RXQ_CTRL4_VFFQ_SHIFT (17U) 1358 #define EMAC_MAC_RXQ_CTRL4_VFFQ_WIDTH (1U) 1359 #define EMAC_MAC_RXQ_CTRL4_VFFQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & EMAC_MAC_RXQ_CTRL4_VFFQ_MASK) 1360 /*! @} */ 1361 1362 /*! @name MAC_RXQ_CTRL0 - MAC RxQ Control 0 */ 1363 /*! @{ */ 1364 1365 #define EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK (0x3U) 1366 #define EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT (0U) 1367 #define EMAC_MAC_RXQ_CTRL0_RXQ0EN_WIDTH (2U) 1368 #define EMAC_MAC_RXQ_CTRL0_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT)) & EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK) 1369 1370 #define EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK (0xCU) 1371 #define EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2U) 1372 #define EMAC_MAC_RXQ_CTRL0_RXQ1EN_WIDTH (2U) 1373 #define EMAC_MAC_RXQ_CTRL0_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT)) & EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK) 1374 /*! @} */ 1375 1376 /*! @name MAC_RXQ_CTRL1 - Receive Queue Control 1 */ 1377 /*! @{ */ 1378 1379 #define EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK (0x7U) 1380 #define EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT (0U) 1381 #define EMAC_MAC_RXQ_CTRL1_AVCPQ_WIDTH (3U) 1382 #define EMAC_MAC_RXQ_CTRL1_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK) 1383 1384 #define EMAC_MAC_RXQ_CTRL1_PTPQ_MASK (0x70U) 1385 #define EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT (4U) 1386 #define EMAC_MAC_RXQ_CTRL1_PTPQ_WIDTH (3U) 1387 #define EMAC_MAC_RXQ_CTRL1_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_PTPQ_MASK) 1388 1389 #define EMAC_MAC_RXQ_CTRL1_UPQ_MASK (0x7000U) 1390 #define EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT (12U) 1391 #define EMAC_MAC_RXQ_CTRL1_UPQ_WIDTH (3U) 1392 #define EMAC_MAC_RXQ_CTRL1_UPQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_UPQ_MASK) 1393 1394 #define EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK (0x70000U) 1395 #define EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT (16U) 1396 #define EMAC_MAC_RXQ_CTRL1_MCBCQ_WIDTH (3U) 1397 #define EMAC_MAC_RXQ_CTRL1_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK) 1398 1399 #define EMAC_MAC_RXQ_CTRL1_MCBCQEN_MASK (0x100000U) 1400 #define EMAC_MAC_RXQ_CTRL1_MCBCQEN_SHIFT (20U) 1401 #define EMAC_MAC_RXQ_CTRL1_MCBCQEN_WIDTH (1U) 1402 #define EMAC_MAC_RXQ_CTRL1_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_MCBCQEN_SHIFT)) & EMAC_MAC_RXQ_CTRL1_MCBCQEN_MASK) 1403 1404 #define EMAC_MAC_RXQ_CTRL1_TACPQE_MASK (0x200000U) 1405 #define EMAC_MAC_RXQ_CTRL1_TACPQE_SHIFT (21U) 1406 #define EMAC_MAC_RXQ_CTRL1_TACPQE_WIDTH (1U) 1407 #define EMAC_MAC_RXQ_CTRL1_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_TACPQE_SHIFT)) & EMAC_MAC_RXQ_CTRL1_TACPQE_MASK) 1408 1409 #define EMAC_MAC_RXQ_CTRL1_TPQC_MASK (0xC00000U) 1410 #define EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT (22U) 1411 #define EMAC_MAC_RXQ_CTRL1_TPQC_WIDTH (2U) 1412 #define EMAC_MAC_RXQ_CTRL1_TPQC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT)) & EMAC_MAC_RXQ_CTRL1_TPQC_MASK) 1413 1414 #define EMAC_MAC_RXQ_CTRL1_FPRQ_MASK (0x7000000U) 1415 #define EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT (24U) 1416 #define EMAC_MAC_RXQ_CTRL1_FPRQ_WIDTH (3U) 1417 #define EMAC_MAC_RXQ_CTRL1_FPRQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT)) & EMAC_MAC_RXQ_CTRL1_FPRQ_MASK) 1418 /*! @} */ 1419 1420 /*! @name MAC_RXQ_CTRL2 - MAC RxQ Control 2 */ 1421 /*! @{ */ 1422 1423 #define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xFFU) 1424 #define EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT (0U) 1425 #define EMAC_MAC_RXQ_CTRL2_PSRQ0_WIDTH (8U) 1426 #define EMAC_MAC_RXQ_CTRL2_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT)) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK) 1427 1428 #define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xFF00U) 1429 #define EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT (8U) 1430 #define EMAC_MAC_RXQ_CTRL2_PSRQ1_WIDTH (8U) 1431 #define EMAC_MAC_RXQ_CTRL2_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT)) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK) 1432 /*! @} */ 1433 1434 /*! @name MAC_INTERRUPT_STATUS - MAC Interrupt Status */ 1435 /*! @{ */ 1436 1437 #define EMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U) 1438 #define EMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U) 1439 #define EMAC_MAC_INTERRUPT_STATUS_PHYIS_WIDTH (1U) 1440 #define EMAC_MAC_INTERRUPT_STATUS_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK) 1441 1442 #define EMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U) 1443 #define EMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U) 1444 #define EMAC_MAC_INTERRUPT_STATUS_MMCIS_WIDTH (1U) 1445 #define EMAC_MAC_INTERRUPT_STATUS_MMCIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK) 1446 1447 #define EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U) 1448 #define EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U) 1449 #define EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_WIDTH (1U) 1450 #define EMAC_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK) 1451 1452 #define EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U) 1453 #define EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U) 1454 #define EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_WIDTH (1U) 1455 #define EMAC_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK) 1456 1457 #define EMAC_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1000U) 1458 #define EMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U) 1459 #define EMAC_MAC_INTERRUPT_STATUS_TSIS_WIDTH (1U) 1460 #define EMAC_MAC_INTERRUPT_STATUS_TSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_TSIS_MASK) 1461 1462 #define EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U) 1463 #define EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U) 1464 #define EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_WIDTH (1U) 1465 #define EMAC_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK) 1466 1467 #define EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U) 1468 #define EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U) 1469 #define EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_WIDTH (1U) 1470 #define EMAC_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK) 1471 1472 #define EMAC_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U) 1473 #define EMAC_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U) 1474 #define EMAC_MAC_INTERRUPT_STATUS_FPEIS_WIDTH (1U) 1475 #define EMAC_MAC_INTERRUPT_STATUS_FPEIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_FPEIS_MASK) 1476 1477 #define EMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U) 1478 #define EMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U) 1479 #define EMAC_MAC_INTERRUPT_STATUS_MDIOIS_WIDTH (1U) 1480 #define EMAC_MAC_INTERRUPT_STATUS_MDIOIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK) 1481 1482 #define EMAC_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U) 1483 #define EMAC_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U) 1484 #define EMAC_MAC_INTERRUPT_STATUS_MFTIS_WIDTH (1U) 1485 #define EMAC_MAC_INTERRUPT_STATUS_MFTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_MFTIS_MASK) 1486 1487 #define EMAC_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U) 1488 #define EMAC_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U) 1489 #define EMAC_MAC_INTERRUPT_STATUS_MFRIS_WIDTH (1U) 1490 #define EMAC_MAC_INTERRUPT_STATUS_MFRIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & EMAC_MAC_INTERRUPT_STATUS_MFRIS_MASK) 1491 /*! @} */ 1492 1493 /*! @name MAC_INTERRUPT_ENABLE - MAC Interrupt Enable */ 1494 /*! @{ */ 1495 1496 #define EMAC_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U) 1497 #define EMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U) 1498 #define EMAC_MAC_INTERRUPT_ENABLE_PHYIE_WIDTH (1U) 1499 #define EMAC_MAC_INTERRUPT_ENABLE_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & EMAC_MAC_INTERRUPT_ENABLE_PHYIE_MASK) 1500 1501 #define EMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1000U) 1502 #define EMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U) 1503 #define EMAC_MAC_INTERRUPT_ENABLE_TSIE_WIDTH (1U) 1504 #define EMAC_MAC_INTERRUPT_ENABLE_TSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & EMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK) 1505 1506 #define EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U) 1507 #define EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U) 1508 #define EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_WIDTH (1U) 1509 #define EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK) 1510 1511 #define EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U) 1512 #define EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U) 1513 #define EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_WIDTH (1U) 1514 #define EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK) 1515 1516 #define EMAC_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U) 1517 #define EMAC_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U) 1518 #define EMAC_MAC_INTERRUPT_ENABLE_FPEIE_WIDTH (1U) 1519 #define EMAC_MAC_INTERRUPT_ENABLE_FPEIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & EMAC_MAC_INTERRUPT_ENABLE_FPEIE_MASK) 1520 1521 #define EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U) 1522 #define EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U) 1523 #define EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_WIDTH (1U) 1524 #define EMAC_MAC_INTERRUPT_ENABLE_MDIOIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_MASK) 1525 /*! @} */ 1526 1527 /*! @name MAC_RX_TX_STATUS - MAC Rx Transmit Status */ 1528 /*! @{ */ 1529 1530 #define EMAC_MAC_RX_TX_STATUS_TJT_MASK (0x1U) 1531 #define EMAC_MAC_RX_TX_STATUS_TJT_SHIFT (0U) 1532 #define EMAC_MAC_RX_TX_STATUS_TJT_WIDTH (1U) 1533 #define EMAC_MAC_RX_TX_STATUS_TJT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_TX_STATUS_TJT_SHIFT)) & EMAC_MAC_RX_TX_STATUS_TJT_MASK) 1534 1535 #define EMAC_MAC_RX_TX_STATUS_NCARR_MASK (0x2U) 1536 #define EMAC_MAC_RX_TX_STATUS_NCARR_SHIFT (1U) 1537 #define EMAC_MAC_RX_TX_STATUS_NCARR_WIDTH (1U) 1538 #define EMAC_MAC_RX_TX_STATUS_NCARR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_TX_STATUS_NCARR_SHIFT)) & EMAC_MAC_RX_TX_STATUS_NCARR_MASK) 1539 1540 #define EMAC_MAC_RX_TX_STATUS_LCARR_MASK (0x4U) 1541 #define EMAC_MAC_RX_TX_STATUS_LCARR_SHIFT (2U) 1542 #define EMAC_MAC_RX_TX_STATUS_LCARR_WIDTH (1U) 1543 #define EMAC_MAC_RX_TX_STATUS_LCARR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_TX_STATUS_LCARR_SHIFT)) & EMAC_MAC_RX_TX_STATUS_LCARR_MASK) 1544 1545 #define EMAC_MAC_RX_TX_STATUS_EXDEF_MASK (0x8U) 1546 #define EMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U) 1547 #define EMAC_MAC_RX_TX_STATUS_EXDEF_WIDTH (1U) 1548 #define EMAC_MAC_RX_TX_STATUS_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & EMAC_MAC_RX_TX_STATUS_EXDEF_MASK) 1549 1550 #define EMAC_MAC_RX_TX_STATUS_LCOL_MASK (0x10U) 1551 #define EMAC_MAC_RX_TX_STATUS_LCOL_SHIFT (4U) 1552 #define EMAC_MAC_RX_TX_STATUS_LCOL_WIDTH (1U) 1553 #define EMAC_MAC_RX_TX_STATUS_LCOL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_TX_STATUS_LCOL_SHIFT)) & EMAC_MAC_RX_TX_STATUS_LCOL_MASK) 1554 1555 #define EMAC_MAC_RX_TX_STATUS_EXCOL_MASK (0x20U) 1556 #define EMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U) 1557 #define EMAC_MAC_RX_TX_STATUS_EXCOL_WIDTH (1U) 1558 #define EMAC_MAC_RX_TX_STATUS_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & EMAC_MAC_RX_TX_STATUS_EXCOL_MASK) 1559 1560 #define EMAC_MAC_RX_TX_STATUS_RWT_MASK (0x100U) 1561 #define EMAC_MAC_RX_TX_STATUS_RWT_SHIFT (8U) 1562 #define EMAC_MAC_RX_TX_STATUS_RWT_WIDTH (1U) 1563 #define EMAC_MAC_RX_TX_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_RX_TX_STATUS_RWT_SHIFT)) & EMAC_MAC_RX_TX_STATUS_RWT_MASK) 1564 /*! @} */ 1565 1566 /*! @name MAC_VERSION - MAC Version */ 1567 /*! @{ */ 1568 1569 #define EMAC_MAC_VERSION_IPVER_MASK (0xFFU) 1570 #define EMAC_MAC_VERSION_IPVER_SHIFT (0U) 1571 #define EMAC_MAC_VERSION_IPVER_WIDTH (8U) 1572 #define EMAC_MAC_VERSION_IPVER(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VERSION_IPVER_SHIFT)) & EMAC_MAC_VERSION_IPVER_MASK) 1573 1574 #define EMAC_MAC_VERSION_CFGVER_MASK (0xFF00U) 1575 #define EMAC_MAC_VERSION_CFGVER_SHIFT (8U) 1576 #define EMAC_MAC_VERSION_CFGVER_WIDTH (8U) 1577 #define EMAC_MAC_VERSION_CFGVER(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_VERSION_CFGVER_SHIFT)) & EMAC_MAC_VERSION_CFGVER_MASK) 1578 /*! @} */ 1579 1580 /*! @name MAC_DEBUG - MAC Debug */ 1581 /*! @{ */ 1582 1583 #define EMAC_MAC_DEBUG_RPESTS_MASK (0x1U) 1584 #define EMAC_MAC_DEBUG_RPESTS_SHIFT (0U) 1585 #define EMAC_MAC_DEBUG_RPESTS_WIDTH (1U) 1586 #define EMAC_MAC_DEBUG_RPESTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DEBUG_RPESTS_SHIFT)) & EMAC_MAC_DEBUG_RPESTS_MASK) 1587 1588 #define EMAC_MAC_DEBUG_RFCFCSTS_MASK (0x6U) 1589 #define EMAC_MAC_DEBUG_RFCFCSTS_SHIFT (1U) 1590 #define EMAC_MAC_DEBUG_RFCFCSTS_WIDTH (2U) 1591 #define EMAC_MAC_DEBUG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT)) & EMAC_MAC_DEBUG_RFCFCSTS_MASK) 1592 1593 #define EMAC_MAC_DEBUG_TPESTS_MASK (0x10000U) 1594 #define EMAC_MAC_DEBUG_TPESTS_SHIFT (16U) 1595 #define EMAC_MAC_DEBUG_TPESTS_WIDTH (1U) 1596 #define EMAC_MAC_DEBUG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DEBUG_TPESTS_SHIFT)) & EMAC_MAC_DEBUG_TPESTS_MASK) 1597 1598 #define EMAC_MAC_DEBUG_TFCSTS_MASK (0x60000U) 1599 #define EMAC_MAC_DEBUG_TFCSTS_SHIFT (17U) 1600 #define EMAC_MAC_DEBUG_TFCSTS_WIDTH (2U) 1601 #define EMAC_MAC_DEBUG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DEBUG_TFCSTS_SHIFT)) & EMAC_MAC_DEBUG_TFCSTS_MASK) 1602 /*! @} */ 1603 1604 /*! @name MAC_HW_FEATURE0 - MAC Hardware Feature 0 */ 1605 /*! @{ */ 1606 1607 #define EMAC_MAC_HW_FEATURE0_MIISEL_MASK (0x1U) 1608 #define EMAC_MAC_HW_FEATURE0_MIISEL_SHIFT (0U) 1609 #define EMAC_MAC_HW_FEATURE0_MIISEL_WIDTH (1U) 1610 #define EMAC_MAC_HW_FEATURE0_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MIISEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MIISEL_MASK) 1611 1612 #define EMAC_MAC_HW_FEATURE0_GMIISEL_MASK (0x2U) 1613 #define EMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT (1U) 1614 #define EMAC_MAC_HW_FEATURE0_GMIISEL_WIDTH (1U) 1615 #define EMAC_MAC_HW_FEATURE0_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_GMIISEL_MASK) 1616 1617 #define EMAC_MAC_HW_FEATURE0_HDSEL_MASK (0x4U) 1618 #define EMAC_MAC_HW_FEATURE0_HDSEL_SHIFT (2U) 1619 #define EMAC_MAC_HW_FEATURE0_HDSEL_WIDTH (1U) 1620 #define EMAC_MAC_HW_FEATURE0_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_HDSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_HDSEL_MASK) 1621 1622 #define EMAC_MAC_HW_FEATURE0_PCSSEL_MASK (0x8U) 1623 #define EMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT (3U) 1624 #define EMAC_MAC_HW_FEATURE0_PCSSEL_WIDTH (1U) 1625 #define EMAC_MAC_HW_FEATURE0_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_PCSSEL_MASK) 1626 1627 #define EMAC_MAC_HW_FEATURE0_VLHASH_MASK (0x10U) 1628 #define EMAC_MAC_HW_FEATURE0_VLHASH_SHIFT (4U) 1629 #define EMAC_MAC_HW_FEATURE0_VLHASH_WIDTH (1U) 1630 #define EMAC_MAC_HW_FEATURE0_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_VLHASH_SHIFT)) & EMAC_MAC_HW_FEATURE0_VLHASH_MASK) 1631 1632 #define EMAC_MAC_HW_FEATURE0_SMASEL_MASK (0x20U) 1633 #define EMAC_MAC_HW_FEATURE0_SMASEL_SHIFT (5U) 1634 #define EMAC_MAC_HW_FEATURE0_SMASEL_WIDTH (1U) 1635 #define EMAC_MAC_HW_FEATURE0_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_SMASEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_SMASEL_MASK) 1636 1637 #define EMAC_MAC_HW_FEATURE0_RWKSEL_MASK (0x40U) 1638 #define EMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT (6U) 1639 #define EMAC_MAC_HW_FEATURE0_RWKSEL_WIDTH (1U) 1640 #define EMAC_MAC_HW_FEATURE0_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_RWKSEL_MASK) 1641 1642 #define EMAC_MAC_HW_FEATURE0_MGKSEL_MASK (0x80U) 1643 #define EMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT (7U) 1644 #define EMAC_MAC_HW_FEATURE0_MGKSEL_WIDTH (1U) 1645 #define EMAC_MAC_HW_FEATURE0_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MGKSEL_MASK) 1646 1647 #define EMAC_MAC_HW_FEATURE0_MMCSEL_MASK (0x100U) 1648 #define EMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT (8U) 1649 #define EMAC_MAC_HW_FEATURE0_MMCSEL_WIDTH (1U) 1650 #define EMAC_MAC_HW_FEATURE0_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MMCSEL_MASK) 1651 1652 #define EMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK (0x200U) 1653 #define EMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT (9U) 1654 #define EMAC_MAC_HW_FEATURE0_ARPOFFSEL_WIDTH (1U) 1655 #define EMAC_MAC_HW_FEATURE0_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK) 1656 1657 #define EMAC_MAC_HW_FEATURE0_TSSEL_MASK (0x1000U) 1658 #define EMAC_MAC_HW_FEATURE0_TSSEL_SHIFT (12U) 1659 #define EMAC_MAC_HW_FEATURE0_TSSEL_WIDTH (1U) 1660 #define EMAC_MAC_HW_FEATURE0_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_TSSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_TSSEL_MASK) 1661 1662 #define EMAC_MAC_HW_FEATURE0_EEESEL_MASK (0x2000U) 1663 #define EMAC_MAC_HW_FEATURE0_EEESEL_SHIFT (13U) 1664 #define EMAC_MAC_HW_FEATURE0_EEESEL_WIDTH (1U) 1665 #define EMAC_MAC_HW_FEATURE0_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_EEESEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_EEESEL_MASK) 1666 1667 #define EMAC_MAC_HW_FEATURE0_TXCOESEL_MASK (0x4000U) 1668 #define EMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT (14U) 1669 #define EMAC_MAC_HW_FEATURE0_TXCOESEL_WIDTH (1U) 1670 #define EMAC_MAC_HW_FEATURE0_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_TXCOESEL_MASK) 1671 1672 #define EMAC_MAC_HW_FEATURE0_RXCOESEL_MASK (0x10000U) 1673 #define EMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT (16U) 1674 #define EMAC_MAC_HW_FEATURE0_RXCOESEL_WIDTH (1U) 1675 #define EMAC_MAC_HW_FEATURE0_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_RXCOESEL_MASK) 1676 1677 #define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x7C0000U) 1678 #define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18U) 1679 #define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_WIDTH (5U) 1680 #define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK) 1681 1682 #define EMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK (0x800000U) 1683 #define EMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT (23U) 1684 #define EMAC_MAC_HW_FEATURE0_MACADR32SEL_WIDTH (1U) 1685 #define EMAC_MAC_HW_FEATURE0_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK) 1686 1687 #define EMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK (0x1000000U) 1688 #define EMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT (24U) 1689 #define EMAC_MAC_HW_FEATURE0_MACADR64SEL_WIDTH (1U) 1690 #define EMAC_MAC_HW_FEATURE0_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK) 1691 1692 #define EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK (0x6000000U) 1693 #define EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT (25U) 1694 #define EMAC_MAC_HW_FEATURE0_TSSTSSEL_WIDTH (2U) 1695 #define EMAC_MAC_HW_FEATURE0_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK) 1696 1697 #define EMAC_MAC_HW_FEATURE0_SAVLANINS_MASK (0x8000000U) 1698 #define EMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT (27U) 1699 #define EMAC_MAC_HW_FEATURE0_SAVLANINS_WIDTH (1U) 1700 #define EMAC_MAC_HW_FEATURE0_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT)) & EMAC_MAC_HW_FEATURE0_SAVLANINS_MASK) 1701 1702 #define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK (0x70000000U) 1703 #define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT (28U) 1704 #define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_WIDTH (3U) 1705 #define EMAC_MAC_HW_FEATURE0_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT)) & EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK) 1706 /*! @} */ 1707 1708 /*! @name MAC_HW_FEATURE1 - MAC Hardware Feature 1 */ 1709 /*! @{ */ 1710 1711 #define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1FU) 1712 #define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0U) 1713 #define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_WIDTH (5U) 1714 #define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT)) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK) 1715 1716 #define EMAC_MAC_HW_FEATURE1_SPRAM_MASK (0x20U) 1717 #define EMAC_MAC_HW_FEATURE1_SPRAM_SHIFT (5U) 1718 #define EMAC_MAC_HW_FEATURE1_SPRAM_WIDTH (1U) 1719 #define EMAC_MAC_HW_FEATURE1_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_SPRAM_SHIFT)) & EMAC_MAC_HW_FEATURE1_SPRAM_MASK) 1720 1721 #define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x7C0U) 1722 #define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6U) 1723 #define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_WIDTH (5U) 1724 #define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT)) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK) 1725 1726 #define EMAC_MAC_HW_FEATURE1_OSTEN_MASK (0x800U) 1727 #define EMAC_MAC_HW_FEATURE1_OSTEN_SHIFT (11U) 1728 #define EMAC_MAC_HW_FEATURE1_OSTEN_WIDTH (1U) 1729 #define EMAC_MAC_HW_FEATURE1_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_OSTEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_OSTEN_MASK) 1730 1731 #define EMAC_MAC_HW_FEATURE1_PTOEN_MASK (0x1000U) 1732 #define EMAC_MAC_HW_FEATURE1_PTOEN_SHIFT (12U) 1733 #define EMAC_MAC_HW_FEATURE1_PTOEN_WIDTH (1U) 1734 #define EMAC_MAC_HW_FEATURE1_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_PTOEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_PTOEN_MASK) 1735 1736 #define EMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK (0x2000U) 1737 #define EMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT (13U) 1738 #define EMAC_MAC_HW_FEATURE1_ADVTHWORD_WIDTH (1U) 1739 #define EMAC_MAC_HW_FEATURE1_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT)) & EMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK) 1740 1741 #define EMAC_MAC_HW_FEATURE1_ADDR64_MASK (0xC000U) 1742 #define EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT (14U) 1743 #define EMAC_MAC_HW_FEATURE1_ADDR64_WIDTH (2U) 1744 #define EMAC_MAC_HW_FEATURE1_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)) & EMAC_MAC_HW_FEATURE1_ADDR64_MASK) 1745 1746 #define EMAC_MAC_HW_FEATURE1_DCBEN_MASK (0x10000U) 1747 #define EMAC_MAC_HW_FEATURE1_DCBEN_SHIFT (16U) 1748 #define EMAC_MAC_HW_FEATURE1_DCBEN_WIDTH (1U) 1749 #define EMAC_MAC_HW_FEATURE1_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_DCBEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_DCBEN_MASK) 1750 1751 #define EMAC_MAC_HW_FEATURE1_SPHEN_MASK (0x20000U) 1752 #define EMAC_MAC_HW_FEATURE1_SPHEN_SHIFT (17U) 1753 #define EMAC_MAC_HW_FEATURE1_SPHEN_WIDTH (1U) 1754 #define EMAC_MAC_HW_FEATURE1_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_SPHEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_SPHEN_MASK) 1755 1756 #define EMAC_MAC_HW_FEATURE1_TSOEN_MASK (0x40000U) 1757 #define EMAC_MAC_HW_FEATURE1_TSOEN_SHIFT (18U) 1758 #define EMAC_MAC_HW_FEATURE1_TSOEN_WIDTH (1U) 1759 #define EMAC_MAC_HW_FEATURE1_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_TSOEN_SHIFT)) & EMAC_MAC_HW_FEATURE1_TSOEN_MASK) 1760 1761 #define EMAC_MAC_HW_FEATURE1_DBGMEMA_MASK (0x80000U) 1762 #define EMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT (19U) 1763 #define EMAC_MAC_HW_FEATURE1_DBGMEMA_WIDTH (1U) 1764 #define EMAC_MAC_HW_FEATURE1_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT)) & EMAC_MAC_HW_FEATURE1_DBGMEMA_MASK) 1765 1766 #define EMAC_MAC_HW_FEATURE1_AVSEL_MASK (0x100000U) 1767 #define EMAC_MAC_HW_FEATURE1_AVSEL_SHIFT (20U) 1768 #define EMAC_MAC_HW_FEATURE1_AVSEL_WIDTH (1U) 1769 #define EMAC_MAC_HW_FEATURE1_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_AVSEL_SHIFT)) & EMAC_MAC_HW_FEATURE1_AVSEL_MASK) 1770 1771 #define EMAC_MAC_HW_FEATURE1_RAVSEL_MASK (0x200000U) 1772 #define EMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT (21U) 1773 #define EMAC_MAC_HW_FEATURE1_RAVSEL_WIDTH (1U) 1774 #define EMAC_MAC_HW_FEATURE1_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT)) & EMAC_MAC_HW_FEATURE1_RAVSEL_MASK) 1775 1776 #define EMAC_MAC_HW_FEATURE1_POUOST_MASK (0x800000U) 1777 #define EMAC_MAC_HW_FEATURE1_POUOST_SHIFT (23U) 1778 #define EMAC_MAC_HW_FEATURE1_POUOST_WIDTH (1U) 1779 #define EMAC_MAC_HW_FEATURE1_POUOST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_POUOST_SHIFT)) & EMAC_MAC_HW_FEATURE1_POUOST_MASK) 1780 1781 #define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3000000U) 1782 #define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT (24U) 1783 #define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_WIDTH (2U) 1784 #define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT)) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK) 1785 1786 #define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0x78000000U) 1787 #define EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27U) 1788 #define EMAC_MAC_HW_FEATURE1_L3L4FNUM_WIDTH (4U) 1789 #define EMAC_MAC_HW_FEATURE1_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT)) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK) 1790 /*! @} */ 1791 1792 /*! @name MAC_HW_FEATURE2 - MAC Hardware Feature 2 */ 1793 /*! @{ */ 1794 1795 #define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xFU) 1796 #define EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0U) 1797 #define EMAC_MAC_HW_FEATURE2_RXQCNT_WIDTH (4U) 1798 #define EMAC_MAC_HW_FEATURE2_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT)) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK) 1799 1800 #define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0x3C0U) 1801 #define EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6U) 1802 #define EMAC_MAC_HW_FEATURE2_TXQCNT_WIDTH (4U) 1803 #define EMAC_MAC_HW_FEATURE2_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT)) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK) 1804 1805 #define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xF000U) 1806 #define EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12U) 1807 #define EMAC_MAC_HW_FEATURE2_RXCHCNT_WIDTH (4U) 1808 #define EMAC_MAC_HW_FEATURE2_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT)) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK) 1809 1810 #define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0x3C0000U) 1811 #define EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18U) 1812 #define EMAC_MAC_HW_FEATURE2_TXCHCNT_WIDTH (4U) 1813 #define EMAC_MAC_HW_FEATURE2_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT)) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK) 1814 1815 #define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7000000U) 1816 #define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24U) 1817 #define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_WIDTH (3U) 1818 #define EMAC_MAC_HW_FEATURE2_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT)) & EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK) 1819 1820 #define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK (0x70000000U) 1821 #define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT (28U) 1822 #define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_WIDTH (3U) 1823 #define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT)) & EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK) 1824 /*! @} */ 1825 1826 /*! @name MAC_HW_FEATURE3 - MAC Hardware Feature 3 */ 1827 /*! @{ */ 1828 1829 #define EMAC_MAC_HW_FEATURE3_NRVF_MASK (0x7U) 1830 #define EMAC_MAC_HW_FEATURE3_NRVF_SHIFT (0U) 1831 #define EMAC_MAC_HW_FEATURE3_NRVF_WIDTH (3U) 1832 #define EMAC_MAC_HW_FEATURE3_NRVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT)) & EMAC_MAC_HW_FEATURE3_NRVF_MASK) 1833 1834 #define EMAC_MAC_HW_FEATURE3_CBTISEL_MASK (0x10U) 1835 #define EMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT (4U) 1836 #define EMAC_MAC_HW_FEATURE3_CBTISEL_WIDTH (1U) 1837 #define EMAC_MAC_HW_FEATURE3_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_CBTISEL_MASK) 1838 1839 #define EMAC_MAC_HW_FEATURE3_DVLAN_MASK (0x20U) 1840 #define EMAC_MAC_HW_FEATURE3_DVLAN_SHIFT (5U) 1841 #define EMAC_MAC_HW_FEATURE3_DVLAN_WIDTH (1U) 1842 #define EMAC_MAC_HW_FEATURE3_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_DVLAN_SHIFT)) & EMAC_MAC_HW_FEATURE3_DVLAN_MASK) 1843 1844 #define EMAC_MAC_HW_FEATURE3_PDUPSEL_MASK (0x200U) 1845 #define EMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT (9U) 1846 #define EMAC_MAC_HW_FEATURE3_PDUPSEL_WIDTH (1U) 1847 #define EMAC_MAC_HW_FEATURE3_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_PDUPSEL_MASK) 1848 1849 #define EMAC_MAC_HW_FEATURE3_FRPSEL_MASK (0x400U) 1850 #define EMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT (10U) 1851 #define EMAC_MAC_HW_FEATURE3_FRPSEL_WIDTH (1U) 1852 #define EMAC_MAC_HW_FEATURE3_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_FRPSEL_MASK) 1853 1854 #define EMAC_MAC_HW_FEATURE3_FRPBS_MASK (0x1800U) 1855 #define EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT (11U) 1856 #define EMAC_MAC_HW_FEATURE3_FRPBS_WIDTH (2U) 1857 #define EMAC_MAC_HW_FEATURE3_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT)) & EMAC_MAC_HW_FEATURE3_FRPBS_MASK) 1858 1859 #define EMAC_MAC_HW_FEATURE3_FRPES_MASK (0x6000U) 1860 #define EMAC_MAC_HW_FEATURE3_FRPES_SHIFT (13U) 1861 #define EMAC_MAC_HW_FEATURE3_FRPES_WIDTH (2U) 1862 #define EMAC_MAC_HW_FEATURE3_FRPES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT)) & EMAC_MAC_HW_FEATURE3_FRPES_MASK) 1863 1864 #define EMAC_MAC_HW_FEATURE3_ESTSEL_MASK (0x10000U) 1865 #define EMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT (16U) 1866 #define EMAC_MAC_HW_FEATURE3_ESTSEL_WIDTH (1U) 1867 #define EMAC_MAC_HW_FEATURE3_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_ESTSEL_MASK) 1868 1869 #define EMAC_MAC_HW_FEATURE3_ESTDEP_MASK (0xE0000U) 1870 #define EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT (17U) 1871 #define EMAC_MAC_HW_FEATURE3_ESTDEP_WIDTH (3U) 1872 #define EMAC_MAC_HW_FEATURE3_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT)) & EMAC_MAC_HW_FEATURE3_ESTDEP_MASK) 1873 1874 #define EMAC_MAC_HW_FEATURE3_ESTWID_MASK (0x300000U) 1875 #define EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT (20U) 1876 #define EMAC_MAC_HW_FEATURE3_ESTWID_WIDTH (2U) 1877 #define EMAC_MAC_HW_FEATURE3_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT)) & EMAC_MAC_HW_FEATURE3_ESTWID_MASK) 1878 1879 #define EMAC_MAC_HW_FEATURE3_FPESEL_MASK (0x4000000U) 1880 #define EMAC_MAC_HW_FEATURE3_FPESEL_SHIFT (26U) 1881 #define EMAC_MAC_HW_FEATURE3_FPESEL_WIDTH (1U) 1882 #define EMAC_MAC_HW_FEATURE3_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_FPESEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_FPESEL_MASK) 1883 1884 #define EMAC_MAC_HW_FEATURE3_TBSSEL_MASK (0x8000000U) 1885 #define EMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT (27U) 1886 #define EMAC_MAC_HW_FEATURE3_TBSSEL_WIDTH (1U) 1887 #define EMAC_MAC_HW_FEATURE3_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT)) & EMAC_MAC_HW_FEATURE3_TBSSEL_MASK) 1888 1889 #define EMAC_MAC_HW_FEATURE3_ASP_MASK (0x30000000U) 1890 #define EMAC_MAC_HW_FEATURE3_ASP_SHIFT (28U) 1891 #define EMAC_MAC_HW_FEATURE3_ASP_WIDTH (2U) 1892 #define EMAC_MAC_HW_FEATURE3_ASP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_HW_FEATURE3_ASP_SHIFT)) & EMAC_MAC_HW_FEATURE3_ASP_MASK) 1893 /*! @} */ 1894 1895 /*! @name MAC_DPP_FSM_INTERRUPT_STATUS - MAC DPP FSM Interrupt Status */ 1896 /*! @{ */ 1897 1898 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_MASK (0x4U) 1899 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_SHIFT (2U) 1900 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_WIDTH (1U) 1901 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_MASK) 1902 1903 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_MASK (0x8U) 1904 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_SHIFT (3U) 1905 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_WIDTH (1U) 1906 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_MASK) 1907 1908 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_MASK (0x10U) 1909 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_SHIFT (4U) 1910 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_WIDTH (1U) 1911 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_MASK) 1912 1913 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_MASK (0x20U) 1914 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_SHIFT (5U) 1915 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_WIDTH (1U) 1916 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_MASK) 1917 1918 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_MASK (0x100U) 1919 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_SHIFT (8U) 1920 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_WIDTH (1U) 1921 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_MASK) 1922 1923 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_MASK (0x200U) 1924 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_SHIFT (9U) 1925 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_WIDTH (1U) 1926 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_MASK) 1927 1928 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_MASK (0x800U) 1929 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_SHIFT (11U) 1930 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_WIDTH (1U) 1931 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_MASK) 1932 1933 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_MASK (0x1000U) 1934 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_SHIFT (12U) 1935 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_WIDTH (1U) 1936 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_MASK) 1937 1938 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_MASK (0x10000U) 1939 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_SHIFT (16U) 1940 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_WIDTH (1U) 1941 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_MASK) 1942 1943 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_MASK (0x1000000U) 1944 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_SHIFT (24U) 1945 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_WIDTH (1U) 1946 #define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_SHIFT)) & EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_MASK) 1947 /*! @} */ 1948 1949 /*! @name MAC_FSM_CONTROL - MAC FSM Control */ 1950 /*! @{ */ 1951 1952 #define EMAC_MAC_FSM_CONTROL_TMOUTEN_MASK (0x1U) 1953 #define EMAC_MAC_FSM_CONTROL_TMOUTEN_SHIFT (0U) 1954 #define EMAC_MAC_FSM_CONTROL_TMOUTEN_WIDTH (1U) 1955 #define EMAC_MAC_FSM_CONTROL_TMOUTEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_TMOUTEN_SHIFT)) & EMAC_MAC_FSM_CONTROL_TMOUTEN_MASK) 1956 1957 #define EMAC_MAC_FSM_CONTROL_PRTYEN_MASK (0x2U) 1958 #define EMAC_MAC_FSM_CONTROL_PRTYEN_SHIFT (1U) 1959 #define EMAC_MAC_FSM_CONTROL_PRTYEN_WIDTH (1U) 1960 #define EMAC_MAC_FSM_CONTROL_PRTYEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_PRTYEN_SHIFT)) & EMAC_MAC_FSM_CONTROL_PRTYEN_MASK) 1961 1962 #define EMAC_MAC_FSM_CONTROL_TTEIN_MASK (0x100U) 1963 #define EMAC_MAC_FSM_CONTROL_TTEIN_SHIFT (8U) 1964 #define EMAC_MAC_FSM_CONTROL_TTEIN_WIDTH (1U) 1965 #define EMAC_MAC_FSM_CONTROL_TTEIN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_TTEIN_SHIFT)) & EMAC_MAC_FSM_CONTROL_TTEIN_MASK) 1966 1967 #define EMAC_MAC_FSM_CONTROL_RTEIN_MASK (0x200U) 1968 #define EMAC_MAC_FSM_CONTROL_RTEIN_SHIFT (9U) 1969 #define EMAC_MAC_FSM_CONTROL_RTEIN_WIDTH (1U) 1970 #define EMAC_MAC_FSM_CONTROL_RTEIN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_RTEIN_SHIFT)) & EMAC_MAC_FSM_CONTROL_RTEIN_MASK) 1971 1972 #define EMAC_MAC_FSM_CONTROL_ATEIN_MASK (0x800U) 1973 #define EMAC_MAC_FSM_CONTROL_ATEIN_SHIFT (11U) 1974 #define EMAC_MAC_FSM_CONTROL_ATEIN_WIDTH (1U) 1975 #define EMAC_MAC_FSM_CONTROL_ATEIN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_ATEIN_SHIFT)) & EMAC_MAC_FSM_CONTROL_ATEIN_MASK) 1976 1977 #define EMAC_MAC_FSM_CONTROL_PTEIN_MASK (0x1000U) 1978 #define EMAC_MAC_FSM_CONTROL_PTEIN_SHIFT (12U) 1979 #define EMAC_MAC_FSM_CONTROL_PTEIN_WIDTH (1U) 1980 #define EMAC_MAC_FSM_CONTROL_PTEIN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_PTEIN_SHIFT)) & EMAC_MAC_FSM_CONTROL_PTEIN_MASK) 1981 1982 #define EMAC_MAC_FSM_CONTROL_TPEIN_MASK (0x10000U) 1983 #define EMAC_MAC_FSM_CONTROL_TPEIN_SHIFT (16U) 1984 #define EMAC_MAC_FSM_CONTROL_TPEIN_WIDTH (1U) 1985 #define EMAC_MAC_FSM_CONTROL_TPEIN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_TPEIN_SHIFT)) & EMAC_MAC_FSM_CONTROL_TPEIN_MASK) 1986 1987 #define EMAC_MAC_FSM_CONTROL_RPEIN_MASK (0x20000U) 1988 #define EMAC_MAC_FSM_CONTROL_RPEIN_SHIFT (17U) 1989 #define EMAC_MAC_FSM_CONTROL_RPEIN_WIDTH (1U) 1990 #define EMAC_MAC_FSM_CONTROL_RPEIN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_RPEIN_SHIFT)) & EMAC_MAC_FSM_CONTROL_RPEIN_MASK) 1991 1992 #define EMAC_MAC_FSM_CONTROL_APEIN_MASK (0x80000U) 1993 #define EMAC_MAC_FSM_CONTROL_APEIN_SHIFT (19U) 1994 #define EMAC_MAC_FSM_CONTROL_APEIN_WIDTH (1U) 1995 #define EMAC_MAC_FSM_CONTROL_APEIN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_APEIN_SHIFT)) & EMAC_MAC_FSM_CONTROL_APEIN_MASK) 1996 1997 #define EMAC_MAC_FSM_CONTROL_PPEIN_MASK (0x100000U) 1998 #define EMAC_MAC_FSM_CONTROL_PPEIN_SHIFT (20U) 1999 #define EMAC_MAC_FSM_CONTROL_PPEIN_WIDTH (1U) 2000 #define EMAC_MAC_FSM_CONTROL_PPEIN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_PPEIN_SHIFT)) & EMAC_MAC_FSM_CONTROL_PPEIN_MASK) 2001 2002 #define EMAC_MAC_FSM_CONTROL_TLGRNML_MASK (0x1000000U) 2003 #define EMAC_MAC_FSM_CONTROL_TLGRNML_SHIFT (24U) 2004 #define EMAC_MAC_FSM_CONTROL_TLGRNML_WIDTH (1U) 2005 #define EMAC_MAC_FSM_CONTROL_TLGRNML(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_TLGRNML_SHIFT)) & EMAC_MAC_FSM_CONTROL_TLGRNML_MASK) 2006 2007 #define EMAC_MAC_FSM_CONTROL_RLGRNML_MASK (0x2000000U) 2008 #define EMAC_MAC_FSM_CONTROL_RLGRNML_SHIFT (25U) 2009 #define EMAC_MAC_FSM_CONTROL_RLGRNML_WIDTH (1U) 2010 #define EMAC_MAC_FSM_CONTROL_RLGRNML(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_RLGRNML_SHIFT)) & EMAC_MAC_FSM_CONTROL_RLGRNML_MASK) 2011 2012 #define EMAC_MAC_FSM_CONTROL_ALGRNML_MASK (0x8000000U) 2013 #define EMAC_MAC_FSM_CONTROL_ALGRNML_SHIFT (27U) 2014 #define EMAC_MAC_FSM_CONTROL_ALGRNML_WIDTH (1U) 2015 #define EMAC_MAC_FSM_CONTROL_ALGRNML(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_ALGRNML_SHIFT)) & EMAC_MAC_FSM_CONTROL_ALGRNML_MASK) 2016 2017 #define EMAC_MAC_FSM_CONTROL_PLGRNML_MASK (0x10000000U) 2018 #define EMAC_MAC_FSM_CONTROL_PLGRNML_SHIFT (28U) 2019 #define EMAC_MAC_FSM_CONTROL_PLGRNML_WIDTH (1U) 2020 #define EMAC_MAC_FSM_CONTROL_PLGRNML(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_CONTROL_PLGRNML_SHIFT)) & EMAC_MAC_FSM_CONTROL_PLGRNML_MASK) 2021 /*! @} */ 2022 2023 /*! @name MAC_FSM_ACT_TIMER - MAC FSM ACT Timer */ 2024 /*! @{ */ 2025 2026 #define EMAC_MAC_FSM_ACT_TIMER_TMR_MASK (0x3FFU) 2027 #define EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT (0U) 2028 #define EMAC_MAC_FSM_ACT_TIMER_TMR_WIDTH (10U) 2029 #define EMAC_MAC_FSM_ACT_TIMER_TMR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT)) & EMAC_MAC_FSM_ACT_TIMER_TMR_MASK) 2030 2031 #define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK (0xF0000U) 2032 #define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT (16U) 2033 #define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_WIDTH (4U) 2034 #define EMAC_MAC_FSM_ACT_TIMER_NTMRMD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT)) & EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK) 2035 2036 #define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK (0xF00000U) 2037 #define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT (20U) 2038 #define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_WIDTH (4U) 2039 #define EMAC_MAC_FSM_ACT_TIMER_LTMRMD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT)) & EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK) 2040 /*! @} */ 2041 2042 /*! @name SCS_REG1 - SCS_REG 1 */ 2043 /*! @{ */ 2044 2045 #define EMAC_SCS_REG1_MAC_SCS1_MASK (0xFFFFFFFFU) 2046 #define EMAC_SCS_REG1_MAC_SCS1_SHIFT (0U) 2047 #define EMAC_SCS_REG1_MAC_SCS1_WIDTH (32U) 2048 #define EMAC_SCS_REG1_MAC_SCS1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_SCS_REG1_MAC_SCS1_SHIFT)) & EMAC_SCS_REG1_MAC_SCS1_MASK) 2049 /*! @} */ 2050 2051 /*! @name MAC_MDIO_ADDRESS - MAC MDIO Address */ 2052 /*! @{ */ 2053 2054 #define EMAC_MAC_MDIO_ADDRESS_GB_MASK (0x1U) 2055 #define EMAC_MAC_MDIO_ADDRESS_GB_SHIFT (0U) 2056 #define EMAC_MAC_MDIO_ADDRESS_GB_WIDTH (1U) 2057 #define EMAC_MAC_MDIO_ADDRESS_GB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_GB_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_GB_MASK) 2058 2059 #define EMAC_MAC_MDIO_ADDRESS_C45E_MASK (0x2U) 2060 #define EMAC_MAC_MDIO_ADDRESS_C45E_SHIFT (1U) 2061 #define EMAC_MAC_MDIO_ADDRESS_C45E_WIDTH (1U) 2062 #define EMAC_MAC_MDIO_ADDRESS_C45E(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_C45E_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_C45E_MASK) 2063 2064 #define EMAC_MAC_MDIO_ADDRESS_GOC_0_MASK (0x4U) 2065 #define EMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U) 2066 #define EMAC_MAC_MDIO_ADDRESS_GOC_0_WIDTH (1U) 2067 #define EMAC_MAC_MDIO_ADDRESS_GOC_0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_GOC_0_MASK) 2068 2069 #define EMAC_MAC_MDIO_ADDRESS_GOC_1_MASK (0x8U) 2070 #define EMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U) 2071 #define EMAC_MAC_MDIO_ADDRESS_GOC_1_WIDTH (1U) 2072 #define EMAC_MAC_MDIO_ADDRESS_GOC_1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_GOC_1_MASK) 2073 2074 #define EMAC_MAC_MDIO_ADDRESS_SKAP_MASK (0x10U) 2075 #define EMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U) 2076 #define EMAC_MAC_MDIO_ADDRESS_SKAP_WIDTH (1U) 2077 #define EMAC_MAC_MDIO_ADDRESS_SKAP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_SKAP_MASK) 2078 2079 #define EMAC_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) 2080 #define EMAC_MAC_MDIO_ADDRESS_CR_SHIFT (8U) 2081 #define EMAC_MAC_MDIO_ADDRESS_CR_WIDTH (4U) 2082 #define EMAC_MAC_MDIO_ADDRESS_CR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_CR_MASK) 2083 2084 #define EMAC_MAC_MDIO_ADDRESS_NTC_MASK (0x7000U) 2085 #define EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT (12U) 2086 #define EMAC_MAC_MDIO_ADDRESS_NTC_WIDTH (3U) 2087 #define EMAC_MAC_MDIO_ADDRESS_NTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_NTC_MASK) 2088 2089 #define EMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1F0000U) 2090 #define EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT (16U) 2091 #define EMAC_MAC_MDIO_ADDRESS_RDA_WIDTH (5U) 2092 #define EMAC_MAC_MDIO_ADDRESS_RDA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_RDA_MASK) 2093 2094 #define EMAC_MAC_MDIO_ADDRESS_PA_MASK (0x3E00000U) 2095 #define EMAC_MAC_MDIO_ADDRESS_PA_SHIFT (21U) 2096 #define EMAC_MAC_MDIO_ADDRESS_PA_WIDTH (5U) 2097 #define EMAC_MAC_MDIO_ADDRESS_PA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_PA_MASK) 2098 2099 #define EMAC_MAC_MDIO_ADDRESS_BTB_MASK (0x4000000U) 2100 #define EMAC_MAC_MDIO_ADDRESS_BTB_SHIFT (26U) 2101 #define EMAC_MAC_MDIO_ADDRESS_BTB_WIDTH (1U) 2102 #define EMAC_MAC_MDIO_ADDRESS_BTB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_BTB_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_BTB_MASK) 2103 2104 #define EMAC_MAC_MDIO_ADDRESS_PSE_MASK (0x8000000U) 2105 #define EMAC_MAC_MDIO_ADDRESS_PSE_SHIFT (27U) 2106 #define EMAC_MAC_MDIO_ADDRESS_PSE_WIDTH (1U) 2107 #define EMAC_MAC_MDIO_ADDRESS_PSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_ADDRESS_PSE_SHIFT)) & EMAC_MAC_MDIO_ADDRESS_PSE_MASK) 2108 /*! @} */ 2109 2110 /*! @name MAC_MDIO_DATA - MAC MDIO Data */ 2111 /*! @{ */ 2112 2113 #define EMAC_MAC_MDIO_DATA_GD_MASK (0xFFFFU) 2114 #define EMAC_MAC_MDIO_DATA_GD_SHIFT (0U) 2115 #define EMAC_MAC_MDIO_DATA_GD_WIDTH (16U) 2116 #define EMAC_MAC_MDIO_DATA_GD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_DATA_GD_SHIFT)) & EMAC_MAC_MDIO_DATA_GD_MASK) 2117 2118 #define EMAC_MAC_MDIO_DATA_RA_MASK (0xFFFF0000U) 2119 #define EMAC_MAC_MDIO_DATA_RA_SHIFT (16U) 2120 #define EMAC_MAC_MDIO_DATA_RA_WIDTH (16U) 2121 #define EMAC_MAC_MDIO_DATA_RA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_MDIO_DATA_RA_SHIFT)) & EMAC_MAC_MDIO_DATA_RA_MASK) 2122 /*! @} */ 2123 2124 /*! @name MAC_CSR_SW_CTRL - MAC CSR Software Control */ 2125 /*! @{ */ 2126 2127 #define EMAC_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U) 2128 #define EMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U) 2129 #define EMAC_MAC_CSR_SW_CTRL_RCWE_WIDTH (1U) 2130 #define EMAC_MAC_CSR_SW_CTRL_RCWE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & EMAC_MAC_CSR_SW_CTRL_RCWE_MASK) 2131 2132 #define EMAC_MAC_CSR_SW_CTRL_SEEN_MASK (0x100U) 2133 #define EMAC_MAC_CSR_SW_CTRL_SEEN_SHIFT (8U) 2134 #define EMAC_MAC_CSR_SW_CTRL_SEEN_WIDTH (1U) 2135 #define EMAC_MAC_CSR_SW_CTRL_SEEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_CSR_SW_CTRL_SEEN_SHIFT)) & EMAC_MAC_CSR_SW_CTRL_SEEN_MASK) 2136 /*! @} */ 2137 2138 /*! @name MAC_FPE_CTRL_STS - MAC FPE Control STS */ 2139 /*! @{ */ 2140 2141 #define EMAC_MAC_FPE_CTRL_STS_EFPE_MASK (0x1U) 2142 #define EMAC_MAC_FPE_CTRL_STS_EFPE_SHIFT (0U) 2143 #define EMAC_MAC_FPE_CTRL_STS_EFPE_WIDTH (1U) 2144 #define EMAC_MAC_FPE_CTRL_STS_EFPE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & EMAC_MAC_FPE_CTRL_STS_EFPE_MASK) 2145 2146 #define EMAC_MAC_FPE_CTRL_STS_SVER_MASK (0x2U) 2147 #define EMAC_MAC_FPE_CTRL_STS_SVER_SHIFT (1U) 2148 #define EMAC_MAC_FPE_CTRL_STS_SVER_WIDTH (1U) 2149 #define EMAC_MAC_FPE_CTRL_STS_SVER(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FPE_CTRL_STS_SVER_SHIFT)) & EMAC_MAC_FPE_CTRL_STS_SVER_MASK) 2150 2151 #define EMAC_MAC_FPE_CTRL_STS_SRSP_MASK (0x4U) 2152 #define EMAC_MAC_FPE_CTRL_STS_SRSP_SHIFT (2U) 2153 #define EMAC_MAC_FPE_CTRL_STS_SRSP_WIDTH (1U) 2154 #define EMAC_MAC_FPE_CTRL_STS_SRSP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & EMAC_MAC_FPE_CTRL_STS_SRSP_MASK) 2155 2156 #define EMAC_MAC_FPE_CTRL_STS_S1_SET_0_MASK (0x8U) 2157 #define EMAC_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U) 2158 #define EMAC_MAC_FPE_CTRL_STS_S1_SET_0_WIDTH (1U) 2159 #define EMAC_MAC_FPE_CTRL_STS_S1_SET_0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & EMAC_MAC_FPE_CTRL_STS_S1_SET_0_MASK) 2160 2161 #define EMAC_MAC_FPE_CTRL_STS_RVER_MASK (0x10000U) 2162 #define EMAC_MAC_FPE_CTRL_STS_RVER_SHIFT (16U) 2163 #define EMAC_MAC_FPE_CTRL_STS_RVER_WIDTH (1U) 2164 #define EMAC_MAC_FPE_CTRL_STS_RVER(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FPE_CTRL_STS_RVER_SHIFT)) & EMAC_MAC_FPE_CTRL_STS_RVER_MASK) 2165 2166 #define EMAC_MAC_FPE_CTRL_STS_RRSP_MASK (0x20000U) 2167 #define EMAC_MAC_FPE_CTRL_STS_RRSP_SHIFT (17U) 2168 #define EMAC_MAC_FPE_CTRL_STS_RRSP_WIDTH (1U) 2169 #define EMAC_MAC_FPE_CTRL_STS_RRSP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & EMAC_MAC_FPE_CTRL_STS_RRSP_MASK) 2170 2171 #define EMAC_MAC_FPE_CTRL_STS_TVER_MASK (0x40000U) 2172 #define EMAC_MAC_FPE_CTRL_STS_TVER_SHIFT (18U) 2173 #define EMAC_MAC_FPE_CTRL_STS_TVER_WIDTH (1U) 2174 #define EMAC_MAC_FPE_CTRL_STS_TVER(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FPE_CTRL_STS_TVER_SHIFT)) & EMAC_MAC_FPE_CTRL_STS_TVER_MASK) 2175 2176 #define EMAC_MAC_FPE_CTRL_STS_TRSP_MASK (0x80000U) 2177 #define EMAC_MAC_FPE_CTRL_STS_TRSP_SHIFT (19U) 2178 #define EMAC_MAC_FPE_CTRL_STS_TRSP_WIDTH (1U) 2179 #define EMAC_MAC_FPE_CTRL_STS_TRSP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & EMAC_MAC_FPE_CTRL_STS_TRSP_MASK) 2180 /*! @} */ 2181 2182 /*! @name MAC_PRESN_TIME_NS - MAC Presentation Time */ 2183 /*! @{ */ 2184 2185 #define EMAC_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFFU) 2186 #define EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT (0U) 2187 #define EMAC_MAC_PRESN_TIME_NS_MPTN_WIDTH (32U) 2188 #define EMAC_MAC_PRESN_TIME_NS_MPTN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & EMAC_MAC_PRESN_TIME_NS_MPTN_MASK) 2189 /*! @} */ 2190 2191 /*! @name MAC_PRESN_TIME_UPDT - MAC Presentation Time Update */ 2192 /*! @{ */ 2193 2194 #define EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFFU) 2195 #define EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0U) 2196 #define EMAC_MAC_PRESN_TIME_UPDT_MPTU_WIDTH (32U) 2197 #define EMAC_MAC_PRESN_TIME_UPDT_MPTU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK) 2198 /*! @} */ 2199 2200 /*! @name MAC_ADDRESS0_HIGH - MAC Address 0 High */ 2201 /*! @{ */ 2202 2203 #define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFFU) 2204 #define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0U) 2205 #define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_WIDTH (16U) 2206 #define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT)) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK) 2207 2208 #define EMAC_MAC_ADDRESS0_HIGH_DCS_MASK (0x30000U) 2209 #define EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT (16U) 2210 #define EMAC_MAC_ADDRESS0_HIGH_DCS_WIDTH (2U) 2211 #define EMAC_MAC_ADDRESS0_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT)) & EMAC_MAC_ADDRESS0_HIGH_DCS_MASK) 2212 2213 #define EMAC_MAC_ADDRESS0_HIGH_AE_MASK (0x80000000U) 2214 #define EMAC_MAC_ADDRESS0_HIGH_AE_SHIFT (31U) 2215 #define EMAC_MAC_ADDRESS0_HIGH_AE_WIDTH (1U) 2216 #define EMAC_MAC_ADDRESS0_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS0_HIGH_AE_SHIFT)) & EMAC_MAC_ADDRESS0_HIGH_AE_MASK) 2217 /*! @} */ 2218 2219 /*! @name MAC_ADDRESS0_LOW - MAC Address 0 Low */ 2220 /*! @{ */ 2221 2222 #define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFFU) 2223 #define EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0U) 2224 #define EMAC_MAC_ADDRESS0_LOW_ADDRLO_WIDTH (32U) 2225 #define EMAC_MAC_ADDRESS0_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT)) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK) 2226 /*! @} */ 2227 2228 /*! @name MAC_ADDRESS1_HIGH - MAC Address 1 High */ 2229 /*! @{ */ 2230 2231 #define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xFFFFU) 2232 #define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT (0U) 2233 #define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_WIDTH (16U) 2234 #define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK) 2235 2236 #define EMAC_MAC_ADDRESS1_HIGH_DCS_MASK (0x30000U) 2237 #define EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT (16U) 2238 #define EMAC_MAC_ADDRESS1_HIGH_DCS_WIDTH (2U) 2239 #define EMAC_MAC_ADDRESS1_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK) 2240 2241 #define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3F000000U) 2242 #define EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT (24U) 2243 #define EMAC_MAC_ADDRESS1_HIGH_MBC_WIDTH (6U) 2244 #define EMAC_MAC_ADDRESS1_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK) 2245 2246 #define EMAC_MAC_ADDRESS1_HIGH_SA_MASK (0x40000000U) 2247 #define EMAC_MAC_ADDRESS1_HIGH_SA_SHIFT (30U) 2248 #define EMAC_MAC_ADDRESS1_HIGH_SA_WIDTH (1U) 2249 #define EMAC_MAC_ADDRESS1_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_SA_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_SA_MASK) 2250 2251 #define EMAC_MAC_ADDRESS1_HIGH_AE_MASK (0x80000000U) 2252 #define EMAC_MAC_ADDRESS1_HIGH_AE_SHIFT (31U) 2253 #define EMAC_MAC_ADDRESS1_HIGH_AE_WIDTH (1U) 2254 #define EMAC_MAC_ADDRESS1_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_HIGH_AE_SHIFT)) & EMAC_MAC_ADDRESS1_HIGH_AE_MASK) 2255 /*! @} */ 2256 2257 /*! @name MAC_ADDRESS1_LOW - MAC Address 1 Low */ 2258 /*! @{ */ 2259 2260 #define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xFFFFFFFFU) 2261 #define EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT (0U) 2262 #define EMAC_MAC_ADDRESS1_LOW_ADDRLO_WIDTH (32U) 2263 #define EMAC_MAC_ADDRESS1_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT)) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK) 2264 /*! @} */ 2265 2266 /*! @name MAC_ADDRESS2_HIGH - MAC Address 2 High */ 2267 /*! @{ */ 2268 2269 #define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xFFFFU) 2270 #define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT (0U) 2271 #define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_WIDTH (16U) 2272 #define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK) 2273 2274 #define EMAC_MAC_ADDRESS2_HIGH_DCS_MASK (0x30000U) 2275 #define EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT (16U) 2276 #define EMAC_MAC_ADDRESS2_HIGH_DCS_WIDTH (2U) 2277 #define EMAC_MAC_ADDRESS2_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK) 2278 2279 #define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3F000000U) 2280 #define EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT (24U) 2281 #define EMAC_MAC_ADDRESS2_HIGH_MBC_WIDTH (6U) 2282 #define EMAC_MAC_ADDRESS2_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK) 2283 2284 #define EMAC_MAC_ADDRESS2_HIGH_SA_MASK (0x40000000U) 2285 #define EMAC_MAC_ADDRESS2_HIGH_SA_SHIFT (30U) 2286 #define EMAC_MAC_ADDRESS2_HIGH_SA_WIDTH (1U) 2287 #define EMAC_MAC_ADDRESS2_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_SA_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_SA_MASK) 2288 2289 #define EMAC_MAC_ADDRESS2_HIGH_AE_MASK (0x80000000U) 2290 #define EMAC_MAC_ADDRESS2_HIGH_AE_SHIFT (31U) 2291 #define EMAC_MAC_ADDRESS2_HIGH_AE_WIDTH (1U) 2292 #define EMAC_MAC_ADDRESS2_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_HIGH_AE_SHIFT)) & EMAC_MAC_ADDRESS2_HIGH_AE_MASK) 2293 /*! @} */ 2294 2295 /*! @name MAC_ADDRESS2_LOW - MAC Address 2 Low */ 2296 /*! @{ */ 2297 2298 #define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xFFFFFFFFU) 2299 #define EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT (0U) 2300 #define EMAC_MAC_ADDRESS2_LOW_ADDRLO_WIDTH (32U) 2301 #define EMAC_MAC_ADDRESS2_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT)) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK) 2302 /*! @} */ 2303 2304 /*! @name MMC_CONTROL - MMC Control */ 2305 /*! @{ */ 2306 2307 #define EMAC_MMC_CONTROL_CNTRST_MASK (0x1U) 2308 #define EMAC_MMC_CONTROL_CNTRST_SHIFT (0U) 2309 #define EMAC_MMC_CONTROL_CNTRST_WIDTH (1U) 2310 #define EMAC_MMC_CONTROL_CNTRST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_CONTROL_CNTRST_SHIFT)) & EMAC_MMC_CONTROL_CNTRST_MASK) 2311 2312 #define EMAC_MMC_CONTROL_CNTSTOPRO_MASK (0x2U) 2313 #define EMAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U) 2314 #define EMAC_MMC_CONTROL_CNTSTOPRO_WIDTH (1U) 2315 #define EMAC_MMC_CONTROL_CNTSTOPRO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & EMAC_MMC_CONTROL_CNTSTOPRO_MASK) 2316 2317 #define EMAC_MMC_CONTROL_RSTONRD_MASK (0x4U) 2318 #define EMAC_MMC_CONTROL_RSTONRD_SHIFT (2U) 2319 #define EMAC_MMC_CONTROL_RSTONRD_WIDTH (1U) 2320 #define EMAC_MMC_CONTROL_RSTONRD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_CONTROL_RSTONRD_SHIFT)) & EMAC_MMC_CONTROL_RSTONRD_MASK) 2321 2322 #define EMAC_MMC_CONTROL_CNTFREEZ_MASK (0x8U) 2323 #define EMAC_MMC_CONTROL_CNTFREEZ_SHIFT (3U) 2324 #define EMAC_MMC_CONTROL_CNTFREEZ_WIDTH (1U) 2325 #define EMAC_MMC_CONTROL_CNTFREEZ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & EMAC_MMC_CONTROL_CNTFREEZ_MASK) 2326 2327 #define EMAC_MMC_CONTROL_CNTPRST_MASK (0x10U) 2328 #define EMAC_MMC_CONTROL_CNTPRST_SHIFT (4U) 2329 #define EMAC_MMC_CONTROL_CNTPRST_WIDTH (1U) 2330 #define EMAC_MMC_CONTROL_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_CONTROL_CNTPRST_SHIFT)) & EMAC_MMC_CONTROL_CNTPRST_MASK) 2331 2332 #define EMAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U) 2333 #define EMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U) 2334 #define EMAC_MMC_CONTROL_CNTPRSTLVL_WIDTH (1U) 2335 #define EMAC_MMC_CONTROL_CNTPRSTLVL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & EMAC_MMC_CONTROL_CNTPRSTLVL_MASK) 2336 2337 #define EMAC_MMC_CONTROL_UCDBC_MASK (0x100U) 2338 #define EMAC_MMC_CONTROL_UCDBC_SHIFT (8U) 2339 #define EMAC_MMC_CONTROL_UCDBC_WIDTH (1U) 2340 #define EMAC_MMC_CONTROL_UCDBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_CONTROL_UCDBC_SHIFT)) & EMAC_MMC_CONTROL_UCDBC_MASK) 2341 /*! @} */ 2342 2343 /*! @name MMC_RX_INTERRUPT - MMC Receive Interrupt */ 2344 /*! @{ */ 2345 2346 #define EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U) 2347 #define EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U) 2348 #define EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_WIDTH (1U) 2349 #define EMAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK) 2350 2351 #define EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U) 2352 #define EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U) 2353 #define EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_WIDTH (1U) 2354 #define EMAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK) 2355 2356 #define EMAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U) 2357 #define EMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U) 2358 #define EMAC_MMC_RX_INTERRUPT_RXGOCTIS_WIDTH (1U) 2359 #define EMAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK) 2360 2361 #define EMAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U) 2362 #define EMAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U) 2363 #define EMAC_MMC_RX_INTERRUPT_RXBCGPIS_WIDTH (1U) 2364 #define EMAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK) 2365 2366 #define EMAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U) 2367 #define EMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U) 2368 #define EMAC_MMC_RX_INTERRUPT_RXMCGPIS_WIDTH (1U) 2369 #define EMAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK) 2370 2371 #define EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U) 2372 #define EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U) 2373 #define EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_WIDTH (1U) 2374 #define EMAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK) 2375 2376 #define EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U) 2377 #define EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U) 2378 #define EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_WIDTH (1U) 2379 #define EMAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK) 2380 2381 #define EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U) 2382 #define EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U) 2383 #define EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_WIDTH (1U) 2384 #define EMAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK) 2385 2386 #define EMAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U) 2387 #define EMAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U) 2388 #define EMAC_MMC_RX_INTERRUPT_RXJABERPIS_WIDTH (1U) 2389 #define EMAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK) 2390 2391 #define EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U) 2392 #define EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U) 2393 #define EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_WIDTH (1U) 2394 #define EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK) 2395 2396 #define EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U) 2397 #define EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U) 2398 #define EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_WIDTH (1U) 2399 #define EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK) 2400 2401 #define EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U) 2402 #define EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U) 2403 #define EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_WIDTH (1U) 2404 #define EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK) 2405 2406 #define EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U) 2407 #define EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U) 2408 #define EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_WIDTH (1U) 2409 #define EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK) 2410 2411 #define EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U) 2412 #define EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U) 2413 #define EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_WIDTH (1U) 2414 #define EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK) 2415 2416 #define EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U) 2417 #define EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U) 2418 #define EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_WIDTH (1U) 2419 #define EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK) 2420 2421 #define EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U) 2422 #define EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U) 2423 #define EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_WIDTH (1U) 2424 #define EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK) 2425 2426 #define EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U) 2427 #define EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U) 2428 #define EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_WIDTH (1U) 2429 #define EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK) 2430 2431 #define EMAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U) 2432 #define EMAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U) 2433 #define EMAC_MMC_RX_INTERRUPT_RXUCGPIS_WIDTH (1U) 2434 #define EMAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK) 2435 2436 #define EMAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U) 2437 #define EMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U) 2438 #define EMAC_MMC_RX_INTERRUPT_RXLENERPIS_WIDTH (1U) 2439 #define EMAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK) 2440 2441 #define EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U) 2442 #define EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U) 2443 #define EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_WIDTH (1U) 2444 #define EMAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK) 2445 2446 #define EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U) 2447 #define EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U) 2448 #define EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_WIDTH (1U) 2449 #define EMAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK) 2450 2451 #define EMAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U) 2452 #define EMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U) 2453 #define EMAC_MMC_RX_INTERRUPT_RXFOVPIS_WIDTH (1U) 2454 #define EMAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK) 2455 2456 #define EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U) 2457 #define EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U) 2458 #define EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_WIDTH (1U) 2459 #define EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK) 2460 2461 #define EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U) 2462 #define EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U) 2463 #define EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_WIDTH (1U) 2464 #define EMAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK) 2465 2466 #define EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U) 2467 #define EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U) 2468 #define EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_WIDTH (1U) 2469 #define EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK) 2470 2471 #define EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U) 2472 #define EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U) 2473 #define EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_WIDTH (1U) 2474 #define EMAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK) 2475 /*! @} */ 2476 2477 /*! @name MMC_TX_INTERRUPT - MMC Transmit Interrupt */ 2478 /*! @{ */ 2479 2480 #define EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U) 2481 #define EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U) 2482 #define EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_WIDTH (1U) 2483 #define EMAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK) 2484 2485 #define EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U) 2486 #define EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U) 2487 #define EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_WIDTH (1U) 2488 #define EMAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK) 2489 2490 #define EMAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U) 2491 #define EMAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U) 2492 #define EMAC_MMC_TX_INTERRUPT_TXBCGPIS_WIDTH (1U) 2493 #define EMAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK) 2494 2495 #define EMAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U) 2496 #define EMAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U) 2497 #define EMAC_MMC_TX_INTERRUPT_TXMCGPIS_WIDTH (1U) 2498 #define EMAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK) 2499 2500 #define EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U) 2501 #define EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U) 2502 #define EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_WIDTH (1U) 2503 #define EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK) 2504 2505 #define EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U) 2506 #define EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U) 2507 #define EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_WIDTH (1U) 2508 #define EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK) 2509 2510 #define EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U) 2511 #define EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U) 2512 #define EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_WIDTH (1U) 2513 #define EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK) 2514 2515 #define EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U) 2516 #define EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U) 2517 #define EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_WIDTH (1U) 2518 #define EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK) 2519 2520 #define EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U) 2521 #define EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U) 2522 #define EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_WIDTH (1U) 2523 #define EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK) 2524 2525 #define EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U) 2526 #define EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U) 2527 #define EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_WIDTH (1U) 2528 #define EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK) 2529 2530 #define EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U) 2531 #define EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U) 2532 #define EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_WIDTH (1U) 2533 #define EMAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK) 2534 2535 #define EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U) 2536 #define EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U) 2537 #define EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_WIDTH (1U) 2538 #define EMAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK) 2539 2540 #define EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U) 2541 #define EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U) 2542 #define EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_WIDTH (1U) 2543 #define EMAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK) 2544 2545 #define EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U) 2546 #define EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U) 2547 #define EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_WIDTH (1U) 2548 #define EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK) 2549 2550 #define EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U) 2551 #define EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U) 2552 #define EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_WIDTH (1U) 2553 #define EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK) 2554 2555 #define EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U) 2556 #define EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U) 2557 #define EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_WIDTH (1U) 2558 #define EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK) 2559 2560 #define EMAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U) 2561 #define EMAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U) 2562 #define EMAC_MMC_TX_INTERRUPT_TXDEFPIS_WIDTH (1U) 2563 #define EMAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK) 2564 2565 #define EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U) 2566 #define EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U) 2567 #define EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_WIDTH (1U) 2568 #define EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK) 2569 2570 #define EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U) 2571 #define EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U) 2572 #define EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_WIDTH (1U) 2573 #define EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK) 2574 2575 #define EMAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U) 2576 #define EMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U) 2577 #define EMAC_MMC_TX_INTERRUPT_TXCARERPIS_WIDTH (1U) 2578 #define EMAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK) 2579 2580 #define EMAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U) 2581 #define EMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U) 2582 #define EMAC_MMC_TX_INTERRUPT_TXGOCTIS_WIDTH (1U) 2583 #define EMAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK) 2584 2585 #define EMAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U) 2586 #define EMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U) 2587 #define EMAC_MMC_TX_INTERRUPT_TXGPKTIS_WIDTH (1U) 2588 #define EMAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK) 2589 2590 #define EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U) 2591 #define EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U) 2592 #define EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_WIDTH (1U) 2593 #define EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK) 2594 2595 #define EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U) 2596 #define EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U) 2597 #define EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_WIDTH (1U) 2598 #define EMAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK) 2599 2600 #define EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U) 2601 #define EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U) 2602 #define EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_WIDTH (1U) 2603 #define EMAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK) 2604 2605 #define EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U) 2606 #define EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U) 2607 #define EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_WIDTH (1U) 2608 #define EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK) 2609 /*! @} */ 2610 2611 /*! @name MMC_RX_INTERRUPT_MASK - MMC Receive Interrupt Mask */ 2612 /*! @{ */ 2613 2614 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U) 2615 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U) 2616 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_WIDTH (1U) 2617 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK) 2618 2619 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U) 2620 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U) 2621 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_WIDTH (1U) 2622 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK) 2623 2624 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U) 2625 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U) 2626 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_WIDTH (1U) 2627 #define EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK) 2628 2629 #define EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U) 2630 #define EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U) 2631 #define EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_WIDTH (1U) 2632 #define EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK) 2633 2634 #define EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U) 2635 #define EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U) 2636 #define EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_WIDTH (1U) 2637 #define EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK) 2638 2639 #define EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U) 2640 #define EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U) 2641 #define EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_WIDTH (1U) 2642 #define EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK) 2643 2644 #define EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U) 2645 #define EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U) 2646 #define EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_WIDTH (1U) 2647 #define EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK) 2648 2649 #define EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U) 2650 #define EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U) 2651 #define EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_WIDTH (1U) 2652 #define EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK) 2653 2654 #define EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U) 2655 #define EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U) 2656 #define EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_WIDTH (1U) 2657 #define EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK) 2658 2659 #define EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U) 2660 #define EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U) 2661 #define EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_WIDTH (1U) 2662 #define EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK) 2663 2664 #define EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U) 2665 #define EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U) 2666 #define EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_WIDTH (1U) 2667 #define EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK) 2668 2669 #define EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U) 2670 #define EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U) 2671 #define EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_WIDTH (1U) 2672 #define EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK) 2673 2674 #define EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U) 2675 #define EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U) 2676 #define EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_WIDTH (1U) 2677 #define EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK) 2678 2679 #define EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U) 2680 #define EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U) 2681 #define EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_WIDTH (1U) 2682 #define EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK) 2683 2684 #define EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U) 2685 #define EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U) 2686 #define EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_WIDTH (1U) 2687 #define EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK) 2688 2689 #define EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U) 2690 #define EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U) 2691 #define EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_WIDTH (1U) 2692 #define EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK) 2693 2694 #define EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U) 2695 #define EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U) 2696 #define EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_WIDTH (1U) 2697 #define EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK) 2698 2699 #define EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U) 2700 #define EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U) 2701 #define EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_WIDTH (1U) 2702 #define EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK) 2703 2704 #define EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U) 2705 #define EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U) 2706 #define EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_WIDTH (1U) 2707 #define EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK) 2708 2709 #define EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U) 2710 #define EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U) 2711 #define EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_WIDTH (1U) 2712 #define EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK) 2713 2714 #define EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U) 2715 #define EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U) 2716 #define EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_WIDTH (1U) 2717 #define EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK) 2718 2719 #define EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U) 2720 #define EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U) 2721 #define EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_WIDTH (1U) 2722 #define EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK) 2723 2724 #define EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U) 2725 #define EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U) 2726 #define EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_WIDTH (1U) 2727 #define EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK) 2728 2729 #define EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U) 2730 #define EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U) 2731 #define EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_WIDTH (1U) 2732 #define EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK) 2733 2734 #define EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U) 2735 #define EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U) 2736 #define EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_WIDTH (1U) 2737 #define EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK) 2738 2739 #define EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U) 2740 #define EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U) 2741 #define EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_WIDTH (1U) 2742 #define EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK) 2743 /*! @} */ 2744 2745 /*! @name MMC_TX_INTERRUPT_MASK - MMC Transmit Interrupt Mask */ 2746 /*! @{ */ 2747 2748 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U) 2749 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U) 2750 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_WIDTH (1U) 2751 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK) 2752 2753 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U) 2754 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U) 2755 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_WIDTH (1U) 2756 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK) 2757 2758 #define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U) 2759 #define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U) 2760 #define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_WIDTH (1U) 2761 #define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK) 2762 2763 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U) 2764 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U) 2765 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_WIDTH (1U) 2766 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK) 2767 2768 #define EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U) 2769 #define EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U) 2770 #define EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_WIDTH (1U) 2771 #define EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK) 2772 2773 #define EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U) 2774 #define EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U) 2775 #define EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_WIDTH (1U) 2776 #define EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK) 2777 2778 #define EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U) 2779 #define EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U) 2780 #define EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_WIDTH (1U) 2781 #define EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK) 2782 2783 #define EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U) 2784 #define EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U) 2785 #define EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_WIDTH (1U) 2786 #define EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK) 2787 2788 #define EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U) 2789 #define EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U) 2790 #define EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_WIDTH (1U) 2791 #define EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK) 2792 2793 #define EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U) 2794 #define EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U) 2795 #define EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_WIDTH (1U) 2796 #define EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK) 2797 2798 #define EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U) 2799 #define EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U) 2800 #define EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_WIDTH (1U) 2801 #define EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK) 2802 2803 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U) 2804 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U) 2805 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_WIDTH (1U) 2806 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK) 2807 2808 #define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U) 2809 #define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U) 2810 #define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_WIDTH (1U) 2811 #define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK) 2812 2813 #define EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U) 2814 #define EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U) 2815 #define EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_WIDTH (1U) 2816 #define EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK) 2817 2818 #define EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U) 2819 #define EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U) 2820 #define EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_WIDTH (1U) 2821 #define EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK) 2822 2823 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U) 2824 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U) 2825 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_WIDTH (1U) 2826 #define EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK) 2827 2828 #define EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U) 2829 #define EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U) 2830 #define EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_WIDTH (1U) 2831 #define EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK) 2832 2833 #define EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U) 2834 #define EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U) 2835 #define EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_WIDTH (1U) 2836 #define EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK) 2837 2838 #define EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U) 2839 #define EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U) 2840 #define EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_WIDTH (1U) 2841 #define EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK) 2842 2843 #define EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U) 2844 #define EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U) 2845 #define EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_WIDTH (1U) 2846 #define EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK) 2847 2848 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U) 2849 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U) 2850 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_WIDTH (1U) 2851 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK) 2852 2853 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U) 2854 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U) 2855 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_WIDTH (1U) 2856 #define EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK) 2857 2858 #define EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U) 2859 #define EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U) 2860 #define EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_WIDTH (1U) 2861 #define EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK) 2862 2863 #define EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U) 2864 #define EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U) 2865 #define EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_WIDTH (1U) 2866 #define EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK) 2867 2868 #define EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U) 2869 #define EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U) 2870 #define EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_WIDTH (1U) 2871 #define EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK) 2872 2873 #define EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U) 2874 #define EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U) 2875 #define EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_WIDTH (1U) 2876 #define EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK) 2877 /*! @} */ 2878 2879 /*! @name TX_OCTET_COUNT_GOOD_BAD - Transmit Octet Count Good Bad */ 2880 /*! @{ */ 2881 2882 #define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU) 2883 #define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U) 2884 #define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_WIDTH (32U) 2885 #define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK) 2886 /*! @} */ 2887 2888 /*! @name TX_PACKET_COUNT_GOOD_BAD - Transmit Packet Count Good Bad */ 2889 /*! @{ */ 2890 2891 #define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU) 2892 #define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U) 2893 #define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_WIDTH (32U) 2894 #define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK) 2895 /*! @} */ 2896 2897 /*! @name TX_BROADCAST_PACKETS_GOOD - Transmit Broadcast Packets Good */ 2898 /*! @{ */ 2899 2900 #define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU) 2901 #define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U) 2902 #define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_WIDTH (32U) 2903 #define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK) 2904 /*! @} */ 2905 2906 /*! @name TX_MULTICAST_PACKETS_GOOD - Transmit Multicast Packets Good */ 2907 /*! @{ */ 2908 2909 #define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU) 2910 #define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U) 2911 #define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_WIDTH (32U) 2912 #define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK) 2913 /*! @} */ 2914 2915 /*! @name TX_64OCTETS_PACKETS_GOOD_BAD - Transmit 64-Octet Packets Good Bad */ 2916 /*! @{ */ 2917 2918 #define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU) 2919 #define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U) 2920 #define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_WIDTH (32U) 2921 #define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK) 2922 /*! @} */ 2923 2924 /*! @name TX_65TO127OCTETS_PACKETS_GOOD_BAD - Transmit 65 To 127 Octet Packets Good Bad */ 2925 /*! @{ */ 2926 2927 #define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU) 2928 #define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U) 2929 #define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_WIDTH (32U) 2930 #define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK) 2931 /*! @} */ 2932 2933 /*! @name TX_128TO255OCTETS_PACKETS_GOOD_BAD - Transmit 128 To 255 Octet Packets Good Bad */ 2934 /*! @{ */ 2935 2936 #define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU) 2937 #define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U) 2938 #define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_WIDTH (32U) 2939 #define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK) 2940 /*! @} */ 2941 2942 /*! @name TX_256TO511OCTETS_PACKETS_GOOD_BAD - Transmit 256 To 511 Octet Packets Good Bad */ 2943 /*! @{ */ 2944 2945 #define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU) 2946 #define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U) 2947 #define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_WIDTH (32U) 2948 #define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK) 2949 /*! @} */ 2950 2951 /*! @name TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Transmit 512 To 1023 Octet Packets Good Bad */ 2952 /*! @{ */ 2953 2954 #define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU) 2955 #define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U) 2956 #define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_WIDTH (32U) 2957 #define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK) 2958 /*! @} */ 2959 2960 /*! @name TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Transmit 1024 To Max Octet Packets Good Bad */ 2961 /*! @{ */ 2962 2963 #define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU) 2964 #define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U) 2965 #define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_WIDTH (32U) 2966 #define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK) 2967 /*! @} */ 2968 2969 /*! @name TX_UNICAST_PACKETS_GOOD_BAD - Transmit Unicast Packets Good Bad */ 2970 /*! @{ */ 2971 2972 #define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU) 2973 #define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U) 2974 #define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_WIDTH (32U) 2975 #define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK) 2976 /*! @} */ 2977 2978 /*! @name TX_MULTICAST_PACKETS_GOOD_BAD - Transmit Multicast Packets Good Bad */ 2979 /*! @{ */ 2980 2981 #define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU) 2982 #define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U) 2983 #define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_WIDTH (32U) 2984 #define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK) 2985 /*! @} */ 2986 2987 /*! @name TX_BROADCAST_PACKETS_GOOD_BAD - Transmit Broadcast Packets Good Bad */ 2988 /*! @{ */ 2989 2990 #define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU) 2991 #define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U) 2992 #define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_WIDTH (32U) 2993 #define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK) 2994 /*! @} */ 2995 2996 /*! @name TX_UNDERFLOW_ERROR_PACKETS - Transmit Underflow Error Packets */ 2997 /*! @{ */ 2998 2999 #define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU) 3000 #define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U) 3001 #define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_WIDTH (32U) 3002 #define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK) 3003 /*! @} */ 3004 3005 /*! @name TX_SINGLE_COLLISION_GOOD_PACKETS - Transmit Single Collision Good Packets */ 3006 /*! @{ */ 3007 3008 #define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU) 3009 #define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U) 3010 #define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_WIDTH (32U) 3011 #define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK) 3012 /*! @} */ 3013 3014 /*! @name TX_MULTIPLE_COLLISION_GOOD_PACKETS - Transmit Multiple Collision Good Packets */ 3015 /*! @{ */ 3016 3017 #define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU) 3018 #define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U) 3019 #define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_WIDTH (32U) 3020 #define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK) 3021 /*! @} */ 3022 3023 /*! @name TX_DEFERRED_PACKETS - Transmit Deferred Packets */ 3024 /*! @{ */ 3025 3026 #define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU) 3027 #define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U) 3028 #define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_WIDTH (32U) 3029 #define EMAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK) 3030 /*! @} */ 3031 3032 /*! @name TX_LATE_COLLISION_PACKETS - Transmit Late Collision Packets */ 3033 /*! @{ */ 3034 3035 #define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU) 3036 #define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U) 3037 #define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_WIDTH (32U) 3038 #define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK) 3039 /*! @} */ 3040 3041 /*! @name TX_EXCESSIVE_COLLISION_PACKETS - Transmit Excessive Collision Packets */ 3042 /*! @{ */ 3043 3044 #define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU) 3045 #define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U) 3046 #define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_WIDTH (32U) 3047 #define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK) 3048 /*! @} */ 3049 3050 /*! @name TX_CARRIER_ERROR_PACKETS - Transmit Carrier Error Packets */ 3051 /*! @{ */ 3052 3053 #define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU) 3054 #define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U) 3055 #define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_WIDTH (32U) 3056 #define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK) 3057 /*! @} */ 3058 3059 /*! @name TX_OCTET_COUNT_GOOD - Transmit Octet Count Good */ 3060 /*! @{ */ 3061 3062 #define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU) 3063 #define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U) 3064 #define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_WIDTH (32U) 3065 #define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK) 3066 /*! @} */ 3067 3068 /*! @name TX_PACKET_COUNT_GOOD - Transmit Packet Count Good */ 3069 /*! @{ */ 3070 3071 #define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU) 3072 #define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U) 3073 #define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_WIDTH (32U) 3074 #define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK) 3075 /*! @} */ 3076 3077 /*! @name TX_EXCESSIVE_DEFERRAL_ERROR - Transmit Excessive Deferral Error */ 3078 /*! @{ */ 3079 3080 #define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU) 3081 #define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U) 3082 #define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_WIDTH (32U) 3083 #define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK) 3084 /*! @} */ 3085 3086 /*! @name TX_PAUSE_PACKETS - Transmit Pause Packets */ 3087 /*! @{ */ 3088 3089 #define EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU) 3090 #define EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U) 3091 #define EMAC_TX_PAUSE_PACKETS_TXPAUSE_WIDTH (32U) 3092 #define EMAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK) 3093 /*! @} */ 3094 3095 /*! @name TX_VLAN_PACKETS_GOOD - Transmit VLAN Packets Good */ 3096 /*! @{ */ 3097 3098 #define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU) 3099 #define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U) 3100 #define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_WIDTH (32U) 3101 #define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK) 3102 /*! @} */ 3103 3104 /*! @name TX_OSIZE_PACKETS_GOOD - Transmit O Size Packets Good */ 3105 /*! @{ */ 3106 3107 #define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU) 3108 #define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U) 3109 #define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_WIDTH (32U) 3110 #define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK) 3111 /*! @} */ 3112 3113 /*! @name RX_PACKETS_COUNT_GOOD_BAD - Receive Packets Count Good Bad */ 3114 /*! @{ */ 3115 3116 #define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU) 3117 #define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U) 3118 #define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_WIDTH (32U) 3119 #define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK) 3120 /*! @} */ 3121 3122 /*! @name RX_OCTET_COUNT_GOOD_BAD - Receive Octet Count Good Bad */ 3123 /*! @{ */ 3124 3125 #define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU) 3126 #define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U) 3127 #define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_WIDTH (32U) 3128 #define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK) 3129 /*! @} */ 3130 3131 /*! @name RX_OCTET_COUNT_GOOD - Receive Octet Count Good */ 3132 /*! @{ */ 3133 3134 #define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU) 3135 #define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U) 3136 #define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_WIDTH (32U) 3137 #define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK) 3138 /*! @} */ 3139 3140 /*! @name RX_BROADCAST_PACKETS_GOOD - Receive Broadcast Packets Good */ 3141 /*! @{ */ 3142 3143 #define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU) 3144 #define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U) 3145 #define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_WIDTH (32U) 3146 #define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK) 3147 /*! @} */ 3148 3149 /*! @name RX_MULTICAST_PACKETS_GOOD - Receive Multicast Packets Good */ 3150 /*! @{ */ 3151 3152 #define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU) 3153 #define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U) 3154 #define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_WIDTH (32U) 3155 #define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK) 3156 /*! @} */ 3157 3158 /*! @name RX_CRC_ERROR_PACKETS - Receive CRC Error Packets */ 3159 /*! @{ */ 3160 3161 #define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU) 3162 #define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U) 3163 #define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_WIDTH (32U) 3164 #define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK) 3165 /*! @} */ 3166 3167 /*! @name RX_ALIGNMENT_ERROR_PACKETS - Receive Alignment Error Packets */ 3168 /*! @{ */ 3169 3170 #define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU) 3171 #define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U) 3172 #define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_WIDTH (32U) 3173 #define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK) 3174 /*! @} */ 3175 3176 /*! @name RX_RUNT_ERROR_PACKETS - Receive Runt Error Packets */ 3177 /*! @{ */ 3178 3179 #define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU) 3180 #define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U) 3181 #define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_WIDTH (32U) 3182 #define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK) 3183 /*! @} */ 3184 3185 /*! @name RX_JABBER_ERROR_PACKETS - Receive Jabber Error Packets */ 3186 /*! @{ */ 3187 3188 #define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU) 3189 #define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U) 3190 #define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_WIDTH (32U) 3191 #define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK) 3192 /*! @} */ 3193 3194 /*! @name RX_UNDERSIZE_PACKETS_GOOD - Receive Undersize Packets Good */ 3195 /*! @{ */ 3196 3197 #define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU) 3198 #define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U) 3199 #define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_WIDTH (32U) 3200 #define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK) 3201 /*! @} */ 3202 3203 /*! @name RX_OVERSIZE_PACKETS_GOOD - Receive Oversize Packets Good */ 3204 /*! @{ */ 3205 3206 #define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU) 3207 #define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U) 3208 #define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_WIDTH (32U) 3209 #define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK) 3210 /*! @} */ 3211 3212 /*! @name RX_64OCTETS_PACKETS_GOOD_BAD - Receive 64 Octets Packets Good Bad */ 3213 /*! @{ */ 3214 3215 #define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU) 3216 #define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U) 3217 #define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_WIDTH (32U) 3218 #define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK) 3219 /*! @} */ 3220 3221 /*! @name RX_65TO127OCTETS_PACKETS_GOOD_BAD - Receive 65-127 Octets Packets Good Bad */ 3222 /*! @{ */ 3223 3224 #define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU) 3225 #define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U) 3226 #define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_WIDTH (32U) 3227 #define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK) 3228 /*! @} */ 3229 3230 /*! @name RX_128TO255OCTETS_PACKETS_GOOD_BAD - Receive 128-255 Octets Packets Good Bad */ 3231 /*! @{ */ 3232 3233 #define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU) 3234 #define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U) 3235 #define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_WIDTH (32U) 3236 #define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK) 3237 /*! @} */ 3238 3239 /*! @name RX_256TO511OCTETS_PACKETS_GOOD_BAD - Receive 256-511 Octets Packets Good Bad */ 3240 /*! @{ */ 3241 3242 #define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU) 3243 #define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U) 3244 #define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_WIDTH (32U) 3245 #define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK) 3246 /*! @} */ 3247 3248 /*! @name RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Receive 512-1023 Octets Packets Good Bad */ 3249 /*! @{ */ 3250 3251 #define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU) 3252 #define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U) 3253 #define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_WIDTH (32U) 3254 #define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK) 3255 /*! @} */ 3256 3257 /*! @name RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Receive 1024 To Max Octets Good Bad */ 3258 /*! @{ */ 3259 3260 #define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU) 3261 #define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U) 3262 #define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_WIDTH (32U) 3263 #define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK) 3264 /*! @} */ 3265 3266 /*! @name RX_UNICAST_PACKETS_GOOD - Receive Unicast Packets Good */ 3267 /*! @{ */ 3268 3269 #define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU) 3270 #define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U) 3271 #define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_WIDTH (32U) 3272 #define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK) 3273 /*! @} */ 3274 3275 /*! @name RX_LENGTH_ERROR_PACKETS - Receive Length Error Packets */ 3276 /*! @{ */ 3277 3278 #define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU) 3279 #define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U) 3280 #define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_WIDTH (32U) 3281 #define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK) 3282 /*! @} */ 3283 3284 /*! @name RX_OUT_OF_RANGE_TYPE_PACKETS - Receive Out of Range Type Packet */ 3285 /*! @{ */ 3286 3287 #define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU) 3288 #define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U) 3289 #define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_WIDTH (32U) 3290 #define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK) 3291 /*! @} */ 3292 3293 /*! @name RX_PAUSE_PACKETS - Receive Pause Packets */ 3294 /*! @{ */ 3295 3296 #define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU) 3297 #define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U) 3298 #define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_WIDTH (32U) 3299 #define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK) 3300 /*! @} */ 3301 3302 /*! @name RX_FIFO_OVERFLOW_PACKETS - Receive FIFO Overflow Packets */ 3303 /*! @{ */ 3304 3305 #define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU) 3306 #define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U) 3307 #define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_WIDTH (32U) 3308 #define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK) 3309 /*! @} */ 3310 3311 /*! @name RX_VLAN_PACKETS_GOOD_BAD - Receive VLAN Packets Good Bad */ 3312 /*! @{ */ 3313 3314 #define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU) 3315 #define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U) 3316 #define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_WIDTH (32U) 3317 #define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK) 3318 /*! @} */ 3319 3320 /*! @name RX_WATCHDOG_ERROR_PACKETS - Receive Watchdog Error Packets */ 3321 /*! @{ */ 3322 3323 #define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU) 3324 #define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U) 3325 #define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_WIDTH (32U) 3326 #define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK) 3327 /*! @} */ 3328 3329 /*! @name RX_RECEIVE_ERROR_PACKETS - Receive Receive Error Packets */ 3330 /*! @{ */ 3331 3332 #define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU) 3333 #define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U) 3334 #define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_WIDTH (32U) 3335 #define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK) 3336 /*! @} */ 3337 3338 /*! @name RX_CONTROL_PACKETS_GOOD - Receive Control Packets Good */ 3339 /*! @{ */ 3340 3341 #define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU) 3342 #define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U) 3343 #define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_WIDTH (32U) 3344 #define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK) 3345 /*! @} */ 3346 3347 /*! @name MMC_FPE_TX_INTERRUPT - MMC Transmit FPE Fragment Counter Interrupt Status */ 3348 /*! @{ */ 3349 3350 #define EMAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U) 3351 #define EMAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U) 3352 #define EMAC_MMC_FPE_TX_INTERRUPT_FCIS_WIDTH (1U) 3353 #define EMAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & EMAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK) 3354 3355 #define EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U) 3356 #define EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U) 3357 #define EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_WIDTH (1U) 3358 #define EMAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK) 3359 /*! @} */ 3360 3361 /*! @name MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Interrupt Mask */ 3362 /*! @{ */ 3363 3364 #define EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U) 3365 #define EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U) 3366 #define EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_WIDTH (1U) 3367 #define EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK) 3368 3369 #define EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U) 3370 #define EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U) 3371 #define EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_WIDTH (1U) 3372 #define EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK) 3373 /*! @} */ 3374 3375 /*! @name MMC_TX_FPE_FRAGMENT_CNTR - Transmit FPE Fragment Counter */ 3376 /*! @{ */ 3377 3378 #define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU) 3379 #define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U) 3380 #define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_WIDTH (32U) 3381 #define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK) 3382 /*! @} */ 3383 3384 /*! @name MMC_TX_HOLD_REQ_CNTR - Transmit Hold Request Counter */ 3385 /*! @{ */ 3386 3387 #define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU) 3388 #define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U) 3389 #define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_WIDTH (32U) 3390 #define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK) 3391 /*! @} */ 3392 3393 /*! @name MMC_FPE_RX_INTERRUPT - MMC Receive Packet Assembly Error Counter Interrupt Status */ 3394 /*! @{ */ 3395 3396 #define EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U) 3397 #define EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U) 3398 #define EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_WIDTH (1U) 3399 #define EMAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK) 3400 3401 #define EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U) 3402 #define EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U) 3403 #define EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_WIDTH (1U) 3404 #define EMAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK) 3405 3406 #define EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U) 3407 #define EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U) 3408 #define EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_WIDTH (1U) 3409 #define EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK) 3410 3411 #define EMAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U) 3412 #define EMAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U) 3413 #define EMAC_MMC_FPE_RX_INTERRUPT_FCIS_WIDTH (1U) 3414 #define EMAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & EMAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK) 3415 /*! @} */ 3416 3417 /*! @name MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */ 3418 /*! @{ */ 3419 3420 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U) 3421 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U) 3422 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_WIDTH (1U) 3423 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK) 3424 3425 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U) 3426 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U) 3427 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_WIDTH (1U) 3428 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK) 3429 3430 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U) 3431 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U) 3432 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_WIDTH (1U) 3433 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK) 3434 3435 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U) 3436 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U) 3437 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_WIDTH (1U) 3438 #define EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK) 3439 /*! @} */ 3440 3441 /*! @name MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Assembly Error Counter */ 3442 /*! @{ */ 3443 3444 #define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU) 3445 #define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U) 3446 #define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_WIDTH (32U) 3447 #define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK) 3448 /*! @} */ 3449 3450 /*! @name MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */ 3451 /*! @{ */ 3452 3453 #define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU) 3454 #define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U) 3455 #define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_WIDTH (32U) 3456 #define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK) 3457 /*! @} */ 3458 3459 /*! @name MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Assembly OK Counter */ 3460 /*! @{ */ 3461 3462 #define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU) 3463 #define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U) 3464 #define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_WIDTH (32U) 3465 #define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK) 3466 /*! @} */ 3467 3468 /*! @name MMC_RX_FPE_FRAGMENT_CNTR - MMC Receive FPE Fragment Counter */ 3469 /*! @{ */ 3470 3471 #define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU) 3472 #define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U) 3473 #define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_WIDTH (32U) 3474 #define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK) 3475 /*! @} */ 3476 3477 /*! @name MAC_L3_L4_CONTROL0 - MAC Layer 3 Layer 4 Control 0 */ 3478 /*! @{ */ 3479 3480 #define EMAC_MAC_L3_L4_CONTROL0_L3PEN0_MASK (0x1U) 3481 #define EMAC_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U) 3482 #define EMAC_MAC_L3_L4_CONTROL0_L3PEN0_WIDTH (1U) 3483 #define EMAC_MAC_L3_L4_CONTROL0_L3PEN0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L3PEN0_MASK) 3484 3485 #define EMAC_MAC_L3_L4_CONTROL0_L3SAM0_MASK (0x4U) 3486 #define EMAC_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U) 3487 #define EMAC_MAC_L3_L4_CONTROL0_L3SAM0_WIDTH (1U) 3488 #define EMAC_MAC_L3_L4_CONTROL0_L3SAM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L3SAM0_MASK) 3489 3490 #define EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U) 3491 #define EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U) 3492 #define EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_WIDTH (1U) 3493 #define EMAC_MAC_L3_L4_CONTROL0_L3SAIM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_MASK) 3494 3495 #define EMAC_MAC_L3_L4_CONTROL0_L3DAM0_MASK (0x10U) 3496 #define EMAC_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U) 3497 #define EMAC_MAC_L3_L4_CONTROL0_L3DAM0_WIDTH (1U) 3498 #define EMAC_MAC_L3_L4_CONTROL0_L3DAM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L3DAM0_MASK) 3499 3500 #define EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U) 3501 #define EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U) 3502 #define EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_WIDTH (1U) 3503 #define EMAC_MAC_L3_L4_CONTROL0_L3DAIM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_MASK) 3504 3505 #define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U) 3506 #define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U) 3507 #define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_WIDTH (5U) 3508 #define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK) 3509 3510 #define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U) 3511 #define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U) 3512 #define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_WIDTH (5U) 3513 #define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK) 3514 3515 #define EMAC_MAC_L3_L4_CONTROL0_L4PEN0_MASK (0x10000U) 3516 #define EMAC_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U) 3517 #define EMAC_MAC_L3_L4_CONTROL0_L4PEN0_WIDTH (1U) 3518 #define EMAC_MAC_L3_L4_CONTROL0_L4PEN0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L4PEN0_MASK) 3519 3520 #define EMAC_MAC_L3_L4_CONTROL0_L4SPM0_MASK (0x40000U) 3521 #define EMAC_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U) 3522 #define EMAC_MAC_L3_L4_CONTROL0_L4SPM0_WIDTH (1U) 3523 #define EMAC_MAC_L3_L4_CONTROL0_L4SPM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L4SPM0_MASK) 3524 3525 #define EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U) 3526 #define EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U) 3527 #define EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_WIDTH (1U) 3528 #define EMAC_MAC_L3_L4_CONTROL0_L4SPIM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_MASK) 3529 3530 #define EMAC_MAC_L3_L4_CONTROL0_L4DPM0_MASK (0x100000U) 3531 #define EMAC_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U) 3532 #define EMAC_MAC_L3_L4_CONTROL0_L4DPM0_WIDTH (1U) 3533 #define EMAC_MAC_L3_L4_CONTROL0_L4DPM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L4DPM0_MASK) 3534 3535 #define EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U) 3536 #define EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U) 3537 #define EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_WIDTH (1U) 3538 #define EMAC_MAC_L3_L4_CONTROL0_L4DPIM0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_MASK) 3539 3540 #define EMAC_MAC_L3_L4_CONTROL0_DMCHN0_MASK (0x1000000U) 3541 #define EMAC_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U) 3542 #define EMAC_MAC_L3_L4_CONTROL0_DMCHN0_WIDTH (1U) 3543 #define EMAC_MAC_L3_L4_CONTROL0_DMCHN0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_DMCHN0_MASK) 3544 3545 #define EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U) 3546 #define EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U) 3547 #define EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_WIDTH (1U) 3548 #define EMAC_MAC_L3_L4_CONTROL0_DMCHEN0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_MASK) 3549 /*! @} */ 3550 3551 /*! @name MAC_LAYER4_ADDRESS0 - MAC Layer 4 Address 0 */ 3552 /*! @{ */ 3553 3554 #define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFFU) 3555 #define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U) 3556 #define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_WIDTH (16U) 3557 #define EMAC_MAC_LAYER4_ADDRESS0_L4SP0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK) 3558 3559 #define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF0000U) 3560 #define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U) 3561 #define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_WIDTH (16U) 3562 #define EMAC_MAC_LAYER4_ADDRESS0_L4DP0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK) 3563 /*! @} */ 3564 3565 /*! @name MAC_LAYER3_ADDR0_REG0 - MAC Layer 3 Address 0 Reg 0 */ 3566 /*! @{ */ 3567 3568 #define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU) 3569 #define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U) 3570 #define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_WIDTH (32U) 3571 #define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK) 3572 /*! @} */ 3573 3574 /*! @name MAC_LAYER3_ADDR1_REG0 - MAC Layer 3 Address 1 Reg 0 */ 3575 /*! @{ */ 3576 3577 #define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU) 3578 #define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U) 3579 #define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_WIDTH (32U) 3580 #define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK) 3581 /*! @} */ 3582 3583 /*! @name MAC_LAYER3_ADDR2_REG0 - MAC Layer 3 Address 2 Reg 0 */ 3584 /*! @{ */ 3585 3586 #define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU) 3587 #define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U) 3588 #define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_WIDTH (32U) 3589 #define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK) 3590 /*! @} */ 3591 3592 /*! @name MAC_LAYER3_ADDR3_REG0 - MAC Layer 3 Address 3 Reg 0 */ 3593 /*! @{ */ 3594 3595 #define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU) 3596 #define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U) 3597 #define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_WIDTH (32U) 3598 #define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK) 3599 /*! @} */ 3600 3601 /*! @name MAC_L3_L4_CONTROL1 - MAC L3 L4 Control 1 */ 3602 /*! @{ */ 3603 3604 #define EMAC_MAC_L3_L4_CONTROL1_L3PEN1_MASK (0x1U) 3605 #define EMAC_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U) 3606 #define EMAC_MAC_L3_L4_CONTROL1_L3PEN1_WIDTH (1U) 3607 #define EMAC_MAC_L3_L4_CONTROL1_L3PEN1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L3PEN1_MASK) 3608 3609 #define EMAC_MAC_L3_L4_CONTROL1_L3SAM1_MASK (0x4U) 3610 #define EMAC_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U) 3611 #define EMAC_MAC_L3_L4_CONTROL1_L3SAM1_WIDTH (1U) 3612 #define EMAC_MAC_L3_L4_CONTROL1_L3SAM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L3SAM1_MASK) 3613 3614 #define EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U) 3615 #define EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U) 3616 #define EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_WIDTH (1U) 3617 #define EMAC_MAC_L3_L4_CONTROL1_L3SAIM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_MASK) 3618 3619 #define EMAC_MAC_L3_L4_CONTROL1_L3DAM1_MASK (0x10U) 3620 #define EMAC_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U) 3621 #define EMAC_MAC_L3_L4_CONTROL1_L3DAM1_WIDTH (1U) 3622 #define EMAC_MAC_L3_L4_CONTROL1_L3DAM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L3DAM1_MASK) 3623 3624 #define EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U) 3625 #define EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U) 3626 #define EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_WIDTH (1U) 3627 #define EMAC_MAC_L3_L4_CONTROL1_L3DAIM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_MASK) 3628 3629 #define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U) 3630 #define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U) 3631 #define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_WIDTH (5U) 3632 #define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK) 3633 3634 #define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U) 3635 #define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U) 3636 #define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_WIDTH (5U) 3637 #define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK) 3638 3639 #define EMAC_MAC_L3_L4_CONTROL1_L4PEN1_MASK (0x10000U) 3640 #define EMAC_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U) 3641 #define EMAC_MAC_L3_L4_CONTROL1_L4PEN1_WIDTH (1U) 3642 #define EMAC_MAC_L3_L4_CONTROL1_L4PEN1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L4PEN1_MASK) 3643 3644 #define EMAC_MAC_L3_L4_CONTROL1_L4SPM1_MASK (0x40000U) 3645 #define EMAC_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U) 3646 #define EMAC_MAC_L3_L4_CONTROL1_L4SPM1_WIDTH (1U) 3647 #define EMAC_MAC_L3_L4_CONTROL1_L4SPM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L4SPM1_MASK) 3648 3649 #define EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U) 3650 #define EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U) 3651 #define EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_WIDTH (1U) 3652 #define EMAC_MAC_L3_L4_CONTROL1_L4SPIM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_MASK) 3653 3654 #define EMAC_MAC_L3_L4_CONTROL1_L4DPM1_MASK (0x100000U) 3655 #define EMAC_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U) 3656 #define EMAC_MAC_L3_L4_CONTROL1_L4DPM1_WIDTH (1U) 3657 #define EMAC_MAC_L3_L4_CONTROL1_L4DPM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L4DPM1_MASK) 3658 3659 #define EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U) 3660 #define EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U) 3661 #define EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_WIDTH (1U) 3662 #define EMAC_MAC_L3_L4_CONTROL1_L4DPIM1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_MASK) 3663 3664 #define EMAC_MAC_L3_L4_CONTROL1_DMCHN1_MASK (0x1000000U) 3665 #define EMAC_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U) 3666 #define EMAC_MAC_L3_L4_CONTROL1_DMCHN1_WIDTH (1U) 3667 #define EMAC_MAC_L3_L4_CONTROL1_DMCHN1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_DMCHN1_MASK) 3668 3669 #define EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U) 3670 #define EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U) 3671 #define EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_WIDTH (1U) 3672 #define EMAC_MAC_L3_L4_CONTROL1_DMCHEN1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_MASK) 3673 /*! @} */ 3674 3675 /*! @name MAC_LAYER4_ADDRESS1 - MAC Layer 4 Address 1 */ 3676 /*! @{ */ 3677 3678 #define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFFU) 3679 #define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U) 3680 #define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_WIDTH (16U) 3681 #define EMAC_MAC_LAYER4_ADDRESS1_L4SP1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK) 3682 3683 #define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF0000U) 3684 #define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U) 3685 #define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_WIDTH (16U) 3686 #define EMAC_MAC_LAYER4_ADDRESS1_L4DP1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK) 3687 /*! @} */ 3688 3689 /*! @name MAC_LAYER3_ADDR0_REG1 - MAC Layer 3 Address 0 Reg 1 */ 3690 /*! @{ */ 3691 3692 #define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU) 3693 #define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U) 3694 #define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_WIDTH (32U) 3695 #define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK) 3696 /*! @} */ 3697 3698 /*! @name MAC_LAYER3_ADDR1_REG1 - MAC Layer 3 Address 1 Reg 1 */ 3699 /*! @{ */ 3700 3701 #define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU) 3702 #define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U) 3703 #define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_WIDTH (32U) 3704 #define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK) 3705 /*! @} */ 3706 3707 /*! @name MAC_LAYER3_ADDR2_REG1 - MAC Layer 3 Address 2 Reg 1 */ 3708 /*! @{ */ 3709 3710 #define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU) 3711 #define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U) 3712 #define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_WIDTH (32U) 3713 #define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK) 3714 /*! @} */ 3715 3716 /*! @name MAC_LAYER3_ADDR3_REG1 - MAC Layer 3 Address 3 Reg 1 */ 3717 /*! @{ */ 3718 3719 #define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU) 3720 #define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U) 3721 #define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_WIDTH (32U) 3722 #define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK) 3723 /*! @} */ 3724 3725 /*! @name MAC_L3_L4_CONTROL2 - MAC L3 L4 Control 2 */ 3726 /*! @{ */ 3727 3728 #define EMAC_MAC_L3_L4_CONTROL2_L3PEN2_MASK (0x1U) 3729 #define EMAC_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U) 3730 #define EMAC_MAC_L3_L4_CONTROL2_L3PEN2_WIDTH (1U) 3731 #define EMAC_MAC_L3_L4_CONTROL2_L3PEN2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L3PEN2_MASK) 3732 3733 #define EMAC_MAC_L3_L4_CONTROL2_L3SAM2_MASK (0x4U) 3734 #define EMAC_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U) 3735 #define EMAC_MAC_L3_L4_CONTROL2_L3SAM2_WIDTH (1U) 3736 #define EMAC_MAC_L3_L4_CONTROL2_L3SAM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L3SAM2_MASK) 3737 3738 #define EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U) 3739 #define EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U) 3740 #define EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_WIDTH (1U) 3741 #define EMAC_MAC_L3_L4_CONTROL2_L3SAIM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_MASK) 3742 3743 #define EMAC_MAC_L3_L4_CONTROL2_L3DAM2_MASK (0x10U) 3744 #define EMAC_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U) 3745 #define EMAC_MAC_L3_L4_CONTROL2_L3DAM2_WIDTH (1U) 3746 #define EMAC_MAC_L3_L4_CONTROL2_L3DAM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L3DAM2_MASK) 3747 3748 #define EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U) 3749 #define EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U) 3750 #define EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_WIDTH (1U) 3751 #define EMAC_MAC_L3_L4_CONTROL2_L3DAIM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_MASK) 3752 3753 #define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U) 3754 #define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U) 3755 #define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_WIDTH (5U) 3756 #define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK) 3757 3758 #define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U) 3759 #define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U) 3760 #define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_WIDTH (5U) 3761 #define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK) 3762 3763 #define EMAC_MAC_L3_L4_CONTROL2_L4PEN2_MASK (0x10000U) 3764 #define EMAC_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U) 3765 #define EMAC_MAC_L3_L4_CONTROL2_L4PEN2_WIDTH (1U) 3766 #define EMAC_MAC_L3_L4_CONTROL2_L4PEN2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L4PEN2_MASK) 3767 3768 #define EMAC_MAC_L3_L4_CONTROL2_L4SPM2_MASK (0x40000U) 3769 #define EMAC_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U) 3770 #define EMAC_MAC_L3_L4_CONTROL2_L4SPM2_WIDTH (1U) 3771 #define EMAC_MAC_L3_L4_CONTROL2_L4SPM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L4SPM2_MASK) 3772 3773 #define EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U) 3774 #define EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U) 3775 #define EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_WIDTH (1U) 3776 #define EMAC_MAC_L3_L4_CONTROL2_L4SPIM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_MASK) 3777 3778 #define EMAC_MAC_L3_L4_CONTROL2_L4DPM2_MASK (0x100000U) 3779 #define EMAC_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U) 3780 #define EMAC_MAC_L3_L4_CONTROL2_L4DPM2_WIDTH (1U) 3781 #define EMAC_MAC_L3_L4_CONTROL2_L4DPM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L4DPM2_MASK) 3782 3783 #define EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U) 3784 #define EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U) 3785 #define EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_WIDTH (1U) 3786 #define EMAC_MAC_L3_L4_CONTROL2_L4DPIM2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_MASK) 3787 3788 #define EMAC_MAC_L3_L4_CONTROL2_DMCHN2_MASK (0x1000000U) 3789 #define EMAC_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U) 3790 #define EMAC_MAC_L3_L4_CONTROL2_DMCHN2_WIDTH (1U) 3791 #define EMAC_MAC_L3_L4_CONTROL2_DMCHN2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_DMCHN2_MASK) 3792 3793 #define EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U) 3794 #define EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U) 3795 #define EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_WIDTH (1U) 3796 #define EMAC_MAC_L3_L4_CONTROL2_DMCHEN2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_MASK) 3797 /*! @} */ 3798 3799 /*! @name MAC_LAYER4_ADDRESS2 - MAC Layer 4 Address 2 */ 3800 /*! @{ */ 3801 3802 #define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFFU) 3803 #define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U) 3804 #define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_WIDTH (16U) 3805 #define EMAC_MAC_LAYER4_ADDRESS2_L4SP2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK) 3806 3807 #define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF0000U) 3808 #define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U) 3809 #define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_WIDTH (16U) 3810 #define EMAC_MAC_LAYER4_ADDRESS2_L4DP2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK) 3811 /*! @} */ 3812 3813 /*! @name MAC_LAYER3_ADDR0_REG2 - MAC Layer 3 Address 0 Reg 2 */ 3814 /*! @{ */ 3815 3816 #define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU) 3817 #define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U) 3818 #define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_WIDTH (32U) 3819 #define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK) 3820 /*! @} */ 3821 3822 /*! @name MAC_LAYER3_ADDR1_REG2 - MAC Layer 3 Address 1 Reg 2 */ 3823 /*! @{ */ 3824 3825 #define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU) 3826 #define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U) 3827 #define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_WIDTH (32U) 3828 #define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK) 3829 /*! @} */ 3830 3831 /*! @name MAC_LAYER3_ADDR2_REG2 - MAC Layer 3 Address 2 Reg 2 */ 3832 /*! @{ */ 3833 3834 #define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU) 3835 #define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U) 3836 #define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_WIDTH (32U) 3837 #define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK) 3838 /*! @} */ 3839 3840 /*! @name MAC_LAYER3_ADDR3_REG2 - MAC Layer 3 Address 3 Reg 2 */ 3841 /*! @{ */ 3842 3843 #define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU) 3844 #define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U) 3845 #define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_WIDTH (32U) 3846 #define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK) 3847 /*! @} */ 3848 3849 /*! @name MAC_L3_L4_CONTROL3 - MAC L3 L4 Control 3 */ 3850 /*! @{ */ 3851 3852 #define EMAC_MAC_L3_L4_CONTROL3_L3PEN3_MASK (0x1U) 3853 #define EMAC_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U) 3854 #define EMAC_MAC_L3_L4_CONTROL3_L3PEN3_WIDTH (1U) 3855 #define EMAC_MAC_L3_L4_CONTROL3_L3PEN3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L3PEN3_MASK) 3856 3857 #define EMAC_MAC_L3_L4_CONTROL3_L3SAM3_MASK (0x4U) 3858 #define EMAC_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U) 3859 #define EMAC_MAC_L3_L4_CONTROL3_L3SAM3_WIDTH (1U) 3860 #define EMAC_MAC_L3_L4_CONTROL3_L3SAM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L3SAM3_MASK) 3861 3862 #define EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U) 3863 #define EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U) 3864 #define EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_WIDTH (1U) 3865 #define EMAC_MAC_L3_L4_CONTROL3_L3SAIM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_MASK) 3866 3867 #define EMAC_MAC_L3_L4_CONTROL3_L3DAM3_MASK (0x10U) 3868 #define EMAC_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U) 3869 #define EMAC_MAC_L3_L4_CONTROL3_L3DAM3_WIDTH (1U) 3870 #define EMAC_MAC_L3_L4_CONTROL3_L3DAM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L3DAM3_MASK) 3871 3872 #define EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U) 3873 #define EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U) 3874 #define EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_WIDTH (1U) 3875 #define EMAC_MAC_L3_L4_CONTROL3_L3DAIM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_MASK) 3876 3877 #define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U) 3878 #define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U) 3879 #define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_WIDTH (5U) 3880 #define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK) 3881 3882 #define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U) 3883 #define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U) 3884 #define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_WIDTH (5U) 3885 #define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK) 3886 3887 #define EMAC_MAC_L3_L4_CONTROL3_L4PEN3_MASK (0x10000U) 3888 #define EMAC_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U) 3889 #define EMAC_MAC_L3_L4_CONTROL3_L4PEN3_WIDTH (1U) 3890 #define EMAC_MAC_L3_L4_CONTROL3_L4PEN3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L4PEN3_MASK) 3891 3892 #define EMAC_MAC_L3_L4_CONTROL3_L4SPM3_MASK (0x40000U) 3893 #define EMAC_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U) 3894 #define EMAC_MAC_L3_L4_CONTROL3_L4SPM3_WIDTH (1U) 3895 #define EMAC_MAC_L3_L4_CONTROL3_L4SPM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L4SPM3_MASK) 3896 3897 #define EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U) 3898 #define EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U) 3899 #define EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_WIDTH (1U) 3900 #define EMAC_MAC_L3_L4_CONTROL3_L4SPIM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_MASK) 3901 3902 #define EMAC_MAC_L3_L4_CONTROL3_L4DPM3_MASK (0x100000U) 3903 #define EMAC_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U) 3904 #define EMAC_MAC_L3_L4_CONTROL3_L4DPM3_WIDTH (1U) 3905 #define EMAC_MAC_L3_L4_CONTROL3_L4DPM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L4DPM3_MASK) 3906 3907 #define EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U) 3908 #define EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U) 3909 #define EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_WIDTH (1U) 3910 #define EMAC_MAC_L3_L4_CONTROL3_L4DPIM3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_MASK) 3911 3912 #define EMAC_MAC_L3_L4_CONTROL3_DMCHN3_MASK (0x1000000U) 3913 #define EMAC_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U) 3914 #define EMAC_MAC_L3_L4_CONTROL3_DMCHN3_WIDTH (1U) 3915 #define EMAC_MAC_L3_L4_CONTROL3_DMCHN3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_DMCHN3_MASK) 3916 3917 #define EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U) 3918 #define EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U) 3919 #define EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_WIDTH (1U) 3920 #define EMAC_MAC_L3_L4_CONTROL3_DMCHEN3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_MASK) 3921 /*! @} */ 3922 3923 /*! @name MAC_LAYER4_ADDRESS3 - MAC Layer 4 Address 3 */ 3924 /*! @{ */ 3925 3926 #define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFFU) 3927 #define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U) 3928 #define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_WIDTH (16U) 3929 #define EMAC_MAC_LAYER4_ADDRESS3_L4SP3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK) 3930 3931 #define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF0000U) 3932 #define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U) 3933 #define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_WIDTH (16U) 3934 #define EMAC_MAC_LAYER4_ADDRESS3_L4DP3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK) 3935 /*! @} */ 3936 3937 /*! @name MAC_LAYER3_ADDR0_REG3 - MAC Layer 3 Address 0 Reg 3 */ 3938 /*! @{ */ 3939 3940 #define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU) 3941 #define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U) 3942 #define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_WIDTH (32U) 3943 #define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK) 3944 /*! @} */ 3945 3946 /*! @name MAC_LAYER3_ADDR1_REG3 - MAC Layer 3 Address 1 Reg 3 */ 3947 /*! @{ */ 3948 3949 #define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU) 3950 #define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U) 3951 #define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_WIDTH (32U) 3952 #define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK) 3953 /*! @} */ 3954 3955 /*! @name MAC_LAYER3_ADDR2_REG3 - MAC Layer 3 Address 2 Reg 3 */ 3956 /*! @{ */ 3957 3958 #define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU) 3959 #define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U) 3960 #define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_WIDTH (32U) 3961 #define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK) 3962 /*! @} */ 3963 3964 /*! @name MAC_LAYER3_ADDR3_REG3 - MAC Layer 3 Address 3 Reg 3 */ 3965 /*! @{ */ 3966 3967 #define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU) 3968 #define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U) 3969 #define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_WIDTH (32U) 3970 #define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK) 3971 /*! @} */ 3972 3973 /*! @name MAC_TIMESTAMP_CONTROL - MAC Timestamp Control */ 3974 /*! @{ */ 3975 3976 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U) 3977 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U) 3978 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENA_WIDTH (1U) 3979 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK) 3980 3981 #define EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U) 3982 #define EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U) 3983 #define EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_WIDTH (1U) 3984 #define EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK) 3985 3986 #define EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U) 3987 #define EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U) 3988 #define EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_WIDTH (1U) 3989 #define EMAC_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK) 3990 3991 #define EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U) 3992 #define EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U) 3993 #define EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_WIDTH (1U) 3994 #define EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK) 3995 3996 #define EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U) 3997 #define EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U) 3998 #define EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_WIDTH (1U) 3999 #define EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK) 4000 4001 #define EMAC_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U) 4002 #define EMAC_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U) 4003 #define EMAC_MAC_TIMESTAMP_CONTROL_PTGE_WIDTH (1U) 4004 #define EMAC_MAC_TIMESTAMP_CONTROL_PTGE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_PTGE_MASK) 4005 4006 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U) 4007 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U) 4008 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_WIDTH (1U) 4009 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK) 4010 4011 #define EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U) 4012 #define EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U) 4013 #define EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_WIDTH (1U) 4014 #define EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK) 4015 4016 #define EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U) 4017 #define EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U) 4018 #define EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_WIDTH (1U) 4019 #define EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK) 4020 4021 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U) 4022 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U) 4023 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_WIDTH (1U) 4024 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK) 4025 4026 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U) 4027 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U) 4028 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_WIDTH (1U) 4029 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK) 4030 4031 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U) 4032 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U) 4033 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_WIDTH (1U) 4034 #define EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK) 4035 4036 #define EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U) 4037 #define EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U) 4038 #define EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_WIDTH (1U) 4039 #define EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK) 4040 4041 #define EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U) 4042 #define EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U) 4043 #define EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_WIDTH (1U) 4044 #define EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK) 4045 4046 #define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U) 4047 #define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U) 4048 #define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_WIDTH (2U) 4049 #define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK) 4050 4051 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U) 4052 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U) 4053 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_WIDTH (1U) 4054 #define EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK) 4055 4056 #define EMAC_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U) 4057 #define EMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U) 4058 #define EMAC_MAC_TIMESTAMP_CONTROL_ESTI_WIDTH (1U) 4059 #define EMAC_MAC_TIMESTAMP_CONTROL_ESTI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_ESTI_MASK) 4060 4061 #define EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U) 4062 #define EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U) 4063 #define EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_WIDTH (1U) 4064 #define EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK) 4065 4066 #define EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U) 4067 #define EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U) 4068 #define EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_WIDTH (1U) 4069 #define EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK) 4070 /*! @} */ 4071 4072 /*! @name MAC_SUB_SECOND_INCREMENT - MAC Sub Second Increment */ 4073 /*! @{ */ 4074 4075 #define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U) 4076 #define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U) 4077 #define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_WIDTH (8U) 4078 #define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) 4079 4080 #define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U) 4081 #define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U) 4082 #define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_WIDTH (8U) 4083 #define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK) 4084 /*! @} */ 4085 4086 /*! @name MAC_SYSTEM_TIME_SECONDS - MAC System Time In Seconds */ 4087 /*! @{ */ 4088 4089 #define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU) 4090 #define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U) 4091 #define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_WIDTH (32U) 4092 #define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK) 4093 /*! @} */ 4094 4095 /*! @name MAC_SYSTEM_TIME_NANOSECONDS - MAC System Time In Nanoseconds */ 4096 /*! @{ */ 4097 4098 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU) 4099 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U) 4100 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_WIDTH (31U) 4101 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK) 4102 /*! @} */ 4103 4104 /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - MAC System Time Seconds Update */ 4105 /*! @{ */ 4106 4107 #define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU) 4108 #define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U) 4109 #define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_WIDTH (32U) 4110 #define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK) 4111 /*! @} */ 4112 4113 /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - MAC System Time Nanoseconds Update */ 4114 /*! @{ */ 4115 4116 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU) 4117 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U) 4118 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_WIDTH (31U) 4119 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) 4120 4121 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U) 4122 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U) 4123 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_WIDTH (1U) 4124 #define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK) 4125 /*! @} */ 4126 4127 /*! @name MAC_TIMESTAMP_ADDEND - MAC Timestamp Addend */ 4128 /*! @{ */ 4129 4130 #define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) 4131 #define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U) 4132 #define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_WIDTH (32U) 4133 #define EMAC_MAC_TIMESTAMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK) 4134 /*! @} */ 4135 4136 /*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - MAC System Time Higher Word In Seconds */ 4137 /*! @{ */ 4138 4139 #define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU) 4140 #define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U) 4141 #define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_WIDTH (16U) 4142 #define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK) 4143 /*! @} */ 4144 4145 /*! @name MAC_TIMESTAMP_STATUS - MAC Timestamp Status */ 4146 /*! @{ */ 4147 4148 #define EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U) 4149 #define EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U) 4150 #define EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_WIDTH (1U) 4151 #define EMAC_MAC_TIMESTAMP_STATUS_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_MASK) 4152 4153 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U) 4154 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U) 4155 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_WIDTH (1U) 4156 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK) 4157 4158 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U) 4159 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U) 4160 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_WIDTH (1U) 4161 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK) 4162 4163 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U) 4164 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U) 4165 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_WIDTH (1U) 4166 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK) 4167 4168 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U) 4169 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U) 4170 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_WIDTH (1U) 4171 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK) 4172 4173 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U) 4174 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U) 4175 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_WIDTH (1U) 4176 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK) 4177 4178 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U) 4179 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U) 4180 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_WIDTH (1U) 4181 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK) 4182 4183 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U) 4184 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U) 4185 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_WIDTH (1U) 4186 #define EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK) 4187 4188 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U) 4189 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U) 4190 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_WIDTH (1U) 4191 #define EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK) 4192 4193 #define EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U) 4194 #define EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U) 4195 #define EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_WIDTH (1U) 4196 #define EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK) 4197 /*! @} */ 4198 4199 /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - MAC Transmit Timestamp Status In Nanoseconds */ 4200 /*! @{ */ 4201 4202 #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU) 4203 #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U) 4204 #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_WIDTH (31U) 4205 #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK) 4206 4207 #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U) 4208 #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U) 4209 #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_WIDTH (1U) 4210 #define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK) 4211 /*! @} */ 4212 4213 /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - MAC Transmit Timestamp Status In Seconds */ 4214 /*! @{ */ 4215 4216 #define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU) 4217 #define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U) 4218 #define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_WIDTH (32U) 4219 #define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK) 4220 /*! @} */ 4221 4222 /*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - MAC Timestamp Ingress Asymmetry Correction */ 4223 /*! @{ */ 4224 4225 #define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU) 4226 #define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U) 4227 #define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_WIDTH (32U) 4228 #define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK) 4229 /*! @} */ 4230 4231 /*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - MAC Timestamp Egress Asymmetry Correction */ 4232 /*! @{ */ 4233 4234 #define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU) 4235 #define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U) 4236 #define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_WIDTH (32U) 4237 #define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK) 4238 /*! @} */ 4239 4240 /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - MAC Timestamp Ingress Correction In Nanoseconds */ 4241 /*! @{ */ 4242 4243 #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) 4244 #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) 4245 #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_WIDTH (32U) 4246 #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) 4247 /*! @} */ 4248 4249 /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - MAC Timestamp Egress Correction In Nanoseconds */ 4250 /*! @{ */ 4251 4252 #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) 4253 #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) 4254 #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_WIDTH (32U) 4255 #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) 4256 /*! @} */ 4257 4258 /*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - MAC Timestamp Ingress Correction In Subnanoseconds */ 4259 /*! @{ */ 4260 4261 #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U) 4262 #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U) 4263 #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_WIDTH (8U) 4264 #define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK) 4265 /*! @} */ 4266 4267 /*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - MAC Timestamp Engress Correction In Subnanoseconds */ 4268 /*! @{ */ 4269 4270 #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U) 4271 #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U) 4272 #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_WIDTH (8U) 4273 #define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK) 4274 /*! @} */ 4275 4276 /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - MAC Timestamp Ingress Latency */ 4277 /*! @{ */ 4278 4279 #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U) 4280 #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U) 4281 #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_WIDTH (8U) 4282 #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) 4283 4284 #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U) 4285 #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U) 4286 #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_WIDTH (12U) 4287 #define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK) 4288 /*! @} */ 4289 4290 /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - MAC Timestamp Egress Latecy */ 4291 /*! @{ */ 4292 4293 #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U) 4294 #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U) 4295 #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_WIDTH (8U) 4296 #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) 4297 4298 #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U) 4299 #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U) 4300 #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_WIDTH (12U) 4301 #define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK) 4302 /*! @} */ 4303 4304 /*! @name MAC_PPS_CONTROL - MAC PPS Control */ 4305 /*! @{ */ 4306 4307 #define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU) 4308 #define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U) 4309 #define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_WIDTH (4U) 4310 #define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) 4311 4312 #define EMAC_MAC_PPS_CONTROL_PPSEN0_MASK (0x10U) 4313 #define EMAC_MAC_PPS_CONTROL_PPSEN0_SHIFT (4U) 4314 #define EMAC_MAC_PPS_CONTROL_PPSEN0_WIDTH (1U) 4315 #define EMAC_MAC_PPS_CONTROL_PPSEN0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & EMAC_MAC_PPS_CONTROL_PPSEN0_MASK) 4316 4317 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U) 4318 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U) 4319 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_WIDTH (2U) 4320 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK) 4321 4322 #define EMAC_MAC_PPS_CONTROL_MCGREN0_MASK (0x80U) 4323 #define EMAC_MAC_PPS_CONTROL_MCGREN0_SHIFT (7U) 4324 #define EMAC_MAC_PPS_CONTROL_MCGREN0_WIDTH (1U) 4325 #define EMAC_MAC_PPS_CONTROL_MCGREN0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & EMAC_MAC_PPS_CONTROL_MCGREN0_MASK) 4326 4327 #define EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF00U) 4328 #define EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8U) 4329 #define EMAC_MAC_PPS_CONTROL_PPSCMD1_WIDTH (4U) 4330 #define EMAC_MAC_PPS_CONTROL_PPSCMD1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK) 4331 4332 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U) 4333 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U) 4334 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_WIDTH (2U) 4335 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK) 4336 4337 #define EMAC_MAC_PPS_CONTROL_MCGREN1_MASK (0x8000U) 4338 #define EMAC_MAC_PPS_CONTROL_MCGREN1_SHIFT (15U) 4339 #define EMAC_MAC_PPS_CONTROL_MCGREN1_WIDTH (1U) 4340 #define EMAC_MAC_PPS_CONTROL_MCGREN1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & EMAC_MAC_PPS_CONTROL_MCGREN1_MASK) 4341 4342 #define EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF0000U) 4343 #define EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16U) 4344 #define EMAC_MAC_PPS_CONTROL_PPSCMD2_WIDTH (4U) 4345 #define EMAC_MAC_PPS_CONTROL_PPSCMD2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK) 4346 4347 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U) 4348 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U) 4349 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_WIDTH (2U) 4350 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK) 4351 4352 #define EMAC_MAC_PPS_CONTROL_MCGREN2_MASK (0x800000U) 4353 #define EMAC_MAC_PPS_CONTROL_MCGREN2_SHIFT (23U) 4354 #define EMAC_MAC_PPS_CONTROL_MCGREN2_WIDTH (1U) 4355 #define EMAC_MAC_PPS_CONTROL_MCGREN2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & EMAC_MAC_PPS_CONTROL_MCGREN2_MASK) 4356 4357 #define EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF000000U) 4358 #define EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24U) 4359 #define EMAC_MAC_PPS_CONTROL_PPSCMD3_WIDTH (4U) 4360 #define EMAC_MAC_PPS_CONTROL_PPSCMD3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK) 4361 4362 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U) 4363 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U) 4364 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_WIDTH (2U) 4365 #define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK) 4366 4367 #define EMAC_MAC_PPS_CONTROL_MCGREN3_MASK (0x80000000U) 4368 #define EMAC_MAC_PPS_CONTROL_MCGREN3_SHIFT (31U) 4369 #define EMAC_MAC_PPS_CONTROL_MCGREN3_WIDTH (1U) 4370 #define EMAC_MAC_PPS_CONTROL_MCGREN3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & EMAC_MAC_PPS_CONTROL_MCGREN3_MASK) 4371 /*! @} */ 4372 4373 /*! @name MAC_PPS0_TARGET_TIME_SECONDS - MAC PPS0 Target Time In Seconds */ 4374 /*! @{ */ 4375 4376 #define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU) 4377 #define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U) 4378 #define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_WIDTH (32U) 4379 #define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK) 4380 /*! @} */ 4381 4382 /*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - MAC PPS0 Target Time In Nanoseconds */ 4383 /*! @{ */ 4384 4385 #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU) 4386 #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U) 4387 #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_WIDTH (31U) 4388 #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK) 4389 4390 #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U) 4391 #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U) 4392 #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_WIDTH (1U) 4393 #define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK) 4394 /*! @} */ 4395 4396 /*! @name MAC_PPS0_INTERVAL - MAC PPS0 Interval */ 4397 /*! @{ */ 4398 4399 #define EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFFU) 4400 #define EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U) 4401 #define EMAC_MAC_PPS0_INTERVAL_PPSINT0_WIDTH (32U) 4402 #define EMAC_MAC_PPS0_INTERVAL_PPSINT0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK) 4403 /*! @} */ 4404 4405 /*! @name MAC_PPS0_WIDTH - MAC PPS0 Width */ 4406 /*! @{ */ 4407 4408 #define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFFU) 4409 #define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0U) 4410 #define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_WIDTH (32U) 4411 #define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK) 4412 /*! @} */ 4413 4414 /*! @name MAC_PPS1_TARGET_TIME_SECONDS - MAC PPS1 Target Time In Seconds */ 4415 /*! @{ */ 4416 4417 #define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU) 4418 #define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U) 4419 #define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_WIDTH (32U) 4420 #define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK) 4421 /*! @} */ 4422 4423 /*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - MAC PPS1 Target Time In Nanoseconds */ 4424 /*! @{ */ 4425 4426 #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU) 4427 #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U) 4428 #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_WIDTH (31U) 4429 #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK) 4430 4431 #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U) 4432 #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U) 4433 #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_WIDTH (1U) 4434 #define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK) 4435 /*! @} */ 4436 4437 /*! @name MAC_PPS1_INTERVAL - MAC PPS1 Interval */ 4438 /*! @{ */ 4439 4440 #define EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFFU) 4441 #define EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U) 4442 #define EMAC_MAC_PPS1_INTERVAL_PPSINT1_WIDTH (32U) 4443 #define EMAC_MAC_PPS1_INTERVAL_PPSINT1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK) 4444 /*! @} */ 4445 4446 /*! @name MAC_PPS1_WIDTH - MAC PPS1 Width */ 4447 /*! @{ */ 4448 4449 #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFFU) 4450 #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0U) 4451 #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_WIDTH (32U) 4452 #define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK) 4453 /*! @} */ 4454 4455 /*! @name MAC_PPS2_TARGET_TIME_SECONDS - MAC PPS2 Taget Time In Seconds */ 4456 /*! @{ */ 4457 4458 #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU) 4459 #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U) 4460 #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_WIDTH (32U) 4461 #define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK) 4462 /*! @} */ 4463 4464 /*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - MAC PPS2 Target Time In Nanoseconds */ 4465 /*! @{ */ 4466 4467 #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU) 4468 #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U) 4469 #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_WIDTH (31U) 4470 #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK) 4471 4472 #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U) 4473 #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U) 4474 #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_WIDTH (1U) 4475 #define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK) 4476 /*! @} */ 4477 4478 /*! @name MAC_PPS2_INTERVAL - MAC PPS2 Interval */ 4479 /*! @{ */ 4480 4481 #define EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFFU) 4482 #define EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U) 4483 #define EMAC_MAC_PPS2_INTERVAL_PPSINT2_WIDTH (32U) 4484 #define EMAC_MAC_PPS2_INTERVAL_PPSINT2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK) 4485 /*! @} */ 4486 4487 /*! @name MAC_PPS2_WIDTH - MAC PPS2 Width */ 4488 /*! @{ */ 4489 4490 #define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFFU) 4491 #define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0U) 4492 #define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_WIDTH (32U) 4493 #define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK) 4494 /*! @} */ 4495 4496 /*! @name MAC_PPS3_TARGET_TIME_SECONDS - MAC PPS3 Target Time In Seconds */ 4497 /*! @{ */ 4498 4499 #define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU) 4500 #define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U) 4501 #define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_WIDTH (32U) 4502 #define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK) 4503 /*! @} */ 4504 4505 /*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - MAC PPS3 Target Time In Nanoseconds */ 4506 /*! @{ */ 4507 4508 #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU) 4509 #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U) 4510 #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_WIDTH (31U) 4511 #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK) 4512 4513 #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U) 4514 #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U) 4515 #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_WIDTH (1U) 4516 #define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK) 4517 /*! @} */ 4518 4519 /*! @name MAC_PPS3_INTERVAL - MAC PPS3 Interval */ 4520 /*! @{ */ 4521 4522 #define EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFFU) 4523 #define EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U) 4524 #define EMAC_MAC_PPS3_INTERVAL_PPSINT3_WIDTH (32U) 4525 #define EMAC_MAC_PPS3_INTERVAL_PPSINT3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK) 4526 /*! @} */ 4527 4528 /*! @name MAC_PPS3_WIDTH - MAC PPS3 Width */ 4529 /*! @{ */ 4530 4531 #define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFFU) 4532 #define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0U) 4533 #define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_WIDTH (32U) 4534 #define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK) 4535 /*! @} */ 4536 4537 /*! @name MTL_OPERATION_MODE - MTL Operation Mode */ 4538 /*! @{ */ 4539 4540 #define EMAC_MTL_OPERATION_MODE_DTXSTS_MASK (0x2U) 4541 #define EMAC_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U) 4542 #define EMAC_MTL_OPERATION_MODE_DTXSTS_WIDTH (1U) 4543 #define EMAC_MTL_OPERATION_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & EMAC_MTL_OPERATION_MODE_DTXSTS_MASK) 4544 4545 #define EMAC_MTL_OPERATION_MODE_RAA_MASK (0x4U) 4546 #define EMAC_MTL_OPERATION_MODE_RAA_SHIFT (2U) 4547 #define EMAC_MTL_OPERATION_MODE_RAA_WIDTH (1U) 4548 #define EMAC_MTL_OPERATION_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_OPERATION_MODE_RAA_SHIFT)) & EMAC_MTL_OPERATION_MODE_RAA_MASK) 4549 4550 #define EMAC_MTL_OPERATION_MODE_SCHALG_MASK (0x60U) 4551 #define EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT (5U) 4552 #define EMAC_MTL_OPERATION_MODE_SCHALG_WIDTH (2U) 4553 #define EMAC_MTL_OPERATION_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT)) & EMAC_MTL_OPERATION_MODE_SCHALG_MASK) 4554 4555 #define EMAC_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U) 4556 #define EMAC_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U) 4557 #define EMAC_MTL_OPERATION_MODE_CNTPRST_WIDTH (1U) 4558 #define EMAC_MTL_OPERATION_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & EMAC_MTL_OPERATION_MODE_CNTPRST_MASK) 4559 4560 #define EMAC_MTL_OPERATION_MODE_CNTCLR_MASK (0x200U) 4561 #define EMAC_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U) 4562 #define EMAC_MTL_OPERATION_MODE_CNTCLR_WIDTH (1U) 4563 #define EMAC_MTL_OPERATION_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & EMAC_MTL_OPERATION_MODE_CNTCLR_MASK) 4564 4565 #define EMAC_MTL_OPERATION_MODE_FRPE_MASK (0x8000U) 4566 #define EMAC_MTL_OPERATION_MODE_FRPE_SHIFT (15U) 4567 #define EMAC_MTL_OPERATION_MODE_FRPE_WIDTH (1U) 4568 #define EMAC_MTL_OPERATION_MODE_FRPE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_OPERATION_MODE_FRPE_SHIFT)) & EMAC_MTL_OPERATION_MODE_FRPE_MASK) 4569 /*! @} */ 4570 4571 /*! @name MTL_DBG_CTL - MTL Debug Control */ 4572 /*! @{ */ 4573 4574 #define EMAC_MTL_DBG_CTL_FDBGEN_MASK (0x1U) 4575 #define EMAC_MTL_DBG_CTL_FDBGEN_SHIFT (0U) 4576 #define EMAC_MTL_DBG_CTL_FDBGEN_WIDTH (1U) 4577 #define EMAC_MTL_DBG_CTL_FDBGEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_FDBGEN_SHIFT)) & EMAC_MTL_DBG_CTL_FDBGEN_MASK) 4578 4579 #define EMAC_MTL_DBG_CTL_DBGMOD_MASK (0x2U) 4580 #define EMAC_MTL_DBG_CTL_DBGMOD_SHIFT (1U) 4581 #define EMAC_MTL_DBG_CTL_DBGMOD_WIDTH (1U) 4582 #define EMAC_MTL_DBG_CTL_DBGMOD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_DBGMOD_SHIFT)) & EMAC_MTL_DBG_CTL_DBGMOD_MASK) 4583 4584 #define EMAC_MTL_DBG_CTL_BYTEEN_MASK (0xCU) 4585 #define EMAC_MTL_DBG_CTL_BYTEEN_SHIFT (2U) 4586 #define EMAC_MTL_DBG_CTL_BYTEEN_WIDTH (2U) 4587 #define EMAC_MTL_DBG_CTL_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_BYTEEN_SHIFT)) & EMAC_MTL_DBG_CTL_BYTEEN_MASK) 4588 4589 #define EMAC_MTL_DBG_CTL_PKTSTATE_MASK (0x60U) 4590 #define EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT (5U) 4591 #define EMAC_MTL_DBG_CTL_PKTSTATE_WIDTH (2U) 4592 #define EMAC_MTL_DBG_CTL_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT)) & EMAC_MTL_DBG_CTL_PKTSTATE_MASK) 4593 4594 #define EMAC_MTL_DBG_CTL_RSTALL_MASK (0x100U) 4595 #define EMAC_MTL_DBG_CTL_RSTALL_SHIFT (8U) 4596 #define EMAC_MTL_DBG_CTL_RSTALL_WIDTH (1U) 4597 #define EMAC_MTL_DBG_CTL_RSTALL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_RSTALL_SHIFT)) & EMAC_MTL_DBG_CTL_RSTALL_MASK) 4598 4599 #define EMAC_MTL_DBG_CTL_RSTSEL_MASK (0x200U) 4600 #define EMAC_MTL_DBG_CTL_RSTSEL_SHIFT (9U) 4601 #define EMAC_MTL_DBG_CTL_RSTSEL_WIDTH (1U) 4602 #define EMAC_MTL_DBG_CTL_RSTSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_RSTSEL_SHIFT)) & EMAC_MTL_DBG_CTL_RSTSEL_MASK) 4603 4604 #define EMAC_MTL_DBG_CTL_FIFORDEN_MASK (0x400U) 4605 #define EMAC_MTL_DBG_CTL_FIFORDEN_SHIFT (10U) 4606 #define EMAC_MTL_DBG_CTL_FIFORDEN_WIDTH (1U) 4607 #define EMAC_MTL_DBG_CTL_FIFORDEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_FIFORDEN_SHIFT)) & EMAC_MTL_DBG_CTL_FIFORDEN_MASK) 4608 4609 #define EMAC_MTL_DBG_CTL_FIFOWREN_MASK (0x800U) 4610 #define EMAC_MTL_DBG_CTL_FIFOWREN_SHIFT (11U) 4611 #define EMAC_MTL_DBG_CTL_FIFOWREN_WIDTH (1U) 4612 #define EMAC_MTL_DBG_CTL_FIFOWREN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_FIFOWREN_SHIFT)) & EMAC_MTL_DBG_CTL_FIFOWREN_MASK) 4613 4614 #define EMAC_MTL_DBG_CTL_FIFOSEL_MASK (0x3000U) 4615 #define EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT (12U) 4616 #define EMAC_MTL_DBG_CTL_FIFOSEL_WIDTH (2U) 4617 #define EMAC_MTL_DBG_CTL_FIFOSEL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT)) & EMAC_MTL_DBG_CTL_FIFOSEL_MASK) 4618 4619 #define EMAC_MTL_DBG_CTL_PKTIE_MASK (0x4000U) 4620 #define EMAC_MTL_DBG_CTL_PKTIE_SHIFT (14U) 4621 #define EMAC_MTL_DBG_CTL_PKTIE_WIDTH (1U) 4622 #define EMAC_MTL_DBG_CTL_PKTIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_PKTIE_SHIFT)) & EMAC_MTL_DBG_CTL_PKTIE_MASK) 4623 4624 #define EMAC_MTL_DBG_CTL_STSIE_MASK (0x8000U) 4625 #define EMAC_MTL_DBG_CTL_STSIE_SHIFT (15U) 4626 #define EMAC_MTL_DBG_CTL_STSIE_WIDTH (1U) 4627 #define EMAC_MTL_DBG_CTL_STSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_STSIE_SHIFT)) & EMAC_MTL_DBG_CTL_STSIE_MASK) 4628 4629 #define EMAC_MTL_DBG_CTL_EIEE_MASK (0x10000U) 4630 #define EMAC_MTL_DBG_CTL_EIEE_SHIFT (16U) 4631 #define EMAC_MTL_DBG_CTL_EIEE_WIDTH (1U) 4632 #define EMAC_MTL_DBG_CTL_EIEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_EIEE_SHIFT)) & EMAC_MTL_DBG_CTL_EIEE_MASK) 4633 4634 #define EMAC_MTL_DBG_CTL_EIEC_MASK (0x60000U) 4635 #define EMAC_MTL_DBG_CTL_EIEC_SHIFT (17U) 4636 #define EMAC_MTL_DBG_CTL_EIEC_WIDTH (2U) 4637 #define EMAC_MTL_DBG_CTL_EIEC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_CTL_EIEC_SHIFT)) & EMAC_MTL_DBG_CTL_EIEC_MASK) 4638 /*! @} */ 4639 4640 /*! @name MTL_DBG_STS - MTL Debug Status */ 4641 /*! @{ */ 4642 4643 #define EMAC_MTL_DBG_STS_FIFOBUSY_MASK (0x1U) 4644 #define EMAC_MTL_DBG_STS_FIFOBUSY_SHIFT (0U) 4645 #define EMAC_MTL_DBG_STS_FIFOBUSY_WIDTH (1U) 4646 #define EMAC_MTL_DBG_STS_FIFOBUSY(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_STS_FIFOBUSY_SHIFT)) & EMAC_MTL_DBG_STS_FIFOBUSY_MASK) 4647 4648 #define EMAC_MTL_DBG_STS_PKTSTATE_MASK (0x6U) 4649 #define EMAC_MTL_DBG_STS_PKTSTATE_SHIFT (1U) 4650 #define EMAC_MTL_DBG_STS_PKTSTATE_WIDTH (2U) 4651 #define EMAC_MTL_DBG_STS_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_STS_PKTSTATE_SHIFT)) & EMAC_MTL_DBG_STS_PKTSTATE_MASK) 4652 4653 #define EMAC_MTL_DBG_STS_BYTEEN_MASK (0x18U) 4654 #define EMAC_MTL_DBG_STS_BYTEEN_SHIFT (3U) 4655 #define EMAC_MTL_DBG_STS_BYTEEN_WIDTH (2U) 4656 #define EMAC_MTL_DBG_STS_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_STS_BYTEEN_SHIFT)) & EMAC_MTL_DBG_STS_BYTEEN_MASK) 4657 4658 #define EMAC_MTL_DBG_STS_PKTI_MASK (0x100U) 4659 #define EMAC_MTL_DBG_STS_PKTI_SHIFT (8U) 4660 #define EMAC_MTL_DBG_STS_PKTI_WIDTH (1U) 4661 #define EMAC_MTL_DBG_STS_PKTI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_STS_PKTI_SHIFT)) & EMAC_MTL_DBG_STS_PKTI_MASK) 4662 4663 #define EMAC_MTL_DBG_STS_STSI_MASK (0x200U) 4664 #define EMAC_MTL_DBG_STS_STSI_SHIFT (9U) 4665 #define EMAC_MTL_DBG_STS_STSI_WIDTH (1U) 4666 #define EMAC_MTL_DBG_STS_STSI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_STS_STSI_SHIFT)) & EMAC_MTL_DBG_STS_STSI_MASK) 4667 4668 #define EMAC_MTL_DBG_STS_LOCR_MASK (0xFFFF8000U) 4669 #define EMAC_MTL_DBG_STS_LOCR_SHIFT (15U) 4670 #define EMAC_MTL_DBG_STS_LOCR_WIDTH (17U) 4671 #define EMAC_MTL_DBG_STS_LOCR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DBG_STS_LOCR_SHIFT)) & EMAC_MTL_DBG_STS_LOCR_MASK) 4672 /*! @} */ 4673 4674 /*! @name MTL_FIFO_DEBUG_DATA - MTL FIFO Debug Data */ 4675 /*! @{ */ 4676 4677 #define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU) 4678 #define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U) 4679 #define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_WIDTH (32U) 4680 #define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK) 4681 /*! @} */ 4682 4683 /*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */ 4684 /*! @{ */ 4685 4686 #define EMAC_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U) 4687 #define EMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U) 4688 #define EMAC_MTL_INTERRUPT_STATUS_Q0IS_WIDTH (1U) 4689 #define EMAC_MTL_INTERRUPT_STATUS_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & EMAC_MTL_INTERRUPT_STATUS_Q0IS_MASK) 4690 4691 #define EMAC_MTL_INTERRUPT_STATUS_Q1IS_MASK (0x2U) 4692 #define EMAC_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U) 4693 #define EMAC_MTL_INTERRUPT_STATUS_Q1IS_WIDTH (1U) 4694 #define EMAC_MTL_INTERRUPT_STATUS_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & EMAC_MTL_INTERRUPT_STATUS_Q1IS_MASK) 4695 4696 #define EMAC_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U) 4697 #define EMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U) 4698 #define EMAC_MTL_INTERRUPT_STATUS_DBGIS_WIDTH (1U) 4699 #define EMAC_MTL_INTERRUPT_STATUS_DBGIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & EMAC_MTL_INTERRUPT_STATUS_DBGIS_MASK) 4700 4701 #define EMAC_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U) 4702 #define EMAC_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U) 4703 #define EMAC_MTL_INTERRUPT_STATUS_ESTIS_WIDTH (1U) 4704 #define EMAC_MTL_INTERRUPT_STATUS_ESTIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & EMAC_MTL_INTERRUPT_STATUS_ESTIS_MASK) 4705 4706 #define EMAC_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U) 4707 #define EMAC_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U) 4708 #define EMAC_MTL_INTERRUPT_STATUS_MTLPIS_WIDTH (1U) 4709 #define EMAC_MTL_INTERRUPT_STATUS_MTLPIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & EMAC_MTL_INTERRUPT_STATUS_MTLPIS_MASK) 4710 /*! @} */ 4711 4712 /*! @name MTL_RXQ_DMA_MAP0 - MTL Receive Queue DMA Map 0 */ 4713 /*! @{ */ 4714 4715 #define EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK (0x1U) 4716 #define EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U) 4717 #define EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_WIDTH (1U) 4718 #define EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK) 4719 4720 #define EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK (0x10U) 4721 #define EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U) 4722 #define EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_WIDTH (1U) 4723 #define EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK) 4724 4725 #define EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK (0x100U) 4726 #define EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U) 4727 #define EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_WIDTH (1U) 4728 #define EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK) 4729 4730 #define EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK (0x1000U) 4731 #define EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U) 4732 #define EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_WIDTH (1U) 4733 #define EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK) 4734 /*! @} */ 4735 4736 /*! @name MTL_TBS_CTRL - MTL TBS Control */ 4737 /*! @{ */ 4738 4739 #define EMAC_MTL_TBS_CTRL_ESTM_MASK (0x1U) 4740 #define EMAC_MTL_TBS_CTRL_ESTM_SHIFT (0U) 4741 #define EMAC_MTL_TBS_CTRL_ESTM_WIDTH (1U) 4742 #define EMAC_MTL_TBS_CTRL_ESTM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TBS_CTRL_ESTM_SHIFT)) & EMAC_MTL_TBS_CTRL_ESTM_MASK) 4743 4744 #define EMAC_MTL_TBS_CTRL_LEOV_MASK (0x2U) 4745 #define EMAC_MTL_TBS_CTRL_LEOV_SHIFT (1U) 4746 #define EMAC_MTL_TBS_CTRL_LEOV_WIDTH (1U) 4747 #define EMAC_MTL_TBS_CTRL_LEOV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TBS_CTRL_LEOV_SHIFT)) & EMAC_MTL_TBS_CTRL_LEOV_MASK) 4748 4749 #define EMAC_MTL_TBS_CTRL_LEGOS_MASK (0x70U) 4750 #define EMAC_MTL_TBS_CTRL_LEGOS_SHIFT (4U) 4751 #define EMAC_MTL_TBS_CTRL_LEGOS_WIDTH (3U) 4752 #define EMAC_MTL_TBS_CTRL_LEGOS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT)) & EMAC_MTL_TBS_CTRL_LEGOS_MASK) 4753 4754 #define EMAC_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF00U) 4755 #define EMAC_MTL_TBS_CTRL_LEOS_SHIFT (8U) 4756 #define EMAC_MTL_TBS_CTRL_LEOS_WIDTH (24U) 4757 #define EMAC_MTL_TBS_CTRL_LEOS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TBS_CTRL_LEOS_SHIFT)) & EMAC_MTL_TBS_CTRL_LEOS_MASK) 4758 /*! @} */ 4759 4760 /*! @name MTL_EST_CONTROL - MTL EST Control */ 4761 /*! @{ */ 4762 4763 #define EMAC_MTL_EST_CONTROL_EEST_MASK (0x1U) 4764 #define EMAC_MTL_EST_CONTROL_EEST_SHIFT (0U) 4765 #define EMAC_MTL_EST_CONTROL_EEST_WIDTH (1U) 4766 #define EMAC_MTL_EST_CONTROL_EEST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_CONTROL_EEST_SHIFT)) & EMAC_MTL_EST_CONTROL_EEST_MASK) 4767 4768 #define EMAC_MTL_EST_CONTROL_SSWL_MASK (0x2U) 4769 #define EMAC_MTL_EST_CONTROL_SSWL_SHIFT (1U) 4770 #define EMAC_MTL_EST_CONTROL_SSWL_WIDTH (1U) 4771 #define EMAC_MTL_EST_CONTROL_SSWL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_CONTROL_SSWL_SHIFT)) & EMAC_MTL_EST_CONTROL_SSWL_MASK) 4772 4773 #define EMAC_MTL_EST_CONTROL_DDBF_MASK (0x10U) 4774 #define EMAC_MTL_EST_CONTROL_DDBF_SHIFT (4U) 4775 #define EMAC_MTL_EST_CONTROL_DDBF_WIDTH (1U) 4776 #define EMAC_MTL_EST_CONTROL_DDBF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_CONTROL_DDBF_SHIFT)) & EMAC_MTL_EST_CONTROL_DDBF_MASK) 4777 4778 #define EMAC_MTL_EST_CONTROL_DFBS_MASK (0x20U) 4779 #define EMAC_MTL_EST_CONTROL_DFBS_SHIFT (5U) 4780 #define EMAC_MTL_EST_CONTROL_DFBS_WIDTH (1U) 4781 #define EMAC_MTL_EST_CONTROL_DFBS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_CONTROL_DFBS_SHIFT)) & EMAC_MTL_EST_CONTROL_DFBS_MASK) 4782 4783 #define EMAC_MTL_EST_CONTROL_LCSE_MASK (0xC0U) 4784 #define EMAC_MTL_EST_CONTROL_LCSE_SHIFT (6U) 4785 #define EMAC_MTL_EST_CONTROL_LCSE_WIDTH (2U) 4786 #define EMAC_MTL_EST_CONTROL_LCSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_CONTROL_LCSE_SHIFT)) & EMAC_MTL_EST_CONTROL_LCSE_MASK) 4787 4788 #define EMAC_MTL_EST_CONTROL_TILS_MASK (0x700U) 4789 #define EMAC_MTL_EST_CONTROL_TILS_SHIFT (8U) 4790 #define EMAC_MTL_EST_CONTROL_TILS_WIDTH (3U) 4791 #define EMAC_MTL_EST_CONTROL_TILS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_CONTROL_TILS_SHIFT)) & EMAC_MTL_EST_CONTROL_TILS_MASK) 4792 4793 #define EMAC_MTL_EST_CONTROL_CTOV_MASK (0xFFF000U) 4794 #define EMAC_MTL_EST_CONTROL_CTOV_SHIFT (12U) 4795 #define EMAC_MTL_EST_CONTROL_CTOV_WIDTH (12U) 4796 #define EMAC_MTL_EST_CONTROL_CTOV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_CONTROL_CTOV_SHIFT)) & EMAC_MTL_EST_CONTROL_CTOV_MASK) 4797 4798 #define EMAC_MTL_EST_CONTROL_PTOV_MASK (0xFF000000U) 4799 #define EMAC_MTL_EST_CONTROL_PTOV_SHIFT (24U) 4800 #define EMAC_MTL_EST_CONTROL_PTOV_WIDTH (8U) 4801 #define EMAC_MTL_EST_CONTROL_PTOV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_CONTROL_PTOV_SHIFT)) & EMAC_MTL_EST_CONTROL_PTOV_MASK) 4802 /*! @} */ 4803 4804 /*! @name MTL_EST_STATUS - MTL EST Status */ 4805 /*! @{ */ 4806 4807 #define EMAC_MTL_EST_STATUS_SWLC_MASK (0x1U) 4808 #define EMAC_MTL_EST_STATUS_SWLC_SHIFT (0U) 4809 #define EMAC_MTL_EST_STATUS_SWLC_WIDTH (1U) 4810 #define EMAC_MTL_EST_STATUS_SWLC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_STATUS_SWLC_SHIFT)) & EMAC_MTL_EST_STATUS_SWLC_MASK) 4811 4812 #define EMAC_MTL_EST_STATUS_BTRE_MASK (0x2U) 4813 #define EMAC_MTL_EST_STATUS_BTRE_SHIFT (1U) 4814 #define EMAC_MTL_EST_STATUS_BTRE_WIDTH (1U) 4815 #define EMAC_MTL_EST_STATUS_BTRE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_STATUS_BTRE_SHIFT)) & EMAC_MTL_EST_STATUS_BTRE_MASK) 4816 4817 #define EMAC_MTL_EST_STATUS_HLBF_MASK (0x4U) 4818 #define EMAC_MTL_EST_STATUS_HLBF_SHIFT (2U) 4819 #define EMAC_MTL_EST_STATUS_HLBF_WIDTH (1U) 4820 #define EMAC_MTL_EST_STATUS_HLBF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_STATUS_HLBF_SHIFT)) & EMAC_MTL_EST_STATUS_HLBF_MASK) 4821 4822 #define EMAC_MTL_EST_STATUS_HLBS_MASK (0x8U) 4823 #define EMAC_MTL_EST_STATUS_HLBS_SHIFT (3U) 4824 #define EMAC_MTL_EST_STATUS_HLBS_WIDTH (1U) 4825 #define EMAC_MTL_EST_STATUS_HLBS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_STATUS_HLBS_SHIFT)) & EMAC_MTL_EST_STATUS_HLBS_MASK) 4826 4827 #define EMAC_MTL_EST_STATUS_CGCE_MASK (0x10U) 4828 #define EMAC_MTL_EST_STATUS_CGCE_SHIFT (4U) 4829 #define EMAC_MTL_EST_STATUS_CGCE_WIDTH (1U) 4830 #define EMAC_MTL_EST_STATUS_CGCE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_STATUS_CGCE_SHIFT)) & EMAC_MTL_EST_STATUS_CGCE_MASK) 4831 4832 #define EMAC_MTL_EST_STATUS_SWOL_MASK (0x80U) 4833 #define EMAC_MTL_EST_STATUS_SWOL_SHIFT (7U) 4834 #define EMAC_MTL_EST_STATUS_SWOL_WIDTH (1U) 4835 #define EMAC_MTL_EST_STATUS_SWOL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_STATUS_SWOL_SHIFT)) & EMAC_MTL_EST_STATUS_SWOL_MASK) 4836 4837 #define EMAC_MTL_EST_STATUS_BTRL_MASK (0xF00U) 4838 #define EMAC_MTL_EST_STATUS_BTRL_SHIFT (8U) 4839 #define EMAC_MTL_EST_STATUS_BTRL_WIDTH (4U) 4840 #define EMAC_MTL_EST_STATUS_BTRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_STATUS_BTRL_SHIFT)) & EMAC_MTL_EST_STATUS_BTRL_MASK) 4841 4842 #define EMAC_MTL_EST_STATUS_CGSN_MASK (0xF0000U) 4843 #define EMAC_MTL_EST_STATUS_CGSN_SHIFT (16U) 4844 #define EMAC_MTL_EST_STATUS_CGSN_WIDTH (4U) 4845 #define EMAC_MTL_EST_STATUS_CGSN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_STATUS_CGSN_SHIFT)) & EMAC_MTL_EST_STATUS_CGSN_MASK) 4846 /*! @} */ 4847 4848 /*! @name MTL_EST_SCH_ERROR - MTL EST Scheduling Error */ 4849 /*! @{ */ 4850 4851 #define EMAC_MTL_EST_SCH_ERROR_SEQN_MASK (0x3U) 4852 #define EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT (0U) 4853 #define EMAC_MTL_EST_SCH_ERROR_SEQN_WIDTH (2U) 4854 #define EMAC_MTL_EST_SCH_ERROR_SEQN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & EMAC_MTL_EST_SCH_ERROR_SEQN_MASK) 4855 /*! @} */ 4856 4857 /*! @name MTL_EST_FRM_SIZE_ERROR - MTL EST Frame Size Error */ 4858 /*! @{ */ 4859 4860 #define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x3U) 4861 #define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U) 4862 #define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_WIDTH (2U) 4863 #define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK) 4864 /*! @} */ 4865 4866 /*! @name MTL_EST_FRM_SIZE_CAPTURE - MTL EST Frame Size Capture */ 4867 /*! @{ */ 4868 4869 #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU) 4870 #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U) 4871 #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_WIDTH (15U) 4872 #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK) 4873 4874 #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x10000U) 4875 #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U) 4876 #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_WIDTH (1U) 4877 #define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK) 4878 /*! @} */ 4879 4880 /*! @name MTL_EST_INTR_ENABLE - MTL EST Interrupt Enable */ 4881 /*! @{ */ 4882 4883 #define EMAC_MTL_EST_INTR_ENABLE_IECC_MASK (0x1U) 4884 #define EMAC_MTL_EST_INTR_ENABLE_IECC_SHIFT (0U) 4885 #define EMAC_MTL_EST_INTR_ENABLE_IECC_WIDTH (1U) 4886 #define EMAC_MTL_EST_INTR_ENABLE_IECC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & EMAC_MTL_EST_INTR_ENABLE_IECC_MASK) 4887 4888 #define EMAC_MTL_EST_INTR_ENABLE_IEBE_MASK (0x2U) 4889 #define EMAC_MTL_EST_INTR_ENABLE_IEBE_SHIFT (1U) 4890 #define EMAC_MTL_EST_INTR_ENABLE_IEBE_WIDTH (1U) 4891 #define EMAC_MTL_EST_INTR_ENABLE_IEBE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & EMAC_MTL_EST_INTR_ENABLE_IEBE_MASK) 4892 4893 #define EMAC_MTL_EST_INTR_ENABLE_IEHF_MASK (0x4U) 4894 #define EMAC_MTL_EST_INTR_ENABLE_IEHF_SHIFT (2U) 4895 #define EMAC_MTL_EST_INTR_ENABLE_IEHF_WIDTH (1U) 4896 #define EMAC_MTL_EST_INTR_ENABLE_IEHF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & EMAC_MTL_EST_INTR_ENABLE_IEHF_MASK) 4897 4898 #define EMAC_MTL_EST_INTR_ENABLE_IEHS_MASK (0x8U) 4899 #define EMAC_MTL_EST_INTR_ENABLE_IEHS_SHIFT (3U) 4900 #define EMAC_MTL_EST_INTR_ENABLE_IEHS_WIDTH (1U) 4901 #define EMAC_MTL_EST_INTR_ENABLE_IEHS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & EMAC_MTL_EST_INTR_ENABLE_IEHS_MASK) 4902 4903 #define EMAC_MTL_EST_INTR_ENABLE_CGCE_MASK (0x10U) 4904 #define EMAC_MTL_EST_INTR_ENABLE_CGCE_SHIFT (4U) 4905 #define EMAC_MTL_EST_INTR_ENABLE_CGCE_WIDTH (1U) 4906 #define EMAC_MTL_EST_INTR_ENABLE_CGCE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & EMAC_MTL_EST_INTR_ENABLE_CGCE_MASK) 4907 /*! @} */ 4908 4909 /*! @name MTL_EST_GCL_CONTROL - MTL EST GCL Control */ 4910 /*! @{ */ 4911 4912 #define EMAC_MTL_EST_GCL_CONTROL_SRWO_MASK (0x1U) 4913 #define EMAC_MTL_EST_GCL_CONTROL_SRWO_SHIFT (0U) 4914 #define EMAC_MTL_EST_GCL_CONTROL_SRWO_WIDTH (1U) 4915 #define EMAC_MTL_EST_GCL_CONTROL_SRWO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_SRWO_MASK) 4916 4917 #define EMAC_MTL_EST_GCL_CONTROL_R1W0_MASK (0x2U) 4918 #define EMAC_MTL_EST_GCL_CONTROL_R1W0_SHIFT (1U) 4919 #define EMAC_MTL_EST_GCL_CONTROL_R1W0_WIDTH (1U) 4920 #define EMAC_MTL_EST_GCL_CONTROL_R1W0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_R1W0_MASK) 4921 4922 #define EMAC_MTL_EST_GCL_CONTROL_GCRR_MASK (0x4U) 4923 #define EMAC_MTL_EST_GCL_CONTROL_GCRR_SHIFT (2U) 4924 #define EMAC_MTL_EST_GCL_CONTROL_GCRR_WIDTH (1U) 4925 #define EMAC_MTL_EST_GCL_CONTROL_GCRR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_GCRR_MASK) 4926 4927 #define EMAC_MTL_EST_GCL_CONTROL_DBGM_MASK (0x10U) 4928 #define EMAC_MTL_EST_GCL_CONTROL_DBGM_SHIFT (4U) 4929 #define EMAC_MTL_EST_GCL_CONTROL_DBGM_WIDTH (1U) 4930 #define EMAC_MTL_EST_GCL_CONTROL_DBGM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_DBGM_MASK) 4931 4932 #define EMAC_MTL_EST_GCL_CONTROL_DBGB_MASK (0x20U) 4933 #define EMAC_MTL_EST_GCL_CONTROL_DBGB_SHIFT (5U) 4934 #define EMAC_MTL_EST_GCL_CONTROL_DBGB_WIDTH (1U) 4935 #define EMAC_MTL_EST_GCL_CONTROL_DBGB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_DBGB_MASK) 4936 4937 #define EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK (0xFF00U) 4938 #define EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8U) 4939 #define EMAC_MTL_EST_GCL_CONTROL_ADDR_WIDTH (8U) 4940 #define EMAC_MTL_EST_GCL_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK) 4941 4942 #define EMAC_MTL_EST_GCL_CONTROL_ERR0_MASK (0x100000U) 4943 #define EMAC_MTL_EST_GCL_CONTROL_ERR0_SHIFT (20U) 4944 #define EMAC_MTL_EST_GCL_CONTROL_ERR0_WIDTH (1U) 4945 #define EMAC_MTL_EST_GCL_CONTROL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_ERR0_MASK) 4946 4947 #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U) 4948 #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U) 4949 #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_WIDTH (1U) 4950 #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_MASK) 4951 4952 #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U) 4953 #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U) 4954 #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_WIDTH (2U) 4955 #define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK) 4956 /*! @} */ 4957 4958 /*! @name MTL_EST_GCL_DATA - MTL EST GCL Data */ 4959 /*! @{ */ 4960 4961 #define EMAC_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFFU) 4962 #define EMAC_MTL_EST_GCL_DATA_GCD_SHIFT (0U) 4963 #define EMAC_MTL_EST_GCL_DATA_GCD_WIDTH (32U) 4964 #define EMAC_MTL_EST_GCL_DATA_GCD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT)) & EMAC_MTL_EST_GCL_DATA_GCD_MASK) 4965 /*! @} */ 4966 4967 /*! @name MTL_FPE_CTRL_STS - MTL FPE Control Status */ 4968 /*! @{ */ 4969 4970 #define EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK (0x3U) 4971 #define EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT (0U) 4972 #define EMAC_MTL_FPE_CTRL_STS_AFSZ_WIDTH (2U) 4973 #define EMAC_MTL_FPE_CTRL_STS_AFSZ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK) 4974 4975 #define EMAC_MTL_FPE_CTRL_STS_PEC_MASK (0x300U) 4976 #define EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT (8U) 4977 #define EMAC_MTL_FPE_CTRL_STS_PEC_WIDTH (2U) 4978 #define EMAC_MTL_FPE_CTRL_STS_PEC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT)) & EMAC_MTL_FPE_CTRL_STS_PEC_MASK) 4979 4980 #define EMAC_MTL_FPE_CTRL_STS_HRS_MASK (0x10000000U) 4981 #define EMAC_MTL_FPE_CTRL_STS_HRS_SHIFT (28U) 4982 #define EMAC_MTL_FPE_CTRL_STS_HRS_WIDTH (1U) 4983 #define EMAC_MTL_FPE_CTRL_STS_HRS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_FPE_CTRL_STS_HRS_SHIFT)) & EMAC_MTL_FPE_CTRL_STS_HRS_MASK) 4984 /*! @} */ 4985 4986 /*! @name MTL_FPE_ADVANCE - MTL FPE Advance */ 4987 /*! @{ */ 4988 4989 #define EMAC_MTL_FPE_ADVANCE_HADV_MASK (0xFFFFU) 4990 #define EMAC_MTL_FPE_ADVANCE_HADV_SHIFT (0U) 4991 #define EMAC_MTL_FPE_ADVANCE_HADV_WIDTH (16U) 4992 #define EMAC_MTL_FPE_ADVANCE_HADV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT)) & EMAC_MTL_FPE_ADVANCE_HADV_MASK) 4993 4994 #define EMAC_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF0000U) 4995 #define EMAC_MTL_FPE_ADVANCE_RADV_SHIFT (16U) 4996 #define EMAC_MTL_FPE_ADVANCE_RADV_WIDTH (16U) 4997 #define EMAC_MTL_FPE_ADVANCE_RADV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT)) & EMAC_MTL_FPE_ADVANCE_RADV_MASK) 4998 /*! @} */ 4999 5000 /*! @name MTL_RXP_CONTROL_STATUS - MTL Rx Parser Control Status */ 5001 /*! @{ */ 5002 5003 #define EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK (0x3FU) 5004 #define EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U) 5005 #define EMAC_MTL_RXP_CONTROL_STATUS_NVE_WIDTH (6U) 5006 #define EMAC_MTL_RXP_CONTROL_STATUS_NVE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK) 5007 5008 #define EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_MASK (0x8000U) 5009 #define EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_SHIFT (15U) 5010 #define EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_WIDTH (1U) 5011 #define EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_SHIFT)) & EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_MASK) 5012 5013 #define EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK (0x3F0000U) 5014 #define EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U) 5015 #define EMAC_MTL_RXP_CONTROL_STATUS_NPE_WIDTH (6U) 5016 #define EMAC_MTL_RXP_CONTROL_STATUS_NPE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK) 5017 5018 #define EMAC_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U) 5019 #define EMAC_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U) 5020 #define EMAC_MTL_RXP_CONTROL_STATUS_RXPI_WIDTH (1U) 5021 #define EMAC_MTL_RXP_CONTROL_STATUS_RXPI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & EMAC_MTL_RXP_CONTROL_STATUS_RXPI_MASK) 5022 /*! @} */ 5023 5024 /*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - MTL Rx Parser Interrupt Control Status */ 5025 /*! @{ */ 5026 5027 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U) 5028 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U) 5029 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_WIDTH (1U) 5030 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK) 5031 5032 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U) 5033 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U) 5034 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_WIDTH (1U) 5035 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK) 5036 5037 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U) 5038 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U) 5039 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_WIDTH (1U) 5040 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK) 5041 5042 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U) 5043 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U) 5044 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_WIDTH (1U) 5045 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK) 5046 5047 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U) 5048 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U) 5049 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_WIDTH (1U) 5050 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK) 5051 5052 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U) 5053 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U) 5054 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_WIDTH (1U) 5055 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK) 5056 5057 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U) 5058 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U) 5059 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_WIDTH (1U) 5060 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK) 5061 5062 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U) 5063 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U) 5064 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_WIDTH (1U) 5065 #define EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK) 5066 /*! @} */ 5067 5068 /*! @name MTL_RXP_DROP_CNT - MTL Rx Parser Drop Count */ 5069 /*! @{ */ 5070 5071 #define EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFFU) 5072 #define EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0U) 5073 #define EMAC_MTL_RXP_DROP_CNT_RXPDC_WIDTH (31U) 5074 #define EMAC_MTL_RXP_DROP_CNT_RXPDC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK) 5075 5076 #define EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_MASK (0x80000000U) 5077 #define EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U) 5078 #define EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_WIDTH (1U) 5079 #define EMAC_MTL_RXP_DROP_CNT_RXPDCOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_MASK) 5080 /*! @} */ 5081 5082 /*! @name MTL_RXP_ERROR_CNT - MTL Rx Parser Error Count */ 5083 /*! @{ */ 5084 5085 #define EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFFU) 5086 #define EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0U) 5087 #define EMAC_MTL_RXP_ERROR_CNT_RXPEC_WIDTH (31U) 5088 #define EMAC_MTL_RXP_ERROR_CNT_RXPEC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK) 5089 5090 #define EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U) 5091 #define EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U) 5092 #define EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_WIDTH (1U) 5093 #define EMAC_MTL_RXP_ERROR_CNT_RXPECOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_MASK) 5094 /*! @} */ 5095 5096 /*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - MTL Rx Parser Indirect Access Control Status */ 5097 /*! @{ */ 5098 5099 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0xFFU) 5100 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U) 5101 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_WIDTH (8U) 5102 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK) 5103 5104 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U) 5105 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U) 5106 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_WIDTH (1U) 5107 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK) 5108 5109 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_MASK (0x100000U) 5110 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_SHIFT (20U) 5111 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_WIDTH (1U) 5112 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_SHIFT)) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_MASK) 5113 5114 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK (0x600000U) 5115 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT (21U) 5116 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_WIDTH (2U) 5117 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT)) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK) 5118 5119 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U) 5120 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U) 5121 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_WIDTH (1U) 5122 #define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK) 5123 /*! @} */ 5124 5125 /*! @name MTL_RXP_INDIRECT_ACC_DATA - MTL Rx Parser Indirect Access Data */ 5126 /*! @{ */ 5127 5128 #define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU) 5129 #define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U) 5130 #define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_WIDTH (32U) 5131 #define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK) 5132 /*! @} */ 5133 5134 /*! @name MTL_ECC_CONTROL - MTL ECC Control */ 5135 /*! @{ */ 5136 5137 #define EMAC_MTL_ECC_CONTROL_MTXEE_MASK (0x1U) 5138 #define EMAC_MTL_ECC_CONTROL_MTXEE_SHIFT (0U) 5139 #define EMAC_MTL_ECC_CONTROL_MTXEE_WIDTH (1U) 5140 #define EMAC_MTL_ECC_CONTROL_MTXEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_CONTROL_MTXEE_SHIFT)) & EMAC_MTL_ECC_CONTROL_MTXEE_MASK) 5141 5142 #define EMAC_MTL_ECC_CONTROL_MRXEE_MASK (0x2U) 5143 #define EMAC_MTL_ECC_CONTROL_MRXEE_SHIFT (1U) 5144 #define EMAC_MTL_ECC_CONTROL_MRXEE_WIDTH (1U) 5145 #define EMAC_MTL_ECC_CONTROL_MRXEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_CONTROL_MRXEE_SHIFT)) & EMAC_MTL_ECC_CONTROL_MRXEE_MASK) 5146 5147 #define EMAC_MTL_ECC_CONTROL_MESTEE_MASK (0x4U) 5148 #define EMAC_MTL_ECC_CONTROL_MESTEE_SHIFT (2U) 5149 #define EMAC_MTL_ECC_CONTROL_MESTEE_WIDTH (1U) 5150 #define EMAC_MTL_ECC_CONTROL_MESTEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_CONTROL_MESTEE_SHIFT)) & EMAC_MTL_ECC_CONTROL_MESTEE_MASK) 5151 5152 #define EMAC_MTL_ECC_CONTROL_MRXPEE_MASK (0x8U) 5153 #define EMAC_MTL_ECC_CONTROL_MRXPEE_SHIFT (3U) 5154 #define EMAC_MTL_ECC_CONTROL_MRXPEE_WIDTH (1U) 5155 #define EMAC_MTL_ECC_CONTROL_MRXPEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_CONTROL_MRXPEE_SHIFT)) & EMAC_MTL_ECC_CONTROL_MRXPEE_MASK) 5156 5157 #define EMAC_MTL_ECC_CONTROL_MEEAO_MASK (0x100U) 5158 #define EMAC_MTL_ECC_CONTROL_MEEAO_SHIFT (8U) 5159 #define EMAC_MTL_ECC_CONTROL_MEEAO_WIDTH (1U) 5160 #define EMAC_MTL_ECC_CONTROL_MEEAO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_CONTROL_MEEAO_SHIFT)) & EMAC_MTL_ECC_CONTROL_MEEAO_MASK) 5161 /*! @} */ 5162 5163 /*! @name MTL_SAFETY_INTERRUPT_STATUS - MTL Safety Interript Status */ 5164 /*! @{ */ 5165 5166 #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_MASK (0x1U) 5167 #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_SHIFT (0U) 5168 #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_WIDTH (1U) 5169 #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_SHIFT)) & EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_MASK) 5170 5171 #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_MASK (0x2U) 5172 #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_SHIFT (1U) 5173 #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_WIDTH (1U) 5174 #define EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_SHIFT)) & EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_MASK) 5175 /*! @} */ 5176 5177 /*! @name MTL_ECC_INTERRUPT_ENABLE - MTL ECC Interrupt Enable */ 5178 /*! @{ */ 5179 5180 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_MASK (0x1U) 5181 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_SHIFT (0U) 5182 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_WIDTH (1U) 5183 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_MASK) 5184 5185 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_MASK (0x10U) 5186 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_SHIFT (4U) 5187 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_WIDTH (1U) 5188 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_MASK) 5189 5190 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_MASK (0x100U) 5191 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_SHIFT (8U) 5192 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_WIDTH (1U) 5193 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_MASK) 5194 5195 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_MASK (0x1000U) 5196 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_SHIFT (12U) 5197 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_WIDTH (1U) 5198 #define EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_MASK) 5199 /*! @} */ 5200 5201 /*! @name MTL_ECC_INTERRUPT_STATUS - MTL ECC Interrupt Status */ 5202 /*! @{ */ 5203 5204 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_MASK (0x1U) 5205 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_SHIFT (0U) 5206 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_WIDTH (1U) 5207 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_MASK) 5208 5209 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_MASK (0x2U) 5210 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_SHIFT (1U) 5211 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_WIDTH (1U) 5212 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_MASK) 5213 5214 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_MASK (0x4U) 5215 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_SHIFT (2U) 5216 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_WIDTH (1U) 5217 #define EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_MASK) 5218 5219 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_MASK (0x10U) 5220 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_SHIFT (4U) 5221 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_WIDTH (1U) 5222 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_MASK) 5223 5224 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_MASK (0x20U) 5225 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_SHIFT (5U) 5226 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_WIDTH (1U) 5227 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_MASK) 5228 5229 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_MASK (0x40U) 5230 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_SHIFT (6U) 5231 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_WIDTH (1U) 5232 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_MASK) 5233 5234 #define EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_MASK (0x100U) 5235 #define EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_SHIFT (8U) 5236 #define EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_WIDTH (1U) 5237 #define EMAC_MTL_ECC_INTERRUPT_STATUS_ECES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_MASK) 5238 5239 #define EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_MASK (0x200U) 5240 #define EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_SHIFT (9U) 5241 #define EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_WIDTH (1U) 5242 #define EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_MASK) 5243 5244 #define EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_MASK (0x400U) 5245 #define EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_SHIFT (10U) 5246 #define EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_WIDTH (1U) 5247 #define EMAC_MTL_ECC_INTERRUPT_STATUS_EUES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_MASK) 5248 5249 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_MASK (0x1000U) 5250 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_SHIFT (12U) 5251 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_WIDTH (1U) 5252 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_MASK) 5253 5254 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_MASK (0x2000U) 5255 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_SHIFT (13U) 5256 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_WIDTH (1U) 5257 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_MASK) 5258 5259 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_MASK (0x4000U) 5260 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_SHIFT (14U) 5261 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_WIDTH (1U) 5262 #define EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_SHIFT)) & EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_MASK) 5263 /*! @} */ 5264 5265 /*! @name MTL_ECC_ERR_STS_RCTL - MTL ECC Error Status */ 5266 /*! @{ */ 5267 5268 #define EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_MASK (0x1U) 5269 #define EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_SHIFT (0U) 5270 #define EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_WIDTH (1U) 5271 #define EMAC_MTL_ECC_ERR_STS_RCTL_EESRE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_SHIFT)) & EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_MASK) 5272 5273 #define EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK (0xEU) 5274 #define EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT (1U) 5275 #define EMAC_MTL_ECC_ERR_STS_RCTL_EMS_WIDTH (3U) 5276 #define EMAC_MTL_ECC_ERR_STS_RCTL_EMS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT)) & EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK) 5277 5278 #define EMAC_MTL_ECC_ERR_STS_RCTL_CCES_MASK (0x10U) 5279 #define EMAC_MTL_ECC_ERR_STS_RCTL_CCES_SHIFT (4U) 5280 #define EMAC_MTL_ECC_ERR_STS_RCTL_CCES_WIDTH (1U) 5281 #define EMAC_MTL_ECC_ERR_STS_RCTL_CCES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_ERR_STS_RCTL_CCES_SHIFT)) & EMAC_MTL_ECC_ERR_STS_RCTL_CCES_MASK) 5282 5283 #define EMAC_MTL_ECC_ERR_STS_RCTL_CUES_MASK (0x20U) 5284 #define EMAC_MTL_ECC_ERR_STS_RCTL_CUES_SHIFT (5U) 5285 #define EMAC_MTL_ECC_ERR_STS_RCTL_CUES_WIDTH (1U) 5286 #define EMAC_MTL_ECC_ERR_STS_RCTL_CUES(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_ERR_STS_RCTL_CUES_SHIFT)) & EMAC_MTL_ECC_ERR_STS_RCTL_CUES_MASK) 5287 /*! @} */ 5288 5289 /*! @name MTL_ECC_ERR_ADDR_STATUS - MTL ECC Error Adress Status */ 5290 /*! @{ */ 5291 5292 #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK (0xFFFFU) 5293 #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT (0U) 5294 #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_WIDTH (16U) 5295 #define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT)) & EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK) 5296 5297 #define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK (0xFFFF0000U) 5298 #define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT (16U) 5299 #define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_WIDTH (16U) 5300 #define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT)) & EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK) 5301 /*! @} */ 5302 5303 /*! @name MTL_ECC_ERR_CNTR_STATUS - MTL ECC Error Control Status */ 5304 /*! @{ */ 5305 5306 #define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK (0xFFU) 5307 #define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT (0U) 5308 #define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_WIDTH (8U) 5309 #define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT)) & EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK) 5310 5311 #define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK (0xF0000U) 5312 #define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT (16U) 5313 #define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_WIDTH (4U) 5314 #define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT)) & EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK) 5315 /*! @} */ 5316 5317 /*! @name MTL_DPP_CONTROL - MTL DPP Control */ 5318 /*! @{ */ 5319 5320 #define EMAC_MTL_DPP_CONTROL_EDPP_MASK (0x1U) 5321 #define EMAC_MTL_DPP_CONTROL_EDPP_SHIFT (0U) 5322 #define EMAC_MTL_DPP_CONTROL_EDPP_WIDTH (1U) 5323 #define EMAC_MTL_DPP_CONTROL_EDPP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_EDPP_SHIFT)) & EMAC_MTL_DPP_CONTROL_EDPP_MASK) 5324 5325 #define EMAC_MTL_DPP_CONTROL_OPE_MASK (0x2U) 5326 #define EMAC_MTL_DPP_CONTROL_OPE_SHIFT (1U) 5327 #define EMAC_MTL_DPP_CONTROL_OPE_WIDTH (1U) 5328 #define EMAC_MTL_DPP_CONTROL_OPE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_OPE_SHIFT)) & EMAC_MTL_DPP_CONTROL_OPE_MASK) 5329 5330 #define EMAC_MTL_DPP_CONTROL_IPEID_MASK (0x10U) 5331 #define EMAC_MTL_DPP_CONTROL_IPEID_SHIFT (4U) 5332 #define EMAC_MTL_DPP_CONTROL_IPEID_WIDTH (1U) 5333 #define EMAC_MTL_DPP_CONTROL_IPEID(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_IPEID_SHIFT)) & EMAC_MTL_DPP_CONTROL_IPEID_MASK) 5334 5335 #define EMAC_MTL_DPP_CONTROL_IPEMC_MASK (0x20U) 5336 #define EMAC_MTL_DPP_CONTROL_IPEMC_SHIFT (5U) 5337 #define EMAC_MTL_DPP_CONTROL_IPEMC_WIDTH (1U) 5338 #define EMAC_MTL_DPP_CONTROL_IPEMC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_IPEMC_SHIFT)) & EMAC_MTL_DPP_CONTROL_IPEMC_MASK) 5339 5340 #define EMAC_MTL_DPP_CONTROL_IPEMTS_MASK (0x40U) 5341 #define EMAC_MTL_DPP_CONTROL_IPEMTS_SHIFT (6U) 5342 #define EMAC_MTL_DPP_CONTROL_IPEMTS_WIDTH (1U) 5343 #define EMAC_MTL_DPP_CONTROL_IPEMTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_IPEMTS_SHIFT)) & EMAC_MTL_DPP_CONTROL_IPEMTS_MASK) 5344 5345 #define EMAC_MTL_DPP_CONTROL_IPEMRF_MASK (0x80U) 5346 #define EMAC_MTL_DPP_CONTROL_IPEMRF_SHIFT (7U) 5347 #define EMAC_MTL_DPP_CONTROL_IPEMRF_WIDTH (1U) 5348 #define EMAC_MTL_DPP_CONTROL_IPEMRF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_IPEMRF_SHIFT)) & EMAC_MTL_DPP_CONTROL_IPEMRF_MASK) 5349 5350 #define EMAC_MTL_DPP_CONTROL_IPEDDC_MASK (0x100U) 5351 #define EMAC_MTL_DPP_CONTROL_IPEDDC_SHIFT (8U) 5352 #define EMAC_MTL_DPP_CONTROL_IPEDDC_WIDTH (1U) 5353 #define EMAC_MTL_DPP_CONTROL_IPEDDC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_IPEDDC_SHIFT)) & EMAC_MTL_DPP_CONTROL_IPEDDC_MASK) 5354 5355 #define EMAC_MTL_DPP_CONTROL_IPETD_MASK (0x400U) 5356 #define EMAC_MTL_DPP_CONTROL_IPETD_SHIFT (10U) 5357 #define EMAC_MTL_DPP_CONTROL_IPETD_WIDTH (1U) 5358 #define EMAC_MTL_DPP_CONTROL_IPETD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_IPETD_SHIFT)) & EMAC_MTL_DPP_CONTROL_IPETD_MASK) 5359 5360 #define EMAC_MTL_DPP_CONTROL_IPERD_MASK (0x800U) 5361 #define EMAC_MTL_DPP_CONTROL_IPERD_SHIFT (11U) 5362 #define EMAC_MTL_DPP_CONTROL_IPERD_WIDTH (1U) 5363 #define EMAC_MTL_DPP_CONTROL_IPERD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_DPP_CONTROL_IPERD_SHIFT)) & EMAC_MTL_DPP_CONTROL_IPERD_MASK) 5364 /*! @} */ 5365 5366 /*! @name MTL_TXQ0_OPERATION_MODE - MTL Tx Queue 0 Operation Mode */ 5367 /*! @{ */ 5368 5369 #define EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK (0x1U) 5370 #define EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT (0U) 5371 #define EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_WIDTH (1U) 5372 #define EMAC_MTL_TXQ0_OPERATION_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK) 5373 5374 #define EMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK (0x2U) 5375 #define EMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT (1U) 5376 #define EMAC_MTL_TXQ0_OPERATION_MODE_TSF_WIDTH (1U) 5377 #define EMAC_MTL_TXQ0_OPERATION_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK) 5378 5379 #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0xCU) 5380 #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT (2U) 5381 #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_WIDTH (2U) 5382 #define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK) 5383 5384 #define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x70U) 5385 #define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT (4U) 5386 #define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_WIDTH (3U) 5387 #define EMAC_MTL_TXQ0_OPERATION_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK) 5388 5389 #define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK (0x1F0000U) 5390 #define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT (16U) 5391 #define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_WIDTH (5U) 5392 #define EMAC_MTL_TXQ0_OPERATION_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT)) & EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK) 5393 /*! @} */ 5394 5395 /*! @name MTL_TXQ0_UNDERFLOW - MTL Tx Queue 0 Underflow */ 5396 /*! @{ */ 5397 5398 #define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7FFU) 5399 #define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT (0U) 5400 #define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_WIDTH (11U) 5401 #define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT)) & EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK) 5402 5403 #define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK (0x800U) 5404 #define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT (11U) 5405 #define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_WIDTH (1U) 5406 #define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT)) & EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK) 5407 /*! @} */ 5408 5409 /*! @name MTL_TXQ0_DEBUG - MTL Tx Queue 0 Debug */ 5410 /*! @{ */ 5411 5412 #define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK (0x1U) 5413 #define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT (0U) 5414 #define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_WIDTH (1U) 5415 #define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK) 5416 5417 #define EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK (0x6U) 5418 #define EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT (1U) 5419 #define EMAC_MTL_TXQ0_DEBUG_TRCSTS_WIDTH (2U) 5420 #define EMAC_MTL_TXQ0_DEBUG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK) 5421 5422 #define EMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK (0x8U) 5423 #define EMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT (3U) 5424 #define EMAC_MTL_TXQ0_DEBUG_TWCSTS_WIDTH (1U) 5425 #define EMAC_MTL_TXQ0_DEBUG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK) 5426 5427 #define EMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK (0x10U) 5428 #define EMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT (4U) 5429 #define EMAC_MTL_TXQ0_DEBUG_TXQSTS_WIDTH (1U) 5430 #define EMAC_MTL_TXQ0_DEBUG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK) 5431 5432 #define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK (0x20U) 5433 #define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT (5U) 5434 #define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_WIDTH (1U) 5435 #define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK) 5436 5437 #define EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK (0x70000U) 5438 #define EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT (16U) 5439 #define EMAC_MTL_TXQ0_DEBUG_PTXQ_WIDTH (3U) 5440 #define EMAC_MTL_TXQ0_DEBUG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK) 5441 5442 #define EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK (0x700000U) 5443 #define EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT (20U) 5444 #define EMAC_MTL_TXQ0_DEBUG_STXSTSF_WIDTH (3U) 5445 #define EMAC_MTL_TXQ0_DEBUG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT)) & EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK) 5446 /*! @} */ 5447 5448 /*! @name MTL_TXQ0_ETS_STATUS - MTL Tx Queue 0 ETS Status */ 5449 /*! @{ */ 5450 5451 #define EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK (0xFFFFFFU) 5452 #define EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT (0U) 5453 #define EMAC_MTL_TXQ0_ETS_STATUS_ABS_WIDTH (24U) 5454 #define EMAC_MTL_TXQ0_ETS_STATUS_ABS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT)) & EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK) 5455 /*! @} */ 5456 5457 /*! @name MTL_TXQ0_QUANTUM_WEIGHT - MTL Tx Queue Quantum Weight */ 5458 /*! @{ */ 5459 5460 #define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFFU) 5461 #define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT (0U) 5462 #define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_WIDTH (21U) 5463 #define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT)) & EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK) 5464 /*! @} */ 5465 5466 /*! @name MTL_Q0_INTERRUPT_CONTROL_STATUS - MTL Queue 0 Interrupt Control Status */ 5467 /*! @{ */ 5468 5469 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK (0x1U) 5470 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT (0U) 5471 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH (1U) 5472 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK) 5473 5474 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK (0x2U) 5475 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT (1U) 5476 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH (1U) 5477 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK) 5478 5479 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MASK (0x100U) 5480 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT (8U) 5481 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH (1U) 5482 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MASK) 5483 5484 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK (0x200U) 5485 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT (9U) 5486 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH (1U) 5487 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK) 5488 5489 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK (0x10000U) 5490 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT (16U) 5491 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH (1U) 5492 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK) 5493 5494 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MASK (0x1000000U) 5495 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT (24U) 5496 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH (1U) 5497 #define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT)) & EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MASK) 5498 /*! @} */ 5499 5500 /*! @name MTL_RXQ0_OPERATION_MODE - MTL Rx Queue 0 Operation Mode */ 5501 /*! @{ */ 5502 5503 #define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK (0x3U) 5504 #define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT (0U) 5505 #define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_WIDTH (2U) 5506 #define EMAC_MTL_RXQ0_OPERATION_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK) 5507 5508 #define EMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK (0x8U) 5509 #define EMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT (3U) 5510 #define EMAC_MTL_RXQ0_OPERATION_MODE_FUP_WIDTH (1U) 5511 #define EMAC_MTL_RXQ0_OPERATION_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK) 5512 5513 #define EMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK (0x10U) 5514 #define EMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT (4U) 5515 #define EMAC_MTL_RXQ0_OPERATION_MODE_FEP_WIDTH (1U) 5516 #define EMAC_MTL_RXQ0_OPERATION_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK) 5517 5518 #define EMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK (0x20U) 5519 #define EMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT (5U) 5520 #define EMAC_MTL_RXQ0_OPERATION_MODE_RSF_WIDTH (1U) 5521 #define EMAC_MTL_RXQ0_OPERATION_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK) 5522 5523 #define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK (0x40U) 5524 #define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT (6U) 5525 #define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_WIDTH (1U) 5526 #define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK) 5527 5528 #define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK (0x80U) 5529 #define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT (7U) 5530 #define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_WIDTH (1U) 5531 #define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK) 5532 5533 #define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0xF00U) 5534 #define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT (8U) 5535 #define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_WIDTH (4U) 5536 #define EMAC_MTL_RXQ0_OPERATION_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK) 5537 5538 #define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0x3C000U) 5539 #define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT (14U) 5540 #define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_WIDTH (4U) 5541 #define EMAC_MTL_RXQ0_OPERATION_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK) 5542 5543 #define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK (0x1F00000U) 5544 #define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT (20U) 5545 #define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_WIDTH (5U) 5546 #define EMAC_MTL_RXQ0_OPERATION_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT)) & EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK) 5547 /*! @} */ 5548 5549 /*! @name MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT - MTL Rx Queue Missed Packet Overflow Count */ 5550 /*! @{ */ 5551 5552 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FFU) 5553 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0U) 5554 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH (11U) 5555 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) 5556 5557 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK (0x800U) 5558 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT (11U) 5559 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH (1U) 5560 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT)) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK) 5561 5562 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF0000U) 5563 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16U) 5564 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH (11U) 5565 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) 5566 5567 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK (0x8000000U) 5568 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT (27U) 5569 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH (1U) 5570 #define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT)) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK) 5571 /*! @} */ 5572 5573 /*! @name MTL_RXQ0_DEBUG - MTL Rx Queue 0 Debug */ 5574 /*! @{ */ 5575 5576 #define EMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK (0x1U) 5577 #define EMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT (0U) 5578 #define EMAC_MTL_RXQ0_DEBUG_RWCSTS_WIDTH (1U) 5579 #define EMAC_MTL_RXQ0_DEBUG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT)) & EMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK) 5580 5581 #define EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK (0x6U) 5582 #define EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT (1U) 5583 #define EMAC_MTL_RXQ0_DEBUG_RRCSTS_WIDTH (2U) 5584 #define EMAC_MTL_RXQ0_DEBUG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT)) & EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK) 5585 5586 #define EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (0x30U) 5587 #define EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT (4U) 5588 #define EMAC_MTL_RXQ0_DEBUG_RXQSTS_WIDTH (2U) 5589 #define EMAC_MTL_RXQ0_DEBUG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT)) & EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK) 5590 5591 #define EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0x3FFF0000U) 5592 #define EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT (16U) 5593 #define EMAC_MTL_RXQ0_DEBUG_PRXQ_WIDTH (14U) 5594 #define EMAC_MTL_RXQ0_DEBUG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT)) & EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK) 5595 /*! @} */ 5596 5597 /*! @name MTL_RXQ0_CONTROL - MTL Rx Queue 0 Control 0 */ 5598 /*! @{ */ 5599 5600 #define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK (0x7U) 5601 #define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT (0U) 5602 #define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_WIDTH (3U) 5603 #define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT)) & EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK) 5604 5605 #define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MASK (0x8U) 5606 #define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_SHIFT (3U) 5607 #define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_WIDTH (1U) 5608 #define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_SHIFT)) & EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MASK) 5609 /*! @} */ 5610 5611 /*! @name MTL_TXQ1_OPERATION_MODE - MTL Tx Queue 1 Operation Mode */ 5612 /*! @{ */ 5613 5614 #define EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_MASK (0x1U) 5615 #define EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_SHIFT (0U) 5616 #define EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_WIDTH (1U) 5617 #define EMAC_MTL_TXQ1_OPERATION_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_MASK) 5618 5619 #define EMAC_MTL_TXQ1_OPERATION_MODE_TSF_MASK (0x2U) 5620 #define EMAC_MTL_TXQ1_OPERATION_MODE_TSF_SHIFT (1U) 5621 #define EMAC_MTL_TXQ1_OPERATION_MODE_TSF_WIDTH (1U) 5622 #define EMAC_MTL_TXQ1_OPERATION_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_TSF_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_TSF_MASK) 5623 5624 #define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK (0xCU) 5625 #define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT (2U) 5626 #define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_WIDTH (2U) 5627 #define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK) 5628 5629 #define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK (0x70U) 5630 #define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT (4U) 5631 #define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_WIDTH (3U) 5632 #define EMAC_MTL_TXQ1_OPERATION_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK) 5633 5634 #define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK (0x1F0000U) 5635 #define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT (16U) 5636 #define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_WIDTH (5U) 5637 #define EMAC_MTL_TXQ1_OPERATION_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT)) & EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK) 5638 /*! @} */ 5639 5640 /*! @name MTL_TXQ1_UNDERFLOW - MTL Tx Queue 1 Underflow */ 5641 /*! @{ */ 5642 5643 #define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK (0x7FFU) 5644 #define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT (0U) 5645 #define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_WIDTH (11U) 5646 #define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT)) & EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK) 5647 5648 #define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_MASK (0x800U) 5649 #define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_SHIFT (11U) 5650 #define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_WIDTH (1U) 5651 #define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_SHIFT)) & EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_MASK) 5652 /*! @} */ 5653 5654 /*! @name MTL_TXQ1_DEBUG - MTL Tx Queue 1 Debug */ 5655 /*! @{ */ 5656 5657 #define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_MASK (0x1U) 5658 #define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_SHIFT (0U) 5659 #define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_WIDTH (1U) 5660 #define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_MASK) 5661 5662 #define EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK (0x6U) 5663 #define EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT (1U) 5664 #define EMAC_MTL_TXQ1_DEBUG_TRCSTS_WIDTH (2U) 5665 #define EMAC_MTL_TXQ1_DEBUG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK) 5666 5667 #define EMAC_MTL_TXQ1_DEBUG_TWCSTS_MASK (0x8U) 5668 #define EMAC_MTL_TXQ1_DEBUG_TWCSTS_SHIFT (3U) 5669 #define EMAC_MTL_TXQ1_DEBUG_TWCSTS_WIDTH (1U) 5670 #define EMAC_MTL_TXQ1_DEBUG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TWCSTS_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TWCSTS_MASK) 5671 5672 #define EMAC_MTL_TXQ1_DEBUG_TXQSTS_MASK (0x10U) 5673 #define EMAC_MTL_TXQ1_DEBUG_TXQSTS_SHIFT (4U) 5674 #define EMAC_MTL_TXQ1_DEBUG_TXQSTS_WIDTH (1U) 5675 #define EMAC_MTL_TXQ1_DEBUG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TXQSTS_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TXQSTS_MASK) 5676 5677 #define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_MASK (0x20U) 5678 #define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_SHIFT (5U) 5679 #define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_WIDTH (1U) 5680 #define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_MASK) 5681 5682 #define EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK (0x70000U) 5683 #define EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT (16U) 5684 #define EMAC_MTL_TXQ1_DEBUG_PTXQ_WIDTH (3U) 5685 #define EMAC_MTL_TXQ1_DEBUG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK) 5686 5687 #define EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK (0x700000U) 5688 #define EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT (20U) 5689 #define EMAC_MTL_TXQ1_DEBUG_STXSTSF_WIDTH (3U) 5690 #define EMAC_MTL_TXQ1_DEBUG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT)) & EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK) 5691 /*! @} */ 5692 5693 /*! @name MTL_TXQ1_ETS_CONTROL - MTL Tx Queue 1 ETS Control */ 5694 /*! @{ */ 5695 5696 #define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_MASK (0x4U) 5697 #define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_SHIFT (2U) 5698 #define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_WIDTH (1U) 5699 #define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_SHIFT)) & EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_MASK) 5700 5701 #define EMAC_MTL_TXQ1_ETS_CONTROL_CC_MASK (0x8U) 5702 #define EMAC_MTL_TXQ1_ETS_CONTROL_CC_SHIFT (3U) 5703 #define EMAC_MTL_TXQ1_ETS_CONTROL_CC_WIDTH (1U) 5704 #define EMAC_MTL_TXQ1_ETS_CONTROL_CC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_ETS_CONTROL_CC_SHIFT)) & EMAC_MTL_TXQ1_ETS_CONTROL_CC_MASK) 5705 5706 #define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK (0x70U) 5707 #define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT (4U) 5708 #define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_WIDTH (3U) 5709 #define EMAC_MTL_TXQ1_ETS_CONTROL_SLC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT)) & EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK) 5710 /*! @} */ 5711 5712 /*! @name MTL_TXQ1_ETS_STATUS - MTL Tx Queue 1 ETS Status */ 5713 /*! @{ */ 5714 5715 #define EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK (0xFFFFFFU) 5716 #define EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT (0U) 5717 #define EMAC_MTL_TXQ1_ETS_STATUS_ABS_WIDTH (24U) 5718 #define EMAC_MTL_TXQ1_ETS_STATUS_ABS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT)) & EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK) 5719 /*! @} */ 5720 5721 /*! @name MTL_TXQ1_QUANTUM_WEIGHT - MTL Tx Queue 1 Quantum Weight */ 5722 /*! @{ */ 5723 5724 #define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFFU) 5725 #define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT (0U) 5726 #define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_WIDTH (21U) 5727 #define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT)) & EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK) 5728 /*! @} */ 5729 5730 /*! @name MTL_TXQ1_SENDSLOPECREDIT - MTL Tx Queue 1 Sendslope Credit */ 5731 /*! @{ */ 5732 5733 #define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK (0x3FFFU) 5734 #define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT (0U) 5735 #define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_WIDTH (14U) 5736 #define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT)) & EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK) 5737 /*! @} */ 5738 5739 /*! @name MTL_TXQ1_HICREDIT - MTL Tx Queue 1 HiCredit */ 5740 /*! @{ */ 5741 5742 #define EMAC_MTL_TXQ1_HICREDIT_HC_MASK (0x1FFFFFFFU) 5743 #define EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT (0U) 5744 #define EMAC_MTL_TXQ1_HICREDIT_HC_WIDTH (29U) 5745 #define EMAC_MTL_TXQ1_HICREDIT_HC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT)) & EMAC_MTL_TXQ1_HICREDIT_HC_MASK) 5746 /*! @} */ 5747 5748 /*! @name MTL_TXQ1_LOCREDIT - MTL Tx Queue 1 LoCredit */ 5749 /*! @{ */ 5750 5751 #define EMAC_MTL_TXQ1_LOCREDIT_LC_MASK (0x1FFFFFFFU) 5752 #define EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT (0U) 5753 #define EMAC_MTL_TXQ1_LOCREDIT_LC_WIDTH (29U) 5754 #define EMAC_MTL_TXQ1_LOCREDIT_LC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT)) & EMAC_MTL_TXQ1_LOCREDIT_LC_MASK) 5755 /*! @} */ 5756 5757 /*! @name MTL_Q1_INTERRUPT_CONTROL_STATUS - MTL Queue 1 Interrupt Control Status */ 5758 /*! @{ */ 5759 5760 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK (0x1U) 5761 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT (0U) 5762 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH (1U) 5763 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK) 5764 5765 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK (0x2U) 5766 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT (1U) 5767 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH (1U) 5768 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK) 5769 5770 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_MASK (0x100U) 5771 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT (8U) 5772 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH (1U) 5773 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_MASK) 5774 5775 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK (0x200U) 5776 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT (9U) 5777 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH (1U) 5778 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK) 5779 5780 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK (0x10000U) 5781 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT (16U) 5782 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH (1U) 5783 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK) 5784 5785 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_MASK (0x1000000U) 5786 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT (24U) 5787 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH (1U) 5788 #define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT)) & EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_MASK) 5789 /*! @} */ 5790 5791 /*! @name MTL_RXQ1_OPERATION_MODE - MTL Rx Queue 1 Operation Mode */ 5792 /*! @{ */ 5793 5794 #define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK (0x3U) 5795 #define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT (0U) 5796 #define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_WIDTH (2U) 5797 #define EMAC_MTL_RXQ1_OPERATION_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK) 5798 5799 #define EMAC_MTL_RXQ1_OPERATION_MODE_FUP_MASK (0x8U) 5800 #define EMAC_MTL_RXQ1_OPERATION_MODE_FUP_SHIFT (3U) 5801 #define EMAC_MTL_RXQ1_OPERATION_MODE_FUP_WIDTH (1U) 5802 #define EMAC_MTL_RXQ1_OPERATION_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_FUP_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_FUP_MASK) 5803 5804 #define EMAC_MTL_RXQ1_OPERATION_MODE_FEP_MASK (0x10U) 5805 #define EMAC_MTL_RXQ1_OPERATION_MODE_FEP_SHIFT (4U) 5806 #define EMAC_MTL_RXQ1_OPERATION_MODE_FEP_WIDTH (1U) 5807 #define EMAC_MTL_RXQ1_OPERATION_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_FEP_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_FEP_MASK) 5808 5809 #define EMAC_MTL_RXQ1_OPERATION_MODE_RSF_MASK (0x20U) 5810 #define EMAC_MTL_RXQ1_OPERATION_MODE_RSF_SHIFT (5U) 5811 #define EMAC_MTL_RXQ1_OPERATION_MODE_RSF_WIDTH (1U) 5812 #define EMAC_MTL_RXQ1_OPERATION_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RSF_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RSF_MASK) 5813 5814 #define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_MASK (0x40U) 5815 #define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_SHIFT (6U) 5816 #define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_WIDTH (1U) 5817 #define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_MASK) 5818 5819 #define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_MASK (0x80U) 5820 #define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_SHIFT (7U) 5821 #define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_WIDTH (1U) 5822 #define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_MASK) 5823 5824 #define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK (0xF00U) 5825 #define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT (8U) 5826 #define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_WIDTH (4U) 5827 #define EMAC_MTL_RXQ1_OPERATION_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK) 5828 5829 #define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK (0x3C000U) 5830 #define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT (14U) 5831 #define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_WIDTH (4U) 5832 #define EMAC_MTL_RXQ1_OPERATION_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK) 5833 5834 #define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK (0x1F00000U) 5835 #define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT (20U) 5836 #define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_WIDTH (5U) 5837 #define EMAC_MTL_RXQ1_OPERATION_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT)) & EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK) 5838 /*! @} */ 5839 5840 /*! @name MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT - MTL Rx Queue 1 Missed Packet Overflow Counter */ 5841 /*! @{ */ 5842 5843 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FFU) 5844 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0U) 5845 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH (11U) 5846 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK) 5847 5848 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK (0x800U) 5849 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT (11U) 5850 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH (1U) 5851 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT)) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK) 5852 5853 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF0000U) 5854 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16U) 5855 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH (11U) 5856 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK) 5857 5858 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK (0x8000000U) 5859 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT (27U) 5860 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH (1U) 5861 #define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT)) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK) 5862 /*! @} */ 5863 5864 /*! @name MTL_RXQ1_DEBUG - MTL Rx Queue 1 Debug */ 5865 /*! @{ */ 5866 5867 #define EMAC_MTL_RXQ1_DEBUG_RWCSTS_MASK (0x1U) 5868 #define EMAC_MTL_RXQ1_DEBUG_RWCSTS_SHIFT (0U) 5869 #define EMAC_MTL_RXQ1_DEBUG_RWCSTS_WIDTH (1U) 5870 #define EMAC_MTL_RXQ1_DEBUG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_DEBUG_RWCSTS_SHIFT)) & EMAC_MTL_RXQ1_DEBUG_RWCSTS_MASK) 5871 5872 #define EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK (0x6U) 5873 #define EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT (1U) 5874 #define EMAC_MTL_RXQ1_DEBUG_RRCSTS_WIDTH (2U) 5875 #define EMAC_MTL_RXQ1_DEBUG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT)) & EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK) 5876 5877 #define EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK (0x30U) 5878 #define EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT (4U) 5879 #define EMAC_MTL_RXQ1_DEBUG_RXQSTS_WIDTH (2U) 5880 #define EMAC_MTL_RXQ1_DEBUG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT)) & EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK) 5881 5882 #define EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK (0x3FFF0000U) 5883 #define EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT (16U) 5884 #define EMAC_MTL_RXQ1_DEBUG_PRXQ_WIDTH (14U) 5885 #define EMAC_MTL_RXQ1_DEBUG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT)) & EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK) 5886 /*! @} */ 5887 5888 /*! @name MTL_RXQ1_CONTROL - MTL Rx Queue 1 Control */ 5889 /*! @{ */ 5890 5891 #define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK (0x7U) 5892 #define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT (0U) 5893 #define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_WIDTH (3U) 5894 #define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT)) & EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK) 5895 5896 #define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_MASK (0x8U) 5897 #define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_SHIFT (3U) 5898 #define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_WIDTH (1U) 5899 #define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_SHIFT)) & EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_MASK) 5900 /*! @} */ 5901 5902 /*! @name DMA_MODE - DMA Mode */ 5903 /*! @{ */ 5904 5905 #define EMAC_DMA_MODE_SWR_MASK (0x1U) 5906 #define EMAC_DMA_MODE_SWR_SHIFT (0U) 5907 #define EMAC_DMA_MODE_SWR_WIDTH (1U) 5908 #define EMAC_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_SWR_SHIFT)) & EMAC_DMA_MODE_SWR_MASK) 5909 5910 #define EMAC_DMA_MODE_DA_MASK (0x2U) 5911 #define EMAC_DMA_MODE_DA_SHIFT (1U) 5912 #define EMAC_DMA_MODE_DA_WIDTH (1U) 5913 #define EMAC_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_DA_SHIFT)) & EMAC_DMA_MODE_DA_MASK) 5914 5915 #define EMAC_DMA_MODE_TAA_MASK (0x1CU) 5916 #define EMAC_DMA_MODE_TAA_SHIFT (2U) 5917 #define EMAC_DMA_MODE_TAA_WIDTH (3U) 5918 #define EMAC_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_TAA_SHIFT)) & EMAC_DMA_MODE_TAA_MASK) 5919 5920 #define EMAC_DMA_MODE_ARBC_MASK (0x200U) 5921 #define EMAC_DMA_MODE_ARBC_SHIFT (9U) 5922 #define EMAC_DMA_MODE_ARBC_WIDTH (1U) 5923 #define EMAC_DMA_MODE_ARBC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_ARBC_SHIFT)) & EMAC_DMA_MODE_ARBC_MASK) 5924 5925 #define EMAC_DMA_MODE_TXPR_MASK (0x800U) 5926 #define EMAC_DMA_MODE_TXPR_SHIFT (11U) 5927 #define EMAC_DMA_MODE_TXPR_WIDTH (1U) 5928 #define EMAC_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_TXPR_SHIFT)) & EMAC_DMA_MODE_TXPR_MASK) 5929 5930 #define EMAC_DMA_MODE_PR_MASK (0x7000U) 5931 #define EMAC_DMA_MODE_PR_SHIFT (12U) 5932 #define EMAC_DMA_MODE_PR_WIDTH (3U) 5933 #define EMAC_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_PR_SHIFT)) & EMAC_DMA_MODE_PR_MASK) 5934 5935 #define EMAC_DMA_MODE_INTM_MASK (0x30000U) 5936 #define EMAC_DMA_MODE_INTM_SHIFT (16U) 5937 #define EMAC_DMA_MODE_INTM_WIDTH (2U) 5938 #define EMAC_DMA_MODE_INTM(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_MODE_INTM_SHIFT)) & EMAC_DMA_MODE_INTM_MASK) 5939 /*! @} */ 5940 5941 /*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */ 5942 /*! @{ */ 5943 5944 #define EMAC_DMA_SYSBUS_MODE_FB_MASK (0x1U) 5945 #define EMAC_DMA_SYSBUS_MODE_FB_SHIFT (0U) 5946 #define EMAC_DMA_SYSBUS_MODE_FB_WIDTH (1U) 5947 #define EMAC_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_FB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_FB_MASK) 5948 5949 #define EMAC_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) 5950 #define EMAC_DMA_SYSBUS_MODE_AAL_SHIFT (12U) 5951 #define EMAC_DMA_SYSBUS_MODE_AAL_WIDTH (1U) 5952 #define EMAC_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_AAL_SHIFT)) & EMAC_DMA_SYSBUS_MODE_AAL_MASK) 5953 5954 #define EMAC_DMA_SYSBUS_MODE_MB_MASK (0x4000U) 5955 #define EMAC_DMA_SYSBUS_MODE_MB_SHIFT (14U) 5956 #define EMAC_DMA_SYSBUS_MODE_MB_WIDTH (1U) 5957 #define EMAC_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_MB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_MB_MASK) 5958 5959 #define EMAC_DMA_SYSBUS_MODE_RB_MASK (0x8000U) 5960 #define EMAC_DMA_SYSBUS_MODE_RB_SHIFT (15U) 5961 #define EMAC_DMA_SYSBUS_MODE_RB_WIDTH (1U) 5962 #define EMAC_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SYSBUS_MODE_RB_SHIFT)) & EMAC_DMA_SYSBUS_MODE_RB_MASK) 5963 /*! @} */ 5964 5965 /*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */ 5966 /*! @{ */ 5967 5968 #define EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U) 5969 #define EMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) 5970 #define EMAC_DMA_INTERRUPT_STATUS_DC0IS_WIDTH (1U) 5971 #define EMAC_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK) 5972 5973 #define EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U) 5974 #define EMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U) 5975 #define EMAC_DMA_INTERRUPT_STATUS_DC1IS_WIDTH (1U) 5976 #define EMAC_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK) 5977 5978 #define EMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U) 5979 #define EMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) 5980 #define EMAC_DMA_INTERRUPT_STATUS_MTLIS_WIDTH (1U) 5981 #define EMAC_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK) 5982 5983 #define EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U) 5984 #define EMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) 5985 #define EMAC_DMA_INTERRUPT_STATUS_MACIS_WIDTH (1U) 5986 #define EMAC_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK) 5987 /*! @} */ 5988 5989 /*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */ 5990 /*! @{ */ 5991 5992 #define EMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U) 5993 #define EMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) 5994 #define EMAC_DMA_DEBUG_STATUS0_AXWHSTS_WIDTH (1U) 5995 #define EMAC_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK) 5996 5997 #define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U) 5998 #define EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) 5999 #define EMAC_DMA_DEBUG_STATUS0_RPS0_WIDTH (4U) 6000 #define EMAC_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK) 6001 6002 #define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U) 6003 #define EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) 6004 #define EMAC_DMA_DEBUG_STATUS0_TPS0_WIDTH (4U) 6005 #define EMAC_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK) 6006 6007 #define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U) 6008 #define EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U) 6009 #define EMAC_DMA_DEBUG_STATUS0_RPS1_WIDTH (4U) 6010 #define EMAC_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK) 6011 6012 #define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U) 6013 #define EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U) 6014 #define EMAC_DMA_DEBUG_STATUS0_TPS1_WIDTH (4U) 6015 #define EMAC_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK) 6016 /*! @} */ 6017 6018 /*! @name DMA_TBS_CTRL - DMA TBS Control */ 6019 /*! @{ */ 6020 6021 #define EMAC_DMA_TBS_CTRL_FTOV_MASK (0x1U) 6022 #define EMAC_DMA_TBS_CTRL_FTOV_SHIFT (0U) 6023 #define EMAC_DMA_TBS_CTRL_FTOV_WIDTH (1U) 6024 #define EMAC_DMA_TBS_CTRL_FTOV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FTOV_SHIFT)) & EMAC_DMA_TBS_CTRL_FTOV_MASK) 6025 6026 #define EMAC_DMA_TBS_CTRL_FGOS_MASK (0x70U) 6027 #define EMAC_DMA_TBS_CTRL_FGOS_SHIFT (4U) 6028 #define EMAC_DMA_TBS_CTRL_FGOS_WIDTH (3U) 6029 #define EMAC_DMA_TBS_CTRL_FGOS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FGOS_SHIFT)) & EMAC_DMA_TBS_CTRL_FGOS_MASK) 6030 6031 #define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF00U) 6032 #define EMAC_DMA_TBS_CTRL_FTOS_SHIFT (8U) 6033 #define EMAC_DMA_TBS_CTRL_FTOS_WIDTH (24U) 6034 #define EMAC_DMA_TBS_CTRL_FTOS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_TBS_CTRL_FTOS_SHIFT)) & EMAC_DMA_TBS_CTRL_FTOS_MASK) 6035 /*! @} */ 6036 6037 /*! @name DMA_SAFETY_INTERRUPT_STATUS - DMA Safety Interrupt Status */ 6038 /*! @{ */ 6039 6040 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK (0x1U) 6041 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT (0U) 6042 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_WIDTH (1U) 6043 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK) 6044 6045 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK (0x2U) 6046 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT (1U) 6047 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_WIDTH (1U) 6048 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK) 6049 6050 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK (0x10000000U) 6051 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT (28U) 6052 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_WIDTH (1U) 6053 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK) 6054 6055 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK (0x20000000U) 6056 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT (29U) 6057 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_WIDTH (1U) 6058 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK) 6059 6060 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK (0x80000000U) 6061 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT (31U) 6062 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_WIDTH (1U) 6063 #define EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT)) & EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK) 6064 /*! @} */ 6065 6066 /*! @name DMA_CH0_CONTROL - DMA Channel 0 Control */ 6067 /*! @{ */ 6068 6069 #define EMAC_DMA_CH0_CONTROL_PBLx8_MASK (0x10000U) 6070 #define EMAC_DMA_CH0_CONTROL_PBLx8_SHIFT (16U) 6071 #define EMAC_DMA_CH0_CONTROL_PBLx8_WIDTH (1U) 6072 #define EMAC_DMA_CH0_CONTROL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CONTROL_PBLx8_SHIFT)) & EMAC_DMA_CH0_CONTROL_PBLx8_MASK) 6073 6074 #define EMAC_DMA_CH0_CONTROL_DSL_MASK (0x1C0000U) 6075 #define EMAC_DMA_CH0_CONTROL_DSL_SHIFT (18U) 6076 #define EMAC_DMA_CH0_CONTROL_DSL_WIDTH (3U) 6077 #define EMAC_DMA_CH0_CONTROL_DSL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CONTROL_DSL_SHIFT)) & EMAC_DMA_CH0_CONTROL_DSL_MASK) 6078 /*! @} */ 6079 6080 /*! @name DMA_CH0_TX_CONTROL - DMA Channel Tx Control */ 6081 /*! @{ */ 6082 6083 #define EMAC_DMA_CH0_TX_CONTROL_ST_MASK (0x1U) 6084 #define EMAC_DMA_CH0_TX_CONTROL_ST_SHIFT (0U) 6085 #define EMAC_DMA_CH0_TX_CONTROL_ST_WIDTH (1U) 6086 #define EMAC_DMA_CH0_TX_CONTROL_ST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_ST_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_ST_MASK) 6087 6088 #define EMAC_DMA_CH0_TX_CONTROL_TCW_MASK (0xEU) 6089 #define EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT (1U) 6090 #define EMAC_DMA_CH0_TX_CONTROL_TCW_WIDTH (3U) 6091 #define EMAC_DMA_CH0_TX_CONTROL_TCW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_TCW_MASK) 6092 6093 #define EMAC_DMA_CH0_TX_CONTROL_OSF_MASK (0x10U) 6094 #define EMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT (4U) 6095 #define EMAC_DMA_CH0_TX_CONTROL_OSF_WIDTH (1U) 6096 #define EMAC_DMA_CH0_TX_CONTROL_OSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_OSF_MASK) 6097 6098 #define EMAC_DMA_CH0_TX_CONTROL_TxPBL_MASK (0x3F0000U) 6099 #define EMAC_DMA_CH0_TX_CONTROL_TxPBL_SHIFT (16U) 6100 #define EMAC_DMA_CH0_TX_CONTROL_TxPBL_WIDTH (6U) 6101 #define EMAC_DMA_CH0_TX_CONTROL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_TxPBL_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_TxPBL_MASK) 6102 6103 #define EMAC_DMA_CH0_TX_CONTROL_ETIC_MASK (0x400000U) 6104 #define EMAC_DMA_CH0_TX_CONTROL_ETIC_SHIFT (22U) 6105 #define EMAC_DMA_CH0_TX_CONTROL_ETIC_WIDTH (1U) 6106 #define EMAC_DMA_CH0_TX_CONTROL_ETIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_ETIC_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_ETIC_MASK) 6107 6108 #define EMAC_DMA_CH0_TX_CONTROL_EDSE_MASK (0x10000000U) 6109 #define EMAC_DMA_CH0_TX_CONTROL_EDSE_SHIFT (28U) 6110 #define EMAC_DMA_CH0_TX_CONTROL_EDSE_WIDTH (1U) 6111 #define EMAC_DMA_CH0_TX_CONTROL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TX_CONTROL_EDSE_SHIFT)) & EMAC_DMA_CH0_TX_CONTROL_EDSE_MASK) 6112 /*! @} */ 6113 6114 /*! @name DMA_CH0_RX_CONTROL - DMA Channel Rx Control */ 6115 /*! @{ */ 6116 6117 #define EMAC_DMA_CH0_RX_CONTROL_SR_MASK (0x1U) 6118 #define EMAC_DMA_CH0_RX_CONTROL_SR_SHIFT (0U) 6119 #define EMAC_DMA_CH0_RX_CONTROL_SR_WIDTH (1U) 6120 #define EMAC_DMA_CH0_RX_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_SR_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_SR_MASK) 6121 6122 #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_MASK (0x6U) 6123 #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_SHIFT (1U) 6124 #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_WIDTH (2U) 6125 #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_MASK) 6126 6127 #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_MASK (0x7FF8U) 6128 #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_SHIFT (3U) 6129 #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_WIDTH (12U) 6130 #define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_MASK) 6131 6132 #define EMAC_DMA_CH0_RX_CONTROL_RxPBL_MASK (0x3F0000U) 6133 #define EMAC_DMA_CH0_RX_CONTROL_RxPBL_SHIFT (16U) 6134 #define EMAC_DMA_CH0_RX_CONTROL_RxPBL_WIDTH (6U) 6135 #define EMAC_DMA_CH0_RX_CONTROL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_RxPBL_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_RxPBL_MASK) 6136 6137 #define EMAC_DMA_CH0_RX_CONTROL_ERIC_MASK (0x400000U) 6138 #define EMAC_DMA_CH0_RX_CONTROL_ERIC_SHIFT (22U) 6139 #define EMAC_DMA_CH0_RX_CONTROL_ERIC_WIDTH (1U) 6140 #define EMAC_DMA_CH0_RX_CONTROL_ERIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_ERIC_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_ERIC_MASK) 6141 6142 #define EMAC_DMA_CH0_RX_CONTROL_RPF_MASK (0x80000000U) 6143 #define EMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT (31U) 6144 #define EMAC_DMA_CH0_RX_CONTROL_RPF_WIDTH (1U) 6145 #define EMAC_DMA_CH0_RX_CONTROL_RPF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT)) & EMAC_DMA_CH0_RX_CONTROL_RPF_MASK) 6146 /*! @} */ 6147 6148 /*! @name DMA_CH0_TXDESC_LIST_ADDRESS - DMA Channel 0 Tx Descriptor List Address */ 6149 /*! @{ */ 6150 6151 #define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0xFFFFFFFCU) 6152 #define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2U) 6153 #define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_WIDTH (30U) 6154 #define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)) & EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK) 6155 /*! @} */ 6156 6157 /*! @name DMA_CH0_RXDESC_LIST_ADDRESS - DMA Channel 0 Rx Descriptor List Address */ 6158 /*! @{ */ 6159 6160 #define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0xFFFFFFFCU) 6161 #define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2U) 6162 #define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_WIDTH (30U) 6163 #define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)) & EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK) 6164 /*! @} */ 6165 6166 /*! @name DMA_CH0_TXDESC_TAIL_POINTER - DMA Channel 0 Tx Descriptor Tail Pointer */ 6167 /*! @{ */ 6168 6169 #define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0xFFFFFFFCU) 6170 #define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT (2U) 6171 #define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_WIDTH (30U) 6172 #define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT)) & EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK) 6173 /*! @} */ 6174 6175 /*! @name DMA_CH0_RXDESC_TAIL_POINTER - DMA Channeli 0 Rx Descriptor List Pointer */ 6176 /*! @{ */ 6177 6178 #define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK (0xFFFFFFFCU) 6179 #define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT (2U) 6180 #define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_WIDTH (30U) 6181 #define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT)) & EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK) 6182 /*! @} */ 6183 6184 /*! @name DMA_CH0_TXDESC_RING_LENGTH - DMA Channel 0 Tx Descriptor Ring Length */ 6185 /*! @{ */ 6186 6187 #define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) 6188 #define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) 6189 #define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_WIDTH (10U) 6190 #define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT)) & EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK) 6191 /*! @} */ 6192 6193 /*! @name DMA_CH0_RXDESC_RING_LENGTH - DMA Channel 0 Rx Descriptor Ring Length */ 6194 /*! @{ */ 6195 6196 #define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) 6197 #define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) 6198 #define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_WIDTH (10U) 6199 #define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT)) & EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK) 6200 /*! @} */ 6201 6202 /*! @name DMA_CH0_INTERRUPT_ENABLE - DMA Channel 0 Interrupt Enable */ 6203 /*! @{ */ 6204 6205 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK (0x1U) 6206 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT (0U) 6207 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_WIDTH (1U) 6208 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK) 6209 6210 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK (0x2U) 6211 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT (1U) 6212 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_WIDTH (1U) 6213 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK) 6214 6215 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK (0x4U) 6216 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT (2U) 6217 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_WIDTH (1U) 6218 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK) 6219 6220 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK (0x40U) 6221 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT (6U) 6222 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_WIDTH (1U) 6223 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK) 6224 6225 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK (0x80U) 6226 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT (7U) 6227 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_WIDTH (1U) 6228 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK) 6229 6230 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK (0x100U) 6231 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT (8U) 6232 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_WIDTH (1U) 6233 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK) 6234 6235 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK (0x200U) 6236 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT (9U) 6237 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_WIDTH (1U) 6238 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK) 6239 6240 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK (0x400U) 6241 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT (10U) 6242 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_WIDTH (1U) 6243 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK) 6244 6245 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK (0x800U) 6246 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT (11U) 6247 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_WIDTH (1U) 6248 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK) 6249 6250 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK (0x1000U) 6251 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT (12U) 6252 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_WIDTH (1U) 6253 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK) 6254 6255 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK (0x2000U) 6256 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT (13U) 6257 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_WIDTH (1U) 6258 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK) 6259 6260 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK (0x4000U) 6261 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT (14U) 6262 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_WIDTH (1U) 6263 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK) 6264 6265 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK (0x8000U) 6266 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT (15U) 6267 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_WIDTH (1U) 6268 #define EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT)) & EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK) 6269 /*! @} */ 6270 6271 /*! @name DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER - DMA Channel 0 Rx Interrupt Watchdog Timer */ 6272 /*! @{ */ 6273 6274 #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFFU) 6275 #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0U) 6276 #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH (8U) 6277 #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) 6278 6279 #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x30000U) 6280 #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16U) 6281 #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH (2U) 6282 #define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT)) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) 6283 /*! @} */ 6284 6285 /*! @name DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS - DMA Channel 0 Slot Function Control Status */ 6286 /*! @{ */ 6287 6288 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK (0x1U) 6289 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT (0U) 6290 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH (1U) 6291 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT)) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK) 6292 6293 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK (0x2U) 6294 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT (1U) 6295 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH (1U) 6296 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT)) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK) 6297 6298 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF0U) 6299 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4U) 6300 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH (12U) 6301 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) 6302 6303 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF0000U) 6304 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16U) 6305 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH (4U) 6306 #define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) 6307 /*! @} */ 6308 6309 /*! @name DMA_CH0_CURRENT_APP_TXDESC - DMA Channel 0 Current Application Transmit Descriptor */ 6310 /*! @{ */ 6311 6312 #define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) 6313 #define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0U) 6314 #define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH (32U) 6315 #define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)) & EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) 6316 /*! @} */ 6317 6318 /*! @name DMA_CH0_CURRENT_APP_RXDESC - DMA Channel 0 Current Application Receive Descriptor */ 6319 /*! @{ */ 6320 6321 #define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) 6322 #define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0U) 6323 #define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH (32U) 6324 #define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)) & EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) 6325 /*! @} */ 6326 6327 /*! @name DMA_CH0_CURRENT_APP_TXBUFFER - DMA Channel 0 Current Application Transmit Descriptor */ 6328 /*! @{ */ 6329 6330 #define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFFU) 6331 #define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0U) 6332 #define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH (32U) 6333 #define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)) & EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) 6334 /*! @} */ 6335 6336 /*! @name DMA_CH0_CURRENT_APP_RXBUFFER - DMA Channel 0 Current Application Receive Buffer */ 6337 /*! @{ */ 6338 6339 #define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFFU) 6340 #define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0U) 6341 #define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH (32U) 6342 #define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)) & EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) 6343 /*! @} */ 6344 6345 /*! @name DMA_CH0_STATUS - DMA Channel 0 Status */ 6346 /*! @{ */ 6347 6348 #define EMAC_DMA_CH0_STATUS_TI_MASK (0x1U) 6349 #define EMAC_DMA_CH0_STATUS_TI_SHIFT (0U) 6350 #define EMAC_DMA_CH0_STATUS_TI_WIDTH (1U) 6351 #define EMAC_DMA_CH0_STATUS_TI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_TI_SHIFT)) & EMAC_DMA_CH0_STATUS_TI_MASK) 6352 6353 #define EMAC_DMA_CH0_STATUS_TPS_MASK (0x2U) 6354 #define EMAC_DMA_CH0_STATUS_TPS_SHIFT (1U) 6355 #define EMAC_DMA_CH0_STATUS_TPS_WIDTH (1U) 6356 #define EMAC_DMA_CH0_STATUS_TPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_TPS_SHIFT)) & EMAC_DMA_CH0_STATUS_TPS_MASK) 6357 6358 #define EMAC_DMA_CH0_STATUS_TBU_MASK (0x4U) 6359 #define EMAC_DMA_CH0_STATUS_TBU_SHIFT (2U) 6360 #define EMAC_DMA_CH0_STATUS_TBU_WIDTH (1U) 6361 #define EMAC_DMA_CH0_STATUS_TBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_TBU_SHIFT)) & EMAC_DMA_CH0_STATUS_TBU_MASK) 6362 6363 #define EMAC_DMA_CH0_STATUS_RI_MASK (0x40U) 6364 #define EMAC_DMA_CH0_STATUS_RI_SHIFT (6U) 6365 #define EMAC_DMA_CH0_STATUS_RI_WIDTH (1U) 6366 #define EMAC_DMA_CH0_STATUS_RI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_RI_SHIFT)) & EMAC_DMA_CH0_STATUS_RI_MASK) 6367 6368 #define EMAC_DMA_CH0_STATUS_RBU_MASK (0x80U) 6369 #define EMAC_DMA_CH0_STATUS_RBU_SHIFT (7U) 6370 #define EMAC_DMA_CH0_STATUS_RBU_WIDTH (1U) 6371 #define EMAC_DMA_CH0_STATUS_RBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_RBU_SHIFT)) & EMAC_DMA_CH0_STATUS_RBU_MASK) 6372 6373 #define EMAC_DMA_CH0_STATUS_RPS_MASK (0x100U) 6374 #define EMAC_DMA_CH0_STATUS_RPS_SHIFT (8U) 6375 #define EMAC_DMA_CH0_STATUS_RPS_WIDTH (1U) 6376 #define EMAC_DMA_CH0_STATUS_RPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_RPS_SHIFT)) & EMAC_DMA_CH0_STATUS_RPS_MASK) 6377 6378 #define EMAC_DMA_CH0_STATUS_RWT_MASK (0x200U) 6379 #define EMAC_DMA_CH0_STATUS_RWT_SHIFT (9U) 6380 #define EMAC_DMA_CH0_STATUS_RWT_WIDTH (1U) 6381 #define EMAC_DMA_CH0_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_RWT_SHIFT)) & EMAC_DMA_CH0_STATUS_RWT_MASK) 6382 6383 #define EMAC_DMA_CH0_STATUS_ETI_MASK (0x400U) 6384 #define EMAC_DMA_CH0_STATUS_ETI_SHIFT (10U) 6385 #define EMAC_DMA_CH0_STATUS_ETI_WIDTH (1U) 6386 #define EMAC_DMA_CH0_STATUS_ETI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_ETI_SHIFT)) & EMAC_DMA_CH0_STATUS_ETI_MASK) 6387 6388 #define EMAC_DMA_CH0_STATUS_ERI_MASK (0x800U) 6389 #define EMAC_DMA_CH0_STATUS_ERI_SHIFT (11U) 6390 #define EMAC_DMA_CH0_STATUS_ERI_WIDTH (1U) 6391 #define EMAC_DMA_CH0_STATUS_ERI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_ERI_SHIFT)) & EMAC_DMA_CH0_STATUS_ERI_MASK) 6392 6393 #define EMAC_DMA_CH0_STATUS_FBE_MASK (0x1000U) 6394 #define EMAC_DMA_CH0_STATUS_FBE_SHIFT (12U) 6395 #define EMAC_DMA_CH0_STATUS_FBE_WIDTH (1U) 6396 #define EMAC_DMA_CH0_STATUS_FBE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_FBE_SHIFT)) & EMAC_DMA_CH0_STATUS_FBE_MASK) 6397 6398 #define EMAC_DMA_CH0_STATUS_CDE_MASK (0x2000U) 6399 #define EMAC_DMA_CH0_STATUS_CDE_SHIFT (13U) 6400 #define EMAC_DMA_CH0_STATUS_CDE_WIDTH (1U) 6401 #define EMAC_DMA_CH0_STATUS_CDE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_CDE_SHIFT)) & EMAC_DMA_CH0_STATUS_CDE_MASK) 6402 6403 #define EMAC_DMA_CH0_STATUS_AIS_MASK (0x4000U) 6404 #define EMAC_DMA_CH0_STATUS_AIS_SHIFT (14U) 6405 #define EMAC_DMA_CH0_STATUS_AIS_WIDTH (1U) 6406 #define EMAC_DMA_CH0_STATUS_AIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_AIS_SHIFT)) & EMAC_DMA_CH0_STATUS_AIS_MASK) 6407 6408 #define EMAC_DMA_CH0_STATUS_NIS_MASK (0x8000U) 6409 #define EMAC_DMA_CH0_STATUS_NIS_SHIFT (15U) 6410 #define EMAC_DMA_CH0_STATUS_NIS_WIDTH (1U) 6411 #define EMAC_DMA_CH0_STATUS_NIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_NIS_SHIFT)) & EMAC_DMA_CH0_STATUS_NIS_MASK) 6412 6413 #define EMAC_DMA_CH0_STATUS_TEB_MASK (0x70000U) 6414 #define EMAC_DMA_CH0_STATUS_TEB_SHIFT (16U) 6415 #define EMAC_DMA_CH0_STATUS_TEB_WIDTH (3U) 6416 #define EMAC_DMA_CH0_STATUS_TEB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_TEB_SHIFT)) & EMAC_DMA_CH0_STATUS_TEB_MASK) 6417 6418 #define EMAC_DMA_CH0_STATUS_REB_MASK (0x380000U) 6419 #define EMAC_DMA_CH0_STATUS_REB_SHIFT (19U) 6420 #define EMAC_DMA_CH0_STATUS_REB_WIDTH (3U) 6421 #define EMAC_DMA_CH0_STATUS_REB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_STATUS_REB_SHIFT)) & EMAC_DMA_CH0_STATUS_REB_MASK) 6422 /*! @} */ 6423 6424 /*! @name DMA_CH0_MISS_FRAME_CNT - DMA Channel 0 Miss Frame Counter */ 6425 /*! @{ */ 6426 6427 #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7FFU) 6428 #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0U) 6429 #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_WIDTH (11U) 6430 #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT)) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK) 6431 6432 #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_MASK (0x8000U) 6433 #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_SHIFT (15U) 6434 #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_WIDTH (1U) 6435 #define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_SHIFT)) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_MASK) 6436 /*! @} */ 6437 6438 /*! @name DMA_CH0_RXP_ACCEPT_CNT - DMA Channel 0 Rx Parser Accept Count */ 6439 /*! @{ */ 6440 6441 #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU) 6442 #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U) 6443 #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_WIDTH (31U) 6444 #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK) 6445 6446 #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U) 6447 #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) 6448 #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_WIDTH (1U) 6449 #define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_MASK) 6450 /*! @} */ 6451 6452 /*! @name DMA_CH0_RX_ERI_CNT - DMA Channel 0 Rx ERI Count */ 6453 /*! @{ */ 6454 6455 #define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0xFFFU) 6456 #define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT (0U) 6457 #define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_WIDTH (12U) 6458 #define EMAC_DMA_CH0_RX_ERI_CNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT)) & EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK) 6459 /*! @} */ 6460 6461 /*! @name DMA_CH1_CONTROL - DMA Channel 1 Control */ 6462 /*! @{ */ 6463 6464 #define EMAC_DMA_CH1_CONTROL_PBLx8_MASK (0x10000U) 6465 #define EMAC_DMA_CH1_CONTROL_PBLx8_SHIFT (16U) 6466 #define EMAC_DMA_CH1_CONTROL_PBLx8_WIDTH (1U) 6467 #define EMAC_DMA_CH1_CONTROL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CONTROL_PBLx8_SHIFT)) & EMAC_DMA_CH1_CONTROL_PBLx8_MASK) 6468 6469 #define EMAC_DMA_CH1_CONTROL_DSL_MASK (0x1C0000U) 6470 #define EMAC_DMA_CH1_CONTROL_DSL_SHIFT (18U) 6471 #define EMAC_DMA_CH1_CONTROL_DSL_WIDTH (3U) 6472 #define EMAC_DMA_CH1_CONTROL_DSL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CONTROL_DSL_SHIFT)) & EMAC_DMA_CH1_CONTROL_DSL_MASK) 6473 /*! @} */ 6474 6475 /*! @name DMA_CH1_TX_CONTROL - DMA Channel 1 Tx Control */ 6476 /*! @{ */ 6477 6478 #define EMAC_DMA_CH1_TX_CONTROL_ST_MASK (0x1U) 6479 #define EMAC_DMA_CH1_TX_CONTROL_ST_SHIFT (0U) 6480 #define EMAC_DMA_CH1_TX_CONTROL_ST_WIDTH (1U) 6481 #define EMAC_DMA_CH1_TX_CONTROL_ST(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_ST_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_ST_MASK) 6482 6483 #define EMAC_DMA_CH1_TX_CONTROL_TCW_MASK (0xEU) 6484 #define EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT (1U) 6485 #define EMAC_DMA_CH1_TX_CONTROL_TCW_WIDTH (3U) 6486 #define EMAC_DMA_CH1_TX_CONTROL_TCW(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_TCW_MASK) 6487 6488 #define EMAC_DMA_CH1_TX_CONTROL_OSF_MASK (0x10U) 6489 #define EMAC_DMA_CH1_TX_CONTROL_OSF_SHIFT (4U) 6490 #define EMAC_DMA_CH1_TX_CONTROL_OSF_WIDTH (1U) 6491 #define EMAC_DMA_CH1_TX_CONTROL_OSF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_OSF_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_OSF_MASK) 6492 6493 #define EMAC_DMA_CH1_TX_CONTROL_TxPBL_MASK (0x3F0000U) 6494 #define EMAC_DMA_CH1_TX_CONTROL_TxPBL_SHIFT (16U) 6495 #define EMAC_DMA_CH1_TX_CONTROL_TxPBL_WIDTH (6U) 6496 #define EMAC_DMA_CH1_TX_CONTROL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_TxPBL_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_TxPBL_MASK) 6497 6498 #define EMAC_DMA_CH1_TX_CONTROL_ETIC_MASK (0x400000U) 6499 #define EMAC_DMA_CH1_TX_CONTROL_ETIC_SHIFT (22U) 6500 #define EMAC_DMA_CH1_TX_CONTROL_ETIC_WIDTH (1U) 6501 #define EMAC_DMA_CH1_TX_CONTROL_ETIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_ETIC_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_ETIC_MASK) 6502 6503 #define EMAC_DMA_CH1_TX_CONTROL_EDSE_MASK (0x10000000U) 6504 #define EMAC_DMA_CH1_TX_CONTROL_EDSE_SHIFT (28U) 6505 #define EMAC_DMA_CH1_TX_CONTROL_EDSE_WIDTH (1U) 6506 #define EMAC_DMA_CH1_TX_CONTROL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TX_CONTROL_EDSE_SHIFT)) & EMAC_DMA_CH1_TX_CONTROL_EDSE_MASK) 6507 /*! @} */ 6508 6509 /*! @name DMA_CH1_RX_CONTROL - DMA Channel 1 Rx Control */ 6510 /*! @{ */ 6511 6512 #define EMAC_DMA_CH1_RX_CONTROL_SR_MASK (0x1U) 6513 #define EMAC_DMA_CH1_RX_CONTROL_SR_SHIFT (0U) 6514 #define EMAC_DMA_CH1_RX_CONTROL_SR_WIDTH (1U) 6515 #define EMAC_DMA_CH1_RX_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_SR_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_SR_MASK) 6516 6517 #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_MASK (0x6U) 6518 #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_SHIFT (1U) 6519 #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_WIDTH (2U) 6520 #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_MASK) 6521 6522 #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_MASK (0x7FF8U) 6523 #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_SHIFT (3U) 6524 #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_WIDTH (12U) 6525 #define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_MASK) 6526 6527 #define EMAC_DMA_CH1_RX_CONTROL_RxPBL_MASK (0x3F0000U) 6528 #define EMAC_DMA_CH1_RX_CONTROL_RxPBL_SHIFT (16U) 6529 #define EMAC_DMA_CH1_RX_CONTROL_RxPBL_WIDTH (6U) 6530 #define EMAC_DMA_CH1_RX_CONTROL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_RxPBL_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_RxPBL_MASK) 6531 6532 #define EMAC_DMA_CH1_RX_CONTROL_ERIC_MASK (0x400000U) 6533 #define EMAC_DMA_CH1_RX_CONTROL_ERIC_SHIFT (22U) 6534 #define EMAC_DMA_CH1_RX_CONTROL_ERIC_WIDTH (1U) 6535 #define EMAC_DMA_CH1_RX_CONTROL_ERIC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_ERIC_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_ERIC_MASK) 6536 6537 #define EMAC_DMA_CH1_RX_CONTROL_RPF_MASK (0x80000000U) 6538 #define EMAC_DMA_CH1_RX_CONTROL_RPF_SHIFT (31U) 6539 #define EMAC_DMA_CH1_RX_CONTROL_RPF_WIDTH (1U) 6540 #define EMAC_DMA_CH1_RX_CONTROL_RPF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_CONTROL_RPF_SHIFT)) & EMAC_DMA_CH1_RX_CONTROL_RPF_MASK) 6541 /*! @} */ 6542 6543 /*! @name DMA_CH1_TXDESC_LIST_ADDRESS - DMA Channel 1 Tx Descriptor List Address */ 6544 /*! @{ */ 6545 6546 #define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK (0xFFFFFFFCU) 6547 #define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2U) 6548 #define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_WIDTH (30U) 6549 #define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)) & EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK) 6550 /*! @} */ 6551 6552 /*! @name DMA_CH1_RXDESC_LIST_ADDRESS - DMA Channel 1 Rx Descriptor List Address */ 6553 /*! @{ */ 6554 6555 #define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK (0xFFFFFFFCU) 6556 #define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2U) 6557 #define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_WIDTH (30U) 6558 #define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)) & EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK) 6559 /*! @} */ 6560 6561 /*! @name DMA_CH1_TXDESC_TAIL_POINTER - DMA Channel 1 Tx Descriptor Tail Pointer */ 6562 /*! @{ */ 6563 6564 #define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK (0xFFFFFFFCU) 6565 #define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT (2U) 6566 #define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_WIDTH (30U) 6567 #define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT)) & EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK) 6568 /*! @} */ 6569 6570 /*! @name DMA_CH1_RXDESC_TAIL_POINTER - DMA Channel 1 Rx Descriptor Tail Pointer */ 6571 /*! @{ */ 6572 6573 #define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK (0xFFFFFFFCU) 6574 #define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT (2U) 6575 #define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_WIDTH (30U) 6576 #define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT)) & EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK) 6577 /*! @} */ 6578 6579 /*! @name DMA_CH1_TXDESC_RING_LENGTH - DMA Channel 1 Tx Descriptor Ring Length */ 6580 /*! @{ */ 6581 6582 #define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) 6583 #define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) 6584 #define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_WIDTH (10U) 6585 #define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT)) & EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK) 6586 /*! @} */ 6587 6588 /*! @name DMA_CH1_RXDESC_RING_LENGTH - DMA Channel 1 Rx Descriptor Ring Length */ 6589 /*! @{ */ 6590 6591 #define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) 6592 #define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) 6593 #define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_WIDTH (10U) 6594 #define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT)) & EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK) 6595 /*! @} */ 6596 6597 /*! @name DMA_CH1_INTERRUPT_ENABLE - DMA Channel 1 Interrupt Enable */ 6598 /*! @{ */ 6599 6600 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_MASK (0x1U) 6601 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_SHIFT (0U) 6602 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_WIDTH (1U) 6603 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_MASK) 6604 6605 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_MASK (0x2U) 6606 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_SHIFT (1U) 6607 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_WIDTH (1U) 6608 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_MASK) 6609 6610 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_MASK (0x4U) 6611 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_SHIFT (2U) 6612 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_WIDTH (1U) 6613 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_MASK) 6614 6615 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_MASK (0x40U) 6616 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_SHIFT (6U) 6617 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_WIDTH (1U) 6618 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_MASK) 6619 6620 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_MASK (0x80U) 6621 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_SHIFT (7U) 6622 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_WIDTH (1U) 6623 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_MASK) 6624 6625 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_MASK (0x100U) 6626 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_SHIFT (8U) 6627 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_WIDTH (1U) 6628 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_MASK) 6629 6630 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_MASK (0x200U) 6631 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_SHIFT (9U) 6632 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_WIDTH (1U) 6633 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_MASK) 6634 6635 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_MASK (0x400U) 6636 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_SHIFT (10U) 6637 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_WIDTH (1U) 6638 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_MASK) 6639 6640 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_MASK (0x800U) 6641 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_SHIFT (11U) 6642 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_WIDTH (1U) 6643 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_MASK) 6644 6645 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_MASK (0x1000U) 6646 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_SHIFT (12U) 6647 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_WIDTH (1U) 6648 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_MASK) 6649 6650 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_MASK (0x2000U) 6651 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_SHIFT (13U) 6652 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_WIDTH (1U) 6653 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_MASK) 6654 6655 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_MASK (0x4000U) 6656 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_SHIFT (14U) 6657 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_WIDTH (1U) 6658 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_MASK) 6659 6660 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_MASK (0x8000U) 6661 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_SHIFT (15U) 6662 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_WIDTH (1U) 6663 #define EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_SHIFT)) & EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_MASK) 6664 /*! @} */ 6665 6666 /*! @name DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER - DMA Channel 1 Rx Interrupt Watchdog Timer */ 6667 /*! @{ */ 6668 6669 #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFFU) 6670 #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0U) 6671 #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH (8U) 6672 #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK) 6673 6674 #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x30000U) 6675 #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16U) 6676 #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH (2U) 6677 #define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT)) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK) 6678 /*! @} */ 6679 6680 /*! @name DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS - DMA Channel 1 Slot Function Control Status */ 6681 /*! @{ */ 6682 6683 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK (0x1U) 6684 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT (0U) 6685 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH (1U) 6686 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT)) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK) 6687 6688 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK (0x2U) 6689 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT (1U) 6690 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH (1U) 6691 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT)) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK) 6692 6693 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF0U) 6694 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4U) 6695 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH (12U) 6696 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK) 6697 6698 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF0000U) 6699 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16U) 6700 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH (4U) 6701 #define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK) 6702 /*! @} */ 6703 6704 /*! @name DMA_CH1_CURRENT_APP_TXDESC - DMA Channel 1 Current Application Transmit Descriptor */ 6705 /*! @{ */ 6706 6707 #define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) 6708 #define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0U) 6709 #define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH (32U) 6710 #define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)) & EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK) 6711 /*! @} */ 6712 6713 /*! @name DMA_CH1_CURRENT_APP_RXDESC - DMA Channel 1 Current Application Receive Descriptor */ 6714 /*! @{ */ 6715 6716 #define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) 6717 #define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0U) 6718 #define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH (32U) 6719 #define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)) & EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK) 6720 /*! @} */ 6721 6722 /*! @name DMA_CH1_CURRENT_APP_TXBUFFER - DMA Channel 1 Current Application Transmit Buffer */ 6723 /*! @{ */ 6724 6725 #define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFFU) 6726 #define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0U) 6727 #define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH (32U) 6728 #define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)) & EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK) 6729 /*! @} */ 6730 6731 /*! @name DMA_CH1_CURRENT_APP_RXBUFFER - DMA Channel 1 Current Application Receive Buffer */ 6732 /*! @{ */ 6733 6734 #define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFFU) 6735 #define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0U) 6736 #define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH (32U) 6737 #define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)) & EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK) 6738 /*! @} */ 6739 6740 /*! @name DMA_CH1_STATUS - DMA Channel 1 Status */ 6741 /*! @{ */ 6742 6743 #define EMAC_DMA_CH1_STATUS_TI_MASK (0x1U) 6744 #define EMAC_DMA_CH1_STATUS_TI_SHIFT (0U) 6745 #define EMAC_DMA_CH1_STATUS_TI_WIDTH (1U) 6746 #define EMAC_DMA_CH1_STATUS_TI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_TI_SHIFT)) & EMAC_DMA_CH1_STATUS_TI_MASK) 6747 6748 #define EMAC_DMA_CH1_STATUS_TPS_MASK (0x2U) 6749 #define EMAC_DMA_CH1_STATUS_TPS_SHIFT (1U) 6750 #define EMAC_DMA_CH1_STATUS_TPS_WIDTH (1U) 6751 #define EMAC_DMA_CH1_STATUS_TPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_TPS_SHIFT)) & EMAC_DMA_CH1_STATUS_TPS_MASK) 6752 6753 #define EMAC_DMA_CH1_STATUS_TBU_MASK (0x4U) 6754 #define EMAC_DMA_CH1_STATUS_TBU_SHIFT (2U) 6755 #define EMAC_DMA_CH1_STATUS_TBU_WIDTH (1U) 6756 #define EMAC_DMA_CH1_STATUS_TBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_TBU_SHIFT)) & EMAC_DMA_CH1_STATUS_TBU_MASK) 6757 6758 #define EMAC_DMA_CH1_STATUS_RI_MASK (0x40U) 6759 #define EMAC_DMA_CH1_STATUS_RI_SHIFT (6U) 6760 #define EMAC_DMA_CH1_STATUS_RI_WIDTH (1U) 6761 #define EMAC_DMA_CH1_STATUS_RI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_RI_SHIFT)) & EMAC_DMA_CH1_STATUS_RI_MASK) 6762 6763 #define EMAC_DMA_CH1_STATUS_RBU_MASK (0x80U) 6764 #define EMAC_DMA_CH1_STATUS_RBU_SHIFT (7U) 6765 #define EMAC_DMA_CH1_STATUS_RBU_WIDTH (1U) 6766 #define EMAC_DMA_CH1_STATUS_RBU(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_RBU_SHIFT)) & EMAC_DMA_CH1_STATUS_RBU_MASK) 6767 6768 #define EMAC_DMA_CH1_STATUS_RPS_MASK (0x100U) 6769 #define EMAC_DMA_CH1_STATUS_RPS_SHIFT (8U) 6770 #define EMAC_DMA_CH1_STATUS_RPS_WIDTH (1U) 6771 #define EMAC_DMA_CH1_STATUS_RPS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_RPS_SHIFT)) & EMAC_DMA_CH1_STATUS_RPS_MASK) 6772 6773 #define EMAC_DMA_CH1_STATUS_RWT_MASK (0x200U) 6774 #define EMAC_DMA_CH1_STATUS_RWT_SHIFT (9U) 6775 #define EMAC_DMA_CH1_STATUS_RWT_WIDTH (1U) 6776 #define EMAC_DMA_CH1_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_RWT_SHIFT)) & EMAC_DMA_CH1_STATUS_RWT_MASK) 6777 6778 #define EMAC_DMA_CH1_STATUS_ETI_MASK (0x400U) 6779 #define EMAC_DMA_CH1_STATUS_ETI_SHIFT (10U) 6780 #define EMAC_DMA_CH1_STATUS_ETI_WIDTH (1U) 6781 #define EMAC_DMA_CH1_STATUS_ETI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_ETI_SHIFT)) & EMAC_DMA_CH1_STATUS_ETI_MASK) 6782 6783 #define EMAC_DMA_CH1_STATUS_ERI_MASK (0x800U) 6784 #define EMAC_DMA_CH1_STATUS_ERI_SHIFT (11U) 6785 #define EMAC_DMA_CH1_STATUS_ERI_WIDTH (1U) 6786 #define EMAC_DMA_CH1_STATUS_ERI(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_ERI_SHIFT)) & EMAC_DMA_CH1_STATUS_ERI_MASK) 6787 6788 #define EMAC_DMA_CH1_STATUS_FBE_MASK (0x1000U) 6789 #define EMAC_DMA_CH1_STATUS_FBE_SHIFT (12U) 6790 #define EMAC_DMA_CH1_STATUS_FBE_WIDTH (1U) 6791 #define EMAC_DMA_CH1_STATUS_FBE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_FBE_SHIFT)) & EMAC_DMA_CH1_STATUS_FBE_MASK) 6792 6793 #define EMAC_DMA_CH1_STATUS_CDE_MASK (0x2000U) 6794 #define EMAC_DMA_CH1_STATUS_CDE_SHIFT (13U) 6795 #define EMAC_DMA_CH1_STATUS_CDE_WIDTH (1U) 6796 #define EMAC_DMA_CH1_STATUS_CDE(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_CDE_SHIFT)) & EMAC_DMA_CH1_STATUS_CDE_MASK) 6797 6798 #define EMAC_DMA_CH1_STATUS_AIS_MASK (0x4000U) 6799 #define EMAC_DMA_CH1_STATUS_AIS_SHIFT (14U) 6800 #define EMAC_DMA_CH1_STATUS_AIS_WIDTH (1U) 6801 #define EMAC_DMA_CH1_STATUS_AIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_AIS_SHIFT)) & EMAC_DMA_CH1_STATUS_AIS_MASK) 6802 6803 #define EMAC_DMA_CH1_STATUS_NIS_MASK (0x8000U) 6804 #define EMAC_DMA_CH1_STATUS_NIS_SHIFT (15U) 6805 #define EMAC_DMA_CH1_STATUS_NIS_WIDTH (1U) 6806 #define EMAC_DMA_CH1_STATUS_NIS(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_NIS_SHIFT)) & EMAC_DMA_CH1_STATUS_NIS_MASK) 6807 6808 #define EMAC_DMA_CH1_STATUS_TEB_MASK (0x70000U) 6809 #define EMAC_DMA_CH1_STATUS_TEB_SHIFT (16U) 6810 #define EMAC_DMA_CH1_STATUS_TEB_WIDTH (3U) 6811 #define EMAC_DMA_CH1_STATUS_TEB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_TEB_SHIFT)) & EMAC_DMA_CH1_STATUS_TEB_MASK) 6812 6813 #define EMAC_DMA_CH1_STATUS_REB_MASK (0x380000U) 6814 #define EMAC_DMA_CH1_STATUS_REB_SHIFT (19U) 6815 #define EMAC_DMA_CH1_STATUS_REB_WIDTH (3U) 6816 #define EMAC_DMA_CH1_STATUS_REB(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_STATUS_REB_SHIFT)) & EMAC_DMA_CH1_STATUS_REB_MASK) 6817 /*! @} */ 6818 6819 /*! @name DMA_CH1_MISS_FRAME_CNT - DMA Channel 1 Miss Frame Counter */ 6820 /*! @{ */ 6821 6822 #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK (0x7FFU) 6823 #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT (0U) 6824 #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_WIDTH (11U) 6825 #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT)) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK) 6826 6827 #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_MASK (0x8000U) 6828 #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_SHIFT (15U) 6829 #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_WIDTH (1U) 6830 #define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_SHIFT)) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_MASK) 6831 /*! @} */ 6832 6833 /*! @name DMA_CH1_RXP_ACCEPT_CNT - DMA Channel 1 Rx Parser Accept Count */ 6834 /*! @{ */ 6835 6836 #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU) 6837 #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U) 6838 #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_WIDTH (31U) 6839 #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK) 6840 6841 #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U) 6842 #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) 6843 #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_WIDTH (1U) 6844 #define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_MASK) 6845 /*! @} */ 6846 6847 /*! @name DMA_CH1_RX_ERI_CNT - DMA Channel 1 Rx ERI Count */ 6848 /*! @{ */ 6849 6850 #define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK (0xFFFU) 6851 #define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT (0U) 6852 #define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_WIDTH (12U) 6853 #define EMAC_DMA_CH1_RX_ERI_CNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT)) & EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK) 6854 /*! @} */ 6855 6856 /*! 6857 * @} 6858 */ /* end of group EMAC_Register_Masks */ 6859 6860 /*! 6861 * @} 6862 */ /* end of group EMAC_Peripheral_Access_Layer */ 6863 6864 #endif /* #if !defined(S32K344_EMAC_H_) */ 6865