| /hal_nxp-3.6.0/mcux/mcux-sdk/drivers/enet_qos/ |
| D | fsl_enet_qos.c | 724 base->MAC_INTERRUPT_ENABLE &= ~ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK; in ENET_QOS_SetPtp1588()
1340 base->MAC_INTERRUPT_ENABLE |= interrupt; in ENET_QOS_EnableInterrupts()
1418 base->MAC_INTERRUPT_ENABLE &= ~interrupt; in ENET_QOS_DisableInterrupts()
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| /hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/src/ |
| D | Gmac_Ip.c | 672 Base->MAC_INTERRUPT_ENABLE = Config->Gmac_pCtrlConfig->Interrupts; in Gmac_Ip_InitMAC()
|
| /hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_EMAC.h | 116 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< MAC Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1175/ |
| D | MIMXRT1175_cm7.h | 35784 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| D | MIMXRT1175_cm4.h | 35782 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 35784 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1173/ |
| D | MIMXRT1173_cm7.h | 37788 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| D | MIMXRT1173_cm4.h | 37786 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1172/ |
| D | MIMXRT1172.h | 37791 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1176/ |
| D | MIMXRT1176_cm7.h | 37791 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| D | MIMXRT1176_cm4.h | 37789 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML3/ |
| D | MIMX8ML3_cm7.h | 33735 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML4/ |
| D | MIMX8ML4_cm7.h | 33735 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML8/ |
| D | MIMX8ML8_ca53.h | 33761 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| D | MIMX8ML8_cm7.h | 33735 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| D | MIMX8ML8_dsp.h | 32152 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML6/ |
| D | MIMX8ML6_cm7.h | 33735 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| /hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX9352/ |
| D | MIMX9352_cm33.h | 22454 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
| D | MIMX9352_ca55.h | 20134 __IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */ member
|
