LPCG_TUPLE_RSRC (reference) in projects: hal_nxp-3.6.0

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Searched refs:LPCG_TUPLE_RSRC (Results 1 – 25 of 30) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
D	fsl_clock.h	`255 #define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU)) macro`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
D	fsl_clock.c	`63 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExt() 91 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClock() 117 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 141 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
D	fsl_clock.c	`77 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, true, (bool)gate); in CLOCK_EnableClockExtMapped() 117 err = sc_pm_clock_enable(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, false, false); in CLOCK_DisableClockMapped() 143 err = sc_pm_set_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &target); in CLOCK_SetIpFreq() 167 err = sc_pm_get_clock_rate(ipcHandle, LPCG_TUPLE_RSRC(name), SC_PM_CLK_PER, &freq); in CLOCK_GetIpFreq()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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