1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ierc_pci.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_ierc_pci 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ierc_pci_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ierc_pci_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ierc_pci Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ierc_pci_Peripheral_Access_Layer ierc_pci Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ierc_pci - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t PCI_CFH_DID_VID; /**< PCI device ID and vendor ID register, offset: 0x0 */ 74 __IO uint16_t PCI_CFH_CMD; /**< PCI command register, offset: 0x4 */ 75 __I uint16_t PCI_CFH_STAT; /**< PCI status register, offset: 0x6 */ 76 __I uint32_t PCI_CFH_REVID_CLASSCODE; /**< PCI revision ID and classcode register, offset: 0x8 */ 77 __IO uint8_t PCI_CFH_CL_SIZE; /**< PCI cache line size register, offset: 0xC */ 78 uint8_t RESERVED_0[1]; 79 __I uint8_t PCI_CFH_HDR_TYPE; /**< PCI header type register, offset: 0xE */ 80 uint8_t RESERVED_1[29]; 81 __I uint16_t PCI_CFH_SUBSYS_VID; /**< PCI subsystem vendor ID register, offset: 0x2C */ 82 __I uint16_t PCI_CFH_SUBSYS_ID; /**< PCI subsystem ID register, offset: 0x2E */ 83 uint8_t RESERVED_2[4]; 84 __I uint8_t PCI_CFH_CAP_PTR; /**< PCI capabilities pointer register, offset: 0x34 */ 85 uint8_t RESERVED_3[7]; 86 __IO uint8_t PCI_CFH_INT_LINE; /**< PCI interrupt line register, offset: 0x3C */ 87 __I uint8_t PCI_CFH_INT_PIN; /**< PCI interrupt pin register, offset: 0x3D */ 88 uint8_t RESERVED_4[2]; 89 __I uint16_t PCI_CFC_PCIE_CAP_LIST; /**< PCI PCIe capabilities list register, offset: 0x40 */ 90 __I uint16_t PCI_CFC_PCIE_CAP; /**< PCI PCIe capabilities register, offset: 0x42 */ 91 __I uint32_t PCI_CFC_PCIE_DEV_CAP; /**< PCI PCIe device capabilities register, offset: 0x44 */ 92 uint8_t RESERVED_5[2]; 93 __I uint16_t PCI_CFC_PCIE_DEV_STAT; /**< PCI PCIe device status register, offset: 0x4A */ 94 uint8_t RESERVED_6[52]; 95 __I uint16_t PCI_CFC_PCIPM_CAP_LIST; /**< PCI PCI-PM capabilities list register, offset: 0x80 */ 96 __I uint16_t PCI_CFC_PCIPM_CAP; /**< PCI PCI-PM capabilities register, offset: 0x82 */ 97 __IO uint16_t PCI_CFC_PCIPM_CTL_STAT; /**< PCI PCI-PM control and status register, offset: 0x84 */ 98 uint8_t RESERVED_7[1]; 99 uint8_t PCI_CFC_PCIPM_DATA; /**< PCI PCI-PM capabilities data register, offset: 0x87 */ 100 uint8_t RESERVED_8[120]; 101 __I uint32_t PCIE_CFC_AER_EXT_CAP_HDR; /**< PCIe AER extended capability header, offset: 0x100 */ 102 uint8_t RESERVED_9[40]; 103 __IO uint32_t PCIE_CFC_AER_ROOT_ERR_CMD; /**< PCIe AER root error command register, offset: 0x12C */ 104 __IO uint32_t PCIE_CFC_AER_ROOT_ERR_STAT; /**< PCIe AER root error status register, offset: 0x130 */ 105 __I uint32_t PCIE_CFC_AER_ERR_SRC_ID; /**< PCIe AER error source identification register, offset: 0x134 */ 106 __I uint32_t PCIE_CFC_RCEC_EPA_EXT_CAP_HDR; /**< PCIe RCEC Endpoint association extended capability header, offset: 0x138 */ 107 __I uint32_t PCIE_CFC_RCEC_EPA_BITMAP; /**< PCIe RCEC Endpoint association bitmap registerr, offset: 0x13C */ 108 } ierc_pci_Type, *ierc_pci_MemMapPtr; 109 110 /** Number of instances of the ierc_pci module. */ 111 #define ierc_pci_INSTANCE_COUNT (1u) 112 113 /* ierc_pci - Peripheral instance base addresses */ 114 /** Peripheral NETC__IERC_F0_PCI_HDR_TYPE0 base address */ 115 #define IP_NETC__IERC_F0_PCI_HDR_TYPE0_BASE (0x740F8000u) 116 /** Peripheral NETC__IERC_F0_PCI_HDR_TYPE0 base pointer */ 117 #define IP_NETC__IERC_F0_PCI_HDR_TYPE0 ((ierc_pci_Type *)IP_NETC__IERC_F0_PCI_HDR_TYPE0_BASE) 118 /** Array initializer of ierc_pci peripheral base addresses */ 119 #define IP_ierc_pci_BASE_ADDRS { IP_NETC__IERC_F0_PCI_HDR_TYPE0_BASE } 120 /** Array initializer of ierc_pci peripheral base pointers */ 121 #define IP_ierc_pci_BASE_PTRS { IP_NETC__IERC_F0_PCI_HDR_TYPE0 } 122 123 /* ---------------------------------------------------------------------------- 124 -- ierc_pci Register Masks 125 ---------------------------------------------------------------------------- */ 126 127 /*! 128 * @addtogroup ierc_pci_Register_Masks ierc_pci Register Masks 129 * @{ 130 */ 131 132 /*! @name PCI_CFH_DID_VID - PCI device ID and vendor ID register */ 133 /*! @{ */ 134 135 #define ierc_pci_PCI_CFH_DID_VID_VENDOR_ID_MASK (0xFFFFU) 136 #define ierc_pci_PCI_CFH_DID_VID_VENDOR_ID_SHIFT (0U) 137 #define ierc_pci_PCI_CFH_DID_VID_VENDOR_ID_WIDTH (16U) 138 #define ierc_pci_PCI_CFH_DID_VID_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCI_CFH_DID_VID_VENDOR_ID_SHIFT)) & ierc_pci_PCI_CFH_DID_VID_VENDOR_ID_MASK) 139 140 #define ierc_pci_PCI_CFH_DID_VID_DEVICE_ID_MASK (0xFFFF0000U) 141 #define ierc_pci_PCI_CFH_DID_VID_DEVICE_ID_SHIFT (16U) 142 #define ierc_pci_PCI_CFH_DID_VID_DEVICE_ID_WIDTH (16U) 143 #define ierc_pci_PCI_CFH_DID_VID_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCI_CFH_DID_VID_DEVICE_ID_SHIFT)) & ierc_pci_PCI_CFH_DID_VID_DEVICE_ID_MASK) 144 /*! @} */ 145 146 /*! @name PCI_CFH_CMD - PCI command register */ 147 /*! @{ */ 148 149 #define ierc_pci_PCI_CFH_CMD_INTR_DISABLE_MASK (0x400U) 150 #define ierc_pci_PCI_CFH_CMD_INTR_DISABLE_SHIFT (10U) 151 #define ierc_pci_PCI_CFH_CMD_INTR_DISABLE_WIDTH (1U) 152 #define ierc_pci_PCI_CFH_CMD_INTR_DISABLE(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFH_CMD_INTR_DISABLE_SHIFT)) & ierc_pci_PCI_CFH_CMD_INTR_DISABLE_MASK) 153 /*! @} */ 154 155 /*! @name PCI_CFH_STAT - PCI status register */ 156 /*! @{ */ 157 158 #define ierc_pci_PCI_CFH_STAT_INTR_STATUS_MASK (0x8U) 159 #define ierc_pci_PCI_CFH_STAT_INTR_STATUS_SHIFT (3U) 160 #define ierc_pci_PCI_CFH_STAT_INTR_STATUS_WIDTH (1U) 161 #define ierc_pci_PCI_CFH_STAT_INTR_STATUS(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFH_STAT_INTR_STATUS_SHIFT)) & ierc_pci_PCI_CFH_STAT_INTR_STATUS_MASK) 162 163 #define ierc_pci_PCI_CFH_STAT_CAP_LIST_MASK (0x10U) 164 #define ierc_pci_PCI_CFH_STAT_CAP_LIST_SHIFT (4U) 165 #define ierc_pci_PCI_CFH_STAT_CAP_LIST_WIDTH (1U) 166 #define ierc_pci_PCI_CFH_STAT_CAP_LIST(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFH_STAT_CAP_LIST_SHIFT)) & ierc_pci_PCI_CFH_STAT_CAP_LIST_MASK) 167 /*! @} */ 168 169 /*! @name PCI_CFH_REVID_CLASSCODE - PCI revision ID and classcode register */ 170 /*! @{ */ 171 172 #define ierc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK (0xFFU) 173 #define ierc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT (0U) 174 #define ierc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_WIDTH (8U) 175 #define ierc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_SHIFT)) & ierc_pci_PCI_CFH_REVID_CLASSCODE_REV_ID_MASK) 176 177 #define ierc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK (0xFFFFFF00U) 178 #define ierc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT (8U) 179 #define ierc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_WIDTH (24U) 180 #define ierc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_SHIFT)) & ierc_pci_PCI_CFH_REVID_CLASSCODE_CLASS_CODE_MASK) 181 /*! @} */ 182 183 /*! @name PCI_CFH_CL_SIZE - PCI cache line size register */ 184 /*! @{ */ 185 186 #define ierc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK (0xFFU) 187 #define ierc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT (0U) 188 #define ierc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_WIDTH (8U) 189 #define ierc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE(x) (((uint8_t)(((uint8_t)(x)) << ierc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_SHIFT)) & ierc_pci_PCI_CFH_CL_SIZE_CACHE_LINE_SIZE_MASK) 190 /*! @} */ 191 192 /*! @name PCI_CFH_HDR_TYPE - PCI header type register */ 193 /*! @{ */ 194 195 #define ierc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK (0x7FU) 196 #define ierc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT (0U) 197 #define ierc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_WIDTH (7U) 198 #define ierc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE(x) (((uint8_t)(((uint8_t)(x)) << ierc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_SHIFT)) & ierc_pci_PCI_CFH_HDR_TYPE_HDR_TYPE_MASK) 199 200 #define ierc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK (0x80U) 201 #define ierc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT (7U) 202 #define ierc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_WIDTH (1U) 203 #define ierc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV(x) (((uint8_t)(((uint8_t)(x)) << ierc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_SHIFT)) & ierc_pci_PCI_CFH_HDR_TYPE_MULT_FUNC_DEV_MASK) 204 /*! @} */ 205 206 /*! @name PCI_CFH_SUBSYS_VID - PCI subsystem vendor ID register */ 207 /*! @{ */ 208 209 #define ierc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK (0xFFFFU) 210 #define ierc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT (0U) 211 #define ierc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_WIDTH (16U) 212 #define ierc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_SHIFT)) & ierc_pci_PCI_CFH_SUBSYS_VID_SUBSYSTEM_VENDOR_ID_MASK) 213 /*! @} */ 214 215 /*! @name PCI_CFH_SUBSYS_ID - PCI subsystem ID register */ 216 /*! @{ */ 217 218 #define ierc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK (0xFFFFU) 219 #define ierc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT (0U) 220 #define ierc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_WIDTH (16U) 221 #define ierc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_SHIFT)) & ierc_pci_PCI_CFH_SUBSYS_ID_SUBSYSTEM_ID_MASK) 222 /*! @} */ 223 224 /*! @name PCI_CFH_CAP_PTR - PCI capabilities pointer register */ 225 /*! @{ */ 226 227 #define ierc_pci_PCI_CFH_CAP_PTR_CAP_PTR_MASK (0xFFU) 228 #define ierc_pci_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT (0U) 229 #define ierc_pci_PCI_CFH_CAP_PTR_CAP_PTR_WIDTH (8U) 230 #define ierc_pci_PCI_CFH_CAP_PTR_CAP_PTR(x) (((uint8_t)(((uint8_t)(x)) << ierc_pci_PCI_CFH_CAP_PTR_CAP_PTR_SHIFT)) & ierc_pci_PCI_CFH_CAP_PTR_CAP_PTR_MASK) 231 /*! @} */ 232 233 /*! @name PCI_CFH_INT_LINE - PCI interrupt line register */ 234 /*! @{ */ 235 236 #define ierc_pci_PCI_CFH_INT_LINE_INT_LINE_MASK (0xFFU) 237 #define ierc_pci_PCI_CFH_INT_LINE_INT_LINE_SHIFT (0U) 238 #define ierc_pci_PCI_CFH_INT_LINE_INT_LINE_WIDTH (8U) 239 #define ierc_pci_PCI_CFH_INT_LINE_INT_LINE(x) (((uint8_t)(((uint8_t)(x)) << ierc_pci_PCI_CFH_INT_LINE_INT_LINE_SHIFT)) & ierc_pci_PCI_CFH_INT_LINE_INT_LINE_MASK) 240 /*! @} */ 241 242 /*! @name PCI_CFH_INT_PIN - PCI interrupt pin register */ 243 /*! @{ */ 244 245 #define ierc_pci_PCI_CFH_INT_PIN_INT_PIN_MASK (0xFFU) 246 #define ierc_pci_PCI_CFH_INT_PIN_INT_PIN_SHIFT (0U) 247 #define ierc_pci_PCI_CFH_INT_PIN_INT_PIN_WIDTH (8U) 248 #define ierc_pci_PCI_CFH_INT_PIN_INT_PIN(x) (((uint8_t)(((uint8_t)(x)) << ierc_pci_PCI_CFH_INT_PIN_INT_PIN_SHIFT)) & ierc_pci_PCI_CFH_INT_PIN_INT_PIN_MASK) 249 /*! @} */ 250 251 /*! @name PCI_CFC_PCIE_CAP_LIST - PCI PCIe capabilities list register */ 252 /*! @{ */ 253 254 #define ierc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK (0xFFU) 255 #define ierc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT (0U) 256 #define ierc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_WIDTH (8U) 257 #define ierc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_SHIFT)) & ierc_pci_PCI_CFC_PCIE_CAP_LIST_CAP_ID_MASK) 258 259 #define ierc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_MASK (0xFF00U) 260 #define ierc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_SHIFT (8U) 261 #define ierc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_WIDTH (8U) 262 #define ierc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_SHIFT)) & ierc_pci_PCI_CFC_PCIE_CAP_LIST_NEXT_CAP_ID_MASK) 263 /*! @} */ 264 265 /*! @name PCI_CFC_PCIE_CAP - PCI PCIe capabilities register */ 266 /*! @{ */ 267 268 #define ierc_pci_PCI_CFC_PCIE_CAP_CAP_VER_MASK (0xFU) 269 #define ierc_pci_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT (0U) 270 #define ierc_pci_PCI_CFC_PCIE_CAP_CAP_VER_WIDTH (4U) 271 #define ierc_pci_PCI_CFC_PCIE_CAP_CAP_VER(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIE_CAP_CAP_VER_SHIFT)) & ierc_pci_PCI_CFC_PCIE_CAP_CAP_VER_MASK) 272 273 #define ierc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK (0xF0U) 274 #define ierc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT (4U) 275 #define ierc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_WIDTH (4U) 276 #define ierc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_SHIFT)) & ierc_pci_PCI_CFC_PCIE_CAP_DEV_PORT_TYPE_MASK) 277 278 #define ierc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK (0x3E00U) 279 #define ierc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT (9U) 280 #define ierc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_WIDTH (5U) 281 #define ierc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_SHIFT)) & ierc_pci_PCI_CFC_PCIE_CAP_INT_MSG_NUM_MASK) 282 /*! @} */ 283 284 /*! @name PCI_CFC_PCIE_DEV_CAP - PCI PCIe device capabilities register */ 285 /*! @{ */ 286 287 #define ierc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK (0x10000000U) 288 #define ierc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT (28U) 289 #define ierc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_WIDTH (1U) 290 #define ierc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_SHIFT)) & ierc_pci_PCI_CFC_PCIE_DEV_CAP_FLR_CAP_MASK) 291 /*! @} */ 292 293 /*! @name PCI_CFC_PCIE_DEV_STAT - PCI PCIe device status register */ 294 /*! @{ */ 295 296 #define ierc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK (0x20U) 297 #define ierc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT (5U) 298 #define ierc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_WIDTH (1U) 299 #define ierc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_SHIFT)) & ierc_pci_PCI_CFC_PCIE_DEV_STAT_TRANS_PEND_MASK) 300 /*! @} */ 301 302 /*! @name PCI_CFC_PCIPM_CAP_LIST - PCI PCI-PM capabilities list register */ 303 /*! @{ */ 304 305 #define ierc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK (0xFFU) 306 #define ierc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT (0U) 307 #define ierc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_WIDTH (8U) 308 #define ierc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_SHIFT)) & ierc_pci_PCI_CFC_PCIPM_CAP_LIST_CAP_ID_MASK) 309 310 #define ierc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_MASK (0xFF00U) 311 #define ierc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_SHIFT (8U) 312 #define ierc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_WIDTH (8U) 313 #define ierc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_SHIFT)) & ierc_pci_PCI_CFC_PCIPM_CAP_LIST_NEXT_CAP_ID_MASK) 314 /*! @} */ 315 316 /*! @name PCI_CFC_PCIPM_CAP - PCI PCI-PM capabilities register */ 317 /*! @{ */ 318 319 #define ierc_pci_PCI_CFC_PCIPM_CAP_VERSION_MASK (0x7U) 320 #define ierc_pci_PCI_CFC_PCIPM_CAP_VERSION_SHIFT (0U) 321 #define ierc_pci_PCI_CFC_PCIPM_CAP_VERSION_WIDTH (3U) 322 #define ierc_pci_PCI_CFC_PCIPM_CAP_VERSION(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIPM_CAP_VERSION_SHIFT)) & ierc_pci_PCI_CFC_PCIPM_CAP_VERSION_MASK) 323 324 #define ierc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK (0xF800U) 325 #define ierc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT (11U) 326 #define ierc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_WIDTH (5U) 327 #define ierc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_SHIFT)) & ierc_pci_PCI_CFC_PCIPM_CAP_PME_SUPPORT_MASK) 328 /*! @} */ 329 330 /*! @name PCI_CFC_PCIPM_CTL_STAT - PCI PCI-PM control and status register */ 331 /*! @{ */ 332 333 #define ierc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK (0x3U) 334 #define ierc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT (0U) 335 #define ierc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_WIDTH (2U) 336 #define ierc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_SHIFT)) & ierc_pci_PCI_CFC_PCIPM_CTL_STAT_PWR_STATE_MASK) 337 338 #define ierc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK (0x8U) 339 #define ierc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT (3U) 340 #define ierc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_WIDTH (1U) 341 #define ierc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST(x) (((uint16_t)(((uint16_t)(x)) << ierc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_SHIFT)) & ierc_pci_PCI_CFC_PCIPM_CTL_STAT_NO_SOFT_RST_MASK) 342 /*! @} */ 343 344 /*! @name PCIE_CFC_AER_EXT_CAP_HDR - PCIe AER extended capability header */ 345 /*! @{ */ 346 347 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) 348 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) 349 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_WIDTH (16U) 350 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK) 351 352 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U) 353 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT (16U) 354 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_WIDTH (4U) 355 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_SHIFT)) & ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_CAP_VER_MASK) 356 357 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) 358 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) 359 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_WIDTH (12U) 360 #define ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ierc_pci_PCIE_CFC_AER_EXT_CAP_HDR_NEXT_CAP_OFF_MASK) 361 /*! @} */ 362 363 /*! @name PCIE_CFC_AER_ROOT_ERR_CMD - PCIe AER root error command register */ 364 /*! @{ */ 365 366 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_MASK (0x1U) 367 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_SHIFT (0U) 368 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_WIDTH (1U) 369 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_CORR_ERR_RPT_EN_MASK) 370 371 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_MASK (0x2U) 372 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_SHIFT (1U) 373 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_WIDTH (1U) 374 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_NON_FATAL_ERR_RPT_EN_MASK) 375 376 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_MASK (0x4U) 377 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_SHIFT (2U) 378 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_WIDTH (1U) 379 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_CMD_FATAL_ERR_RPT_EN_MASK) 380 /*! @} */ 381 382 /*! @name PCIE_CFC_AER_ROOT_ERR_STAT - PCIe AER root error status register */ 383 /*! @{ */ 384 385 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_MASK (0x1U) 386 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_SHIFT (0U) 387 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_WIDTH (1U) 388 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_CORR_MASK) 389 390 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_MASK (0x2U) 391 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_SHIFT (1U) 392 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_WIDTH (1U) 393 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_CORR_MASK) 394 395 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_MASK (0x4U) 396 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_SHIFT (2U) 397 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_WIDTH (1U) 398 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_NON_FATAL_MASK) 399 400 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_MASK (0x8U) 401 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_SHIFT (3U) 402 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_WIDTH (1U) 403 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_MULT_ERR_FATAL_NON_FATAL_MASK) 404 405 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_MASK (0x10U) 406 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_SHIFT (4U) 407 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_WIDTH (1U) 408 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_FIRST_UCORR_FATAL_MASK) 409 410 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_MASK (0x20U) 411 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_SHIFT (5U) 412 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_WIDTH (1U) 413 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_NON_FATAL_MASK) 414 415 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_MASK (0x40U) 416 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_SHIFT (6U) 417 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_WIDTH (1U) 418 #define ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_SHIFT)) & ierc_pci_PCIE_CFC_AER_ROOT_ERR_STAT_ERR_FATAL_MASK) 419 /*! @} */ 420 421 /*! @name PCIE_CFC_AER_ERR_SRC_ID - PCIe AER error source identification register */ 422 /*! @{ */ 423 424 #define ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_MASK (0xFFFFU) 425 #define ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_SHIFT (0U) 426 #define ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_WIDTH (16U) 427 #define ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_SHIFT)) & ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_CORR_SRC_ID_MASK) 428 429 #define ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_MASK (0xFFFF0000U) 430 #define ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_SHIFT (16U) 431 #define ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_WIDTH (16U) 432 #define ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_SHIFT)) & ierc_pci_PCIE_CFC_AER_ERR_SRC_ID_ERR_FATAL_NON_FATAL_SRC_ID_MASK) 433 /*! @} */ 434 435 /*! @name PCIE_CFC_RCEC_EPA_EXT_CAP_HDR - PCIe RCEC Endpoint association extended capability header */ 436 /*! @{ */ 437 438 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK (0xFFFFU) 439 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT (0U) 440 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_WIDTH (16U) 441 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_SHIFT)) & ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_PCIE_EXT_CAP_ID_MASK) 442 443 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_MASK (0xF0000U) 444 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_SHIFT (16U) 445 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_WIDTH (4U) 446 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_SHIFT)) & ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_CAP_VER_MASK) 447 448 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_MASK (0xFFF00000U) 449 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT (20U) 450 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_WIDTH (12U) 451 #define ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_SHIFT)) & ierc_pci_PCIE_CFC_RCEC_EPA_EXT_CAP_HDR_NEXT_CAP_OFF_MASK) 452 /*! @} */ 453 454 /*! @name PCIE_CFC_RCEC_EPA_BITMAP - PCIe RCEC Endpoint association bitmap registerr */ 455 /*! @{ */ 456 457 #define ierc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_MASK (0xFFFFFFFFU) 458 #define ierc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_SHIFT (0U) 459 #define ierc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_WIDTH (32U) 460 #define ierc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP(x) (((uint32_t)(((uint32_t)(x)) << ierc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_SHIFT)) & ierc_pci_PCIE_CFC_RCEC_EPA_BITMAP_DEV_BITMAP_MASK) 461 /*! @} */ 462 463 /*! 464 * @} 465 */ /* end of group ierc_pci_Register_Masks */ 466 467 /*! 468 * @} 469 */ /* end of group ierc_pci_Peripheral_Access_Layer */ 470 471 #endif /* #if !defined(S32Z2_ierc_pci_H_) */ 472
