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Searched refs:ICIMVAU (Results 1 – 21 of 21) sorted by relevance

/hal_nxp-3.6.0/mcux/mcux-sdk/CMSIS/Core/Include/
Dcachel1_armv7.h125 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
Dcore_cm7.h496 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_cm33.h540 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/cache/armv7-m7/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1173/drivers/cm7/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML3/drivers/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1172/drivers/cm7/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1171/drivers/cm7/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML4/drivers/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8ML6/drivers/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1165/drivers/cm7/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1175/drivers/cm7/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1176/drivers/cm7/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1166/drivers/cm7/
Dfsl_cache.c506 SCB->ICIMVAU = addr; in L1CACHE_InvalidateICacheByRange()
/hal_nxp-3.6.0/mcux/mcux-sdk/CMSIS/Include/
Dcore_cm7.h491 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
2309 …SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..… in SCB_InvalidateICache_by_Addr()
Dcore_armv8mml.h533 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_cm33.h533 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_cm35p.h533 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
Dcore_armv81mml.h534 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU … member
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SCB.h121 …__O uint32_t ICIMVAU; /**< Instruction cache invalidate by address to P… member
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_SCB.h119 …__O uint32_t ICIMVAU; /**< Instruction cache invalidate by address to P… member