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Searched refs:I2S_TCSR_FEF_MASK (Results 1 – 25 of 93) sorted by relevance

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/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/sai/
Dfsl_sai.c2743 if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FEF_MASK)) in SAI_TransferTxHandleIRQ()
2746 SAI_TxClearStatusFlags(base, I2S_TCSR_FEF_MASK); in SAI_TransferTxHandleIRQ()
2823 SAI_RxClearStatusFlags(base, I2S_TCSR_FEF_MASK); in SAI_TransferRxHandleIRQ()
2888 … (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) in I2S0_DriverIRQHandler()
2891 … (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) in I2S0_DriverIRQHandler()
2898 … (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) in I2S0_DriverIRQHandler()
2901 … (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) in I2S0_DriverIRQHandler()
2932 … (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) in I2S1_DriverIRQHandler()
2935 … (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) in I2S1_DriverIRQHandler()
2943 … (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) in I2S1_DriverIRQHandler()
[all …]
Dfsl_sai.h183 kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h5695 #define I2S_TCSR_FEF_MASK (0x40000U) macro
5701 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h6462 #define I2S_TCSR_FEF_MASK (0x40000U) macro
6468 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h6718 #define I2S_TCSR_FEF_MASK (0x40000U) macro
6724 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h4091 #define I2S_TCSR_FEF_MASK (0x40000U) macro
4093 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h4091 #define I2S_TCSR_FEF_MASK (0x40000U) macro
4093 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h10534 #define I2S_TCSR_FEF_MASK (0x40000U) macro
10540 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h13182 #define I2S_TCSR_FEF_MASK (0x40000U) macro
13188 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h14967 #define I2S_TCSR_FEF_MASK (0x40000U) macro
14973 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h15013 #define I2S_TCSR_FEF_MASK (0x40000U) macro
15019 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm0plus.h6387 #define I2S_TCSR_FEF_MASK (0x40000U) macro
6393 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
DK32L3A60_cm4.h7146 #define I2S_TCSR_FEF_MASK (0x40000U) macro
7152 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h13244 #define I2S_TCSR_FEF_MASK (0x40000U) macro
13250 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h13238 #define I2S_TCSR_FEF_MASK (0x40000U) macro
13244 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK26F18/
DMK26F18.h15109 #define I2S_TCSR_FEF_MASK (0x40000U) macro
15115 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h12683 #define I2S_TCSR_FEF_MASK (0x40000U) macro
12689 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h12685 #define I2S_TCSR_FEF_MASK (0x40000U) macro
12691 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h16926 #define I2S_TCSR_FEF_MASK (0x40000U) macro
16932 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK66F18/
DMK66F18.h16926 #define I2S_TCSR_FEF_MASK (0x40000U) macro
16932 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h7522 #define I2S_TCSR_FEF_MASK (0x40000U) macro
7528 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h7523 #define I2S_TCSR_FEF_MASK (0x40000U) macro
7529 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h15692 #define I2S_TCSR_FEF_MASK (0x40000U) macro
15698 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h18272 #define I2S_TCSR_FEF_MASK (0x40000U) macro
18278 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h21718 #define I2S_TCSR_FEF_MASK (0x40000U) macro
21724 … (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

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