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Searched refs:Gmac_apxBases (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip.c374 Base = Gmac_apxBases[Instance]; in Gmac_Ip_ReadTimeStampInfo()
425 Base = Gmac_apxBases[Instance]; in Gmac_Ip_InitDMA()
561 Gmac_apxBases[Instance]->MTL_EST_GCL_DATA = GMAC_MTL_EST_GCL_DATA_GCD(Data); in Gmac_Ip_WriteGateControlList()
563 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL = GMAC_MTL_EST_GCL_CONTROL_ADDR(AddrGateList); in Gmac_Ip_WriteGateControlList()
567 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL |= GMAC_MTL_EST_GCL_CONTROL_GCRR_MASK; in Gmac_Ip_WriteGateControlList()
571 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL &= ~GMAC_MTL_EST_GCL_CONTROL_GCRR_MASK; in Gmac_Ip_WriteGateControlList()
574 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL |= GMAC_MTL_EST_GCL_CONTROL_R1W0(0U); in Gmac_Ip_WriteGateControlList()
576 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL |= GMAC_MTL_EST_GCL_CONTROL_SRWO_MASK; in Gmac_Ip_WriteGateControlList()
587 … if ((Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL & GMAC_MTL_EST_GCL_CONTROL_SRWO_MASK) == 0U) in Gmac_Ip_WriteGateControlList()
612Gmac_apxBases[Instance]->MTL_OPERATION_MODE = GMAC_MTL_OPERATION_MODE_SCHALG((uint32)(Config->Gmac… in Gmac_Ip_InitMTL()
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DGmac_Ip_Hw_Access.c92 GMAC_Type * const Gmac_apxBases[FEATURE_GMAC_NUM_INSTANCES] = IP_GMAC_BASE_PTRS; variable
211 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_IrqFSMDPPHandler()
255 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_MACIRQHandler()
385 const GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_CommonIRQHandler()
432 GMAC_Type *Base = Gmac_apxBases[Instance]; in GMAC_SafetyIRQHandler()
/hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/include/
DGmac_Ip_Hw_Access.h107 extern GMAC_Type * const Gmac_apxBases[FEATURE_GMAC_NUM_INSTANCES];