1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 /**
7 * @file Stm_Ip.c
8 *
9 * @addtogroup stm_ip Stm IPL
10 *
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Stm_Ip.h"
25
26 #if (STD_ON == STM_IP_ENABLE_USER_MODE_SUPPORT)
27 #define USER_MODE_REG_PROT_ENABLED (STM_IP_ENABLE_USER_MODE_SUPPORT)
28 #include "RegLockMacros.h"
29 #endif
30 /*==================================================================================================
31 * SOURCE FILE VERSION INFORMATION
32 ==================================================================================================*/
33
34 #define STM_IP_VENDOR_ID_C 43
35 #define STM_IP_AR_RELEASE_MAJOR_VERSION_C 4
36 #define STM_IP_AR_RELEASE_MINOR_VERSION_C 7
37 #define STM_IP_AR_RELEASE_REVISION_VERSION_C 0
38 #define STM_IP_SW_MAJOR_VERSION_C 1
39 #define STM_IP_SW_MINOR_VERSION_C 0
40 #define STM_IP_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * FILE VERSION CHECKS
44 ==================================================================================================*/
45 #if (STD_ON == STM_IP_ENABLE_USER_MODE_SUPPORT)
46 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
47 #if ((REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION != STM_IP_AR_RELEASE_MAJOR_VERSION_C) || \
48 (REGLOCKMACROS_AR_RELEASE_MINOR_VERSION != STM_IP_AR_RELEASE_MINOR_VERSION_C))
49 #error "AutoSar Version Numbers of RegLockMacros.h and Stm_Ip.c are different"
50 #endif
51 #endif
52 #endif
53
54 #if (STM_IP_VENDOR_ID != STM_IP_VENDOR_ID_C)
55 #error "Stm_Ip.h and Stm_Ip.c have different vendor ids"
56 #endif
57 /* Check if header file and Gpt header file are of the same Autosar version */
58 #if ((STM_IP_AR_RELEASE_MAJOR_VERSION != STM_IP_AR_RELEASE_MAJOR_VERSION_C) || \
59 (STM_IP_AR_RELEASE_MINOR_VERSION != STM_IP_AR_RELEASE_MINOR_VERSION_C) || \
60 (STM_IP_AR_RELEASE_REVISION_VERSION != STM_IP_AR_RELEASE_REVISION_VERSION_C) \
61 )
62 #error "AutoSar Version Numbers of Stm_Ip.h and Stm_Ip.c are different"
63 #endif
64 /* Check if source file and GPT header file are of the same Software version */
65 #if ((STM_IP_SW_MAJOR_VERSION != STM_IP_SW_MAJOR_VERSION_C) || \
66 (STM_IP_SW_MINOR_VERSION != STM_IP_SW_MINOR_VERSION_C) || \
67 (STM_IP_SW_PATCH_VERSION != STM_IP_SW_PATCH_VERSION_C) \
68 )
69 #error "Software Version Numbers of Stm_Ip.h and Stm_Ip.c are different"
70 #endif
71 /*==================================================================================================
72 * LOCAL DEFINIES
73 ==================================================================================================*/
74
75 /*==================================================================================================
76 * LOCAL MACROS
77 ==================================================================================================*/
78
79 /*==================================================================================================
80 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
81 ==================================================================================================*/
82
83 /*==================================================================================================
84 * LOCAL CONSTANTS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL VARIABLES
89 ==================================================================================================*/
90
91 /*==================================================================================================
92 * GLOBAL CONSTANTS
93 ==================================================================================================*/
94
95 /*==================================================================================================
96 * GLOBAL VARIABLES
97 ==================================================================================================*/
98 #if (STM_IP_USED == STD_ON)
99
100 #define GPT_START_SEC_VAR_CLEARED_32
101 #include "Gpt_MemMap.h"
102 /** @brief Global array variable used to store the runtime target time value. */
103 uint32 Stm_Ip_u32TargetValue[GPT_STM_INSTANCE_COUNT][STM_CHANNEL_COUNT];
104 #if ( defined(STM_0_ISR_USED) || defined(STM_1_ISR_USED) || defined(STM_2_ISR_USED) || defined(STM_3_ISR_USED) || \
105 defined(STM_4_ISR_USED) || defined(STM_5_ISR_USED) || defined(STM_6_ISR_USED) || defined(STM_7_ISR_USED) || \
106 defined(STM_8_ISR_USED) || defined(STM_9_ISR_USED) || defined(STM_10_ISR_USED) || defined(STM_11_ISR_USED) || \
107 defined(STM_12_ISR_USED)|| defined(SMU_STM_0_ISR_USED) || defined(SMU_STM_2_ISR_USED) || \
108 defined(CE_STM_0_ISR_USED) || defined(CE_STM_1_ISR_USED) || defined(CE_STM_2_ISR_USED) || \
109 defined(RTU0_STM_0_ISR_USED) || defined(RTU0_STM_1_ISR_USED) || defined(RTU0_STM_2_ISR_USED) || defined(RTU0_STM_3_ISR_USED) || \
110 defined(RTU1_STM_0_ISR_USED) || defined(RTU1_STM_1_ISR_USED) || defined(RTU1_STM_2_ISR_USED) || defined(RTU1_STM_3_ISR_USED) || \
111 defined(RTU2_STM_0_ISR_USED) || defined(RTU2_STM_1_ISR_USED) || defined(RTU2_STM_2_ISR_USED) || defined(RTU2_STM_3_ISR_USED) || \
112 defined(RTU3_STM_0_ISR_USED) || defined(RTU3_STM_1_ISR_USED) || defined(RTU3_STM_2_ISR_USED) || defined(RTU3_STM_3_ISR_USED) || \
113 defined(CRS_STM_0_ISR_USED) || \
114 defined(RTU0_COS_STM_0_CH_0_ISR_USED) || defined(RTU0_COS_STM_0_CH_1_ISR_USED) || defined(RTU0_COS_STM_0_CH_2_ISR_USED) || defined(RTU0_COS_STM_0_CH_3_ISR_USED) || \
115 defined(RTU0_COS_STM_1_CH_0_ISR_USED) || defined(RTU0_COS_STM_1_CH_1_ISR_USED) || defined(RTU0_COS_STM_1_CH_2_ISR_USED) || defined(RTU0_COS_STM_1_CH_3_ISR_USED) || \
116 defined(RTU0_COS_STM_2_CH_0_ISR_USED) || defined(RTU0_COS_STM_2_CH_1_ISR_USED) || defined(RTU0_COS_STM_2_CH_2_ISR_USED) || defined(RTU0_COS_STM_2_CH_3_ISR_USED) || \
117 defined(RTU0_COS_STM_3_CH_0_ISR_USED) || defined(RTU0_COS_STM_3_CH_1_ISR_USED) || defined(RTU0_COS_STM_3_CH_2_ISR_USED) || defined(RTU0_COS_STM_3_CH_3_ISR_USED) || \
118 defined(RTU1_COS_STM_0_CH_0_ISR_USED) || defined(RTU1_COS_STM_0_CH_1_ISR_USED) || defined(RTU1_COS_STM_0_CH_2_ISR_USED) || defined(RTU1_COS_STM_0_CH_3_ISR_USED) || \
119 defined(RTU1_COS_STM_1_CH_0_ISR_USED) || defined(RTU1_COS_STM_1_CH_1_ISR_USED) || defined(RTU1_COS_STM_1_CH_2_ISR_USED) || defined(RTU1_COS_STM_1_CH_3_ISR_USED) || \
120 defined(RTU1_COS_STM_2_CH_0_ISR_USED) || defined(RTU1_COS_STM_2_CH_1_ISR_USED) || defined(RTU1_COS_STM_2_CH_2_ISR_USED) || defined(RTU1_COS_STM_2_CH_3_ISR_USED) || \
121 defined(RTU1_COS_STM_3_CH_0_ISR_USED) || defined(RTU1_COS_STM_3_CH_1_ISR_USED) || defined(RTU1_COS_STM_3_CH_2_ISR_USED) || defined(RTU1_COS_STM_3_CH_3_ISR_USED) || \
122 defined(RTU2_COS_STM_0_CH_0_ISR_USED) || defined(RTU2_COS_STM_0_CH_1_ISR_USED) || defined(RTU2_COS_STM_0_CH_2_ISR_USED) || defined(RTU2_COS_STM_0_CH_3_ISR_USED) || \
123 defined(RTU2_COS_STM_1_CH_0_ISR_USED) || defined(RTU2_COS_STM_1_CH_1_ISR_USED) || defined(RTU2_COS_STM_1_CH_2_ISR_USED) || defined(RTU2_COS_STM_1_CH_3_ISR_USED) || \
124 defined(RTU2_COS_STM_2_CH_0_ISR_USED) || defined(RTU2_COS_STM_2_CH_1_ISR_USED) || defined(RTU2_COS_STM_2_CH_2_ISR_USED) || defined(RTU2_COS_STM_2_CH_3_ISR_USED) || \
125 defined(RTU2_COS_STM_3_CH_0_ISR_USED) || defined(RTU2_COS_STM_3_CH_1_ISR_USED) || defined(RTU2_COS_STM_3_CH_2_ISR_USED) || defined(RTU2_COS_STM_3_CH_3_ISR_USED) || \
126 defined(RTU3_COS_STM_0_CH_0_ISR_USED) || defined(RTU3_COS_STM_0_CH_1_ISR_USED) || defined(RTU3_COS_STM_0_CH_2_ISR_USED) || defined(RTU3_COS_STM_0_CH_3_ISR_USED) || \
127 defined(RTU3_COS_STM_1_CH_0_ISR_USED) || defined(RTU3_COS_STM_1_CH_1_ISR_USED) || defined(RTU3_COS_STM_1_CH_2_ISR_USED) || defined(RTU3_COS_STM_1_CH_3_ISR_USED) || \
128 defined(RTU3_COS_STM_2_CH_0_ISR_USED) || defined(RTU3_COS_STM_2_CH_1_ISR_USED) || defined(RTU3_COS_STM_2_CH_2_ISR_USED) || defined(RTU3_COS_STM_2_CH_3_ISR_USED) || \
129 defined(RTU3_COS_STM_3_CH_0_ISR_USED) || defined(RTU3_COS_STM_3_CH_1_ISR_USED) || defined(RTU3_COS_STM_3_CH_2_ISR_USED) || defined(RTU3_COS_STM_3_CH_3_ISR_USED) )
130 uint32 Stm_Ip_u32NextTargetValue[GPT_STM_INSTANCE_COUNT][STM_CHANNEL_COUNT];
131 #endif
132
133 #define GPT_STOP_SEC_VAR_CLEARED_32
134 #include "Gpt_MemMap.h"
135
136 #define GPT_START_SEC_CONST_UNSPECIFIED
137 #include "Gpt_MemMap.h"
138
139 #if (defined(CRS_FSS_AND_RTU_BASE_ADDR_OF_STM_REGISTERS_CONCATENATED) && (CRS_FSS_AND_RTU_BASE_ADDR_OF_STM_REGISTERS_CONCATENATED == STD_ON))
140 /** @brief Table of base addresses for STM instances. */
141 #define IP_STM_BASE_PTRS_CONCATENATED { IP_CRS__STM, IP_FSS__COSS_STM_0, IP_FSS__COSS_STM_1, IP_FSS__COSS_STM_2, IP_FSS__COSS_STM_3, IP_FSS__STM_0, IP_FSS__STM_1, IP_FSS__STM_AUX_0, IP_FSS__STM_AUX_1, IP_FSS__STM_AUX_2, (STM_Type *)IP_RTU0__RTU_STM0_BASE, (STM_Type *)IP_RTU0__RTU_STM1_BASE, (STM_Type *)IP_RTU0__RTU_STM2_BASE, (STM_Type *)IP_RTU0__RTU_STM3_BASE, (STM_Type *)IP_RTU1__RTU_STM0_BASE, (STM_Type *)IP_RTU1__RTU_STM1_BASE, (STM_Type *)IP_RTU1__RTU_STM2_BASE, (STM_Type *)IP_RTU1__RTU_STM3_BASE, (STM_Type *)IP_RTU2__RTU_STM0_BASE, (STM_Type *)IP_RTU2__RTU_STM1_BASE, (STM_Type *)IP_RTU2__RTU_STM2_BASE, (STM_Type *)IP_RTU2__RTU_STM3_BASE, (STM_Type *)IP_RTU3__RTU_STM0_BASE, (STM_Type *)IP_RTU3__RTU_STM1_BASE, (STM_Type *)IP_RTU3__RTU_STM2_BASE, (STM_Type *)IP_RTU3__RTU_STM3_BASE }
142 STM_Type * const stmBase[GPT_STM_INSTANCE_COUNT] = IP_STM_BASE_PTRS_CONCATENATED;
143 #else
144 /** @brief Table of base addresses for STM instances. */
145 STM_Type * const stmBase[GPT_STM_INSTANCE_COUNT] = IP_STM_BASE_PTRS;
146 #endif
147
148 #define GPT_STOP_SEC_CONST_UNSPECIFIED
149 #include "Gpt_MemMap.h"
150
151 #define GPT_START_SEC_VAR_INIT_UNSPECIFIED
152 #include "Gpt_MemMap.h"
153 #if ( defined(STM_0_ISR_USED) || defined(STM_1_ISR_USED) || defined(STM_2_ISR_USED) || defined(STM_3_ISR_USED) || \
154 defined(STM_4_ISR_USED) || defined(STM_5_ISR_USED) || defined(STM_6_ISR_USED) || defined(STM_7_ISR_USED) || \
155 defined(STM_8_ISR_USED) || defined(STM_9_ISR_USED) || defined(STM_10_ISR_USED) || defined(STM_11_ISR_USED) || \
156 defined(STM_12_ISR_USED)|| defined(SMU_STM_0_ISR_USED) || defined(SMU_STM_2_ISR_USED) || \
157 defined(CE_STM_0_ISR_USED) || defined(CE_STM_1_ISR_USED) || defined(CE_STM_2_ISR_USED) || \
158 defined(RTU0_STM_0_ISR_USED) || defined(RTU0_STM_1_ISR_USED) || defined(RTU0_STM_2_ISR_USED) || defined(RTU0_STM_3_ISR_USED) || \
159 defined(RTU1_STM_0_ISR_USED) || defined(RTU1_STM_1_ISR_USED) || defined(RTU1_STM_2_ISR_USED) || defined(RTU1_STM_3_ISR_USED) || \
160 defined(RTU2_STM_0_ISR_USED) || defined(RTU2_STM_1_ISR_USED) || defined(RTU2_STM_2_ISR_USED) || defined(RTU2_STM_3_ISR_USED) || \
161 defined(RTU3_STM_0_ISR_USED) || defined(RTU3_STM_1_ISR_USED) || defined(RTU3_STM_2_ISR_USED) || defined(RTU3_STM_3_ISR_USED) || \
162 defined(CRS_STM_0_ISR_USED) || \
163 defined(RTU0_COS_STM_0_CH_0_ISR_USED) || defined(RTU0_COS_STM_0_CH_1_ISR_USED) || defined(RTU0_COS_STM_0_CH_2_ISR_USED) || defined(RTU0_COS_STM_0_CH_3_ISR_USED) || \
164 defined(RTU0_COS_STM_1_CH_0_ISR_USED) || defined(RTU0_COS_STM_1_CH_1_ISR_USED) || defined(RTU0_COS_STM_1_CH_2_ISR_USED) || defined(RTU0_COS_STM_1_CH_3_ISR_USED) || \
165 defined(RTU0_COS_STM_2_CH_0_ISR_USED) || defined(RTU0_COS_STM_2_CH_1_ISR_USED) || defined(RTU0_COS_STM_2_CH_2_ISR_USED) || defined(RTU0_COS_STM_2_CH_3_ISR_USED) || \
166 defined(RTU0_COS_STM_3_CH_0_ISR_USED) || defined(RTU0_COS_STM_3_CH_1_ISR_USED) || defined(RTU0_COS_STM_3_CH_2_ISR_USED) || defined(RTU0_COS_STM_3_CH_3_ISR_USED) || \
167 defined(RTU1_COS_STM_0_CH_0_ISR_USED) || defined(RTU1_COS_STM_0_CH_1_ISR_USED) || defined(RTU1_COS_STM_0_CH_2_ISR_USED) || defined(RTU1_COS_STM_0_CH_3_ISR_USED) || \
168 defined(RTU1_COS_STM_1_CH_0_ISR_USED) || defined(RTU1_COS_STM_1_CH_1_ISR_USED) || defined(RTU1_COS_STM_1_CH_2_ISR_USED) || defined(RTU1_COS_STM_1_CH_3_ISR_USED) || \
169 defined(RTU1_COS_STM_2_CH_0_ISR_USED) || defined(RTU1_COS_STM_2_CH_1_ISR_USED) || defined(RTU1_COS_STM_2_CH_2_ISR_USED) || defined(RTU1_COS_STM_2_CH_3_ISR_USED) || \
170 defined(RTU1_COS_STM_3_CH_0_ISR_USED) || defined(RTU1_COS_STM_3_CH_1_ISR_USED) || defined(RTU1_COS_STM_3_CH_2_ISR_USED) || defined(RTU1_COS_STM_3_CH_3_ISR_USED) || \
171 defined(RTU2_COS_STM_0_CH_0_ISR_USED) || defined(RTU2_COS_STM_0_CH_1_ISR_USED) || defined(RTU2_COS_STM_0_CH_2_ISR_USED) || defined(RTU2_COS_STM_0_CH_3_ISR_USED) || \
172 defined(RTU2_COS_STM_1_CH_0_ISR_USED) || defined(RTU2_COS_STM_1_CH_1_ISR_USED) || defined(RTU2_COS_STM_1_CH_2_ISR_USED) || defined(RTU2_COS_STM_1_CH_3_ISR_USED) || \
173 defined(RTU2_COS_STM_2_CH_0_ISR_USED) || defined(RTU2_COS_STM_2_CH_1_ISR_USED) || defined(RTU2_COS_STM_2_CH_2_ISR_USED) || defined(RTU2_COS_STM_2_CH_3_ISR_USED) || \
174 defined(RTU2_COS_STM_3_CH_0_ISR_USED) || defined(RTU2_COS_STM_3_CH_1_ISR_USED) || defined(RTU2_COS_STM_3_CH_2_ISR_USED) || defined(RTU2_COS_STM_3_CH_3_ISR_USED) || \
175 defined(RTU3_COS_STM_0_CH_0_ISR_USED) || defined(RTU3_COS_STM_0_CH_1_ISR_USED) || defined(RTU3_COS_STM_0_CH_2_ISR_USED) || defined(RTU3_COS_STM_0_CH_3_ISR_USED) || \
176 defined(RTU3_COS_STM_1_CH_0_ISR_USED) || defined(RTU3_COS_STM_1_CH_1_ISR_USED) || defined(RTU3_COS_STM_1_CH_2_ISR_USED) || defined(RTU3_COS_STM_1_CH_3_ISR_USED) || \
177 defined(RTU3_COS_STM_2_CH_0_ISR_USED) || defined(RTU3_COS_STM_2_CH_1_ISR_USED) || defined(RTU3_COS_STM_2_CH_2_ISR_USED) || defined(RTU3_COS_STM_2_CH_3_ISR_USED) || \
178 defined(RTU3_COS_STM_3_CH_0_ISR_USED) || defined(RTU3_COS_STM_3_CH_1_ISR_USED) || defined(RTU3_COS_STM_3_CH_2_ISR_USED) || defined(RTU3_COS_STM_3_CH_3_ISR_USED) )
179 /** @brief Global array variable used to channel state for process common interrupt */
180 static Stm_Ip_ChState Stm_Ip_u32ChState[GPT_STM_INSTANCE_COUNT][STM_CHANNEL_COUNT] = {
181 {
182 {
183 (boolean)FALSE,
184 NULL_PTR,
185 0U,
186 STM_IP_CH_MODE_CONTINUOUS
187 }
188 }
189 };
190 #endif
191 #if (STM_IP_SET_CLOCK_MODE == STD_ON)
192 static Stm_Ip_InstanceState Stm_Ip_u32InstanceState[GPT_STM_INSTANCE_COUNT] = {
193 {
194 0U,
195 0U
196 }
197 };
198 #endif
199 #define GPT_STOP_SEC_VAR_INIT_UNSPECIFIED
200 #include "Gpt_MemMap.h"
201 /*==================================================================================================
202 * LOCAL FUNCTION PROTOTYPES
203 ==================================================================================================*/
204 #define GPT_START_SEC_CODE
205 #include "Gpt_MemMap.h"
206
207 static inline void Stm_Ip_SetDebugMode(uint8 instance, boolean stopRun);
208 static inline void Stm_Ip_TimerEnable(uint8 instance, boolean enable);
209 static inline uint32 Stm_Ip_GetTimerEnableBit(uint8 instance);
210 static inline void Stm_Ip_SetPrescaler(uint8 instance, uint8 prescalerValue);
211 static inline void Stm_Ip_SetInterruptEnableFlag(uint8 instance, uint8 channel, boolean enable);
212 static inline void Stm_Ip_ClearInterruptStatusFlag(uint8 instance, uint8 channel);
213 static inline void Stm_Ip_SetCmpValue(uint8 instance, uint8 channel, uint32 compareValue);
214 static inline uint32 Stm_Ip_GetCmpValue(uint8 instance, uint8 channel);
215 static inline void Stm_Ip_SetCntValue(uint8 instance, uint32 counterValue);
216 static inline uint32 Stm_Ip_GetCntValue(uint8 instance);
217
218 #if ( defined(STM_0_ISR_USED) || defined(STM_1_ISR_USED) || defined(STM_2_ISR_USED) || defined(STM_3_ISR_USED) || \
219 defined(STM_4_ISR_USED) || defined(STM_5_ISR_USED) || defined(STM_6_ISR_USED) || defined(STM_7_ISR_USED) || \
220 defined(STM_8_ISR_USED) || defined(STM_9_ISR_USED) || defined(STM_10_ISR_USED) || defined(STM_11_ISR_USED) || \
221 defined(STM_12_ISR_USED)|| defined(SMU_STM_0_ISR_USED) || defined(SMU_STM_2_ISR_USED) || \
222 defined(CE_STM_0_ISR_USED) || defined(CE_STM_1_ISR_USED) || defined(CE_STM_2_ISR_USED) || \
223 defined(RTU0_STM_0_ISR_USED) || defined(RTU0_STM_1_ISR_USED) || defined(RTU0_STM_2_ISR_USED) || defined(RTU0_STM_3_ISR_USED) || \
224 defined(RTU1_STM_0_ISR_USED) || defined(RTU1_STM_1_ISR_USED) || defined(RTU1_STM_2_ISR_USED) || defined(RTU1_STM_3_ISR_USED) || \
225 defined(RTU2_STM_0_ISR_USED) || defined(RTU2_STM_1_ISR_USED) || defined(RTU2_STM_2_ISR_USED) || defined(RTU2_STM_3_ISR_USED) || \
226 defined(RTU3_STM_0_ISR_USED) || defined(RTU3_STM_1_ISR_USED) || defined(RTU3_STM_2_ISR_USED) || defined(RTU3_STM_3_ISR_USED) || \
227 defined(CRS_STM_0_ISR_USED) || \
228 defined(RTU0_COS_STM_0_CH_0_ISR_USED) || defined(RTU0_COS_STM_0_CH_1_ISR_USED) || defined(RTU0_COS_STM_0_CH_2_ISR_USED) || defined(RTU0_COS_STM_0_CH_3_ISR_USED) || \
229 defined(RTU0_COS_STM_1_CH_0_ISR_USED) || defined(RTU0_COS_STM_1_CH_1_ISR_USED) || defined(RTU0_COS_STM_1_CH_2_ISR_USED) || defined(RTU0_COS_STM_1_CH_3_ISR_USED) || \
230 defined(RTU0_COS_STM_2_CH_0_ISR_USED) || defined(RTU0_COS_STM_2_CH_1_ISR_USED) || defined(RTU0_COS_STM_2_CH_2_ISR_USED) || defined(RTU0_COS_STM_2_CH_3_ISR_USED) || \
231 defined(RTU0_COS_STM_3_CH_0_ISR_USED) || defined(RTU0_COS_STM_3_CH_1_ISR_USED) || defined(RTU0_COS_STM_3_CH_2_ISR_USED) || defined(RTU0_COS_STM_3_CH_3_ISR_USED) || \
232 defined(RTU1_COS_STM_0_CH_0_ISR_USED) || defined(RTU1_COS_STM_0_CH_1_ISR_USED) || defined(RTU1_COS_STM_0_CH_2_ISR_USED) || defined(RTU1_COS_STM_0_CH_3_ISR_USED) || \
233 defined(RTU1_COS_STM_1_CH_0_ISR_USED) || defined(RTU1_COS_STM_1_CH_1_ISR_USED) || defined(RTU1_COS_STM_1_CH_2_ISR_USED) || defined(RTU1_COS_STM_1_CH_3_ISR_USED) || \
234 defined(RTU1_COS_STM_2_CH_0_ISR_USED) || defined(RTU1_COS_STM_2_CH_1_ISR_USED) || defined(RTU1_COS_STM_2_CH_2_ISR_USED) || defined(RTU1_COS_STM_2_CH_3_ISR_USED) || \
235 defined(RTU1_COS_STM_3_CH_0_ISR_USED) || defined(RTU1_COS_STM_3_CH_1_ISR_USED) || defined(RTU1_COS_STM_3_CH_2_ISR_USED) || defined(RTU1_COS_STM_3_CH_3_ISR_USED) || \
236 defined(RTU2_COS_STM_0_CH_0_ISR_USED) || defined(RTU2_COS_STM_0_CH_1_ISR_USED) || defined(RTU2_COS_STM_0_CH_2_ISR_USED) || defined(RTU2_COS_STM_0_CH_3_ISR_USED) || \
237 defined(RTU2_COS_STM_1_CH_0_ISR_USED) || defined(RTU2_COS_STM_1_CH_1_ISR_USED) || defined(RTU2_COS_STM_1_CH_2_ISR_USED) || defined(RTU2_COS_STM_1_CH_3_ISR_USED) || \
238 defined(RTU2_COS_STM_2_CH_0_ISR_USED) || defined(RTU2_COS_STM_2_CH_1_ISR_USED) || defined(RTU2_COS_STM_2_CH_2_ISR_USED) || defined(RTU2_COS_STM_2_CH_3_ISR_USED) || \
239 defined(RTU2_COS_STM_3_CH_0_ISR_USED) || defined(RTU2_COS_STM_3_CH_1_ISR_USED) || defined(RTU2_COS_STM_3_CH_2_ISR_USED) || defined(RTU2_COS_STM_3_CH_3_ISR_USED) || \
240 defined(RTU3_COS_STM_0_CH_0_ISR_USED) || defined(RTU3_COS_STM_0_CH_1_ISR_USED) || defined(RTU3_COS_STM_0_CH_2_ISR_USED) || defined(RTU3_COS_STM_0_CH_3_ISR_USED) || \
241 defined(RTU3_COS_STM_1_CH_0_ISR_USED) || defined(RTU3_COS_STM_1_CH_1_ISR_USED) || defined(RTU3_COS_STM_1_CH_2_ISR_USED) || defined(RTU3_COS_STM_1_CH_3_ISR_USED) || \
242 defined(RTU3_COS_STM_2_CH_0_ISR_USED) || defined(RTU3_COS_STM_2_CH_1_ISR_USED) || defined(RTU3_COS_STM_2_CH_2_ISR_USED) || defined(RTU3_COS_STM_2_CH_3_ISR_USED) || \
243 defined(RTU3_COS_STM_3_CH_0_ISR_USED) || defined(RTU3_COS_STM_3_CH_1_ISR_USED) || defined(RTU3_COS_STM_3_CH_2_ISR_USED) || defined(RTU3_COS_STM_3_CH_3_ISR_USED) )
244 static void Stm_Ip_ProcessCommonInterrupt(uint8 instance, uint8 channel);
245 static inline boolean Stm_Ip_GetInterruptEnableFlag(uint8 instance, uint8 channel);
246 #endif
247 /*=============================================================================== )===================
248 * GLOBAL FUNCTION PROTOTYPES
249 ==================================================================================================*/
250 #if (STD_ON == STM_IP_ENABLE_USER_MODE_SUPPORT)
251 void Stm_Ip_SetUserAccessAllowed(uint32 StmBaseAddr);
252 #endif
253
254 #if (defined(MCAL_STM_REG_PROT_AVAILABLE) && (STD_ON == STM_IP_ENABLE_USER_MODE_SUPPORT))
255 #define Call_Stm_Ip_SetUserAccessAllowed(BaseAddr) OsIf_Trusted_Call1param(Stm_Ip_SetUserAccessAllowed,(BaseAddr))
256 #else
257 #define Call_Stm_Ip_SetUserAccessAllowed(BaseAddr)
258 #endif
259
260 #if ((STD_ON == STM_GPT_IP_MODULE_SINGLE_INTERRUPT) || (STD_ON == STM_GPT_IP_MODULE_SINGLE_AND_MULTIPLE_INTERRUPTS))
261
262 #if defined(RTU0_STM_0_ISR_USED)
263 ISR(RTU0_STM_0_ISR);
264 #endif
265 #if defined(RTU0_STM_1_ISR_USED)
266 ISR(RTU0_STM_1_ISR);
267 #endif
268 #if defined(RTU0_STM_2_ISR_USED)
269 ISR(RTU0_STM_2_ISR);
270 #endif
271 #if defined(RTU0_STM_3_ISR_USED)
272 ISR(RTU0_STM_3_ISR);
273 #endif
274 #if defined(RTU1_STM_0_ISR_USED)
275 ISR(RTU1_STM_0_ISR);
276 #endif
277 #if defined(RTU1_STM_1_ISR_USED)
278 ISR(RTU1_STM_1_ISR);
279 #endif
280 #if defined(RTU1_STM_2_ISR_USED)
281 ISR(RTU1_STM_2_ISR);
282 #endif
283 #if defined(RTU1_STM_3_ISR_USED)
284 ISR(RTU1_STM_3_ISR);
285 #endif
286 #if defined(RTU2_STM_0_ISR_USED)
287 ISR(RTU2_STM_0_ISR);
288 #endif
289 #if defined(RTU2_STM_1_ISR_USED)
290 ISR(RTU2_STM_1_ISR);
291 #endif
292 #if defined(RTU2_STM_2_ISR_USED)
293 ISR(RTU2_STM_2_ISR);
294 #endif
295 #if defined(RTU2_STM_3_ISR_USED)
296 ISR(RTU2_STM_3_ISR);
297 #endif
298 #if defined(RTU3_STM_0_ISR_USED)
299 ISR(RTU3_STM_0_ISR);
300 #endif
301 #if defined(RTU3_STM_1_ISR_USED)
302 ISR(RTU3_STM_1_ISR);
303 #endif
304 #if defined(RTU3_STM_2_ISR_USED)
305 ISR(RTU3_STM_2_ISR);
306 #endif
307 #if defined(RTU3_STM_3_ISR_USED)
308 ISR(RTU3_STM_3_ISR);
309 #endif
310
311 #if (STD_ON == STM_GPT_IP_MODULE_SINGLE_AND_MULTIPLE_INTERRUPTS)
312
313 #if defined(CRS_STM_0_ISR_USED)
314 ISR(CRS_STM_0_ISR);
315 #endif
316 #if defined(RTU0_COS_STM_0_CH_0_ISR_USED)
317 ISR(RTU0_COS_STM_0_CH_0_ISR);
318 #endif
319 #if defined(RTU0_COS_STM_0_CH_1_ISR_USED)
320 ISR(RTU0_COS_STM_0_CH_1_ISR);
321 #endif
322 #if defined(RTU0_COS_STM_0_CH_2_ISR_USED)
323 ISR(RTU0_COS_STM_0_CH_2_ISR);
324 #endif
325 #if defined(RTU0_COS_STM_0_CH_3_ISR_USED)
326 ISR(RTU0_COS_STM_0_CH_3_ISR);
327 #endif
328 #if defined(RTU0_COS_STM_1_CH_0_ISR_USED)
329 ISR(RTU0_COS_STM_1_CH_0_ISR);
330 #endif
331 #if defined(RTU0_COS_STM_1_CH_1_ISR_USED)
332 ISR(RTU0_COS_STM_1_CH_1_ISR);
333 #endif
334 #if defined(RTU0_COS_STM_1_CH_2_ISR_USED)
335 ISR(RTU0_COS_STM_1_CH_2_ISR);
336 #endif
337 #if defined(RTU0_COS_STM_1_CH_3_ISR_USED)
338 ISR(RTU0_COS_STM_1_CH_3_ISR);
339 #endif
340 #if defined(RTU0_COS_STM_2_CH_0_ISR_USED)
341 ISR(RTU0_COS_STM_2_CH_0_ISR);
342 #endif
343 #if defined(RTU0_COS_STM_2_CH_1_ISR_USED)
344 ISR(RTU0_COS_STM_2_CH_1_ISR);
345 #endif
346 #if defined(RTU0_COS_STM_2_CH_2_ISR_USED)
347 ISR(RTU0_COS_STM_2_CH_2_ISR);
348 #endif
349 #if defined(RTU0_COS_STM_2_CH_3_ISR_USED)
350 ISR(RTU0_COS_STM_2_CH_3_ISR);
351 #endif
352 #if defined(RTU0_COS_STM_3_CH_0_ISR_USED)
353 ISR(RTU0_COS_STM_3_CH_0_ISR);
354 #endif
355 #if defined(RTU0_COS_STM_3_CH_1_ISR_USED)
356 ISR(RTU0_COS_STM_3_CH_1_ISR);
357 #endif
358 #if defined(RTU0_COS_STM_3_CH_2_ISR_USED)
359 ISR(RTU0_COS_STM_3_CH_2_ISR);
360 #endif
361 #if defined(RTU0_COS_STM_3_CH_3_ISR_USED)
362 ISR(RTU0_COS_STM_3_CH_3_ISR);
363 #endif
364
365 #if defined(RTU1_COS_STM_0_CH_0_ISR_USED)
366 ISR(RTU1_COS_STM_0_CH_0_ISR);
367 #endif
368 #if defined(RTU1_COS_STM_0_CH_1_ISR_USED)
369 ISR(RTU1_COS_STM_0_CH_1_ISR);
370 #endif
371 #if defined(RTU1_COS_STM_0_CH_2_ISR_USED)
372 ISR(RTU1_COS_STM_0_CH_2_ISR);
373 #endif
374 #if defined(RTU1_COS_STM_0_CH_3_ISR_USED)
375 ISR(RTU1_COS_STM_0_CH_3_ISR);
376 #endif
377 #if defined(RTU1_COS_STM_1_CH_0_ISR_USED)
378 ISR(RTU1_COS_STM_1_CH_0_ISR);
379 #endif
380 #if defined(RTU1_COS_STM_1_CH_1_ISR_USED)
381 ISR(RTU1_COS_STM_1_CH_1_ISR);
382 #endif
383 #if defined(RTU1_COS_STM_1_CH_2_ISR_USED)
384 ISR(RTU1_COS_STM_1_CH_2_ISR);
385 #endif
386 #if defined(RTU1_COS_STM_1_CH_3_ISR_USED)
387 ISR(RTU1_COS_STM_1_CH_3_ISR);
388 #endif
389 #if defined(RTU1_COS_STM_2_CH_0_ISR_USED)
390 ISR(RTU1_COS_STM_2_CH_0_ISR);
391 #endif
392 #if defined(RTU1_COS_STM_2_CH_1_ISR_USED)
393 ISR(RTU1_COS_STM_2_CH_1_ISR);
394 #endif
395 #if defined(RTU1_COS_STM_2_CH_2_ISR_USED)
396 ISR(RTU1_COS_STM_2_CH_2_ISR);
397 #endif
398 #if defined(RTU1_COS_STM_2_CH_3_ISR_USED)
399 ISR(RTU1_COS_STM_2_CH_3_ISR);
400 #endif
401
402 #if defined(RTU1_COS_STM_3_CH_0_ISR_USED)
403 ISR(RTU1_COS_STM_3_CH_0_ISR);
404 #endif
405 #if defined(RTU1_COS_STM_3_CH_1_ISR_USED)
406 ISR(RTU1_COS_STM_3_CH_1_ISR);
407 #endif
408 #if defined(RTU1_COS_STM_3_CH_2_ISR_USED)
409 ISR(RTU1_COS_STM_3_CH_2_ISR);
410 #endif
411 #if defined(RTU1_COS_STM_3_CH_3_ISR_USED)
412 ISR(RTU1_COS_STM_3_CH_3_ISR);
413 #endif
414
415 #if defined(RTU2_COS_STM_0_CH_0_ISR_USED)
416 ISR(RTU2_COS_STM_0_CH_0_ISR);
417 #endif
418 #if defined(RTU2_COS_STM_0_CH_1_ISR_USED)
419 ISR(RTU2_COS_STM_0_CH_1_ISR);
420 #endif
421 #if defined(RTU2_COS_STM_0_CH_2_ISR_USED)
422 ISR(RTU2_COS_STM_0_CH_2_ISR);
423 #endif
424 #if defined(RTU2_COS_STM_0_CH_3_ISR_USED)
425 ISR(RTU2_COS_STM_0_CH_3_ISR);
426 #endif
427
428 #if defined(RTU2_COS_STM_1_CH_0_ISR_USED)
429 ISR(RTU2_COS_STM_1_CH_0_ISR);
430 #endif
431 #if defined(RTU2_COS_STM_1_CH_1_ISR_USED)
432 ISR(RTU2_COS_STM_1_CH_1_ISR);
433 #endif
434 #if defined(RTU2_COS_STM_1_CH_2_ISR_USED)
435 ISR(RTU2_COS_STM_1_CH_2_ISR);
436 #endif
437 #if defined(RTU2_COS_STM_1_CH_3_ISR_USED)
438 ISR(RTU2_COS_STM_1_CH_3_ISR);
439 #endif
440
441 #if defined(RTU2_COS_STM_2_CH_0_ISR_USED)
442 ISR(RTU2_COS_STM_2_CH_0_ISR);
443 #endif
444 #if defined(RTU2_COS_STM_2_CH_1_ISR_USED)
445 ISR(RTU2_COS_STM_2_CH_1_ISR);
446 #endif
447 #if defined(RTU2_COS_STM_2_CH_2_ISR_USED)
448 ISR(RTU2_COS_STM_2_CH_2_ISR);
449 #endif
450 #if defined(RTU2_COS_STM_2_CH_3_ISR_USED)
451 ISR(RTU2_COS_STM_2_CH_3_ISR);
452 #endif
453
454 #if defined(RTU2_COS_STM_3_CH_0_ISR_USED)
455 ISR(RTU2_COS_STM_3_CH_0_ISR);
456 #endif
457 #if defined(RTU2_COS_STM_3_CH_1_ISR_USED)
458 ISR(RTU2_COS_STM_3_CH_1_ISR);
459 #endif
460 #if defined(RTU2_COS_STM_3_CH_2_ISR_USED)
461 ISR(RTU2_COS_STM_3_CH_2_ISR);
462 #endif
463 #if defined(RTU2_COS_STM_3_CH_3_ISR_USED)
464 ISR(RTU2_COS_STM_3_CH_3_ISR);
465 #endif
466 #if defined(RTU3_COS_STM_0_CH_0_ISR_USED)
467 ISR(RTU3_COS_STM_0_CH_0_ISR);
468 #endif
469 #if defined(RTU3_COS_STM_0_CH_1_ISR_USED)
470 ISR(RTU3_COS_STM_0_CH_1_ISR);
471 #endif
472 #if defined(RTU3_COS_STM_0_CH_2_ISR_USED)
473 ISR(RTU3_COS_STM_0_CH_2_ISR);
474 #endif
475 #if defined(RTU3_COS_STM_0_CH_3_ISR_USED)
476 ISR(RTU3_COS_STM_0_CH_3_ISR);
477 #endif
478
479 #if defined(RTU3_COS_STM_1_CH_0_ISR_USED)
480 ISR(RTU3_COS_STM_1_CH_0_ISR);
481 #endif
482 #if defined(RTU3_COS_STM_1_CH_1_ISR_USED)
483 ISR(RTU3_COS_STM_1_CH_1_ISR);
484 #endif
485 #if defined(RTU3_COS_STM_1_CH_2_ISR_USED)
486 ISR(RTU3_COS_STM_1_CH_2_ISR);
487 #endif
488 #if defined(RTU3_COS_STM_1_CH_3_ISR_USED)
489 ISR(RTU3_COS_STM_1_CH_3_ISR);
490 #endif
491
492 #if defined(RTU3_COS_STM_2_CH_0_ISR_USED)
493 ISR(RTU3_COS_STM_2_CH_0_ISR);
494 #endif
495 #if defined(RTU3_COS_STM_2_CH_1_ISR_USED)
496 ISR(RTU3_COS_STM_2_CH_1_ISR);
497 #endif
498 #if defined(RTU3_COS_STM_2_CH_2_ISR_USED)
499 ISR(RTU3_COS_STM_2_CH_2_ISR);
500 #endif
501 #if defined(RTU3_COS_STM_2_CH_3_ISR_USED)
502 ISR(RTU3_COS_STM_2_CH_3_ISR);
503 #endif
504
505 #if defined(RTU3_COS_STM_3_CH_0_ISR_USED)
506 ISR(RTU3_COS_STM_3_CH_0_ISR);
507 #endif
508 #if defined(RTU3_COS_STM_3_CH_1_ISR_USED)
509 ISR(RTU3_COS_STM_3_CH_1_ISR);
510 #endif
511 #if defined(RTU3_COS_STM_3_CH_2_ISR_USED)
512 ISR(RTU3_COS_STM_3_CH_2_ISR);
513 #endif
514 #if defined(RTU3_COS_STM_3_CH_3_ISR_USED)
515 ISR(RTU3_COS_STM_3_CH_3_ISR);
516 #endif
517
518 #endif /* STD_ON == STM_GPT_IP_MODULE_SINGLE_AND_MULTIPLE_INTERRUPTS */
519
520 #if (STD_ON == STM_GPT_IP_MODULE_SINGLE_INTERRUPT)
521 #if defined(STM_0_ISR_USED)
522 ISR(STM_0_ISR);
523 #endif
524 #if defined(STM_1_ISR_USED)
525 ISR(STM_1_ISR);
526 #endif
527 #if defined(STM_2_ISR_USED)
528 ISR(STM_2_ISR);
529 #endif
530 #if defined(STM_3_ISR_USED)
531 ISR(STM_3_ISR);
532 #endif
533 #if defined(STM_4_ISR_USED)
534 ISR(STM_4_ISR);
535 #endif
536 #if defined(STM_5_ISR_USED)
537 ISR(STM_5_ISR);
538 #endif
539 #if defined(STM_6_ISR_USED)
540 ISR(STM_6_ISR);
541 #endif
542 #if defined(STM_7_ISR_USED)
543 ISR(STM_7_ISR);
544 #endif
545 #if defined(STM_8_ISR_USED)
546 ISR(STM_8_ISR);
547 #endif
548 #if defined(STM_9_ISR_USED)
549 ISR(STM_9_ISR);
550 #endif
551 #if defined(STM_10_ISR_USED)
552 ISR(STM_10_ISR);
553 #endif
554 #if defined(STM_11_ISR_USED)
555 ISR(STM_11_ISR);
556 #endif
557 #if defined(STM_12_ISR_USED)
558 ISR(STM_12_ISR);
559 #endif
560 #if defined(CE_STM_0_ISR_USED)
561 ISR(CE_STM_0_ISR);
562 #endif
563 #if defined(CE_STM_1_ISR_USED)
564 ISR(CE_STM_1_ISR);
565 #endif
566 #if defined(CE_STM_2_ISR_USED)
567 ISR(CE_STM_2_ISR);
568 #endif
569 #if defined(SMU_STM_0_ISR_USED)
570 ISR(SMU_STM_0_ISR);
571 #endif
572 #if defined(SMU_STM_2_ISR_USED)
573 ISR(SMU_STM_2_ISR);
574 #endif
575
576 #endif /* STD_ON == STM_GPT_IP_MODULE_SINGLE_INTERRUPT */
577
578 #endif /* (STD_ON == STM_GPT_IP_MODULE_SINGLE_INTERRUPT) || (STD_ON == STM_GPT_IP_MODULE_SINGLE_AND_MULTIPLE_INTERRUPTS) */
579
580 /*==================================================================================================
581 * LOCAL FUNCTIONS
582 ==================================================================================================*/
583
Stm_Ip_SetDebugMode(uint8 instance,boolean stopRun)584 static inline void Stm_Ip_SetDebugMode(uint8 instance, boolean stopRun)
585 {
586 SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_29();
587 /* Enable DebugMode */
588 if (TRUE == stopRun)
589 {
590 stmBase[instance]->CR |= STM_CR_FRZ_MASK;
591 }
592 else
593 {
594 stmBase[instance]->CR &= ~STM_CR_FRZ_MASK;
595 }
596 SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_29();
597 }
598
Stm_Ip_TimerEnable(uint8 instance,boolean enable)599 static inline void Stm_Ip_TimerEnable(uint8 instance, boolean enable)
600 {
601 SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_30();
602 /* Enable TEN */
603 if (TRUE == enable)
604 {
605 stmBase[instance]->CR |= STM_CR_TEN_MASK;
606 }
607 else
608 {
609 stmBase[instance]->CR &= ~STM_CR_TEN_MASK;
610 }
611 SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_30();
612 }
613
Stm_Ip_GetTimerEnableBit(uint8 instance)614 static inline uint32 Stm_Ip_GetTimerEnableBit(uint8 instance)
615 {
616 uint32 flag = 0;
617 /* Get TimerEnableBit value*/
618 flag = (stmBase[instance]->CR & STM_CR_TEN_MASK) >> STM_CR_TEN_SHIFT;
619
620 return flag;
621 }
622
Stm_Ip_SetPrescaler(uint8 instance,uint8 prescalerValue)623 static inline void Stm_Ip_SetPrescaler(uint8 instance, uint8 prescalerValue)
624 {
625 /* SetPrescaler value*/
626 stmBase[instance]->CR = (stmBase[instance]->CR & (~STM_CR_CPS_MASK)) | STM_CR_CPS(prescalerValue);
627
628 }
629
630 /**
631 * @brief
632 * Function Name : Stm_Ip_SetInterruptEnableFlag
633 * Description : Set the Channel Interrupt Enable Flag (CEN): channel interrupt enable registers (CCR0 - CCR3)
634 *
635 * @param[in] instance STM hw instance number
636 * @param[in] channel STM hw channel number
637 * @param[in] enable enable/disable the STM Interrupt
638 *
639 * @return void
640 * @pre The driver needs to be initialized.
641 */
Stm_Ip_SetInterruptEnableFlag(uint8 instance,uint8 channel,boolean enable)642 static inline void Stm_Ip_SetInterruptEnableFlag(uint8 instance, uint8 channel, boolean enable)
643 {
644 SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_31();
645 /* Enable ChannelEnable */
646 if (TRUE == enable)
647 {
648 stmBase[instance]->CHANNEL[channel].CCR |= STM_CCR_CEN_MASK;
649 }
650 else
651 {
652 stmBase[instance]->CHANNEL[channel].CCR &= ~STM_CCR_CEN_MASK;
653 }
654 SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_31();
655 }
656
657 /**
658 * @brief
659 * Function Name : Stm_Ip_ClearInterruptStatusFlag
660 * Description : Clear the Channel Interrupt Status Flag (CIF): channel interrupt registers (CIR0 - CIR3)
661 *
662 * @param[in] instance STM hw instance number
663 * @param[in] channel STM hw channel number
664 *
665 * @return void
666 * @pre The driver needs to be initialized.
667 */
Stm_Ip_ClearInterruptStatusFlag(uint8 instance,uint8 channel)668 static inline void Stm_Ip_ClearInterruptStatusFlag(uint8 instance, uint8 channel)
669 {
670 /* Clear Channel Interrupt Status Flag */
671 stmBase[instance]->CHANNEL[channel].CIR = STM_CIR_CIF_MASK;
672 }
673
674 #if ( defined(STM_0_ISR_USED) || defined(STM_1_ISR_USED) || defined(STM_2_ISR_USED) || defined(STM_3_ISR_USED) || \
675 defined(STM_4_ISR_USED) || defined(STM_5_ISR_USED) || defined(STM_6_ISR_USED) || defined(STM_7_ISR_USED) || \
676 defined(STM_8_ISR_USED) || defined(STM_9_ISR_USED) || defined(STM_10_ISR_USED) || defined(STM_11_ISR_USED) || \
677 defined(STM_12_ISR_USED)|| defined(SMU_STM_0_ISR_USED) || defined(SMU_STM_2_ISR_USED) || \
678 defined(CE_STM_0_ISR_USED) || defined(CE_STM_1_ISR_USED) || defined(CE_STM_2_ISR_USED) || \
679 defined(RTU0_STM_0_ISR_USED) || defined(RTU0_STM_1_ISR_USED) || defined(RTU0_STM_2_ISR_USED) || defined(RTU0_STM_3_ISR_USED) || \
680 defined(RTU1_STM_0_ISR_USED) || defined(RTU1_STM_1_ISR_USED) || defined(RTU1_STM_2_ISR_USED) || defined(RTU1_STM_3_ISR_USED) || \
681 defined(RTU2_STM_0_ISR_USED) || defined(RTU2_STM_1_ISR_USED) || defined(RTU2_STM_2_ISR_USED) || defined(RTU2_STM_3_ISR_USED) || \
682 defined(RTU3_STM_0_ISR_USED) || defined(RTU3_STM_1_ISR_USED) || defined(RTU3_STM_2_ISR_USED) || defined(RTU3_STM_3_ISR_USED) || \
683 defined(CRS_STM_0_ISR_USED) || \
684 defined(RTU0_COS_STM_0_CH_0_ISR_USED) || defined(RTU0_COS_STM_0_CH_1_ISR_USED) || defined(RTU0_COS_STM_0_CH_2_ISR_USED) || defined(RTU0_COS_STM_0_CH_3_ISR_USED) || \
685 defined(RTU0_COS_STM_1_CH_0_ISR_USED) || defined(RTU0_COS_STM_1_CH_1_ISR_USED) || defined(RTU0_COS_STM_1_CH_2_ISR_USED) || defined(RTU0_COS_STM_1_CH_3_ISR_USED) || \
686 defined(RTU0_COS_STM_2_CH_0_ISR_USED) || defined(RTU0_COS_STM_2_CH_1_ISR_USED) || defined(RTU0_COS_STM_2_CH_2_ISR_USED) || defined(RTU0_COS_STM_2_CH_3_ISR_USED) || \
687 defined(RTU0_COS_STM_3_CH_0_ISR_USED) || defined(RTU0_COS_STM_3_CH_1_ISR_USED) || defined(RTU0_COS_STM_3_CH_2_ISR_USED) || defined(RTU0_COS_STM_3_CH_3_ISR_USED) || \
688 defined(RTU1_COS_STM_0_CH_0_ISR_USED) || defined(RTU1_COS_STM_0_CH_1_ISR_USED) || defined(RTU1_COS_STM_0_CH_2_ISR_USED) || defined(RTU1_COS_STM_0_CH_3_ISR_USED) || \
689 defined(RTU1_COS_STM_1_CH_0_ISR_USED) || defined(RTU1_COS_STM_1_CH_1_ISR_USED) || defined(RTU1_COS_STM_1_CH_2_ISR_USED) || defined(RTU1_COS_STM_1_CH_3_ISR_USED) || \
690 defined(RTU1_COS_STM_2_CH_0_ISR_USED) || defined(RTU1_COS_STM_2_CH_1_ISR_USED) || defined(RTU1_COS_STM_2_CH_2_ISR_USED) || defined(RTU1_COS_STM_2_CH_3_ISR_USED) || \
691 defined(RTU1_COS_STM_3_CH_0_ISR_USED) || defined(RTU1_COS_STM_3_CH_1_ISR_USED) || defined(RTU1_COS_STM_3_CH_2_ISR_USED) || defined(RTU1_COS_STM_3_CH_3_ISR_USED) || \
692 defined(RTU2_COS_STM_0_CH_0_ISR_USED) || defined(RTU2_COS_STM_0_CH_1_ISR_USED) || defined(RTU2_COS_STM_0_CH_2_ISR_USED) || defined(RTU2_COS_STM_0_CH_3_ISR_USED) || \
693 defined(RTU2_COS_STM_1_CH_0_ISR_USED) || defined(RTU2_COS_STM_1_CH_1_ISR_USED) || defined(RTU2_COS_STM_1_CH_2_ISR_USED) || defined(RTU2_COS_STM_1_CH_3_ISR_USED) || \
694 defined(RTU2_COS_STM_2_CH_0_ISR_USED) || defined(RTU2_COS_STM_2_CH_1_ISR_USED) || defined(RTU2_COS_STM_2_CH_2_ISR_USED) || defined(RTU2_COS_STM_2_CH_3_ISR_USED) || \
695 defined(RTU2_COS_STM_3_CH_0_ISR_USED) || defined(RTU2_COS_STM_3_CH_1_ISR_USED) || defined(RTU2_COS_STM_3_CH_2_ISR_USED) || defined(RTU2_COS_STM_3_CH_3_ISR_USED) || \
696 defined(RTU3_COS_STM_0_CH_0_ISR_USED) || defined(RTU3_COS_STM_0_CH_1_ISR_USED) || defined(RTU3_COS_STM_0_CH_2_ISR_USED) || defined(RTU3_COS_STM_0_CH_3_ISR_USED) || \
697 defined(RTU3_COS_STM_1_CH_0_ISR_USED) || defined(RTU3_COS_STM_1_CH_1_ISR_USED) || defined(RTU3_COS_STM_1_CH_2_ISR_USED) || defined(RTU3_COS_STM_1_CH_3_ISR_USED) || \
698 defined(RTU3_COS_STM_2_CH_0_ISR_USED) || defined(RTU3_COS_STM_2_CH_1_ISR_USED) || defined(RTU3_COS_STM_2_CH_2_ISR_USED) || defined(RTU3_COS_STM_2_CH_3_ISR_USED) || \
699 defined(RTU3_COS_STM_3_CH_0_ISR_USED) || defined(RTU3_COS_STM_3_CH_1_ISR_USED) || defined(RTU3_COS_STM_3_CH_2_ISR_USED) || defined(RTU3_COS_STM_3_CH_3_ISR_USED) )
700
701 /**
702 * @brief
703 * Function Name : Stm_Ip_GetInterruptEnableFlag
704 * Description : Get the state of Channel Interrupt Enable Flag (CEN): channel interrupt enable registers (CCR0 - CCR3)
705 *
706 * @param[in] instance STM hw instance number
707 * @param[in] channel STM hw channel number
708 *
709 * @return TRUE if a Channel Interrupt is enabled, FALSE otherwise
710 * @pre The driver needs to be initialized.
711 */
Stm_Ip_GetInterruptEnableFlag(uint8 instance,uint8 channel)712 static inline boolean Stm_Ip_GetInterruptEnableFlag(uint8 instance, uint8 channel)
713 {
714 return (0U != (stmBase[instance]->CHANNEL[channel].CCR & STM_CCR_CEN_MASK)) ? TRUE : FALSE;
715 }
716 #endif
717
Stm_Ip_SetCmpValue(uint8 instance,uint8 channel,uint32 compareValue)718 static inline void Stm_Ip_SetCmpValue(uint8 instance, uint8 channel, uint32 compareValue)
719 {
720 /* Set compareValue */
721 stmBase[instance]->CHANNEL[channel].CMP = compareValue;
722 }
723
Stm_Ip_GetCmpValue(uint8 instance,uint8 channel)724 static inline uint32 Stm_Ip_GetCmpValue(uint8 instance, uint8 channel)
725 {
726 uint32 currentCmpValue;
727 /* Get compareValue */
728 currentCmpValue = stmBase[instance]->CHANNEL[channel].CMP;
729 return currentCmpValue;
730 }
731
Stm_Ip_SetCntValue(uint8 instance,uint32 counterValue)732 static inline void Stm_Ip_SetCntValue(uint8 instance, uint32 counterValue)
733 {
734 /* Set counterValue */
735 stmBase[instance]->CNT = counterValue;
736 }
737
Stm_Ip_GetCntValue(uint8 instance)738 static inline uint32 Stm_Ip_GetCntValue(uint8 instance)
739 {
740 uint32 currentCntValue;
741 /* Get counterValue */
742 currentCntValue = stmBase[instance]->CNT;
743 return currentCntValue;
744 }
745
746 #if ( defined(STM_0_ISR_USED) || defined(STM_1_ISR_USED) || defined(STM_2_ISR_USED) || defined(STM_3_ISR_USED) || \
747 defined(STM_4_ISR_USED) || defined(STM_5_ISR_USED) || defined(STM_6_ISR_USED) || defined(STM_7_ISR_USED) || \
748 defined(STM_8_ISR_USED) || defined(STM_9_ISR_USED) || defined(STM_10_ISR_USED) || defined(STM_11_ISR_USED) || \
749 defined(STM_12_ISR_USED)|| defined(SMU_STM_0_ISR_USED) || defined(SMU_STM_2_ISR_USED) || \
750 defined(CE_STM_0_ISR_USED) || defined(CE_STM_1_ISR_USED) || defined(CE_STM_2_ISR_USED) || \
751 defined(RTU0_STM_0_ISR_USED) || defined(RTU0_STM_1_ISR_USED) || defined(RTU0_STM_2_ISR_USED) || defined(RTU0_STM_3_ISR_USED) || \
752 defined(RTU1_STM_0_ISR_USED) || defined(RTU1_STM_1_ISR_USED) || defined(RTU1_STM_2_ISR_USED) || defined(RTU1_STM_3_ISR_USED) || \
753 defined(RTU2_STM_0_ISR_USED) || defined(RTU2_STM_1_ISR_USED) || defined(RTU2_STM_2_ISR_USED) || defined(RTU2_STM_3_ISR_USED) || \
754 defined(RTU3_STM_0_ISR_USED) || defined(RTU3_STM_1_ISR_USED) || defined(RTU3_STM_2_ISR_USED) || defined(RTU3_STM_3_ISR_USED) || \
755 defined(CRS_STM_0_ISR_USED) || \
756 defined(RTU0_COS_STM_0_CH_0_ISR_USED) || defined(RTU0_COS_STM_0_CH_1_ISR_USED) || defined(RTU0_COS_STM_0_CH_2_ISR_USED) || defined(RTU0_COS_STM_0_CH_3_ISR_USED) || \
757 defined(RTU0_COS_STM_1_CH_0_ISR_USED) || defined(RTU0_COS_STM_1_CH_1_ISR_USED) || defined(RTU0_COS_STM_1_CH_2_ISR_USED) || defined(RTU0_COS_STM_1_CH_3_ISR_USED) || \
758 defined(RTU0_COS_STM_2_CH_0_ISR_USED) || defined(RTU0_COS_STM_2_CH_1_ISR_USED) || defined(RTU0_COS_STM_2_CH_2_ISR_USED) || defined(RTU0_COS_STM_2_CH_3_ISR_USED) || \
759 defined(RTU0_COS_STM_3_CH_0_ISR_USED) || defined(RTU0_COS_STM_3_CH_1_ISR_USED) || defined(RTU0_COS_STM_3_CH_2_ISR_USED) || defined(RTU0_COS_STM_3_CH_3_ISR_USED) || \
760 defined(RTU1_COS_STM_0_CH_0_ISR_USED) || defined(RTU1_COS_STM_0_CH_1_ISR_USED) || defined(RTU1_COS_STM_0_CH_2_ISR_USED) || defined(RTU1_COS_STM_0_CH_3_ISR_USED) || \
761 defined(RTU1_COS_STM_1_CH_0_ISR_USED) || defined(RTU1_COS_STM_1_CH_1_ISR_USED) || defined(RTU1_COS_STM_1_CH_2_ISR_USED) || defined(RTU1_COS_STM_1_CH_3_ISR_USED) || \
762 defined(RTU1_COS_STM_2_CH_0_ISR_USED) || defined(RTU1_COS_STM_2_CH_1_ISR_USED) || defined(RTU1_COS_STM_2_CH_2_ISR_USED) || defined(RTU1_COS_STM_2_CH_3_ISR_USED) || \
763 defined(RTU1_COS_STM_3_CH_0_ISR_USED) || defined(RTU1_COS_STM_3_CH_1_ISR_USED) || defined(RTU1_COS_STM_3_CH_2_ISR_USED) || defined(RTU1_COS_STM_3_CH_3_ISR_USED) || \
764 defined(RTU2_COS_STM_0_CH_0_ISR_USED) || defined(RTU2_COS_STM_0_CH_1_ISR_USED) || defined(RTU2_COS_STM_0_CH_2_ISR_USED) || defined(RTU2_COS_STM_0_CH_3_ISR_USED) || \
765 defined(RTU2_COS_STM_1_CH_0_ISR_USED) || defined(RTU2_COS_STM_1_CH_1_ISR_USED) || defined(RTU2_COS_STM_1_CH_2_ISR_USED) || defined(RTU2_COS_STM_1_CH_3_ISR_USED) || \
766 defined(RTU2_COS_STM_2_CH_0_ISR_USED) || defined(RTU2_COS_STM_2_CH_1_ISR_USED) || defined(RTU2_COS_STM_2_CH_2_ISR_USED) || defined(RTU2_COS_STM_2_CH_3_ISR_USED) || \
767 defined(RTU2_COS_STM_3_CH_0_ISR_USED) || defined(RTU2_COS_STM_3_CH_1_ISR_USED) || defined(RTU2_COS_STM_3_CH_2_ISR_USED) || defined(RTU2_COS_STM_3_CH_3_ISR_USED) || \
768 defined(RTU3_COS_STM_0_CH_0_ISR_USED) || defined(RTU3_COS_STM_0_CH_1_ISR_USED) || defined(RTU3_COS_STM_0_CH_2_ISR_USED) || defined(RTU3_COS_STM_0_CH_3_ISR_USED) || \
769 defined(RTU3_COS_STM_1_CH_0_ISR_USED) || defined(RTU3_COS_STM_1_CH_1_ISR_USED) || defined(RTU3_COS_STM_1_CH_2_ISR_USED) || defined(RTU3_COS_STM_1_CH_3_ISR_USED) || \
770 defined(RTU3_COS_STM_2_CH_0_ISR_USED) || defined(RTU3_COS_STM_2_CH_1_ISR_USED) || defined(RTU3_COS_STM_2_CH_2_ISR_USED) || defined(RTU3_COS_STM_2_CH_3_ISR_USED) || \
771 defined(RTU3_COS_STM_3_CH_0_ISR_USED) || defined(RTU3_COS_STM_3_CH_1_ISR_USED) || defined(RTU3_COS_STM_3_CH_2_ISR_USED) || defined(RTU3_COS_STM_3_CH_3_ISR_USED) )
772 /**
773 * @brief Driver routine to process all the interrupts of STM.
774 * @details Support function used by interrupt service routines to implement STM specific operations
775 * and call the upper layer handler to implement non-hardware specific operations.
776 *
777 * @param[in] instance STM hw instance number
778 * @param[in] channel STM hw channel number
779 *
780 * @implements Stm_Ip_ProcessCommonInterrupt_Activity
781 */
Stm_Ip_ProcessCommonInterrupt(uint8 instance,uint8 channel)782 static void Stm_Ip_ProcessCommonInterrupt(uint8 instance, uint8 channel)
783 {
784 uint32 oldCmpValue;
785 uint32 targetValue;
786
787 boolean IsChEvEnabled;
788 boolean HasChEvOccurred;
789
790 boolean chInit;
791 Stm_Ip_CallbackType callback;
792 uint8 callbackParam;
793 Stm_Ip_ChannelModeType channelMode;
794
795 if ((instance < GPT_STM_INSTANCE_COUNT) && (channel < STM_CHANNEL_COUNT))
796 {
797 /* enter critical section */
798 SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_11();
799 {
800 /* check if channel event is enabled */
801 IsChEvEnabled = Stm_Ip_GetInterruptEnableFlag(instance, channel);
802
803 /* check if channel event has occurred */
804 HasChEvOccurred = Stm_Ip_GetInterruptStatusFlag(instance, channel);
805
806 if (IsChEvEnabled && HasChEvOccurred)
807 {
808 /* Clear pending interrupts */
809 Stm_Ip_ClearInterruptStatusFlag(instance, channel);
810 }
811 }
812 /* exit critical section */
813 SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_11();
814
815 /* Check for spurious interrupts */
816 if (IsChEvEnabled && HasChEvOccurred)
817 {
818 chInit = Stm_Ip_u32ChState[instance][channel].chInit;
819 callback = Stm_Ip_u32ChState[instance][channel].callback;
820 channelMode = Stm_Ip_u32ChState[instance][channel].channelMode;
821 callbackParam = Stm_Ip_u32ChState[instance][channel].callbackParam;
822
823 #if (STM_IP_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
824 if(0x0U != Stm_Ip_u32NextTargetValue[instance][channel])
825 {
826 Stm_Ip_u32TargetValue[instance][channel] = Stm_Ip_u32NextTargetValue[instance][channel];
827 Stm_Ip_u32NextTargetValue[instance][channel] = 0x0U;
828 }
829 #endif
830 /* Check if channel mode is ONE-SHOT */
831 if(STM_IP_CH_MODE_ONESHOT == channelMode)
832 {
833 Stm_Ip_DisableChannel(instance, channel);
834 }
835 else
836 {
837 /*Get current CMP value*/
838 oldCmpValue = Stm_Ip_GetCmpValue(instance, channel);
839 /*Get current target value*/
840 targetValue = Stm_Ip_u32TargetValue[instance][channel];
841 /*Set new CMP value*/
842 Stm_Ip_SetCmpValue(instance, channel, (oldCmpValue + targetValue));
843 }
844
845 /* Call GPT upper layer handler */
846 if ((TRUE == chInit) && (NULL_PTR != callback))
847 {
848 callback(callbackParam);
849 }
850 }
851 }
852 }
853 #endif
854
855 /*==================================================================================================
856 * GLOBAL FUNCTIONS
857 ==================================================================================================*/
858 #if (defined(MCAL_STM_REG_PROT_AVAILABLE) && (STD_ON == STM_IP_ENABLE_USER_MODE_SUPPORT))
859 /**
860 * @brief Enables STM registers writing in User Mode by configuring REG_PROT
861 * @details Sets the UAA (User Access Allowed) bit of the STM IP allowing STM registers writing in User Mode
862 *
863 * @param[in] StmBaseAddr
864 *
865 * @return none
866 *
867 * @pre Should be executed in supervisor mode
868 */
Stm_Ip_SetUserAccessAllowed(uint32 StmBaseAddr)869 void Stm_Ip_SetUserAccessAllowed(uint32 StmBaseAddr)
870 {
871 SET_USER_ACCESS_ALLOWED(StmBaseAddr, STM_PROT_MEM_U32);
872 }
873 #endif
874
875
876 /**
877 * @brief Function Name : Stm_Ip_Init
878 * @details Initializes the STM instance. This functions is called for each STM hw Instance and:
879 * - sets the counter value
880 * - configures the freeze mode
881 * - sets the prescaler value
882 * - enables the STM counter
883 *
884 * @param[in] instance STM hw instance number
885 * @param[in] configPtr Pointer to a selected configuration structure
886 * @return void
887 * @pre The data structure including the configuration set required for initializing the GPT driver
888 * @implements Stm_Ip_Init_Activity
889 */
Stm_Ip_Init(uint8 instance,const Stm_Ip_InstanceConfigType * configPtr)890 void Stm_Ip_Init(uint8 instance, const Stm_Ip_InstanceConfigType *configPtr)
891 {
892 #if STM_IP_DEV_ERROR_DETECT == STD_ON
893 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
894 DevAssert(NULL_PTR != configPtr);
895 #endif
896
897 /* Enable register access from user mode, if enabled from configuration file */
898 Call_Stm_Ip_SetUserAccessAllowed((uint32)stmBase[instance]);
899 Stm_Ip_SetCntValue(instance, 0U);
900 Stm_Ip_SetDebugMode(instance, configPtr->stopInDebugMode);
901 Stm_Ip_SetPrescaler(instance, configPtr->clockPrescaler);
902 Stm_Ip_TimerEnable(instance, TRUE);
903 #if (STM_IP_SET_CLOCK_MODE == STD_ON)
904 Stm_Ip_u32InstanceState[instance].clockPrescaler = configPtr->clockPrescaler;
905 Stm_Ip_u32InstanceState[instance].clockAlternatePrescaler = configPtr->clockAlternatePrescaler;
906 #endif
907 }
908
909 /*================================================================================================*/
910 /**
911 * @brief Function Name : Stm_Ip_InitChannel
912 * @details Initializes the STM channels. This functions is called for each STM hw channel and:
913 * - disables hw channel
914 * - clears interrupt clear
915 * - sets compare value to 0
916 * - initializes the state sructure for common process interrupt
917 *
918 * @param[in] instance STM hw instance number
919 * @param[in] configPtr Pointer to a selected configuration structure
920 * @return void
921 * @pre The data structure including the configuration set required for initializing the GPT driver
922 * @implements Stm_Ip_InitChannel_Activity
923 */
Stm_Ip_InitChannel(uint8 instance,const Stm_Ip_ChannelConfigType * configPtr)924 void Stm_Ip_InitChannel(uint8 instance, const Stm_Ip_ChannelConfigType *configPtr)
925 {
926 #if STM_IP_DEV_ERROR_DETECT == STD_ON
927 DevAssert(NULL_PTR != configPtr);
928 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
929 DevAssert(STM_CHANNEL_COUNT > configPtr->hwChannel);
930 #endif
931
932 /* Disable Channel Interrupt */
933 Stm_Ip_SetInterruptEnableFlag(instance, configPtr->hwChannel, FALSE);
934 /* Clear Channel Interrupt Status Flag */
935 Stm_Ip_ClearInterruptStatusFlag(instance, configPtr->hwChannel);
936 /*Set compare value to 0*/
937 Stm_Ip_SetCmpValue(instance, configPtr->hwChannel, 0U);
938 #if ( defined(STM_0_ISR_USED) || defined(STM_1_ISR_USED) || defined(STM_2_ISR_USED) || defined(STM_3_ISR_USED) || \
939 defined(STM_4_ISR_USED) || defined(STM_5_ISR_USED) || defined(STM_6_ISR_USED) || defined(STM_7_ISR_USED) || \
940 defined(STM_8_ISR_USED) || defined(STM_9_ISR_USED) || defined(STM_10_ISR_USED) || defined(STM_11_ISR_USED) || \
941 defined(STM_12_ISR_USED)|| defined(SMU_STM_0_ISR_USED) || defined(SMU_STM_2_ISR_USED) || \
942 defined(CE_STM_0_ISR_USED) || defined(CE_STM_1_ISR_USED) || defined(CE_STM_2_ISR_USED) || \
943 defined(RTU0_STM_0_ISR_USED) || defined(RTU0_STM_1_ISR_USED) || defined(RTU0_STM_2_ISR_USED) || defined(RTU0_STM_3_ISR_USED) || \
944 defined(RTU1_STM_0_ISR_USED) || defined(RTU1_STM_1_ISR_USED) || defined(RTU1_STM_2_ISR_USED) || defined(RTU1_STM_3_ISR_USED) || \
945 defined(RTU2_STM_0_ISR_USED) || defined(RTU2_STM_1_ISR_USED) || defined(RTU2_STM_2_ISR_USED) || defined(RTU2_STM_3_ISR_USED) || \
946 defined(RTU3_STM_0_ISR_USED) || defined(RTU3_STM_1_ISR_USED) || defined(RTU3_STM_2_ISR_USED) || defined(RTU3_STM_3_ISR_USED) || \
947 defined(CRS_STM_0_ISR_USED) || \
948 defined(RTU0_COS_STM_0_CH_0_ISR_USED) || defined(RTU0_COS_STM_0_CH_1_ISR_USED) || defined(RTU0_COS_STM_0_CH_2_ISR_USED) || defined(RTU0_COS_STM_0_CH_3_ISR_USED) || \
949 defined(RTU0_COS_STM_1_CH_0_ISR_USED) || defined(RTU0_COS_STM_1_CH_1_ISR_USED) || defined(RTU0_COS_STM_1_CH_2_ISR_USED) || defined(RTU0_COS_STM_1_CH_3_ISR_USED) || \
950 defined(RTU0_COS_STM_2_CH_0_ISR_USED) || defined(RTU0_COS_STM_2_CH_1_ISR_USED) || defined(RTU0_COS_STM_2_CH_2_ISR_USED) || defined(RTU0_COS_STM_2_CH_3_ISR_USED) || \
951 defined(RTU0_COS_STM_3_CH_0_ISR_USED) || defined(RTU0_COS_STM_3_CH_1_ISR_USED) || defined(RTU0_COS_STM_3_CH_2_ISR_USED) || defined(RTU0_COS_STM_3_CH_3_ISR_USED) || \
952 defined(RTU1_COS_STM_0_CH_0_ISR_USED) || defined(RTU1_COS_STM_0_CH_1_ISR_USED) || defined(RTU1_COS_STM_0_CH_2_ISR_USED) || defined(RTU1_COS_STM_0_CH_3_ISR_USED) || \
953 defined(RTU1_COS_STM_1_CH_0_ISR_USED) || defined(RTU1_COS_STM_1_CH_1_ISR_USED) || defined(RTU1_COS_STM_1_CH_2_ISR_USED) || defined(RTU1_COS_STM_1_CH_3_ISR_USED) || \
954 defined(RTU1_COS_STM_2_CH_0_ISR_USED) || defined(RTU1_COS_STM_2_CH_1_ISR_USED) || defined(RTU1_COS_STM_2_CH_2_ISR_USED) || defined(RTU1_COS_STM_2_CH_3_ISR_USED) || \
955 defined(RTU1_COS_STM_3_CH_0_ISR_USED) || defined(RTU1_COS_STM_3_CH_1_ISR_USED) || defined(RTU1_COS_STM_3_CH_2_ISR_USED) || defined(RTU1_COS_STM_3_CH_3_ISR_USED) || \
956 defined(RTU2_COS_STM_0_CH_0_ISR_USED) || defined(RTU2_COS_STM_0_CH_1_ISR_USED) || defined(RTU2_COS_STM_0_CH_2_ISR_USED) || defined(RTU2_COS_STM_0_CH_3_ISR_USED) || \
957 defined(RTU2_COS_STM_1_CH_0_ISR_USED) || defined(RTU2_COS_STM_1_CH_1_ISR_USED) || defined(RTU2_COS_STM_1_CH_2_ISR_USED) || defined(RTU2_COS_STM_1_CH_3_ISR_USED) || \
958 defined(RTU2_COS_STM_2_CH_0_ISR_USED) || defined(RTU2_COS_STM_2_CH_1_ISR_USED) || defined(RTU2_COS_STM_2_CH_2_ISR_USED) || defined(RTU2_COS_STM_2_CH_3_ISR_USED) || \
959 defined(RTU2_COS_STM_3_CH_0_ISR_USED) || defined(RTU2_COS_STM_3_CH_1_ISR_USED) || defined(RTU2_COS_STM_3_CH_2_ISR_USED) || defined(RTU2_COS_STM_3_CH_3_ISR_USED) || \
960 defined(RTU3_COS_STM_0_CH_0_ISR_USED) || defined(RTU3_COS_STM_0_CH_1_ISR_USED) || defined(RTU3_COS_STM_0_CH_2_ISR_USED) || defined(RTU3_COS_STM_0_CH_3_ISR_USED) || \
961 defined(RTU3_COS_STM_1_CH_0_ISR_USED) || defined(RTU3_COS_STM_1_CH_1_ISR_USED) || defined(RTU3_COS_STM_1_CH_2_ISR_USED) || defined(RTU3_COS_STM_1_CH_3_ISR_USED) || \
962 defined(RTU3_COS_STM_2_CH_0_ISR_USED) || defined(RTU3_COS_STM_2_CH_1_ISR_USED) || defined(RTU3_COS_STM_2_CH_2_ISR_USED) || defined(RTU3_COS_STM_2_CH_3_ISR_USED) || \
963 defined(RTU3_COS_STM_3_CH_0_ISR_USED) || defined(RTU3_COS_STM_3_CH_1_ISR_USED) || defined(RTU3_COS_STM_3_CH_2_ISR_USED) || defined(RTU3_COS_STM_3_CH_3_ISR_USED) )
964 Stm_Ip_u32ChState[instance][configPtr->hwChannel].chInit = TRUE;
965 Stm_Ip_u32ChState[instance][configPtr->hwChannel].callback = configPtr->callback;
966 Stm_Ip_u32ChState[instance][configPtr->hwChannel].callbackParam = configPtr->callbackParam;
967 Stm_Ip_u32ChState[instance][configPtr->hwChannel].channelMode = configPtr->channelMode;
968 #endif
969 }
970
971 /*================================================================================================*/
972 /**
973 * @brief Function Name : Stm_Ip_Deinit
974 * @details De-Initializes the STM module. This functions is called for each STM hw instance and:
975 * - resets all channels to default
976 * - sets to default prescaler bits
977 * - disables the STM counter
978 *
979 * @param[in] instance STM hw instance number
980 * @return void
981 * @pre The data structure including the configuration set required for initializing the GPT driver.
982 * @implements Stm_Ip_Deinit_Activity
983 */
Stm_Ip_Deinit(uint8 instance)984 void Stm_Ip_Deinit(uint8 instance)
985 {
986 #if STM_IP_DEV_ERROR_DETECT == STD_ON
987 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
988 #endif
989
990 uint8 channelIndex;
991
992 /* Reset all channels to default */
993 for (channelIndex = 0; channelIndex < STM_CHANNEL_COUNT; channelIndex++)
994 {
995 /* Disable Channel Interrupt */
996 Stm_Ip_SetInterruptEnableFlag(instance, channelIndex, FALSE);
997 /* Clear Channel Interrupt Status Flag */
998 Stm_Ip_ClearInterruptStatusFlag(instance, channelIndex);
999 /* Sets compare value to 0 */
1000 Stm_Ip_SetCmpValue(instance, channelIndex, 0x0U);
1001 }
1002
1003 /* Set to default prescaler bits */
1004 Stm_Ip_SetPrescaler(instance, 0x0U);
1005
1006 /* Disable counter */
1007 Stm_Ip_TimerEnable(instance, FALSE);
1008 }
1009
1010 /*================================================================================================*/
1011 /**
1012 * @brief Function Name : Stm_Ip_StartCounting
1013 * @details This function is called for starting the Stm timer channel
1014 * - reads the current counter register value and sets the compare register to the sum of
1015 * counter register value plus the timeout value
1016 * - enables the STM channel
1017 *
1018 * @param[in] instance STM hw instance number
1019 * @param[in] channel Stm channel
1020 * @param[in] compareValue Compare value
1021 * @return void
1022 * @pre The driver needs to be initialized. This function is called for starting the STM timer channel.
1023 * @implements Stm_Ip_StartCounting_Activity
1024 */
Stm_Ip_StartCounting(uint8 instance,uint8 channel,uint32 compareValue)1025 void Stm_Ip_StartCounting(uint8 instance, uint8 channel, uint32 compareValue)
1026 {
1027 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1028 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1029 DevAssert(STM_CHANNEL_COUNT > channel);
1030 #endif
1031
1032 uint32 currentCntValue;
1033
1034 /* enter critical section */
1035 SchM_Enter_Gpt_GPT_EXCLUSIVE_AREA_39();
1036 {
1037 currentCntValue = Stm_Ip_GetCntValue(instance);
1038 Stm_Ip_SetCmpValue(instance, channel, (currentCntValue + compareValue));
1039 }
1040 /* exit critical section */
1041 SchM_Exit_Gpt_GPT_EXCLUSIVE_AREA_39();
1042
1043 Stm_Ip_u32TargetValue[instance][channel] = compareValue;
1044
1045 /* Enable Channel Interrupt */
1046 Stm_Ip_SetInterruptEnableFlag(instance, channel, TRUE);
1047 }
1048 /*================================================================================================*/
1049 #if STM_IP_ABSOLUTE_COUNTING_API == STD_ON
1050 /**
1051 * @brief Function Name : Stm_Ip_StartCountingAbsolute
1052 * @details This function is called for starting the Stm timer channel
1053 * - sets the compare value without adding the current counter value to the timeout value
1054 * - enables the STM channel
1055 *
1056 * @param[in] instance STM hw instance number
1057 * @param[in] channel Stm channel
1058 * @param[in] compareValue Compare value
1059 * @return void
1060 * @pre The driver needs to be initialized. This function is called for starting the STM timer channel.
1061 * @implements Stm_Ip_StartCountingAbsolute_Activity
1062 */
Stm_Ip_StartCountingAbsolute(uint8 instance,uint8 channel,uint32 compareValue)1063 void Stm_Ip_StartCountingAbsolute(uint8 instance, uint8 channel, uint32 compareValue)
1064 {
1065 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1066 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1067 DevAssert(STM_CHANNEL_COUNT > channel);
1068 #endif
1069
1070 Stm_Ip_u32TargetValue[instance][channel] = 0U;
1071 Stm_Ip_SetCmpValue(instance, channel, compareValue);
1072 /* Enable Channel Interrupt */
1073 Stm_Ip_SetInterruptEnableFlag(instance, channel, TRUE);
1074 }
1075 #endif
1076 /*================================================================================================*/
1077 /**
1078 * @brief Function Name : Stm_Ip_StartTimer
1079 * @details This function is called for setting a new start counter value and enables the STM counter:
1080 * - sets the new counter value
1081 * - enables the STM counter
1082 *
1083 * @param[in] instance Stm hw instance
1084 * @param[in] startValue counter value
1085 * @return void
1086 * @pre The driver needs to be initialized. This function is called for starting the STM timer channel.
1087 * @implements Stm_Ip_StartTimer_Activity
1088 */
Stm_Ip_StartTimer(uint8 instance,uint32 startValue)1089 void Stm_Ip_StartTimer(uint8 instance, uint32 startValue)
1090 {
1091 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1092 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1093 #endif
1094
1095 Stm_Ip_SetCntValue(instance, startValue);
1096 Stm_Ip_TimerEnable(instance, TRUE);
1097 }
1098
1099 /*================================================================================================*/
1100 /**
1101 * @brief Function Name : Stm_Ip_StopTimer
1102 * @details Gpt driver function for stopping the Stm counter.
1103 * - disables the STM counter
1104 *
1105 * @param[in] instance Stm hw instance
1106 * @return void
1107 * @pre The driver needs to be initialized. This function is called for stoping the STM timer channel.
1108 * @implements Stm_Ip_StopTimer_Activity
1109 */
Stm_Ip_StopTimer(uint8 instance)1110 void Stm_Ip_StopTimer(uint8 instance)
1111 {
1112 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1113 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1114 #endif
1115
1116 Stm_Ip_TimerEnable(instance, FALSE);
1117 }
1118
1119 /*================================================================================================*/
1120 /**
1121 * @brief Function Name : Stm_Ip_EnableChannel
1122 * @details Enables the channel selected.
1123 *
1124 * @param[in] instance Stm hw instance
1125 * @param[in] channel Stm hw channel
1126 * @return void
1127 * @pre The driver needs to be initialized.
1128 * @implements Stm_Ip_EnableChannel_Activity
1129 */
Stm_Ip_EnableChannel(uint8 instance,uint8 channel)1130 void Stm_Ip_EnableChannel(uint8 instance, uint8 channel)
1131 {
1132 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1133 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1134 DevAssert(STM_CHANNEL_COUNT > channel);
1135 #endif
1136
1137 Stm_Ip_ClearInterruptStatusFlag(instance, channel);
1138 Stm_Ip_SetInterruptEnableFlag(instance, channel, TRUE);
1139 }
1140
1141 /*================================================================================================*/
1142 /**
1143 * @brief Function Name : Stm_Ip_DisableChannel
1144 * @details Disables the channel selected.
1145 *
1146 * @param[in] instance Stm hw instance
1147 * @param[in] channel Stm hw channel
1148 * @return void
1149 * @pre The driver needs to be initialized.
1150 * @implements Stm_Ip_DisableChannel_Activity
1151 */
Stm_Ip_DisableChannel(uint8 instance,uint8 channel)1152 void Stm_Ip_DisableChannel(uint8 instance, uint8 channel)
1153 {
1154 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1155 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1156 DevAssert(STM_CHANNEL_COUNT > channel);
1157 #endif
1158
1159 Stm_Ip_SetInterruptEnableFlag(instance, channel, FALSE);
1160 Stm_Ip_ClearInterruptStatusFlag(instance, channel);
1161 }
1162
1163 /*================================================================================================*/
1164 /**
1165 * @brief Function Name : Stm_Ip_GetCounterValue
1166 * @details Gets the counter value.
1167 *
1168 * @param[in] instance Stm hw instance
1169 *
1170 * @return currentCounterValue current counter value
1171 * @pre The driver needs to be initialized. This function is called for starting the STM timer channel.
1172 * @implements Stm_Ip_GetCounterValue_Activity
1173 */
Stm_Ip_GetCounterValue(uint8 instance)1174 uint32 Stm_Ip_GetCounterValue(uint8 instance)
1175 {
1176 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1177 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1178 #endif
1179
1180 uint32 currentCounterValue = 0;
1181
1182 currentCounterValue = Stm_Ip_GetCntValue(instance);
1183
1184 return currentCounterValue;
1185 }
1186
1187 /*================================================================================================*/
1188 /**
1189 * @brief Function Name : Stm_Ip_GetCompareValue
1190 * @details Gets the compare value for selected channel
1191 *
1192 * @param[in] instance Stm hw instance
1193 * @param[in] channel Stm hw channel
1194 *
1195 * @return currentCompareValue compare value for selected channel
1196 * @pre The driver needs to be initialized.
1197 * @implements Stm_Ip_GetCompareValue_Activity
1198 */
Stm_Ip_GetCompareValue(uint8 instance,uint8 channel)1199 uint32 Stm_Ip_GetCompareValue(uint8 instance, uint8 channel)
1200 {
1201 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1202 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1203 DevAssert(STM_CHANNEL_COUNT > channel);
1204 #endif
1205
1206 uint32 currentCompareValue = 0;
1207
1208 currentCompareValue = Stm_Ip_GetCmpValue(instance, channel);
1209
1210 return currentCompareValue;
1211 }
1212
1213 #if (STM_IP_CHANGE_NEXT_TIMEOUT_VALUE == STD_ON)
1214 /*================================================================================================*/
1215 /**
1216 * @brief The function changes the Stm compare register value.
1217 * @details This function:
1218 * - Write next timeout to local variable
1219 *
1220 * @param[in] instance Stm hw instance
1221 * @param[in] channel Channel
1222 * @param[in] value Channel timeout value
1223 * @return void
1224 * @pre The driver needs to be initialized.
1225 * @implements Stm_Ip_ChangeNextTimeoutValue_Activity
1226 */
Stm_Ip_ChangeNextTimeoutValue(uint8 instance,uint8 channel,uint32 value)1227 void Stm_Ip_ChangeNextTimeoutValue(uint8 instance, uint8 channel, uint32 value)
1228 {
1229 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1230 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1231 DevAssert(STM_CHANNEL_COUNT > channel);
1232 #endif
1233 #if ( defined(STM_0_ISR_USED) || defined(STM_1_ISR_USED) || defined(STM_2_ISR_USED) || defined(STM_3_ISR_USED) || \
1234 defined(STM_4_ISR_USED) || defined(STM_5_ISR_USED) || defined(STM_6_ISR_USED) || defined(STM_7_ISR_USED) || \
1235 defined(STM_8_ISR_USED) || defined(STM_9_ISR_USED) || defined(STM_10_ISR_USED) || defined(STM_11_ISR_USED) || \
1236 defined(STM_12_ISR_USED)|| defined(SMU_STM_0_ISR_USED) || defined(SMU_STM_2_ISR_USED) || \
1237 defined(CE_STM_0_ISR_USED) || defined(CE_STM_1_ISR_USED) || defined(CE_STM_2_ISR_USED) || \
1238 defined(RTU0_STM_0_ISR_USED) || defined(RTU0_STM_1_ISR_USED) || defined(RTU0_STM_2_ISR_USED) || defined(RTU0_STM_3_ISR_USED) || \
1239 defined(RTU1_STM_0_ISR_USED) || defined(RTU1_STM_1_ISR_USED) || defined(RTU1_STM_2_ISR_USED) || defined(RTU1_STM_3_ISR_USED) || \
1240 defined(RTU2_STM_0_ISR_USED) || defined(RTU2_STM_1_ISR_USED) || defined(RTU2_STM_2_ISR_USED) || defined(RTU2_STM_3_ISR_USED) || \
1241 defined(RTU3_STM_0_ISR_USED) || defined(RTU3_STM_1_ISR_USED) || defined(RTU3_STM_2_ISR_USED) || defined(RTU3_STM_3_ISR_USED) || \
1242 defined(CRS_STM_0_ISR_USED) || \
1243 defined(RTU0_COS_STM_0_CH_0_ISR_USED) || defined(RTU0_COS_STM_0_CH_1_ISR_USED) || defined(RTU0_COS_STM_0_CH_2_ISR_USED) || defined(RTU0_COS_STM_0_CH_3_ISR_USED) || \
1244 defined(RTU0_COS_STM_1_CH_0_ISR_USED) || defined(RTU0_COS_STM_1_CH_1_ISR_USED) || defined(RTU0_COS_STM_1_CH_2_ISR_USED) || defined(RTU0_COS_STM_1_CH_3_ISR_USED) || \
1245 defined(RTU0_COS_STM_2_CH_0_ISR_USED) || defined(RTU0_COS_STM_2_CH_1_ISR_USED) || defined(RTU0_COS_STM_2_CH_2_ISR_USED) || defined(RTU0_COS_STM_2_CH_3_ISR_USED) || \
1246 defined(RTU0_COS_STM_3_CH_0_ISR_USED) || defined(RTU0_COS_STM_3_CH_1_ISR_USED) || defined(RTU0_COS_STM_3_CH_2_ISR_USED) || defined(RTU0_COS_STM_3_CH_3_ISR_USED) || \
1247 defined(RTU1_COS_STM_0_CH_0_ISR_USED) || defined(RTU1_COS_STM_0_CH_1_ISR_USED) || defined(RTU1_COS_STM_0_CH_2_ISR_USED) || defined(RTU1_COS_STM_0_CH_3_ISR_USED) || \
1248 defined(RTU1_COS_STM_1_CH_0_ISR_USED) || defined(RTU1_COS_STM_1_CH_1_ISR_USED) || defined(RTU1_COS_STM_1_CH_2_ISR_USED) || defined(RTU1_COS_STM_1_CH_3_ISR_USED) || \
1249 defined(RTU1_COS_STM_2_CH_0_ISR_USED) || defined(RTU1_COS_STM_2_CH_1_ISR_USED) || defined(RTU1_COS_STM_2_CH_2_ISR_USED) || defined(RTU1_COS_STM_2_CH_3_ISR_USED) || \
1250 defined(RTU1_COS_STM_3_CH_0_ISR_USED) || defined(RTU1_COS_STM_3_CH_1_ISR_USED) || defined(RTU1_COS_STM_3_CH_2_ISR_USED) || defined(RTU1_COS_STM_3_CH_3_ISR_USED) || \
1251 defined(RTU2_COS_STM_0_CH_0_ISR_USED) || defined(RTU2_COS_STM_0_CH_1_ISR_USED) || defined(RTU2_COS_STM_0_CH_2_ISR_USED) || defined(RTU2_COS_STM_0_CH_3_ISR_USED) || \
1252 defined(RTU2_COS_STM_1_CH_0_ISR_USED) || defined(RTU2_COS_STM_1_CH_1_ISR_USED) || defined(RTU2_COS_STM_1_CH_2_ISR_USED) || defined(RTU2_COS_STM_1_CH_3_ISR_USED) || \
1253 defined(RTU2_COS_STM_2_CH_0_ISR_USED) || defined(RTU2_COS_STM_2_CH_1_ISR_USED) || defined(RTU2_COS_STM_2_CH_2_ISR_USED) || defined(RTU2_COS_STM_2_CH_3_ISR_USED) || \
1254 defined(RTU2_COS_STM_3_CH_0_ISR_USED) || defined(RTU2_COS_STM_3_CH_1_ISR_USED) || defined(RTU2_COS_STM_3_CH_2_ISR_USED) || defined(RTU2_COS_STM_3_CH_3_ISR_USED) || \
1255 defined(RTU3_COS_STM_0_CH_0_ISR_USED) || defined(RTU3_COS_STM_0_CH_1_ISR_USED) || defined(RTU3_COS_STM_0_CH_2_ISR_USED) || defined(RTU3_COS_STM_0_CH_3_ISR_USED) || \
1256 defined(RTU3_COS_STM_1_CH_0_ISR_USED) || defined(RTU3_COS_STM_1_CH_1_ISR_USED) || defined(RTU3_COS_STM_1_CH_2_ISR_USED) || defined(RTU3_COS_STM_1_CH_3_ISR_USED) || \
1257 defined(RTU3_COS_STM_2_CH_0_ISR_USED) || defined(RTU3_COS_STM_2_CH_1_ISR_USED) || defined(RTU3_COS_STM_2_CH_2_ISR_USED) || defined(RTU3_COS_STM_2_CH_3_ISR_USED) || \
1258 defined(RTU3_COS_STM_3_CH_0_ISR_USED) || defined(RTU3_COS_STM_3_CH_1_ISR_USED) || defined(RTU3_COS_STM_3_CH_2_ISR_USED) || defined(RTU3_COS_STM_3_CH_3_ISR_USED) )
1259
1260 /* Update the target time value to be used on next cycle */
1261 Stm_Ip_u32NextTargetValue[instance][channel] = value;
1262 #endif
1263 }
1264 #endif
1265
1266 #if (STM_IP_SET_CLOCK_MODE == STD_ON)
1267 /*================================================================================================*/
1268 /**
1269 * @brief The function changes the STM prescaler value.
1270 * @details This function sets the STM prescaler based on the input mode.
1271 *
1272 * @param[in] instance Stm hw instance
1273 * @param[in] clockMode STM_IP_CLOCKMODE_NORMAL or STM_IP_CLOCKMODE_ALTERNATE
1274 *
1275 * @return void
1276 * @pre The driver needs to be initialized. On/Off by the configuration parameter: GPT_DUAL_CLOCK_MODE
1277 * @implements Stm_Ip_SetClockMode_Activity
1278 */
Stm_Ip_SetClockMode(uint8 instance,Stm_Ip_ClockModeType clockMode)1279 void Stm_Ip_SetClockMode(uint8 instance, Stm_Ip_ClockModeType clockMode)
1280 {
1281 #if STM_IP_DEV_ERROR_DETECT == STD_ON
1282 DevAssert(GPT_STM_INSTANCE_COUNT > instance);
1283 #endif
1284
1285 if(STM_IP_CLOCKMODE_NORMAL == clockMode)
1286 {
1287 Stm_Ip_SetPrescaler(instance, Stm_Ip_u32InstanceState[instance].clockPrescaler);
1288 }
1289 else
1290 {
1291 Stm_Ip_SetPrescaler(instance, Stm_Ip_u32InstanceState[instance].clockAlternatePrescaler);
1292 }
1293
1294 }
1295 #endif
1296
1297 /*================================================================================================*/
1298 /**
1299 * @brief This function sets the STM prescaler, freeze bit and enables counter
1300 * @details This function start counting with predefined values(like a free running timer)
1301 *
1302 * @param[in] instance Stm hw instance
1303 * @param[in] prescaler Prescaler value
1304 * @param[in] freezeEnable Freeze value
1305 * @return void
1306 * @pre The driver needs to be initialized
1307 * @implements Stm_Ip_PredefCounting_Activity
1308 */
Stm_Ip_PredefCounting(uint8 instance,uint8 prescaler,boolean freezeEnable)1309 void Stm_Ip_PredefCounting(uint8 instance, uint8 prescaler, boolean freezeEnable)
1310 {
1311 /* Enable register access from user mode, if enabled from configuration file */
1312 Call_Stm_Ip_SetUserAccessAllowed((uint32)stmBase[instance]);
1313 /* check if the timer is not enabled - TEN bit*/
1314 if(1U != Stm_Ip_GetTimerEnableBit(instance))
1315 {
1316 /* clear counter */
1317 Stm_Ip_SetCntValue(instance, 0x0000U);
1318 /* Set prescaler for stm timer */
1319 Stm_Ip_SetPrescaler(instance, prescaler);
1320 if (TRUE == freezeEnable)
1321 {
1322 Stm_Ip_SetDebugMode(instance, TRUE);
1323 }
1324 else
1325 {
1326 Stm_Ip_SetDebugMode(instance, FALSE);
1327 }
1328 /*Enable counting*/
1329 Stm_Ip_TimerEnable(instance, TRUE);
1330 }
1331 }
1332
1333 #if ((STD_ON == STM_GPT_IP_MODULE_SINGLE_INTERRUPT) || (STD_ON == STM_GPT_IP_MODULE_SINGLE_AND_MULTIPLE_INTERRUPTS))
1334
1335 #if defined(RTU0_STM_0_ISR_USED)
1336 /**
1337 * @brief Interrupt handler for STM channels.
1338 * @details Interrupt Service Routine corresponding to common RTU0_STM_0 module.
1339 * @param[in] none
1340 * @return none
1341 * @isr
1342 * @pre The driver needs to be initialized.
1343 */
ISR(RTU0_STM_0_ISR)1344 ISR(RTU0_STM_0_ISR){
1345 uint8 channel;
1346 #if defined(RTU0_STM_0_IP_EXISTS)
1347 uint8 instance = RTU0_STM_0_IP_INSTANCE_NUMBER;
1348 #else
1349 #error "undefined STM instance number"
1350 #endif
1351 for (channel = 0U; channel < RTU0_STM_0_IP_CHANNELS_NUMBER; ++channel)
1352 {
1353 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1354 }
1355 }
1356 #endif
1357
1358 #if defined(RTU0_STM_1_ISR_USED)
1359 /**
1360 * @brief Interrupt handler for STM channels.
1361 * @details Interrupt Service Routine corresponding to common RTU0_STM_1 module.
1362 * @param[in] none
1363 * @return none
1364 * @isr
1365 * @pre The driver needs to be initialized.
1366 */
ISR(RTU0_STM_1_ISR)1367 ISR(RTU0_STM_1_ISR){
1368 uint8 channel;
1369 #if defined(RTU0_STM_1_IP_EXISTS)
1370 uint8 instance = RTU0_STM_1_IP_INSTANCE_NUMBER;
1371 #else
1372 #error "undefined STM instance number"
1373 #endif
1374 for (channel = 0U; channel < RTU0_STM_1_IP_CHANNELS_NUMBER; ++channel)
1375 {
1376 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1377 }
1378 }
1379 #endif
1380
1381 #if defined(RTU0_STM_2_ISR_USED)
1382 /**
1383 * @brief Interrupt handler for STM channels.
1384 * @details Interrupt Service Routine corresponding to common RTU0_STM_2 module.
1385 * @param[in] none
1386 * @return none
1387 * @isr
1388 * @pre The driver needs to be initialized.
1389 */
ISR(RTU0_STM_2_ISR)1390 ISR(RTU0_STM_2_ISR){
1391 uint8 channel;
1392 #if defined(RTU0_STM_2_IP_EXISTS)
1393 uint8 instance = RTU0_STM_2_IP_INSTANCE_NUMBER;
1394 #else
1395 #error "undefined STM instance number"
1396 #endif
1397 for (channel = 0U; channel < RTU0_STM_2_IP_CHANNELS_NUMBER; ++channel)
1398 {
1399 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1400 }
1401 }
1402 #endif
1403
1404 #if defined(RTU0_STM_3_ISR_USED)
1405 /**
1406 * @brief Interrupt handler for STM channels.
1407 * @details Interrupt Service Routine corresponding to common RTU0_STM_3 module.
1408 * @param[in] none
1409 * @return none
1410 * @isr
1411 * @pre The driver needs to be initialized.
1412 */
ISR(RTU0_STM_3_ISR)1413 ISR(RTU0_STM_3_ISR){
1414 uint8 channel;
1415 #if defined(RTU0_STM_3_IP_EXISTS)
1416 uint8 instance = RTU0_STM_3_IP_INSTANCE_NUMBER;
1417 #else
1418 #error "undefined STM instance number"
1419 #endif
1420 for (channel = 0U; channel < RTU0_STM_3_IP_CHANNELS_NUMBER; ++channel)
1421 {
1422 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1423 }
1424 }
1425 #endif
1426
1427 #if defined(RTU1_STM_0_ISR_USED)
1428 /**
1429 * @brief Interrupt handler for STM channels.
1430 * @details Interrupt Service Routine corresponding to common RTU1_STM_0 module.
1431 * @param[in] none
1432 * @return none
1433 * @isr
1434 * @pre The driver needs to be initialized.
1435 */
ISR(RTU1_STM_0_ISR)1436 ISR(RTU1_STM_0_ISR){
1437 uint8 channel;
1438 #if defined(RTU1_STM_0_IP_EXISTS)
1439 uint8 instance = RTU1_STM_0_IP_INSTANCE_NUMBER;
1440 #else
1441 #error "undefined STM instance number"
1442 #endif
1443 for (channel = 0U; channel < RTU1_STM_0_IP_CHANNELS_NUMBER; ++channel)
1444 {
1445 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1446 }
1447 }
1448 #endif
1449
1450 #if defined(RTU1_STM_1_ISR_USED)
1451 /**
1452 * @brief Interrupt handler for STM channels.
1453 * @details Interrupt Service Routine corresponding to common RTU1_STM_1 module.
1454 * @param[in] none
1455 * @return none
1456 * @isr
1457 * @pre The driver needs to be initialized.
1458 */
ISR(RTU1_STM_1_ISR)1459 ISR(RTU1_STM_1_ISR){
1460 uint8 channel;
1461 #if defined(RTU1_STM_1_IP_EXISTS)
1462 uint8 instance = RTU1_STM_1_IP_INSTANCE_NUMBER;
1463 #else
1464 #error "undefined STM instance number"
1465 #endif
1466 for (channel = 0U; channel < RTU1_STM_1_IP_CHANNELS_NUMBER; ++channel)
1467 {
1468 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1469 }
1470 }
1471 #endif
1472
1473 #if defined(RTU1_STM_2_ISR_USED)
1474 /**
1475 * @brief Interrupt handler for STM channels.
1476 * @details Interrupt Service Routine corresponding to common RTU1_STM_2 module.
1477 * @param[in] none
1478 * @return none
1479 * @isr
1480 * @pre The driver needs to be initialized.
1481 */
ISR(RTU1_STM_2_ISR)1482 ISR(RTU1_STM_2_ISR){
1483 uint8 channel;
1484 #if defined(RTU1_STM_2_IP_EXISTS)
1485 uint8 instance = RTU1_STM_2_IP_INSTANCE_NUMBER;
1486 #else
1487 #error "undefined STM instance number"
1488 #endif
1489 for (channel = 0U; channel < RTU1_STM_2_IP_CHANNELS_NUMBER; ++channel)
1490 {
1491 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1492 }
1493 }
1494 #endif
1495
1496 #if defined(RTU1_STM_3_ISR_USED)
1497 /**
1498 * @brief Interrupt handler for STM channels.
1499 * @details Interrupt Service Routine corresponding to common RTU1_STM_3 module.
1500 * @param[in] none
1501 * @return none
1502 * @isr
1503 * @pre The driver needs to be initialized.
1504 */
ISR(RTU1_STM_3_ISR)1505 ISR(RTU1_STM_3_ISR){
1506 uint8 channel;
1507 #if defined(RTU1_STM_3_IP_EXISTS)
1508 uint8 instance = RTU1_STM_3_IP_INSTANCE_NUMBER;
1509 #else
1510 #error "undefined STM instance number"
1511 #endif
1512 for (channel = 0U; channel < RTU1_STM_3_IP_CHANNELS_NUMBER; ++channel)
1513 {
1514 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1515 }
1516 }
1517 #endif
1518
1519 #if defined(RTU2_STM_0_ISR_USED)
1520 /**
1521 * @brief Interrupt handler for STM channels.
1522 * @details Interrupt Service Routine corresponding to common RTU2_STM_0 module.
1523 * @param[in] none
1524 * @return none
1525 * @isr
1526 * @pre The driver needs to be initialized.
1527 */
ISR(RTU2_STM_0_ISR)1528 ISR(RTU2_STM_0_ISR){
1529 uint8 channel;
1530 #if defined(RTU2_STM_0_IP_EXISTS)
1531 uint8 instance = RTU2_STM_0_IP_INSTANCE_NUMBER;
1532 #else
1533 #error "undefined STM instance number"
1534 #endif
1535 for (channel = 0U; channel < RTU2_STM_0_IP_CHANNELS_NUMBER; ++channel)
1536 {
1537 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1538 }
1539 }
1540 #endif
1541
1542 #if defined(RTU2_STM_1_ISR_USED)
1543 /**
1544 * @brief Interrupt handler for STM channels.
1545 * @details Interrupt Service Routine corresponding to common RTU2_STM_1 module.
1546 * @param[in] none
1547 * @return none
1548 * @isr
1549 * @pre The driver needs to be initialized.
1550 */
ISR(RTU2_STM_1_ISR)1551 ISR(RTU2_STM_1_ISR){
1552 uint8 channel;
1553 #if defined(RTU2_STM_1_IP_EXISTS)
1554 uint8 instance = RTU2_STM_1_IP_INSTANCE_NUMBER;
1555 #else
1556 #error "undefined STM instance number"
1557 #endif
1558 for (channel = 0U; channel < RTU2_STM_1_IP_CHANNELS_NUMBER; ++channel)
1559 {
1560 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1561 }
1562 }
1563 #endif
1564
1565 #if defined(RTU2_STM_2_ISR_USED)
1566 /**
1567 * @brief Interrupt handler for STM channels.
1568 * @details Interrupt Service Routine corresponding to common RTU2_STM_2 module.
1569 * @param[in] none
1570 * @return none
1571 * @isr
1572 * @pre The driver needs to be initialized.
1573 */
ISR(RTU2_STM_2_ISR)1574 ISR(RTU2_STM_2_ISR){
1575 uint8 channel;
1576 #if defined(RTU2_STM_2_IP_EXISTS)
1577 uint8 instance = RTU2_STM_2_IP_INSTANCE_NUMBER;
1578 #else
1579 #error "undefined STM instance number"
1580 #endif
1581 for (channel = 0U; channel < RTU2_STM_2_IP_CHANNELS_NUMBER; ++channel)
1582 {
1583 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1584 }
1585 }
1586 #endif
1587
1588 #if defined(RTU2_STM_3_ISR_USED)
1589 /**
1590 * @brief Interrupt handler for STM channels.
1591 * @details Interrupt Service Routine corresponding to common RTU2_STM_3 module.
1592 * @param[in] none
1593 * @return none
1594 * @isr
1595 * @pre The driver needs to be initialized.
1596 */
ISR(RTU2_STM_3_ISR)1597 ISR(RTU2_STM_3_ISR){
1598 uint8 channel;
1599 #if defined(RTU2_STM_3_IP_EXISTS)
1600 uint8 instance = RTU2_STM_3_IP_INSTANCE_NUMBER;
1601 #else
1602 #error "undefined STM instance number"
1603 #endif
1604 for (channel = 0U; channel < RTU2_STM_3_IP_CHANNELS_NUMBER; ++channel)
1605 {
1606 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1607 }
1608 }
1609 #endif
1610
1611 #if defined(RTU3_STM_0_ISR_USED)
1612 /**
1613 * @brief Interrupt handler for STM channels.
1614 * @details Interrupt Service Routine corresponding to common RTU3_STM_0 module.
1615 * @param[in] none
1616 * @return none
1617 * @isr
1618 * @pre The driver needs to be initialized.
1619 */
ISR(RTU3_STM_0_ISR)1620 ISR(RTU3_STM_0_ISR){
1621 uint8 channel;
1622 #if defined(RTU3_STM_0_IP_EXISTS)
1623 uint8 instance = RTU3_STM_0_IP_INSTANCE_NUMBER;
1624 #else
1625 #error "undefined STM instance number"
1626 #endif
1627 for (channel = 0U; channel < RTU3_STM_0_IP_CHANNELS_NUMBER; ++channel)
1628 {
1629 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1630 }
1631 }
1632 #endif
1633
1634 #if defined(RTU3_STM_1_ISR_USED)
1635 /**
1636 * @brief Interrupt handler for STM channels.
1637 * @details Interrupt Service Routine corresponding to common RTU3_STM_1 module.
1638 * @param[in] none
1639 * @return none
1640 * @isr
1641 * @pre The driver needs to be initialized.
1642 */
ISR(RTU3_STM_1_ISR)1643 ISR(RTU3_STM_1_ISR){
1644 uint8 channel;
1645 #if defined(RTU3_STM_1_IP_EXISTS)
1646 uint8 instance = RTU3_STM_1_IP_INSTANCE_NUMBER;
1647 #else
1648 #error "undefined STM instance number"
1649 #endif
1650 for (channel = 0U; channel < RTU3_STM_1_IP_CHANNELS_NUMBER; ++channel)
1651 {
1652 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1653 }
1654 }
1655 #endif
1656
1657 #if defined(RTU3_STM_2_ISR_USED)
1658 /**
1659 * @brief Interrupt handler for STM channels.
1660 * @details Interrupt Service Routine corresponding to common RTU3_STM_2 module.
1661 * @param[in] none
1662 * @return none
1663 * @isr
1664 * @pre The driver needs to be initialized.
1665 */
ISR(RTU3_STM_2_ISR)1666 ISR(RTU3_STM_2_ISR){
1667 uint8 channel;
1668 #if defined(RTU3_STM_2_IP_EXISTS)
1669 uint8 instance = RTU3_STM_2_IP_INSTANCE_NUMBER;
1670 #else
1671 #error "undefined STM instance number"
1672 #endif
1673 for (channel = 0U; channel < RTU3_STM_2_IP_CHANNELS_NUMBER; ++channel)
1674 {
1675 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1676 }
1677 }
1678 #endif
1679
1680 #if defined(RTU3_STM_3_ISR_USED)
1681 /**
1682 * @brief Interrupt handler for STM channels.
1683 * @details Interrupt Service Routine corresponding to common RTU3_STM_3 module.
1684 * @param[in] none
1685 * @return none
1686 * @isr
1687 * @pre The driver needs to be initialized.
1688 */
ISR(RTU3_STM_3_ISR)1689 ISR(RTU3_STM_3_ISR){
1690 uint8 channel;
1691 #if defined(RTU3_STM_3_IP_EXISTS)
1692 uint8 instance = RTU3_STM_3_IP_INSTANCE_NUMBER;
1693 #else
1694 #error "undefined STM instance number"
1695 #endif
1696 for (channel = 0U; channel < RTU3_STM_3_IP_CHANNELS_NUMBER; ++channel)
1697 {
1698 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1699 }
1700 }
1701 #endif
1702
1703 #if (STD_ON == STM_GPT_IP_MODULE_SINGLE_AND_MULTIPLE_INTERRUPTS)
1704
1705 #if defined(CRS_STM_0_ISR_USED)
1706 /**
1707 * @brief Interrupt handler for STM channels.
1708 * @details Interrupt Service Routine corresponding to common CRS_STM_0 module.
1709 * @param[in] none
1710 * @return none
1711 * @isr
1712 * @pre The driver needs to be initialized.
1713 */
ISR(CRS_STM_0_ISR)1714 ISR(CRS_STM_0_ISR){
1715 uint8 channel;
1716 #if defined(CRS_STM_0_IP_EXISTS)
1717 uint8 instance = CRS_STM_0_IP_INSTANCE_NUMBER;
1718 #else
1719 #error "undefined STM instance number"
1720 #endif
1721 for (channel = 0U; channel < CRS_STM_0_IP_CHANNELS_NUMBER; ++channel)
1722 {
1723 Stm_Ip_ProcessCommonInterrupt(instance, channel);
1724 }
1725 }
1726 #endif
1727
1728 #if defined(RTU0_COS_STM_0_CH_0_ISR_USED)
ISR(RTU0_COS_STM_0_CH_0_ISR)1729 ISR(RTU0_COS_STM_0_CH_0_ISR){
1730 uint8 channel = 0U;
1731 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1732 }
1733 #endif
1734 #if defined(RTU0_COS_STM_0_CH_1_ISR_USED)
ISR(RTU0_COS_STM_0_CH_1_ISR)1735 ISR(RTU0_COS_STM_0_CH_1_ISR){
1736 uint8 channel = 1U;
1737 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1738 }
1739 #endif
1740 #if defined(RTU0_COS_STM_0_CH_2_ISR_USED)
ISR(RTU0_COS_STM_0_CH_2_ISR)1741 ISR(RTU0_COS_STM_0_CH_2_ISR){
1742 uint8 channel = 2U;
1743 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1744 }
1745 #endif
1746 #if defined(RTU0_COS_STM_0_CH_3_ISR_USED)
ISR(RTU0_COS_STM_0_CH_3_ISR)1747 ISR(RTU0_COS_STM_0_CH_3_ISR){
1748 uint8 channel = 3U;
1749 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1750 }
1751 #endif
1752 #if defined(RTU0_COS_STM_1_CH_0_ISR_USED)
ISR(RTU0_COS_STM_1_CH_0_ISR)1753 ISR(RTU0_COS_STM_1_CH_0_ISR){
1754 uint8 channel = 0U;
1755 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1756 }
1757 #endif
1758 #if defined(RTU0_COS_STM_1_CH_1_ISR_USED)
ISR(RTU0_COS_STM_1_CH_1_ISR)1759 ISR(RTU0_COS_STM_1_CH_1_ISR){
1760 uint8 channel = 1U;
1761 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1762 }
1763 #endif
1764 #if defined(RTU0_COS_STM_1_CH_2_ISR_USED)
ISR(RTU0_COS_STM_1_CH_2_ISR)1765 ISR(RTU0_COS_STM_1_CH_2_ISR){
1766 uint8 channel = 2U;
1767 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1768 }
1769 #endif
1770 #if defined(RTU0_COS_STM_1_CH_3_ISR_USED)
ISR(RTU0_COS_STM_1_CH_3_ISR)1771 ISR(RTU0_COS_STM_1_CH_3_ISR){
1772 uint8 channel = 3U;
1773 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1774 }
1775 #endif
1776 #if defined(RTU0_COS_STM_2_CH_0_ISR_USED)
ISR(RTU0_COS_STM_2_CH_0_ISR)1777 ISR(RTU0_COS_STM_2_CH_0_ISR){
1778 uint8 channel = 0U;
1779 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1780 }
1781 #endif
1782 #if defined(RTU0_COS_STM_2_CH_1_ISR_USED)
ISR(RTU0_COS_STM_2_CH_1_ISR)1783 ISR(RTU0_COS_STM_2_CH_1_ISR){
1784 uint8 channel = 1U;
1785 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1786 }
1787 #endif
1788 #if defined(RTU0_COS_STM_2_CH_2_ISR_USED)
ISR(RTU0_COS_STM_2_CH_2_ISR)1789 ISR(RTU0_COS_STM_2_CH_2_ISR){
1790 uint8 channel = 2U;
1791 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1792 }
1793 #endif
1794 #if defined(RTU0_COS_STM_2_CH_3_ISR_USED)
ISR(RTU0_COS_STM_2_CH_3_ISR)1795 ISR(RTU0_COS_STM_2_CH_3_ISR){
1796 uint8 channel = 3U;
1797 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1798 }
1799 #endif
1800 #if defined(RTU0_COS_STM_3_CH_0_ISR_USED)
ISR(RTU0_COS_STM_3_CH_0_ISR)1801 ISR(RTU0_COS_STM_3_CH_0_ISR){
1802 uint8 channel = 0U;
1803 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1804 }
1805 #endif
1806 #if defined(RTU0_COS_STM_3_CH_1_ISR_USED)
ISR(RTU0_COS_STM_3_CH_1_ISR)1807 ISR(RTU0_COS_STM_3_CH_1_ISR){
1808 uint8 channel = 1U;
1809 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1810 }
1811 #endif
1812 #if defined(RTU0_COS_STM_3_CH_2_ISR_USED)
ISR(RTU0_COS_STM_3_CH_2_ISR)1813 ISR(RTU0_COS_STM_3_CH_2_ISR){
1814 uint8 channel = 2U;
1815 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1816 }
1817 #endif
1818 #if defined(RTU0_COS_STM_3_CH_3_ISR_USED)
ISR(RTU0_COS_STM_3_CH_3_ISR)1819 ISR(RTU0_COS_STM_3_CH_3_ISR){
1820 uint8 channel = 3U;
1821 Stm_Ip_ProcessCommonInterrupt(RTU0_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1822 }
1823 #endif
1824 #if defined(RTU1_COS_STM_0_CH_0_ISR_USED)
ISR(RTU1_COS_STM_0_CH_0_ISR)1825 ISR(RTU1_COS_STM_0_CH_0_ISR){
1826 uint8 channel = 0U;
1827 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1828 }
1829 #endif
1830 #if defined(RTU1_COS_STM_0_CH_1_ISR_USED)
ISR(RTU1_COS_STM_0_CH_1_ISR)1831 ISR(RTU1_COS_STM_0_CH_1_ISR){
1832 uint8 channel = 1U;
1833 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1834 }
1835 #endif
1836 #if defined(RTU1_COS_STM_0_CH_2_ISR_USED)
ISR(RTU1_COS_STM_0_CH_2_ISR)1837 ISR(RTU1_COS_STM_0_CH_2_ISR){
1838 uint8 channel = 2U;
1839 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1840 }
1841 #endif
1842 #if defined(RTU1_COS_STM_0_CH_3_ISR_USED)
ISR(RTU1_COS_STM_0_CH_3_ISR)1843 ISR(RTU1_COS_STM_0_CH_3_ISR){
1844 uint8 channel = 3U;
1845 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1846 }
1847 #endif
1848 #if defined(RTU1_COS_STM_1_CH_0_ISR_USED)
ISR(RTU1_COS_STM_1_CH_0_ISR)1849 ISR(RTU1_COS_STM_1_CH_0_ISR){
1850 uint8 channel = 0U;
1851 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1852 }
1853 #endif
1854 #if defined(RTU1_COS_STM_1_CH_1_ISR_USED)
ISR(RTU1_COS_STM_1_CH_1_ISR)1855 ISR(RTU1_COS_STM_1_CH_1_ISR){
1856 uint8 channel = 1U;
1857 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1858 }
1859 #endif
1860 #if defined(RTU1_COS_STM_1_CH_2_ISR_USED)
ISR(RTU1_COS_STM_1_CH_2_ISR)1861 ISR(RTU1_COS_STM_1_CH_2_ISR){
1862 uint8 channel = 2U;
1863 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1864 }
1865 #endif
1866 #if defined(RTU1_COS_STM_1_CH_3_ISR_USED)
ISR(RTU1_COS_STM_1_CH_3_ISR)1867 ISR(RTU1_COS_STM_1_CH_3_ISR){
1868 uint8 channel = 3U;
1869 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1870 }
1871 #endif
1872 #if defined(RTU1_COS_STM_2_CH_0_ISR_USED)
ISR(RTU1_COS_STM_2_CH_0_ISR)1873 ISR(RTU1_COS_STM_2_CH_0_ISR){
1874 uint8 channel = 0U;
1875 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1876 }
1877 #endif
1878 #if defined(RTU1_COS_STM_2_CH_1_ISR_USED)
ISR(RTU1_COS_STM_2_CH_1_ISR)1879 ISR(RTU1_COS_STM_2_CH_1_ISR){
1880 uint8 channel = 1U;
1881 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1882 }
1883 #endif
1884 #if defined(RTU1_COS_STM_2_CH_2_ISR_USED)
ISR(RTU1_COS_STM_2_CH_2_ISR)1885 ISR(RTU1_COS_STM_2_CH_2_ISR){
1886 uint8 channel = 2U;
1887 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1888 }
1889 #endif
1890 #if defined(RTU1_COS_STM_2_CH_3_ISR_USED)
ISR(RTU1_COS_STM_2_CH_3_ISR)1891 ISR(RTU1_COS_STM_2_CH_3_ISR){
1892 uint8 channel = 3U;
1893 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1894 }
1895 #endif
1896 #if defined(RTU1_COS_STM_3_CH_0_ISR_USED)
ISR(RTU1_COS_STM_3_CH_0_ISR)1897 ISR(RTU1_COS_STM_3_CH_0_ISR){
1898 uint8 channel = 0U;
1899 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1900 }
1901 #endif
1902 #if defined(RTU1_COS_STM_3_CH_1_ISR_USED)
ISR(RTU1_COS_STM_3_CH_1_ISR)1903 ISR(RTU1_COS_STM_3_CH_1_ISR){
1904 uint8 channel = 1U;
1905 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1906 }
1907 #endif
1908 #if defined(RTU1_COS_STM_3_CH_2_ISR_USED)
ISR(RTU1_COS_STM_3_CH_2_ISR)1909 ISR(RTU1_COS_STM_3_CH_2_ISR){
1910 uint8 channel = 2U;
1911 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1912 }
1913 #endif
1914 #if defined(RTU1_COS_STM_3_CH_3_ISR_USED)
ISR(RTU1_COS_STM_3_CH_3_ISR)1915 ISR(RTU1_COS_STM_3_CH_3_ISR){
1916 uint8 channel = 3U;
1917 Stm_Ip_ProcessCommonInterrupt(RTU1_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1918 }
1919 #endif
1920 #if defined(RTU2_COS_STM_0_CH_0_ISR_USED)
ISR(RTU2_COS_STM_0_CH_0_ISR)1921 ISR(RTU2_COS_STM_0_CH_0_ISR){
1922 uint8 channel = 0U;
1923 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1924 }
1925 #endif
1926 #if defined(RTU2_COS_STM_0_CH_1_ISR_USED)
ISR(RTU2_COS_STM_0_CH_1_ISR)1927 ISR(RTU2_COS_STM_0_CH_1_ISR){
1928 uint8 channel = 1U;
1929 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1930 }
1931 #endif
1932 #if defined(RTU2_COS_STM_0_CH_2_ISR_USED)
ISR(RTU2_COS_STM_0_CH_2_ISR)1933 ISR(RTU2_COS_STM_0_CH_2_ISR){
1934 uint8 channel = 2U;
1935 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1936 }
1937 #endif
1938 #if defined(RTU2_COS_STM_0_CH_3_ISR_USED)
ISR(RTU2_COS_STM_0_CH_3_ISR)1939 ISR(RTU2_COS_STM_0_CH_3_ISR){
1940 uint8 channel = 3U;
1941 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_0_IP_INSTANCE_NUMBER, channel);
1942 }
1943 #endif
1944 #if defined(RTU2_COS_STM_1_CH_0_ISR_USED)
ISR(RTU2_COS_STM_1_CH_0_ISR)1945 ISR(RTU2_COS_STM_1_CH_0_ISR){
1946 uint8 channel = 0U;
1947 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1948 }
1949 #endif
1950 #if defined(RTU2_COS_STM_1_CH_1_ISR_USED)
ISR(RTU2_COS_STM_1_CH_1_ISR)1951 ISR(RTU2_COS_STM_1_CH_1_ISR){
1952 uint8 channel = 1U;
1953 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1954 }
1955 #endif
1956 #if defined(RTU2_COS_STM_1_CH_2_ISR_USED)
ISR(RTU2_COS_STM_1_CH_2_ISR)1957 ISR(RTU2_COS_STM_1_CH_2_ISR){
1958 uint8 channel = 2U;
1959 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1960 }
1961 #endif
1962 #if defined(RTU2_COS_STM_1_CH_3_ISR_USED)
ISR(RTU2_COS_STM_1_CH_3_ISR)1963 ISR(RTU2_COS_STM_1_CH_3_ISR){
1964 uint8 channel = 3U;
1965 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_1_IP_INSTANCE_NUMBER, channel);
1966 }
1967 #endif
1968 #if defined(RTU2_COS_STM_2_CH_0_ISR_USED)
ISR(RTU2_COS_STM_2_CH_0_ISR)1969 ISR(RTU2_COS_STM_2_CH_0_ISR){
1970 uint8 channel = 0U;
1971 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1972 }
1973 #endif
1974 #if defined(RTU2_COS_STM_2_CH_1_ISR_USED)
ISR(RTU2_COS_STM_2_CH_1_ISR)1975 ISR(RTU2_COS_STM_2_CH_1_ISR){
1976 uint8 channel = 1U;
1977 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1978 }
1979 #endif
1980 #if defined(RTU2_COS_STM_2_CH_2_ISR_USED)
ISR(RTU2_COS_STM_2_CH_2_ISR)1981 ISR(RTU2_COS_STM_2_CH_2_ISR){
1982 uint8 channel = 2U;
1983 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1984 }
1985 #endif
1986 #if defined(RTU2_COS_STM_2_CH_3_ISR_USED)
ISR(RTU2_COS_STM_2_CH_3_ISR)1987 ISR(RTU2_COS_STM_2_CH_3_ISR){
1988 uint8 channel = 3U;
1989 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_2_IP_INSTANCE_NUMBER, channel);
1990 }
1991 #endif
1992 #if defined(RTU2_COS_STM_3_CH_0_ISR_USED)
ISR(RTU2_COS_STM_3_CH_0_ISR)1993 ISR(RTU2_COS_STM_3_CH_0_ISR){
1994 uint8 channel = 0U;
1995 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_3_IP_INSTANCE_NUMBER, channel);
1996 }
1997 #endif
1998 #if defined(RTU2_COS_STM_3_CH_1_ISR_USED)
ISR(RTU2_COS_STM_3_CH_1_ISR)1999 ISR(RTU2_COS_STM_3_CH_1_ISR){
2000 uint8 channel = 1U;
2001 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_3_IP_INSTANCE_NUMBER, channel);
2002 }
2003 #endif
2004 #if defined(RTU2_COS_STM_3_CH_2_ISR_USED)
ISR(RTU2_COS_STM_3_CH_2_ISR)2005 ISR(RTU2_COS_STM_3_CH_2_ISR){
2006 uint8 channel = 2U;
2007 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_3_IP_INSTANCE_NUMBER, channel);
2008 }
2009 #endif
2010 #if defined(RTU2_COS_STM_3_CH_3_ISR_USED)
ISR(RTU2_COS_STM_3_CH_3_ISR)2011 ISR(RTU2_COS_STM_3_CH_3_ISR){
2012 uint8 channel = 3U;
2013 Stm_Ip_ProcessCommonInterrupt(RTU2_COS_STM_3_IP_INSTANCE_NUMBER, channel);
2014 }
2015 #endif
2016 #if defined(RTU3_COS_STM_0_CH_0_ISR_USED)
ISR(RTU3_COS_STM_0_CH_0_ISR)2017 ISR(RTU3_COS_STM_0_CH_0_ISR){
2018 uint8 channel = 0U;
2019 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_0_IP_INSTANCE_NUMBER, channel);
2020 }
2021 #endif
2022 #if defined(RTU3_COS_STM_0_CH_1_ISR_USED)
ISR(RTU3_COS_STM_0_CH_1_ISR)2023 ISR(RTU3_COS_STM_0_CH_1_ISR){
2024 uint8 channel = 1U;
2025 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_0_IP_INSTANCE_NUMBER, channel);
2026 }
2027 #endif
2028 #if defined(RTU3_COS_STM_0_CH_2_ISR_USED)
ISR(RTU3_COS_STM_0_CH_2_ISR)2029 ISR(RTU3_COS_STM_0_CH_2_ISR){
2030 uint8 channel = 2U;
2031 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_0_IP_INSTANCE_NUMBER, channel);
2032 }
2033 #endif
2034 #if defined(RTU3_COS_STM_0_CH_3_ISR_USED)
ISR(RTU3_COS_STM_0_CH_3_ISR)2035 ISR(RTU3_COS_STM_0_CH_3_ISR){
2036 uint8 channel = 3U;
2037 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_0_IP_INSTANCE_NUMBER, channel);
2038 }
2039 #endif
2040 #if defined(RTU3_COS_STM_1_CH_0_ISR_USED)
ISR(RTU3_COS_STM_1_CH_0_ISR)2041 ISR(RTU3_COS_STM_1_CH_0_ISR){
2042 uint8 channel = 0U;
2043 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_1_IP_INSTANCE_NUMBER, channel);
2044 }
2045 #endif
2046 #if defined(RTU3_COS_STM_1_CH_1_ISR_USED)
ISR(RTU3_COS_STM_1_CH_1_ISR)2047 ISR(RTU3_COS_STM_1_CH_1_ISR){
2048 uint8 channel = 1U;
2049 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_1_IP_INSTANCE_NUMBER, channel);
2050 }
2051 #endif
2052 #if defined(RTU3_COS_STM_1_CH_2_ISR_USED)
ISR(RTU3_COS_STM_1_CH_2_ISR)2053 ISR(RTU3_COS_STM_1_CH_2_ISR){
2054 uint8 channel = 2U;
2055 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_1_IP_INSTANCE_NUMBER, channel);
2056 }
2057 #endif
2058 #if defined(RTU3_COS_STM_1_CH_3_ISR_USED)
ISR(RTU3_COS_STM_1_CH_3_ISR)2059 ISR(RTU3_COS_STM_1_CH_3_ISR){
2060 uint8 channel = 3U;
2061 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_1_IP_INSTANCE_NUMBER, channel);
2062 }
2063 #endif
2064 #if defined(RTU3_COS_STM_2_CH_0_ISR_USED)
ISR(RTU3_COS_STM_2_CH_0_ISR)2065 ISR(RTU3_COS_STM_2_CH_0_ISR){
2066 uint8 channel = 0U;
2067 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_2_IP_INSTANCE_NUMBER, channel);
2068 }
2069 #endif
2070 #if defined(RTU3_COS_STM_2_CH_1_ISR_USED)
ISR(RTU3_COS_STM_2_CH_1_ISR)2071 ISR(RTU3_COS_STM_2_CH_1_ISR){
2072 uint8 channel = 1U;
2073 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_2_IP_INSTANCE_NUMBER, channel);
2074 }
2075 #endif
2076 #if defined(RTU3_COS_STM_2_CH_2_ISR_USED)
ISR(RTU3_COS_STM_2_CH_2_ISR)2077 ISR(RTU3_COS_STM_2_CH_2_ISR){
2078 uint8 channel = 2U;
2079 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_2_IP_INSTANCE_NUMBER, channel);
2080 }
2081 #endif
2082 #if defined(RTU3_COS_STM_2_CH_3_ISR_USED)
ISR(RTU3_COS_STM_2_CH_3_ISR)2083 ISR(RTU3_COS_STM_2_CH_3_ISR){
2084 uint8 channel = 3U;
2085 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_2_IP_INSTANCE_NUMBER, channel);
2086 }
2087 #endif
2088 #if defined(RTU3_COS_STM_3_CH_0_ISR_USED)
ISR(RTU3_COS_STM_3_CH_0_ISR)2089 ISR(RTU3_COS_STM_3_CH_0_ISR){
2090 uint8 channel = 0U;
2091 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_3_IP_INSTANCE_NUMBER, channel);
2092 }
2093 #endif
2094 #if defined(RTU3_COS_STM_3_CH_1_ISR_USED)
ISR(RTU3_COS_STM_3_CH_1_ISR)2095 ISR(RTU3_COS_STM_3_CH_1_ISR){
2096 uint8 channel = 1U;
2097 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_3_IP_INSTANCE_NUMBER, channel);
2098 }
2099 #endif
2100 #if defined(RTU3_COS_STM_3_CH_2_ISR_USED)
ISR(RTU3_COS_STM_3_CH_2_ISR)2101 ISR(RTU3_COS_STM_3_CH_2_ISR){
2102 uint8 channel = 2U;
2103 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_3_IP_INSTANCE_NUMBER, channel);
2104 }
2105 #endif
2106 #if defined(RTU3_COS_STM_3_CH_3_ISR_USED)
ISR(RTU3_COS_STM_3_CH_3_ISR)2107 ISR(RTU3_COS_STM_3_CH_3_ISR){
2108 uint8 channel = 3U;
2109 Stm_Ip_ProcessCommonInterrupt(RTU3_COS_STM_3_IP_INSTANCE_NUMBER, channel);
2110 }
2111 #endif
2112
2113 #endif /* STD_ON == STM_GPT_IP_MODULE_SINGLE_AND_MULTIPLE_INTERRUPTS */
2114
2115 /*================================================================================================*/
2116 #if (STD_ON == STM_GPT_IP_MODULE_SINGLE_INTERRUPT)
2117 #if defined(STM_0_ISR_USED)
2118 /**
2119 * @brief Interrupt handler for STM channels.
2120 * @details Interrupt Service Routine corresponding to common STM_0 module.
2121 * @param[in] none
2122 * @return none
2123 * @isr
2124 * @pre The driver needs to be initialized.
2125 */
ISR(STM_0_ISR)2126 ISR(STM_0_ISR){
2127 uint8 channel;
2128 #if defined(STM_0_IP_EXISTS)
2129 uint8 instance = STM_0_IP_INSTANCE_NUMBER;
2130 #else
2131 #error "undefined STM instance number"
2132 #endif
2133 for (channel = 0U; channel < STM_0_IP_CHANNELS_NUMBER; ++channel)
2134 {
2135 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2136 }
2137 }
2138 #endif
2139
2140 #if defined(STM_1_ISR_USED)
2141 /**
2142 * @brief Interrupt handler for STM channels.
2143 * @details Interrupt Service Routine corresponding to common STM_1 module.
2144 * @param[in] none
2145 * @return none
2146 * @isr
2147 * @pre The driver needs to be initialized.
2148 */
ISR(STM_1_ISR)2149 ISR(STM_1_ISR){
2150 uint8 channel;
2151 #if defined(STM_1_IP_EXISTS)
2152 uint8 instance = STM_1_IP_INSTANCE_NUMBER;
2153 #else
2154 #error "undefined STM instance number"
2155 #endif
2156 for (channel = 0U; channel < STM_1_IP_CHANNELS_NUMBER; ++channel)
2157 {
2158 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2159 }
2160 }
2161 #endif
2162
2163 #if defined(STM_2_ISR_USED)
2164 /**
2165 * @brief Interrupt handler for STM channels.
2166 * @details Interrupt Service Routine corresponding to common STM_2 module.
2167 * @param[in] none
2168 * @return none
2169 * @isr
2170 * @pre The driver needs to be initialized.
2171 */
ISR(STM_2_ISR)2172 ISR(STM_2_ISR){
2173 uint8 channel;
2174 #if defined(STM_2_IP_EXISTS)
2175 uint8 instance = STM_2_IP_INSTANCE_NUMBER;
2176 #else
2177 #error "undefined STM instance number"
2178 #endif
2179 for (channel = 0U; channel < STM_2_IP_CHANNELS_NUMBER; ++channel)
2180 {
2181 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2182 }
2183 }
2184 #endif
2185
2186 #if defined(STM_3_ISR_USED)
2187 /**
2188 * @brief Interrupt handler for STM channels.
2189 * @details Interrupt Service Routine corresponding to common STM_3 module.
2190 * @param[in] none
2191 * @return none
2192 * @isr
2193 * @pre The driver needs to be initialized.
2194 */
ISR(STM_3_ISR)2195 ISR(STM_3_ISR){
2196 uint8 channel;
2197 #if defined(STM_3_IP_EXISTS)
2198 uint8 instance = STM_3_IP_INSTANCE_NUMBER;
2199 #else
2200 #error "undefined STM instance number"
2201 #endif
2202 for (channel = 0U; channel < STM_3_IP_CHANNELS_NUMBER; ++channel)
2203 {
2204 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2205 }
2206 }
2207 #endif
2208 #if defined(STM_4_ISR_USED)
2209 /**
2210 * @brief Interrupt handler for STM channels.
2211 * @details Interrupt Service Routine corresponding to common STM_4 module.
2212 * @param[in] none
2213 * @return none
2214 * @isr
2215 * @pre The driver needs to be initialized.
2216 */
ISR(STM_4_ISR)2217 ISR(STM_4_ISR){
2218 uint8 channel;
2219 #if defined(STM_4_IP_EXISTS)
2220 uint8 instance = STM_4_IP_INSTANCE_NUMBER;
2221 #else
2222 #error "undefined STM instance number"
2223 #endif
2224 for (channel = 0U; channel < STM_4_IP_CHANNELS_NUMBER; ++channel)
2225 {
2226 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2227 }
2228 }
2229 #endif
2230
2231 #if defined(STM_5_ISR_USED)
2232 /**
2233 * @brief Interrupt handler for STM channels.
2234 * @details Interrupt Service Routine corresponding to common STM_5 module.
2235 * @param[in] none
2236 * @return none
2237 * @isr
2238 * @pre The driver needs to be initialized.
2239 */
ISR(STM_5_ISR)2240 ISR(STM_5_ISR){
2241 uint8 channel;
2242 #if defined(STM_5_IP_EXISTS)
2243 uint8 instance = STM_5_IP_INSTANCE_NUMBER;
2244 #else
2245 #error "undefined STM instance number"
2246 #endif
2247 for (channel = 0U; channel < STM_5_IP_CHANNELS_NUMBER; ++channel)
2248 {
2249 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2250 }
2251 }
2252 #endif
2253
2254 #if defined(STM_6_ISR_USED)
2255 /**
2256 * @brief Interrupt handler for STM channels.
2257 * @details Interrupt Service Routine corresponding to common STM_6 module.
2258 * @param[in] none
2259 * @return none
2260 * @isr
2261 * @pre The driver needs to be initialized.
2262 */
ISR(STM_6_ISR)2263 ISR(STM_6_ISR){
2264 uint8 channel;
2265 #if defined(STM_6_IP_EXISTS)
2266 uint8 instance = STM_6_IP_INSTANCE_NUMBER;
2267 #else
2268 #error "undefined STM instance number"
2269 #endif
2270 for (channel = 0U; channel < STM_6_IP_CHANNELS_NUMBER; ++channel)
2271 {
2272 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2273 }
2274 }
2275 #endif
2276
2277 #if defined(STM_7_ISR_USED)
2278 /**
2279 * @brief Interrupt handler for STM channels.
2280 * @details Interrupt Service Routine corresponding to common STM_7 module.
2281 * @param[in] none
2282 * @return none
2283 * @isr
2284 * @pre The driver needs to be initialized.
2285 */
ISR(STM_7_ISR)2286 ISR(STM_7_ISR){
2287 uint8 channel;
2288 #if defined(STM_7_IP_EXISTS)
2289 uint8 instance = STM_7_IP_INSTANCE_NUMBER;
2290 #else
2291 #error "undefined STM instance number"
2292 #endif
2293 for (channel = 0U; channel < STM_7_IP_CHANNELS_NUMBER; ++channel)
2294 {
2295 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2296 }
2297 }
2298 #endif
2299 #if defined(STM_8_ISR_USED)
2300 /**
2301 * @brief Interrupt handler for STM channels.
2302 * @details Interrupt Service Routine corresponding to common STM_8 module.
2303 * @param[in] none
2304 * @return none
2305 * @isr
2306 * @pre The driver needs to be initialized.
2307 */
ISR(STM_8_ISR)2308 ISR(STM_8_ISR){
2309 uint8 channel;
2310 #if defined(STM_8_IP_EXISTS)
2311 uint8 instance = STM_8_IP_INSTANCE_NUMBER;
2312 #else
2313 #error "undefined STM instance number"
2314 #endif
2315 for (channel = 0U; channel < STM_8_IP_CHANNELS_NUMBER; ++channel)
2316 {
2317 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2318 }
2319 }
2320 #endif
2321
2322 #if defined(STM_9_ISR_USED)
2323 /**
2324 * @brief Interrupt handler for STM channels.
2325 * @details Interrupt Service Routine corresponding to common STM_9 module.
2326 * @param[in] none
2327 * @return none
2328 * @isr
2329 * @pre The driver needs to be initialized.
2330 */
ISR(STM_9_ISR)2331 ISR(STM_9_ISR){
2332 uint8 channel;
2333 #if defined(STM_9_IP_EXISTS)
2334 uint8 instance = STM_9_IP_INSTANCE_NUMBER;
2335 #else
2336 #error "undefined STM instance number"
2337 #endif
2338 for (channel = 0U; channel < STM_9_IP_CHANNELS_NUMBER; ++channel)
2339 {
2340 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2341 }
2342 }
2343 #endif
2344
2345 #if defined(STM_10_ISR_USED)
2346 /**
2347 * @brief Interrupt handler for STM channels.
2348 * @details Interrupt Service Routine corresponding to common STM_10 module.
2349 * @param[in] none
2350 * @return none
2351 * @isr
2352 * @pre The driver needs to be initialized.
2353 */
ISR(STM_10_ISR)2354 ISR(STM_10_ISR){
2355 uint8 channel;
2356 #if defined(STM_10_IP_EXISTS)
2357 uint8 instance = STM_10_IP_INSTANCE_NUMBER;
2358 #else
2359 #error "undefined STM instance number"
2360 #endif
2361 for (channel = 0U; channel < STM_10_IP_CHANNELS_NUMBER; ++channel)
2362 {
2363 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2364 }
2365 }
2366 #endif
2367
2368 #if defined(STM_11_ISR_USED)
2369 /**
2370 * @brief Interrupt handler for STM channels.
2371 * @details Interrupt Service Routine corresponding to common STM_11 module.
2372 * @param[in] none
2373 * @return none
2374 * @isr
2375 * @pre The driver needs to be initialized.
2376 */
ISR(STM_11_ISR)2377 ISR(STM_11_ISR){
2378 uint8 channel;
2379 #if defined(STM_11_IP_EXISTS)
2380 uint8 instance = STM_11_IP_INSTANCE_NUMBER;
2381 #else
2382 #error "undefined STM instance number"
2383 #endif
2384 for (channel = 0U; channel < STM_11_IP_CHANNELS_NUMBER; ++channel)
2385 {
2386 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2387 }
2388 }
2389 #endif
2390
2391 #if defined(STM_12_ISR_USED)
2392 /**
2393 * @brief Interrupt handler for STM channels.
2394 * @details Interrupt Service Routine corresponding to common STM_12 module.
2395 * @param[in] none
2396 * @return none
2397 * @isr
2398 * @pre The driver needs to be initialized.
2399 */
ISR(STM_12_ISR)2400 ISR(STM_12_ISR){
2401 uint8 channel;
2402 #if defined(STM_12_IP_EXISTS)
2403 uint8 instance = STM_12_IP_INSTANCE_NUMBER;
2404 #else
2405 #error "undefined STM instance number"
2406 #endif
2407 for (channel = 0U; channel < STM_12_IP_CHANNELS_NUMBER; ++channel)
2408 {
2409 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2410 }
2411 }
2412 #endif
2413 /*================================================================================================*/
2414 #if defined(CE_STM_0_ISR_USED)
2415 /**
2416 * @brief Interrupt handler for STM channels.
2417 * @details Interrupt Service Routine corresponding to common CE_STM_0 module.
2418 * @param[in] none
2419 * @return none
2420 * @isr
2421 * @pre The driver needs to be initialized.
2422 */
ISR(CE_STM_0_ISR)2423 ISR(CE_STM_0_ISR){
2424 uint8 channel;
2425 #if defined(CE_STM_0_IP_EXISTS)
2426 uint8 instance = CE_STM_0_IP_INSTANCE_NUMBER;
2427 #else
2428 #error "undefined STM instance number"
2429 #endif
2430 for (channel = 0U; channel < CE_STM_0_IP_CHANNELS_NUMBER; ++channel)
2431 {
2432 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2433 }
2434 }
2435 #endif
2436
2437 #if defined(CE_STM_1_ISR_USED)
2438 /**
2439 * @brief Interrupt handler for STM channels.
2440 * @details Interrupt Service Routine corresponding to common CE_STM_1 module.
2441 * @param[in] none
2442 * @return none
2443 * @isr
2444 * @pre The driver needs to be initialized.
2445 */
ISR(CE_STM_1_ISR)2446 ISR(CE_STM_1_ISR){
2447 uint8 channel;
2448 #if defined(CE_STM_1_IP_EXISTS)
2449 uint8 instance = CE_STM_1_IP_INSTANCE_NUMBER;
2450 #else
2451 #error "undefined STM instance number"
2452 #endif
2453 for (channel = 0U; channel < CE_STM_1_IP_CHANNELS_NUMBER; ++channel)
2454 {
2455 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2456 }
2457 }
2458 #endif
2459
2460 #if defined(CE_STM_2_ISR_USED)
2461 /**
2462 * @brief Interrupt handler for STM channels.
2463 * @details Interrupt Service Routine corresponding to common CE_STM_2 module.
2464 * @param[in] none
2465 * @return none
2466 * @isr
2467 * @pre The driver needs to be initialized.
2468 */
ISR(CE_STM_2_ISR)2469 ISR(CE_STM_2_ISR){
2470 uint8 channel;
2471 #if defined(CE_STM_2_IP_EXISTS)
2472 uint8 instance = CE_STM_2_IP_INSTANCE_NUMBER;
2473 #else
2474 #error "undefined STM instance number"
2475 #endif
2476 for (channel = 0U; channel < CE_STM_2_IP_CHANNELS_NUMBER; ++channel)
2477 {
2478 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2479 }
2480 }
2481 #endif
2482
2483 #if defined(SMU_STM_0_ISR_USED)
2484 /**
2485 * @brief Interrupt handler for STM channels.
2486 * @details Interrupt Service Routine corresponding to common SMU_STM_0 module.
2487 * @param[in] none
2488 * @return none
2489 * @isr
2490 * @pre The driver needs to be initialized.
2491 */
ISR(SMU_STM_0_ISR)2492 ISR(SMU_STM_0_ISR){
2493 uint8 channel;
2494 #if defined(SMU_STM_0_IP_EXISTS)
2495 uint8 instance = SMU_STM_0_IP_INSTANCE_NUMBER;
2496 #else
2497 #error "undefined STM instance number"
2498 #endif
2499 for (channel = 0U; channel < SMU_STM_0_IP_CHANNELS_NUMBER; ++channel)
2500 {
2501 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2502 }
2503 }
2504 #endif
2505
2506 #if defined(SMU_STM_2_ISR_USED)
2507 /**
2508 * @brief Interrupt handler for STM channels.
2509 * @details Interrupt Service Routine corresponding to common SMU_STM_2 module.
2510 * @param[in] none
2511 * @return none
2512 * @isr
2513 * @pre The driver needs to be initialized.
2514 */
ISR(SMU_STM_2_ISR)2515 ISR(SMU_STM_2_ISR){
2516 uint8 channel;
2517 #if defined(SMU_STM_2_IP_EXISTS)
2518 uint8 instance = SMU_STM_2_IP_INSTANCE_NUMBER;
2519 #else
2520 #error "undefined STM instance number"
2521 #endif
2522 for (channel = 0U; channel < SMU_STM_2_IP_CHANNELS_NUMBER; ++channel)
2523 {
2524 Stm_Ip_ProcessCommonInterrupt(instance, channel);
2525 }
2526 }
2527 #endif
2528
2529 #endif /* STD_ON == STM_GPT_IP_MODULE_SINGLE_INTERRUPT */
2530
2531 #endif /* (STD_ON == STM_GPT_IP_MODULE_SINGLE_INTERRUPT) || (STD_ON == STM_GPT_IP_MODULE_SINGLE_AND_MULTIPLE_INTERRUPTS) */
2532
2533 #define GPT_STOP_SEC_CODE
2534 #include "Gpt_MemMap.h"
2535
2536 #endif /* STM_IP_USED == STD_ON */
2537 #ifdef __cplusplus
2538 }
2539 #endif /*STM_IP_C*/
2540 /** @} */
2541
2542
