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Searched refs:GPR0_PCTL_EDMA0PCTL_PCTL_3_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GPR0_PCTL.h172 #define GPR0_PCTL_EDMA0PCTL_PCTL_3_MASK (0x8U) macro
175 …(uint32_t)(((uint32_t)(x)) << GPR0_PCTL_EDMA0PCTL_PCTL_3_SHIFT)) & GPR0_PCTL_EDMA0PCTL_PCTL_3_MASK)
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c3777 …Frequency &= Clock_Ip_u32EnableGate[((IP_GPR0_PCTL->EDMA0PCTL & GPR0_PCTL_EDMA0PCTL_PCTL_3_MASK) >… in Clock_Ip_Get_PIT0_CLK_Frequency()