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Searched refs:GPR0 (Results 1 – 25 of 75) sorted by relevance

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/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_iomuxc.h1701 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1702 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1706 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1707 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_iomuxc.h1701 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1702 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1706 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1707 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_iomuxc.h1701 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1702 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1706 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1707 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_iomuxc.h1701 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1702 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1706 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1707 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_iomuxc.h1701 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1702 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1706 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1707 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_iomuxc.h1701 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1702 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1706 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1707 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_iomuxc.h1701 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1702 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
1706 gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); in IOMUXC_SetSaiMClkClockSource()
1707 base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; in IOMUXC_SetSaiMClkClockSource()
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1176/mcuxpresso/
Dboot_multicore_slave.c49 IOMUXC_LPSR_GPR->GPR0 = IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(bootAddress >> 3u); in boot_multicore_slave()
/hal_nxp-3.6.0/imx/devices/MCIMX7D/
DMCIMX7D_M4.h4533 …__IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 … member
4587 #define CCM_GPR0_REG(base) ((base)->GPR0)
26555 …__IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset:… member
26590 #define IOMUXC_GPR_GPR0_REG(base) ((base)->GPR0)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h16634 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
18084 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h19217 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
21122 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h22664 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
25260 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h22681 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
25277 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h23616 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
26316 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h25068 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
27963 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h25070 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
27965 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h24401 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
27101 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h25575 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
28547 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h5822 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ member
35044 uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h5824 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ member
35046 uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h5824 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ member
35046 uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h5822 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ member
35044 uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h5824 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ member
35046 uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_ca53.h5851 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */ member
35058 uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */ member
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h26361 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member
29333 … uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ member

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