1 /*
2  * Copyright 2020-2023 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef EMAC_IP_WRAPPER_H
8 #define EMAC_IP_WRAPPER_H
9 
10 /**
11 *   @file
12 *
13 *   @internal
14 *   @addtogroup GMAC_DRIVER GMAC Driver
15 *   @{
16 */
17 
18 #ifdef __cplusplus
19 extern "C"{
20 #endif
21 
22 /*==================================================================================================
23 *                              SOURCE FILE VERSION INFORMATION
24 ==================================================================================================*/
25 #define EMAC_IP_WRAPPER_VENDOR_ID                      43
26 #define EMAC_IP_WRAPPER_AR_RELEASE_MAJOR_VERSION       4
27 #define EMAC_IP_WRAPPER_AR_RELEASE_MINOR_VERSION       7
28 #define EMAC_IP_WRAPPER_AR_RELEASE_REVISION_VERSION    0
29 #define EMAC_IP_WRAPPER_SW_MAJOR_VERSION               3
30 #define EMAC_IP_WRAPPER_SW_MINOR_VERSION               0
31 #define EMAC_IP_WRAPPER_SW_PATCH_VERSION               0
32 
33 /*==================================================================================================
34                                        DEFINES AND MACROS
35 ==================================================================================================*/
36 
37 typedef EMAC_Type GMAC_Type;
38 
39 
40 #define IP_GMAC_0_BASE                              IP_EMAC_BASE
41 /** Peripheral IP_GMAC_0 base pointer */
42 #define IP_GMAC_0                                   IP_EMAC
43 /** Array initializer of GMAC peripheral base addresses */
44 #define IP_GMAC_BASE_ADDRS                          IP_EMAC_BASE_ADDRS
45 /** Array initializer of EMAC peripheral base pointers */
46 #define IP_GMAC_BASE_PTRS                           IP_EMAC_BASE_PTRS
47 
48 
49 /* ----------------------------------------------------------------------------
50    -- EMAC Register Masks
51    ---------------------------------------------------------------------------- */
52 
53 /*!
54  * @internal
55  * @addtogroup GMAC_Register_Masks EMAC Register Masks
56  * @{
57  */
58 
59 /*! @name MAC_CONFIGURATION -  */
60 /*! @{ */
61 #define GMAC_MAC_CONFIGURATION_RE_MASK           EMAC_MAC_CONFIGURATION_RE_MASK
62 #define GMAC_MAC_CONFIGURATION_RE_SHIFT          EMAC_MAC_CONFIGURATION_RE_SHIFT
63 #define GMAC_MAC_CONFIGURATION_RE_WIDTH          EMAC_MAC_CONFIGURATION_RE_WIDTH
64 #define GMAC_MAC_CONFIGURATION_RE(x)             EMAC_MAC_CONFIGURATION_RE(x)
65 #define GMAC_MAC_CONFIGURATION_TE_MASK           EMAC_MAC_CONFIGURATION_TE_MASK
66 #define GMAC_MAC_CONFIGURATION_TE_SHIFT          EMAC_MAC_CONFIGURATION_TE_SHIFT
67 #define GMAC_MAC_CONFIGURATION_TE_WIDTH          EMAC_MAC_CONFIGURATION_TE_WIDTH
68 #define GMAC_MAC_CONFIGURATION_TE(x)             EMAC_MAC_CONFIGURATION_TE(x)
69 #define GMAC_MAC_CONFIGURATION_PRELEN_MASK       EMAC_MAC_CONFIGURATION_PRELEN_MASK
70 #define GMAC_MAC_CONFIGURATION_PRELEN_SHIFT      EMAC_MAC_CONFIGURATION_PRELEN_SHIFT
71 #define GMAC_MAC_CONFIGURATION_PRELEN_WIDTH      EMAC_MAC_CONFIGURATION_PRELEN_WIDTH
72 #define GMAC_MAC_CONFIGURATION_PRELEN(x)         EMAC_MAC_CONFIGURATION_PRELEN(x)
73 #define GMAC_MAC_CONFIGURATION_DC_MASK           EMAC_MAC_CONFIGURATION_DC_MASK
74 #define GMAC_MAC_CONFIGURATION_DC_SHIFT          EMAC_MAC_CONFIGURATION_DC_SHIFT
75 #define GMAC_MAC_CONFIGURATION_DC_WIDTH          EMAC_MAC_CONFIGURATION_DC_WIDTH
76 #define GMAC_MAC_CONFIGURATION_DC(x)             EMAC_MAC_CONFIGURATION_DC(x)
77 #define GMAC_MAC_CONFIGURATION_BL_MASK           EMAC_MAC_CONFIGURATION_BL_MASK
78 #define GMAC_MAC_CONFIGURATION_BL_SHIFT          EMAC_MAC_CONFIGURATION_BL_SHIFT
79 #define GMAC_MAC_CONFIGURATION_BL_WIDTH          EMAC_MAC_CONFIGURATION_BL_WIDTH
80 #define GMAC_MAC_CONFIGURATION_BL(x)             EMAC_MAC_CONFIGURATION_BL(x)
81 #define GMAC_MAC_CONFIGURATION_DR_MASK           EMAC_MAC_CONFIGURATION_DR_MASK
82 #define GMAC_MAC_CONFIGURATION_DR_SHIFT          EMAC_MAC_CONFIGURATION_DR_SHIFT
83 #define GMAC_MAC_CONFIGURATION_DR_WIDTH          EMAC_MAC_CONFIGURATION_DR_WIDTH
84 #define GMAC_MAC_CONFIGURATION_DR(x)             EMAC_MAC_CONFIGURATION_DR(x)
85 #define GMAC_MAC_CONFIGURATION_DCRS_MASK         EMAC_MAC_CONFIGURATION_DCRS_MASK
86 #define GMAC_MAC_CONFIGURATION_DCRS_SHIFT        EMAC_MAC_CONFIGURATION_DCRS_SHIFT
87 #define GMAC_MAC_CONFIGURATION_DCRS_WIDTH        EMAC_MAC_CONFIGURATION_DCRS_WIDTH
88 #define GMAC_MAC_CONFIGURATION_DCRS(x)           EMAC_MAC_CONFIGURATION_DCRS(x)
89 #define GMAC_MAC_CONFIGURATION_DO_MASK           EMAC_MAC_CONFIGURATION_DO_MASK
90 #define GMAC_MAC_CONFIGURATION_DO_SHIFT          EMAC_MAC_CONFIGURATION_DO_SHIFT
91 #define GMAC_MAC_CONFIGURATION_DO_WIDTH          EMAC_MAC_CONFIGURATION_DO_WIDTH
92 #define GMAC_MAC_CONFIGURATION_DO(x)             EMAC_MAC_CONFIGURATION_DO(x)
93 #define GMAC_MAC_CONFIGURATION_ECRSFD_MASK       EMAC_MAC_CONFIGURATION_ECRSFD_MASK
94 #define GMAC_MAC_CONFIGURATION_ECRSFD_SHIFT      EMAC_MAC_CONFIGURATION_ECRSFD_SHIFT
95 #define GMAC_MAC_CONFIGURATION_ECRSFD_WIDTH      EMAC_MAC_CONFIGURATION_ECRSFD_WIDTH
96 #define GMAC_MAC_CONFIGURATION_ECRSFD(x)         EMAC_MAC_CONFIGURATION_ECRSFD(x)
97 #define GMAC_MAC_CONFIGURATION_LM_MASK           EMAC_MAC_CONFIGURATION_LM_MASK
98 #define GMAC_MAC_CONFIGURATION_LM_SHIFT          EMAC_MAC_CONFIGURATION_LM_SHIFT
99 #define GMAC_MAC_CONFIGURATION_LM_WIDTH          EMAC_MAC_CONFIGURATION_LM_WIDTH
100 #define GMAC_MAC_CONFIGURATION_LM(x)             EMAC_MAC_CONFIGURATION_LM(x)
101 #define GMAC_MAC_CONFIGURATION_DM_MASK           EMAC_MAC_CONFIGURATION_DM_MASK
102 #define GMAC_MAC_CONFIGURATION_DM_SHIFT          EMAC_MAC_CONFIGURATION_DM_SHIFT
103 #define GMAC_MAC_CONFIGURATION_DM_WIDTH          EMAC_MAC_CONFIGURATION_DM_WIDTH
104 #define GMAC_MAC_CONFIGURATION_DM(x)             EMAC_MAC_CONFIGURATION_DM(x)
105 #define GMAC_MAC_CONFIGURATION_FES_MASK          EMAC_MAC_CONFIGURATION_FES_MASK
106 #define GMAC_MAC_CONFIGURATION_FES_SHIFT         EMAC_MAC_CONFIGURATION_FES_SHIFT
107 #define GMAC_MAC_CONFIGURATION_FES_WIDTH         EMAC_MAC_CONFIGURATION_FES_WIDTH
108 #define GMAC_MAC_CONFIGURATION_FES(x)            EMAC_MAC_CONFIGURATION_FES(x)
109 #define GMAC_MAC_CONFIGURATION_PS_MASK           EMAC_MAC_CONFIGURATION_PS_MASK
110 #define GMAC_MAC_CONFIGURATION_PS_SHIFT          EMAC_MAC_CONFIGURATION_PS_SHIFT
111 #define GMAC_MAC_CONFIGURATION_PS_WIDTH          EMAC_MAC_CONFIGURATION_PS_WIDTH
112 #define GMAC_MAC_CONFIGURATION_PS(x)             EMAC_MAC_CONFIGURATION_PS(x)
113 #define GMAC_MAC_CONFIGURATION_JE_MASK           EMAC_MAC_CONFIGURATION_JE_MASK
114 #define GMAC_MAC_CONFIGURATION_JE_SHIFT          EMAC_MAC_CONFIGURATION_JE_SHIFT
115 #define GMAC_MAC_CONFIGURATION_JE_WIDTH          EMAC_MAC_CONFIGURATION_JE_WIDTH
116 #define GMAC_MAC_CONFIGURATION_JE(x)             EMAC_MAC_CONFIGURATION_JE(x)
117 #define GMAC_MAC_CONFIGURATION_JD_MASK           EMAC_MAC_CONFIGURATION_JD_MASK
118 #define GMAC_MAC_CONFIGURATION_JD_SHIFT          EMAC_MAC_CONFIGURATION_JD_SHIFT
119 #define GMAC_MAC_CONFIGURATION_JD_WIDTH          EMAC_MAC_CONFIGURATION_JD_WIDTH
120 #define GMAC_MAC_CONFIGURATION_JD(x)             EMAC_MAC_CONFIGURATION_JD(x)
121 #define GMAC_MAC_CONFIGURATION_WD_MASK           EMAC_MAC_CONFIGURATION_WD_MASK
122 #define GMAC_MAC_CONFIGURATION_WD_SHIFT          EMAC_MAC_CONFIGURATION_WD_SHIFT
123 #define GMAC_MAC_CONFIGURATION_WD_WIDTH          EMAC_MAC_CONFIGURATION_WD_WIDTH
124 #define GMAC_MAC_CONFIGURATION_WD(x)             EMAC_MAC_CONFIGURATION_WD(x)
125 #define GMAC_MAC_CONFIGURATION_ACS_MASK          EMAC_MAC_CONFIGURATION_ACS_MASK
126 #define GMAC_MAC_CONFIGURATION_ACS_SHIFT         EMAC_MAC_CONFIGURATION_ACS_SHIFT
127 #define GMAC_MAC_CONFIGURATION_ACS_WIDTH         EMAC_MAC_CONFIGURATION_ACS_WIDTH
128 #define GMAC_MAC_CONFIGURATION_ACS(x)            EMAC_MAC_CONFIGURATION_ACS(x)
129 #define GMAC_MAC_CONFIGURATION_CST_MASK          EMAC_MAC_CONFIGURATION_CST_MASK
130 #define GMAC_MAC_CONFIGURATION_CST_SHIFT         EMAC_MAC_CONFIGURATION_CST_SHIFT
131 #define GMAC_MAC_CONFIGURATION_CST_WIDTH         EMAC_MAC_CONFIGURATION_CST_WIDTH
132 #define GMAC_MAC_CONFIGURATION_CST(x)            EMAC_MAC_CONFIGURATION_CST(x)
133 #define GMAC_MAC_CONFIGURATION_S2KP_MASK         EMAC_MAC_CONFIGURATION_S2KP_MASK
134 #define GMAC_MAC_CONFIGURATION_S2KP_SHIFT        EMAC_MAC_CONFIGURATION_S2KP_SHIFT
135 #define GMAC_MAC_CONFIGURATION_S2KP_WIDTH        EMAC_MAC_CONFIGURATION_S2KP_WIDTH
136 #define GMAC_MAC_CONFIGURATION_S2KP(x)           EMAC_MAC_CONFIGURATION_S2KP(x)
137 #define GMAC_MAC_CONFIGURATION_GPSLCE_MASK       EMAC_MAC_CONFIGURATION_GPSLCE_MASK
138 #define GMAC_MAC_CONFIGURATION_GPSLCE_SHIFT      EMAC_MAC_CONFIGURATION_GPSLCE_SHIFT
139 #define GMAC_MAC_CONFIGURATION_GPSLCE_WIDTH      EMAC_MAC_CONFIGURATION_GPSLCE_WIDTH
140 #define GMAC_MAC_CONFIGURATION_GPSLCE(x)         EMAC_MAC_CONFIGURATION_GPSLCE(x)
141 #define GMAC_MAC_CONFIGURATION_IPG_MASK          EMAC_MAC_CONFIGURATION_IPG_MASK
142 #define GMAC_MAC_CONFIGURATION_IPG_SHIFT         EMAC_MAC_CONFIGURATION_IPG_SHIFT
143 #define GMAC_MAC_CONFIGURATION_IPG_WIDTH         EMAC_MAC_CONFIGURATION_IPG_WIDTH
144 #define GMAC_MAC_CONFIGURATION_IPG(x)            EMAC_MAC_CONFIGURATION_IPG(x)
145 #define GMAC_MAC_CONFIGURATION_IPC_MASK          EMAC_MAC_CONFIGURATION_IPC_MASK
146 #define GMAC_MAC_CONFIGURATION_IPC_SHIFT         EMAC_MAC_CONFIGURATION_IPC_SHIFT
147 #define GMAC_MAC_CONFIGURATION_IPC_WIDTH         EMAC_MAC_CONFIGURATION_IPC_WIDTH
148 #define GMAC_MAC_CONFIGURATION_IPC(x)            EMAC_MAC_CONFIGURATION_IPC(x)
149 #define GMAC_MAC_CONFIGURATION_SARC_MASK         EMAC_MAC_CONFIGURATION_SARC_MASK
150 #define GMAC_MAC_CONFIGURATION_SARC_SHIFT        EMAC_MAC_CONFIGURATION_SARC_SHIFT
151 #define GMAC_MAC_CONFIGURATION_SARC_WIDTH        EMAC_MAC_CONFIGURATION_SARC_WIDTH
152 #define GMAC_MAC_CONFIGURATION_SARC(x)           EMAC_MAC_CONFIGURATION_SARC(x)
153 /*! @} */
154 
155 /*! @name MAC_EXT_CONFIGURATION -  */
156 /*! @{ */
157 #define GMAC_MAC_EXT_CONFIGURATION_GPSL_MASK     EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK
158 #define GMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT    EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT
159 #define GMAC_MAC_EXT_CONFIGURATION_GPSL_WIDTH    EMAC_MAC_EXT_CONFIGURATION_GPSL_WIDTH
160 #define GMAC_MAC_EXT_CONFIGURATION_GPSL(x)       EMAC_MAC_EXT_CONFIGURATION_GPSL(x)
161 #define GMAC_MAC_EXT_CONFIGURATION_DCRCC_MASK    EMAC_MAC_EXT_CONFIGURATION_DCRCC_MASK
162 #define GMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT   EMAC_MAC_EXT_CONFIGURATION_DCRCC_SHIFT
163 #define GMAC_MAC_EXT_CONFIGURATION_DCRCC_WIDTH   EMAC_MAC_EXT_CONFIGURATION_DCRCC_WIDTH
164 #define GMAC_MAC_EXT_CONFIGURATION_DCRCC(x)      EMAC_MAC_EXT_CONFIGURATION_DCRCC(x)
165 #define GMAC_MAC_EXT_CONFIGURATION_SPEN_MASK     EMAC_MAC_EXT_CONFIGURATION_SPEN_MASK
166 #define GMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT    EMAC_MAC_EXT_CONFIGURATION_SPEN_SHIFT
167 #define GMAC_MAC_EXT_CONFIGURATION_SPEN_WIDTH    EMAC_MAC_EXT_CONFIGURATION_SPEN_WIDTH
168 #define GMAC_MAC_EXT_CONFIGURATION_SPEN(x)       EMAC_MAC_EXT_CONFIGURATION_SPEN(x)
169 #define GMAC_MAC_EXT_CONFIGURATION_USP_MASK      EMAC_MAC_EXT_CONFIGURATION_USP_MASK
170 #define GMAC_MAC_EXT_CONFIGURATION_USP_SHIFT     EMAC_MAC_EXT_CONFIGURATION_USP_SHIFT
171 #define GMAC_MAC_EXT_CONFIGURATION_USP_WIDTH     EMAC_MAC_EXT_CONFIGURATION_USP_WIDTH
172 #define GMAC_MAC_EXT_CONFIGURATION_USP(x)        EMAC_MAC_EXT_CONFIGURATION_USP(x)
173 #define GMAC_MAC_EXT_CONFIGURATION_PDC_MASK      EMAC_MAC_EXT_CONFIGURATION_PDC_MASK
174 #define GMAC_MAC_EXT_CONFIGURATION_PDC_SHIFT     EMAC_MAC_EXT_CONFIGURATION_PDC_SHIFT
175 #define GMAC_MAC_EXT_CONFIGURATION_PDC_WIDTH     EMAC_MAC_EXT_CONFIGURATION_PDC_WIDTH
176 #define GMAC_MAC_EXT_CONFIGURATION_PDC(x)        EMAC_MAC_EXT_CONFIGURATION_PDC(x)
177 #define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_MASK   EMAC_MAC_EXT_CONFIGURATION_EIPGEN_MASK
178 #define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT  EMAC_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT
179 #define GMAC_MAC_EXT_CONFIGURATION_EIPGEN_WIDTH  EMAC_MAC_EXT_CONFIGURATION_EIPGEN_WIDTH
180 #define GMAC_MAC_EXT_CONFIGURATION_EIPGEN(x)     EMAC_MAC_EXT_CONFIGURATION_EIPGEN(x)
181 #define GMAC_MAC_EXT_CONFIGURATION_EIPG_MASK     EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK
182 #define GMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT    EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT
183 #define GMAC_MAC_EXT_CONFIGURATION_EIPG_WIDTH    EMAC_MAC_EXT_CONFIGURATION_EIPG_WIDTH
184 #define GMAC_MAC_EXT_CONFIGURATION_EIPG(x)       EMAC_MAC_EXT_CONFIGURATION_EIPG(x)
185 /*! @} */
186 
187 /*! @name MAC_PACKET_FILTER -  */
188 /*! @{ */
189 #define GMAC_MAC_PACKET_FILTER_PR_MASK           EMAC_MAC_PACKET_FILTER_PR_MASK
190 #define GMAC_MAC_PACKET_FILTER_PR_SHIFT          EMAC_MAC_PACKET_FILTER_PR_SHIFT
191 #define GMAC_MAC_PACKET_FILTER_PR_WIDTH          EMAC_MAC_PACKET_FILTER_PR_WIDTH
192 #define GMAC_MAC_PACKET_FILTER_PR(x)             EMAC_MAC_PACKET_FILTER_PR(x)
193 #define GMAC_MAC_PACKET_FILTER_HUC_MASK          EMAC_MAC_PACKET_FILTER_HUC_MASK
194 #define GMAC_MAC_PACKET_FILTER_HUC_SHIFT         EMAC_MAC_PACKET_FILTER_HUC_SHIFT
195 #define GMAC_MAC_PACKET_FILTER_HUC_WIDTH         EMAC_MAC_PACKET_FILTER_HUC_WIDTH
196 #define GMAC_MAC_PACKET_FILTER_HUC(x)            EMAC_MAC_PACKET_FILTER_HUC(x)
197 #define GMAC_MAC_PACKET_FILTER_HMC_MASK          EMAC_MAC_PACKET_FILTER_HMC_MASK
198 #define GMAC_MAC_PACKET_FILTER_HMC_SHIFT         EMAC_MAC_PACKET_FILTER_HMC_SHIFT
199 #define GMAC_MAC_PACKET_FILTER_HMC_WIDTH         EMAC_MAC_PACKET_FILTER_HMC_WIDTH
200 #define GMAC_MAC_PACKET_FILTER_HMC(x)            EMAC_MAC_PACKET_FILTER_HMC(x)
201 #define GMAC_MAC_PACKET_FILTER_DAIF_MASK         EMAC_MAC_PACKET_FILTER_DAIF_MASK
202 #define GMAC_MAC_PACKET_FILTER_DAIF_SHIFT        EMAC_MAC_PACKET_FILTER_DAIF_SHIFT
203 #define GMAC_MAC_PACKET_FILTER_DAIF_WIDTH        EMAC_MAC_PACKET_FILTER_DAIF_WIDTH
204 #define GMAC_MAC_PACKET_FILTER_DAIF(x)           EMAC_MAC_PACKET_FILTER_DAIF(x)
205 #define GMAC_MAC_PACKET_FILTER_PM_MASK           EMAC_MAC_PACKET_FILTER_PM_MASK
206 #define GMAC_MAC_PACKET_FILTER_PM_SHIFT          EMAC_MAC_PACKET_FILTER_PM_SHIFT
207 #define GMAC_MAC_PACKET_FILTER_PM_WIDTH          EMAC_MAC_PACKET_FILTER_PM_WIDTH
208 #define GMAC_MAC_PACKET_FILTER_PM(x)             EMAC_MAC_PACKET_FILTER_PM(x)
209 #define GMAC_MAC_PACKET_FILTER_DBF_MASK          EMAC_MAC_PACKET_FILTER_DBF_MASK
210 #define GMAC_MAC_PACKET_FILTER_DBF_SHIFT         EMAC_MAC_PACKET_FILTER_DBF_SHIFT
211 #define GMAC_MAC_PACKET_FILTER_DBF_WIDTH         EMAC_MAC_PACKET_FILTER_DBF_WIDTH
212 #define GMAC_MAC_PACKET_FILTER_DBF(x)            EMAC_MAC_PACKET_FILTER_DBF(x)
213 #define GMAC_MAC_PACKET_FILTER_PCF_MASK          EMAC_MAC_PACKET_FILTER_PCF_MASK
214 #define GMAC_MAC_PACKET_FILTER_PCF_SHIFT         EMAC_MAC_PACKET_FILTER_PCF_SHIFT
215 #define GMAC_MAC_PACKET_FILTER_PCF_WIDTH         EMAC_MAC_PACKET_FILTER_PCF_WIDTH
216 #define GMAC_MAC_PACKET_FILTER_PCF(x)            EMAC_MAC_PACKET_FILTER_PCF(x)
217 #define GMAC_MAC_PACKET_FILTER_SAIF_MASK         EMAC_MAC_PACKET_FILTER_SAIF_MASK
218 #define GMAC_MAC_PACKET_FILTER_SAIF_SHIFT        EMAC_MAC_PACKET_FILTER_SAIF_SHIFT
219 #define GMAC_MAC_PACKET_FILTER_SAIF_WIDTH        EMAC_MAC_PACKET_FILTER_SAIF_WIDTH
220 #define GMAC_MAC_PACKET_FILTER_SAIF(x)           EMAC_MAC_PACKET_FILTER_SAIF(x)
221 #define GMAC_MAC_PACKET_FILTER_SAF_MASK          EMAC_MAC_PACKET_FILTER_SAF_MASK
222 #define GMAC_MAC_PACKET_FILTER_SAF_SHIFT         EMAC_MAC_PACKET_FILTER_SAF_SHIFT
223 #define GMAC_MAC_PACKET_FILTER_SAF_WIDTH         EMAC_MAC_PACKET_FILTER_SAF_WIDTH
224 #define GMAC_MAC_PACKET_FILTER_SAF(x)            EMAC_MAC_PACKET_FILTER_SAF(x)
225 #define GMAC_MAC_PACKET_FILTER_HPF_MASK          EMAC_MAC_PACKET_FILTER_HPF_MASK
226 #define GMAC_MAC_PACKET_FILTER_HPF_SHIFT         EMAC_MAC_PACKET_FILTER_HPF_SHIFT
227 #define GMAC_MAC_PACKET_FILTER_HPF_WIDTH         EMAC_MAC_PACKET_FILTER_HPF_WIDTH
228 #define GMAC_MAC_PACKET_FILTER_HPF(x)            EMAC_MAC_PACKET_FILTER_HPF(x)
229 #define GMAC_MAC_PACKET_FILTER_VTFE_MASK         EMAC_MAC_PACKET_FILTER_VTFE_MASK
230 #define GMAC_MAC_PACKET_FILTER_VTFE_SHIFT        EMAC_MAC_PACKET_FILTER_VTFE_SHIFT
231 #define GMAC_MAC_PACKET_FILTER_VTFE_WIDTH        EMAC_MAC_PACKET_FILTER_VTFE_WIDTH
232 #define GMAC_MAC_PACKET_FILTER_VTFE(x)           EMAC_MAC_PACKET_FILTER_VTFE(x)
233 #define GMAC_MAC_PACKET_FILTER_IPFE_MASK         EMAC_MAC_PACKET_FILTER_IPFE_MASK
234 #define GMAC_MAC_PACKET_FILTER_IPFE_SHIFT        EMAC_MAC_PACKET_FILTER_IPFE_SHIFT
235 #define GMAC_MAC_PACKET_FILTER_IPFE_WIDTH        EMAC_MAC_PACKET_FILTER_IPFE_WIDTH
236 #define GMAC_MAC_PACKET_FILTER_IPFE(x)           EMAC_MAC_PACKET_FILTER_IPFE(x)
237 #define GMAC_MAC_PACKET_FILTER_DNTU_MASK         EMAC_MAC_PACKET_FILTER_DNTU_MASK
238 #define GMAC_MAC_PACKET_FILTER_DNTU_SHIFT        EMAC_MAC_PACKET_FILTER_DNTU_SHIFT
239 #define GMAC_MAC_PACKET_FILTER_DNTU_WIDTH        EMAC_MAC_PACKET_FILTER_DNTU_WIDTH
240 #define GMAC_MAC_PACKET_FILTER_DNTU(x)           EMAC_MAC_PACKET_FILTER_DNTU(x)
241 #define GMAC_MAC_PACKET_FILTER_RA_MASK           EMAC_MAC_PACKET_FILTER_RA_MASK
242 #define GMAC_MAC_PACKET_FILTER_RA_SHIFT          EMAC_MAC_PACKET_FILTER_RA_SHIFT
243 #define GMAC_MAC_PACKET_FILTER_RA_WIDTH          EMAC_MAC_PACKET_FILTER_RA_WIDTH
244 #define GMAC_MAC_PACKET_FILTER_RA(x)             EMAC_MAC_PACKET_FILTER_RA(x)
245 /*! @} */
246 
247 /*! @name MAC_WATCHDOG_TIMEOUT -  */
248 /*! @{ */
249 #define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK       EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK
250 #define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT      EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT
251 #define GMAC_MAC_WATCHDOG_TIMEOUT_WTO_WIDTH      EMAC_MAC_WATCHDOG_TIMEOUT_WTO_WIDTH
252 #define GMAC_MAC_WATCHDOG_TIMEOUT_WTO(x)         EMAC_MAC_WATCHDOG_TIMEOUT_WTO(x)
253 #define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_MASK       EMAC_MAC_WATCHDOG_TIMEOUT_PWE_MASK
254 #define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT      EMAC_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT
255 #define GMAC_MAC_WATCHDOG_TIMEOUT_PWE_WIDTH      EMAC_MAC_WATCHDOG_TIMEOUT_PWE_WIDTH
256 #define GMAC_MAC_WATCHDOG_TIMEOUT_PWE(x)         EMAC_MAC_WATCHDOG_TIMEOUT_PWE(x)
257 /*! @} */
258 
259 /*! @name MAC_HASH_TABLE_REG0 -  */
260 /*! @{ */
261 #define GMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK     EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK
262 #define GMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT    EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT
263 #define GMAC_MAC_HASH_TABLE_REG0_HT31T0_WIDTH    EMAC_MAC_HASH_TABLE_REG0_HT31T0_WIDTH
264 #define GMAC_MAC_HASH_TABLE_REG0_HT31T0(x)       EMAC_MAC_HASH_TABLE_REG0_HT31T0(x)
265 /*! @} */
266 
267 /*! @name MAC_HASH_TABLE_REG1 -  */
268 /*! @{ */
269 #define GMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK    EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK
270 #define GMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT   EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT
271 #define GMAC_MAC_HASH_TABLE_REG1_HT63T32_WIDTH   EMAC_MAC_HASH_TABLE_REG1_HT63T32_WIDTH
272 #define GMAC_MAC_HASH_TABLE_REG1_HT63T32(x)      EMAC_MAC_HASH_TABLE_REG1_HT63T32(x)
273 /*! @} */
274 
275 /*! @name MAC_VLAN_TAG_CTRL -  */
276 /*! @{ */
277 #define GMAC_MAC_VLAN_TAG_CTRL_OB_MASK           EMAC_MAC_VLAN_TAG_CTRL_OB_MASK
278 #define GMAC_MAC_VLAN_TAG_CTRL_OB_SHIFT          EMAC_MAC_VLAN_TAG_CTRL_OB_SHIFT
279 #define GMAC_MAC_VLAN_TAG_CTRL_OB_WIDTH          EMAC_MAC_VLAN_TAG_CTRL_OB_WIDTH
280 #define GMAC_MAC_VLAN_TAG_CTRL_OB(x)             EMAC_MAC_VLAN_TAG_CTRL_OB(x)
281 #define GMAC_MAC_VLAN_TAG_CTRL_CT_MASK           EMAC_MAC_VLAN_TAG_CTRL_CT_MASK
282 #define GMAC_MAC_VLAN_TAG_CTRL_CT_SHIFT          EMAC_MAC_VLAN_TAG_CTRL_CT_SHIFT
283 #define GMAC_MAC_VLAN_TAG_CTRL_CT_WIDTH          EMAC_MAC_VLAN_TAG_CTRL_CT_WIDTH
284 #define GMAC_MAC_VLAN_TAG_CTRL_CT(x)             EMAC_MAC_VLAN_TAG_CTRL_CT(x)
285 #define GMAC_MAC_VLAN_TAG_CTRL_OFS_MASK          EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK
286 #define GMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT         EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT
287 #define GMAC_MAC_VLAN_TAG_CTRL_OFS_WIDTH         EMAC_MAC_VLAN_TAG_CTRL_OFS_WIDTH
288 #define GMAC_MAC_VLAN_TAG_CTRL_OFS(x)            EMAC_MAC_VLAN_TAG_CTRL_OFS(x)
289 #define GMAC_MAC_VLAN_TAG_CTRL_ETV_MASK          EMAC_MAC_VLAN_TAG_CTRL_ETV_MASK
290 #define GMAC_MAC_VLAN_TAG_CTRL_ETV_SHIFT         EMAC_MAC_VLAN_TAG_CTRL_ETV_SHIFT
291 #define GMAC_MAC_VLAN_TAG_CTRL_ETV_WIDTH         EMAC_MAC_VLAN_TAG_CTRL_ETV_WIDTH
292 #define GMAC_MAC_VLAN_TAG_CTRL_ETV(x)            EMAC_MAC_VLAN_TAG_CTRL_ETV(x)
293 #define GMAC_MAC_VLAN_TAG_CTRL_VTIM_MASK         EMAC_MAC_VLAN_TAG_CTRL_VTIM_MASK
294 #define GMAC_MAC_VLAN_TAG_CTRL_VTIM_SHIFT        EMAC_MAC_VLAN_TAG_CTRL_VTIM_SHIFT
295 #define GMAC_MAC_VLAN_TAG_CTRL_VTIM_WIDTH        EMAC_MAC_VLAN_TAG_CTRL_VTIM_WIDTH
296 #define GMAC_MAC_VLAN_TAG_CTRL_VTIM(x)           EMAC_MAC_VLAN_TAG_CTRL_VTIM(x)
297 #define GMAC_MAC_VLAN_TAG_CTRL_ESVL_MASK         EMAC_MAC_VLAN_TAG_CTRL_ESVL_MASK
298 #define GMAC_MAC_VLAN_TAG_CTRL_ESVL_SHIFT        EMAC_MAC_VLAN_TAG_CTRL_ESVL_SHIFT
299 #define GMAC_MAC_VLAN_TAG_CTRL_ESVL_WIDTH        EMAC_MAC_VLAN_TAG_CTRL_ESVL_WIDTH
300 #define GMAC_MAC_VLAN_TAG_CTRL_ESVL(x)           EMAC_MAC_VLAN_TAG_CTRL_ESVL(x)
301 #define GMAC_MAC_VLAN_TAG_CTRL_ERSVLM_MASK       EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_MASK
302 #define GMAC_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT      EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_SHIFT
303 #define GMAC_MAC_VLAN_TAG_CTRL_ERSVLM_WIDTH      EMAC_MAC_VLAN_TAG_CTRL_ERSVLM_WIDTH
304 #define GMAC_MAC_VLAN_TAG_CTRL_ERSVLM(x)         EMAC_MAC_VLAN_TAG_CTRL_ERSVLM(x)
305 #define GMAC_MAC_VLAN_TAG_CTRL_DOVLTC_MASK       EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_MASK
306 #define GMAC_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT      EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_SHIFT
307 #define GMAC_MAC_VLAN_TAG_CTRL_DOVLTC_WIDTH      EMAC_MAC_VLAN_TAG_CTRL_DOVLTC_WIDTH
308 #define GMAC_MAC_VLAN_TAG_CTRL_DOVLTC(x)         EMAC_MAC_VLAN_TAG_CTRL_DOVLTC(x)
309 #define GMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK         EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK
310 #define GMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT        EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT
311 #define GMAC_MAC_VLAN_TAG_CTRL_EVLS_WIDTH        EMAC_MAC_VLAN_TAG_CTRL_EVLS_WIDTH
312 #define GMAC_MAC_VLAN_TAG_CTRL_EVLS(x)           EMAC_MAC_VLAN_TAG_CTRL_EVLS(x)
313 #define GMAC_MAC_VLAN_TAG_CTRL_EVLRXS_MASK       EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_MASK
314 #define GMAC_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT      EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT
315 #define GMAC_MAC_VLAN_TAG_CTRL_EVLRXS_WIDTH      EMAC_MAC_VLAN_TAG_CTRL_EVLRXS_WIDTH
316 #define GMAC_MAC_VLAN_TAG_CTRL_EVLRXS(x)         EMAC_MAC_VLAN_TAG_CTRL_EVLRXS(x)
317 #define GMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK         EMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK
318 #define GMAC_MAC_VLAN_TAG_CTRL_VTHM_SHIFT        EMAC_MAC_VLAN_TAG_CTRL_VTHM_SHIFT
319 #define GMAC_MAC_VLAN_TAG_CTRL_VTHM_WIDTH        EMAC_MAC_VLAN_TAG_CTRL_VTHM_WIDTH
320 #define GMAC_MAC_VLAN_TAG_CTRL_VTHM(x)           EMAC_MAC_VLAN_TAG_CTRL_VTHM(x)
321 #define GMAC_MAC_VLAN_TAG_CTRL_EDVLP_MASK        EMAC_MAC_VLAN_TAG_CTRL_EDVLP_MASK
322 #define GMAC_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT       EMAC_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT
323 #define GMAC_MAC_VLAN_TAG_CTRL_EDVLP_WIDTH       EMAC_MAC_VLAN_TAG_CTRL_EDVLP_WIDTH
324 #define GMAC_MAC_VLAN_TAG_CTRL_EDVLP(x)          EMAC_MAC_VLAN_TAG_CTRL_EDVLP(x)
325 #define GMAC_MAC_VLAN_TAG_CTRL_ERIVLT_MASK       EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_MASK
326 #define GMAC_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT      EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT
327 #define GMAC_MAC_VLAN_TAG_CTRL_ERIVLT_WIDTH      EMAC_MAC_VLAN_TAG_CTRL_ERIVLT_WIDTH
328 #define GMAC_MAC_VLAN_TAG_CTRL_ERIVLT(x)         EMAC_MAC_VLAN_TAG_CTRL_ERIVLT(x)
329 #define GMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK        EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK
330 #define GMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT       EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT
331 #define GMAC_MAC_VLAN_TAG_CTRL_EIVLS_WIDTH       EMAC_MAC_VLAN_TAG_CTRL_EIVLS_WIDTH
332 #define GMAC_MAC_VLAN_TAG_CTRL_EIVLS(x)          EMAC_MAC_VLAN_TAG_CTRL_EIVLS(x)
333 #define GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK      EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK
334 #define GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT     EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT
335 #define GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_WIDTH     EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS_WIDTH
336 #define GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS(x)        EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS(x)
337 /*! @} */
338 
339 /*! @name MAC_VLAN_TAG_DATA -  */
340 /*! @{ */
341 #define GMAC_MAC_VLAN_TAG_DATA_VID_MASK          EMAC_MAC_VLAN_TAG_DATA_VID_MASK
342 #define GMAC_MAC_VLAN_TAG_DATA_VID_SHIFT         EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT
343 #define GMAC_MAC_VLAN_TAG_DATA_VID_WIDTH         EMAC_MAC_VLAN_TAG_DATA_VID_WIDTH
344 #define GMAC_MAC_VLAN_TAG_DATA_VID(x)            EMAC_MAC_VLAN_TAG_DATA_VID(x)
345 #define GMAC_MAC_VLAN_TAG_DATA_VEN_MASK          EMAC_MAC_VLAN_TAG_DATA_VEN_MASK
346 #define GMAC_MAC_VLAN_TAG_DATA_VEN_SHIFT         EMAC_MAC_VLAN_TAG_DATA_VEN_SHIFT
347 #define GMAC_MAC_VLAN_TAG_DATA_VEN_WIDTH         EMAC_MAC_VLAN_TAG_DATA_VEN_WIDTH
348 #define GMAC_MAC_VLAN_TAG_DATA_VEN(x)            EMAC_MAC_VLAN_TAG_DATA_VEN(x)
349 #define GMAC_MAC_VLAN_TAG_DATA_ETV_MASK          EMAC_MAC_VLAN_TAG_DATA_ETV_MASK
350 #define GMAC_MAC_VLAN_TAG_DATA_ETV_SHIFT         EMAC_MAC_VLAN_TAG_DATA_ETV_SHIFT
351 #define GMAC_MAC_VLAN_TAG_DATA_ETV_WIDTH         EMAC_MAC_VLAN_TAG_DATA_ETV_WIDTH
352 #define GMAC_MAC_VLAN_TAG_DATA_ETV(x)            EMAC_MAC_VLAN_TAG_DATA_ETV(x)
353 #define GMAC_MAC_VLAN_TAG_DATA_DOVLTC_MASK       EMAC_MAC_VLAN_TAG_DATA_DOVLTC_MASK
354 #define GMAC_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT      EMAC_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT
355 #define GMAC_MAC_VLAN_TAG_DATA_DOVLTC_WIDTH      EMAC_MAC_VLAN_TAG_DATA_DOVLTC_WIDTH
356 #define GMAC_MAC_VLAN_TAG_DATA_DOVLTC(x)         EMAC_MAC_VLAN_TAG_DATA_DOVLTC(x)
357 #define GMAC_MAC_VLAN_TAG_DATA_ERSVLM_MASK       EMAC_MAC_VLAN_TAG_DATA_ERSVLM_MASK
358 #define GMAC_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT      EMAC_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT
359 #define GMAC_MAC_VLAN_TAG_DATA_ERSVLM_WIDTH      EMAC_MAC_VLAN_TAG_DATA_ERSVLM_WIDTH
360 #define GMAC_MAC_VLAN_TAG_DATA_ERSVLM(x)         EMAC_MAC_VLAN_TAG_DATA_ERSVLM(x)
361 #define GMAC_MAC_VLAN_TAG_DATA_ERIVLT_MASK       EMAC_MAC_VLAN_TAG_DATA_ERIVLT_MASK
362 #define GMAC_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT      EMAC_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT
363 #define GMAC_MAC_VLAN_TAG_DATA_ERIVLT_WIDTH      EMAC_MAC_VLAN_TAG_DATA_ERIVLT_WIDTH
364 #define GMAC_MAC_VLAN_TAG_DATA_ERIVLT(x)         EMAC_MAC_VLAN_TAG_DATA_ERIVLT(x)
365 #define GMAC_MAC_VLAN_TAG_DATA_DMACHEN_MASK      EMAC_MAC_VLAN_TAG_DATA_DMACHEN_MASK
366 #define GMAC_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT     EMAC_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT
367 #define GMAC_MAC_VLAN_TAG_DATA_DMACHEN_WIDTH     EMAC_MAC_VLAN_TAG_DATA_DMACHEN_WIDTH
368 #define GMAC_MAC_VLAN_TAG_DATA_DMACHEN(x)        EMAC_MAC_VLAN_TAG_DATA_DMACHEN(x)
369 #define GMAC_MAC_VLAN_TAG_DATA_DMACHN_MASK       EMAC_MAC_VLAN_TAG_DATA_DMACHN_MASK
370 #define GMAC_MAC_VLAN_TAG_DATA_DMACHN_SHIFT      EMAC_MAC_VLAN_TAG_DATA_DMACHN_SHIFT
371 #define GMAC_MAC_VLAN_TAG_DATA_DMACHN_WIDTH      EMAC_MAC_VLAN_TAG_DATA_DMACHN_WIDTH
372 #define GMAC_MAC_VLAN_TAG_DATA_DMACHN(x)         EMAC_MAC_VLAN_TAG_DATA_DMACHN(x)
373 /*! @} */
374 
375 /*! @name MAC_VLAN_HASH_TABLE -  */
376 /*! @{ */
377 #define GMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK       EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK
378 #define GMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT      EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT
379 #define GMAC_MAC_VLAN_HASH_TABLE_VLHT_WIDTH      EMAC_MAC_VLAN_HASH_TABLE_VLHT_WIDTH
380 #define GMAC_MAC_VLAN_HASH_TABLE_VLHT(x)         EMAC_MAC_VLAN_HASH_TABLE_VLHT(x)
381 /*! @} */
382 
383 /*! @name MAC_VLAN_INCL -  */
384 /*! @{ */
385 #define GMAC_MAC_VLAN_INCL_VLT_MASK              EMAC_MAC_VLAN_INCL_VLT_MASK
386 #define GMAC_MAC_VLAN_INCL_VLT_SHIFT             EMAC_MAC_VLAN_INCL_VLT_SHIFT
387 #define GMAC_MAC_VLAN_INCL_VLT_WIDTH             EMAC_MAC_VLAN_INCL_VLT_WIDTH
388 #define GMAC_MAC_VLAN_INCL_VLT(x)                EMAC_MAC_VLAN_INCL_VLT(x)
389 #define GMAC_MAC_VLAN_INCL_VLC_MASK              EMAC_MAC_VLAN_INCL_VLC_MASK
390 #define GMAC_MAC_VLAN_INCL_VLC_SHIFT             EMAC_MAC_VLAN_INCL_VLC_SHIFT
391 #define GMAC_MAC_VLAN_INCL_VLC_WIDTH             EMAC_MAC_VLAN_INCL_VLC_WIDTH
392 #define GMAC_MAC_VLAN_INCL_VLC(x)                EMAC_MAC_VLAN_INCL_VLC(x)
393 #define GMAC_MAC_VLAN_INCL_VLP_MASK              EMAC_MAC_VLAN_INCL_VLP_MASK
394 #define GMAC_MAC_VLAN_INCL_VLP_SHIFT             EMAC_MAC_VLAN_INCL_VLP_SHIFT
395 #define GMAC_MAC_VLAN_INCL_VLP_WIDTH             EMAC_MAC_VLAN_INCL_VLP_WIDTH
396 #define GMAC_MAC_VLAN_INCL_VLP(x)                EMAC_MAC_VLAN_INCL_VLP(x)
397 #define GMAC_MAC_VLAN_INCL_CSVL_MASK             EMAC_MAC_VLAN_INCL_CSVL_MASK
398 #define GMAC_MAC_VLAN_INCL_CSVL_SHIFT            EMAC_MAC_VLAN_INCL_CSVL_SHIFT
399 #define GMAC_MAC_VLAN_INCL_CSVL_WIDTH            EMAC_MAC_VLAN_INCL_CSVL_WIDTH
400 #define GMAC_MAC_VLAN_INCL_CSVL(x)               EMAC_MAC_VLAN_INCL_CSVL(x)
401 #define GMAC_MAC_VLAN_INCL_VLTI_MASK             EMAC_MAC_VLAN_INCL_VLTI_MASK
402 #define GMAC_MAC_VLAN_INCL_VLTI_SHIFT            EMAC_MAC_VLAN_INCL_VLTI_SHIFT
403 #define GMAC_MAC_VLAN_INCL_VLTI_WIDTH            EMAC_MAC_VLAN_INCL_VLTI_WIDTH
404 #define GMAC_MAC_VLAN_INCL_VLTI(x)               EMAC_MAC_VLAN_INCL_VLTI(x)
405 #define GMAC_MAC_VLAN_INCL_CBTI_MASK             EMAC_MAC_VLAN_INCL_CBTI_MASK
406 #define GMAC_MAC_VLAN_INCL_CBTI_SHIFT            EMAC_MAC_VLAN_INCL_CBTI_SHIFT
407 #define GMAC_MAC_VLAN_INCL_CBTI_WIDTH            EMAC_MAC_VLAN_INCL_CBTI_WIDTH
408 #define GMAC_MAC_VLAN_INCL_CBTI(x)               EMAC_MAC_VLAN_INCL_CBTI(x)
409 #define GMAC_MAC_VLAN_INCL_ADDR_MASK             EMAC_MAC_VLAN_INCL_ADDR_MASK
410 #define GMAC_MAC_VLAN_INCL_ADDR_SHIFT            EMAC_MAC_VLAN_INCL_ADDR_SHIFT
411 #define GMAC_MAC_VLAN_INCL_ADDR_WIDTH            EMAC_MAC_VLAN_INCL_ADDR_WIDTH
412 #define GMAC_MAC_VLAN_INCL_ADDR(x)               EMAC_MAC_VLAN_INCL_ADDR(x)
413 #define GMAC_MAC_VLAN_INCL_RDWR_MASK             EMAC_MAC_VLAN_INCL_RDWR_MASK
414 #define GMAC_MAC_VLAN_INCL_RDWR_SHIFT            EMAC_MAC_VLAN_INCL_RDWR_SHIFT
415 #define GMAC_MAC_VLAN_INCL_RDWR_WIDTH            EMAC_MAC_VLAN_INCL_RDWR_WIDTH
416 #define GMAC_MAC_VLAN_INCL_RDWR(x)               EMAC_MAC_VLAN_INCL_RDWR(x)
417 #define GMAC_MAC_VLAN_INCL_BUSY_MASK             EMAC_MAC_VLAN_INCL_BUSY_MASK
418 #define GMAC_MAC_VLAN_INCL_BUSY_SHIFT            EMAC_MAC_VLAN_INCL_BUSY_SHIFT
419 #define GMAC_MAC_VLAN_INCL_BUSY_WIDTH            EMAC_MAC_VLAN_INCL_BUSY_WIDTH
420 #define GMAC_MAC_VLAN_INCL_BUSY(x)               EMAC_MAC_VLAN_INCL_BUSY(x)
421 /*! @} */
422 
423 /*! @name MAC_INNER_VLAN_INCL -  */
424 /*! @{ */
425 #define GMAC_MAC_INNER_VLAN_INCL_VLT_MASK        EMAC_MAC_INNER_VLAN_INCL_VLT_MASK
426 #define GMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT       EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT
427 #define GMAC_MAC_INNER_VLAN_INCL_VLT_WIDTH       EMAC_MAC_INNER_VLAN_INCL_VLT_WIDTH
428 #define GMAC_MAC_INNER_VLAN_INCL_VLT(x)          EMAC_MAC_INNER_VLAN_INCL_VLT(x)
429 #define GMAC_MAC_INNER_VLAN_INCL_VLC_MASK        EMAC_MAC_INNER_VLAN_INCL_VLC_MASK
430 #define GMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT       EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT
431 #define GMAC_MAC_INNER_VLAN_INCL_VLC_WIDTH       EMAC_MAC_INNER_VLAN_INCL_VLC_WIDTH
432 #define GMAC_MAC_INNER_VLAN_INCL_VLC(x)          EMAC_MAC_INNER_VLAN_INCL_VLC(x)
433 #define GMAC_MAC_INNER_VLAN_INCL_VLP_MASK        EMAC_MAC_INNER_VLAN_INCL_VLP_MASK
434 #define GMAC_MAC_INNER_VLAN_INCL_VLP_SHIFT       EMAC_MAC_INNER_VLAN_INCL_VLP_SHIFT
435 #define GMAC_MAC_INNER_VLAN_INCL_VLP_WIDTH       EMAC_MAC_INNER_VLAN_INCL_VLP_WIDTH
436 #define GMAC_MAC_INNER_VLAN_INCL_VLP(x)          EMAC_MAC_INNER_VLAN_INCL_VLP(x)
437 #define GMAC_MAC_INNER_VLAN_INCL_CSVL_MASK       EMAC_MAC_INNER_VLAN_INCL_CSVL_MASK
438 #define GMAC_MAC_INNER_VLAN_INCL_CSVL_SHIFT      EMAC_MAC_INNER_VLAN_INCL_CSVL_SHIFT
439 #define GMAC_MAC_INNER_VLAN_INCL_CSVL_WIDTH      EMAC_MAC_INNER_VLAN_INCL_CSVL_WIDTH
440 #define GMAC_MAC_INNER_VLAN_INCL_CSVL(x)         EMAC_MAC_INNER_VLAN_INCL_CSVL(x)
441 #define GMAC_MAC_INNER_VLAN_INCL_VLTI_MASK       EMAC_MAC_INNER_VLAN_INCL_VLTI_MASK
442 #define GMAC_MAC_INNER_VLAN_INCL_VLTI_SHIFT      EMAC_MAC_INNER_VLAN_INCL_VLTI_SHIFT
443 #define GMAC_MAC_INNER_VLAN_INCL_VLTI_WIDTH      EMAC_MAC_INNER_VLAN_INCL_VLTI_WIDTH
444 #define GMAC_MAC_INNER_VLAN_INCL_VLTI(x)         EMAC_MAC_INNER_VLAN_INCL_VLTI(x)
445 /*! @} */
446 
447 /*! @name MAC_Q0_TX_FLOW_CTRL -  */
448 /*! @{ */
449 #define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK    EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MASK
450 #define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT   EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_SHIFT
451 #define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_WIDTH   EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_WIDTH
452 #define GMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA(x)      EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA(x)
453 #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK        EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_MASK
454 #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT       EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_SHIFT
455 #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE_WIDTH       EMAC_MAC_Q0_TX_FLOW_CTRL_TFE_WIDTH
456 #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE(x)          EMAC_MAC_Q0_TX_FLOW_CTRL_TFE(x)
457 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK        EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK
458 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT       EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT
459 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT_WIDTH       EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_WIDTH
460 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PLT(x)          EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(x)
461 #define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK       EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_MASK
462 #define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT      EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_SHIFT
463 #define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_WIDTH      EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ_WIDTH
464 #define GMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ(x)         EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ(x)
465 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK         EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK
466 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT        EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT
467 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_WIDTH        EMAC_MAC_Q0_TX_FLOW_CTRL_PT_WIDTH
468 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT(x)           EMAC_MAC_Q0_TX_FLOW_CTRL_PT(x)
469 /*! @} */
470 
471 /*! @name MAC_RX_FLOW_CTRL -  */
472 /*! @{ */
473 #define GMAC_MAC_RX_FLOW_CTRL_RFE_MASK           EMAC_MAC_RX_FLOW_CTRL_RFE_MASK
474 #define GMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT          EMAC_MAC_RX_FLOW_CTRL_RFE_SHIFT
475 #define GMAC_MAC_RX_FLOW_CTRL_RFE_WIDTH          EMAC_MAC_RX_FLOW_CTRL_RFE_WIDTH
476 #define GMAC_MAC_RX_FLOW_CTRL_RFE(x)             EMAC_MAC_RX_FLOW_CTRL_RFE(x)
477 #define GMAC_MAC_RX_FLOW_CTRL_UP_MASK            EMAC_MAC_RX_FLOW_CTRL_UP_MASK
478 #define GMAC_MAC_RX_FLOW_CTRL_UP_SHIFT           EMAC_MAC_RX_FLOW_CTRL_UP_SHIFT
479 #define GMAC_MAC_RX_FLOW_CTRL_UP_WIDTH           EMAC_MAC_RX_FLOW_CTRL_UP_WIDTH
480 #define GMAC_MAC_RX_FLOW_CTRL_UP(x)              EMAC_MAC_RX_FLOW_CTRL_UP(x)
481 /*! @} */
482 
483 /*! @name MAC_RXQ_CTRL4 -  */
484 /*! @{ */
485 #define GMAC_MAC_RXQ_CTRL4_UFFQE_MASK            EMAC_MAC_RXQ_CTRL4_UFFQE_MASK
486 #define GMAC_MAC_RXQ_CTRL4_UFFQE_SHIFT           EMAC_MAC_RXQ_CTRL4_UFFQE_SHIFT
487 #define GMAC_MAC_RXQ_CTRL4_UFFQE_WIDTH           EMAC_MAC_RXQ_CTRL4_UFFQE_WIDTH
488 #define GMAC_MAC_RXQ_CTRL4_UFFQE(x)              EMAC_MAC_RXQ_CTRL4_UFFQE(x)
489 #define GMAC_MAC_RXQ_CTRL4_UFFQ_MASK             EMAC_MAC_RXQ_CTRL4_UFFQ_MASK
490 #define GMAC_MAC_RXQ_CTRL4_UFFQ_SHIFT            EMAC_MAC_RXQ_CTRL4_UFFQ_SHIFT
491 #define GMAC_MAC_RXQ_CTRL4_UFFQ_WIDTH            EMAC_MAC_RXQ_CTRL4_UFFQ_WIDTH
492 #define GMAC_MAC_RXQ_CTRL4_UFFQ(x)               EMAC_MAC_RXQ_CTRL4_UFFQ(x)
493 #define GMAC_MAC_RXQ_CTRL4_MFFQE_MASK            EMAC_MAC_RXQ_CTRL4_MFFQE_MASK
494 #define GMAC_MAC_RXQ_CTRL4_MFFQE_SHIFT           EMAC_MAC_RXQ_CTRL4_MFFQE_SHIFT
495 #define GMAC_MAC_RXQ_CTRL4_MFFQE_WIDTH           EMAC_MAC_RXQ_CTRL4_MFFQE_WIDTH
496 #define GMAC_MAC_RXQ_CTRL4_MFFQE(x)              EMAC_MAC_RXQ_CTRL4_MFFQE(x)
497 #define GMAC_MAC_RXQ_CTRL4_MFFQ_MASK             EMAC_MAC_RXQ_CTRL4_MFFQ_MASK
498 #define GMAC_MAC_RXQ_CTRL4_MFFQ_SHIFT            EMAC_MAC_RXQ_CTRL4_MFFQ_SHIFT
499 #define GMAC_MAC_RXQ_CTRL4_MFFQ_WIDTH            EMAC_MAC_RXQ_CTRL4_MFFQ_WIDTH
500 #define GMAC_MAC_RXQ_CTRL4_MFFQ(x)               EMAC_MAC_RXQ_CTRL4_MFFQ(x)
501 #define GMAC_MAC_RXQ_CTRL4_VFFQE_MASK            EMAC_MAC_RXQ_CTRL4_VFFQE_MASK
502 #define GMAC_MAC_RXQ_CTRL4_VFFQE_SHIFT           EMAC_MAC_RXQ_CTRL4_VFFQE_SHIFT
503 #define GMAC_MAC_RXQ_CTRL4_VFFQE_WIDTH           EMAC_MAC_RXQ_CTRL4_VFFQE_WIDTH
504 #define GMAC_MAC_RXQ_CTRL4_VFFQE(x)              EMAC_MAC_RXQ_CTRL4_VFFQE(x)
505 #define GMAC_MAC_RXQ_CTRL4_VFFQ_MASK             EMAC_MAC_RXQ_CTRL4_VFFQ_MASK
506 #define GMAC_MAC_RXQ_CTRL4_VFFQ_SHIFT            EMAC_MAC_RXQ_CTRL4_VFFQ_SHIFT
507 #define GMAC_MAC_RXQ_CTRL4_VFFQ_WIDTH            EMAC_MAC_RXQ_CTRL4_VFFQ_WIDTH
508 #define GMAC_MAC_RXQ_CTRL4_VFFQ(x)               EMAC_MAC_RXQ_CTRL4_VFFQ(x)
509 /*! @} */
510 
511 /*! @name MAC_RXQ_CTRL0 -  */
512 /*! @{ */
513 #define GMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK           EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK
514 #define GMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT          EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT
515 #define GMAC_MAC_RXQ_CTRL0_RXQ0EN_WIDTH          EMAC_MAC_RXQ_CTRL0_RXQ0EN_WIDTH
516 #define GMAC_MAC_RXQ_CTRL0_RXQ0EN(x)             EMAC_MAC_RXQ_CTRL0_RXQ0EN(x)
517 #define GMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK           EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK
518 #define GMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT          EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT
519 #define GMAC_MAC_RXQ_CTRL0_RXQ1EN_WIDTH          EMAC_MAC_RXQ_CTRL0_RXQ1EN_WIDTH
520 #define GMAC_MAC_RXQ_CTRL0_RXQ1EN(x)             EMAC_MAC_RXQ_CTRL0_RXQ1EN(x)
521 /*! @} */
522 
523 /*! @name MAC_RXQ_CTRL1 -  */
524 /*! @{ */
525 #define GMAC_MAC_RXQ_CTRL1_AVCPQ_MASK            EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK
526 #define GMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT           EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT
527 #define GMAC_MAC_RXQ_CTRL1_AVCPQ_WIDTH           EMAC_MAC_RXQ_CTRL1_AVCPQ_WIDTH
528 #define GMAC_MAC_RXQ_CTRL1_AVCPQ(x)              EMAC_MAC_RXQ_CTRL1_AVCPQ(x)
529 #define GMAC_MAC_RXQ_CTRL1_PTPQ_MASK             EMAC_MAC_RXQ_CTRL1_PTPQ_MASK
530 #define GMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT            EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT
531 #define GMAC_MAC_RXQ_CTRL1_PTPQ_WIDTH            EMAC_MAC_RXQ_CTRL1_PTPQ_WIDTH
532 #define GMAC_MAC_RXQ_CTRL1_PTPQ(x)               EMAC_MAC_RXQ_CTRL1_PTPQ(x)
533 #define GMAC_MAC_RXQ_CTRL1_UPQ_MASK              EMAC_MAC_RXQ_CTRL1_UPQ_MASK
534 #define GMAC_MAC_RXQ_CTRL1_UPQ_SHIFT             EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT
535 #define GMAC_MAC_RXQ_CTRL1_UPQ_WIDTH             EMAC_MAC_RXQ_CTRL1_UPQ_WIDTH
536 #define GMAC_MAC_RXQ_CTRL1_UPQ(x)                EMAC_MAC_RXQ_CTRL1_UPQ(x)
537 #define GMAC_MAC_RXQ_CTRL1_MCBCQ_MASK            EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK
538 #define GMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT           EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT
539 #define GMAC_MAC_RXQ_CTRL1_MCBCQ_WIDTH           EMAC_MAC_RXQ_CTRL1_MCBCQ_WIDTH
540 #define GMAC_MAC_RXQ_CTRL1_MCBCQ(x)              EMAC_MAC_RXQ_CTRL1_MCBCQ(x)
541 #define GMAC_MAC_RXQ_CTRL1_MCBCQEN_MASK          EMAC_MAC_RXQ_CTRL1_MCBCQEN_MASK
542 #define GMAC_MAC_RXQ_CTRL1_MCBCQEN_SHIFT         EMAC_MAC_RXQ_CTRL1_MCBCQEN_SHIFT
543 #define GMAC_MAC_RXQ_CTRL1_MCBCQEN_WIDTH         EMAC_MAC_RXQ_CTRL1_MCBCQEN_WIDTH
544 #define GMAC_MAC_RXQ_CTRL1_MCBCQEN(x)            EMAC_MAC_RXQ_CTRL1_MCBCQEN(x)
545 #define GMAC_MAC_RXQ_CTRL1_TACPQE_MASK           EMAC_MAC_RXQ_CTRL1_TACPQE_MASK
546 #define GMAC_MAC_RXQ_CTRL1_TACPQE_SHIFT          EMAC_MAC_RXQ_CTRL1_TACPQE_SHIFT
547 #define GMAC_MAC_RXQ_CTRL1_TACPQE_WIDTH          EMAC_MAC_RXQ_CTRL1_TACPQE_WIDTH
548 #define GMAC_MAC_RXQ_CTRL1_TACPQE(x)             EMAC_MAC_RXQ_CTRL1_TACPQE(x)
549 #define GMAC_MAC_RXQ_CTRL1_TPQC_MASK             EMAC_MAC_RXQ_CTRL1_TPQC_MASK
550 #define GMAC_MAC_RXQ_CTRL1_TPQC_SHIFT            EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT
551 #define GMAC_MAC_RXQ_CTRL1_TPQC_WIDTH            EMAC_MAC_RXQ_CTRL1_TPQC_WIDTH
552 #define GMAC_MAC_RXQ_CTRL1_TPQC(x)               EMAC_MAC_RXQ_CTRL1_TPQC(x)
553 #define GMAC_MAC_RXQ_CTRL1_FPRQ_MASK             EMAC_MAC_RXQ_CTRL1_FPRQ_MASK
554 #define GMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT            EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT
555 #define GMAC_MAC_RXQ_CTRL1_FPRQ_WIDTH            EMAC_MAC_RXQ_CTRL1_FPRQ_WIDTH
556 #define GMAC_MAC_RXQ_CTRL1_FPRQ(x)               EMAC_MAC_RXQ_CTRL1_FPRQ(x)
557 /*! @} */
558 
559 /*! @name MAC_RXQ_CTRL2 -  */
560 /*! @{ */
561 #define GMAC_MAC_RXQ_CTRL2_PSRQ0_MASK            EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK
562 #define GMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT           EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT
563 #define GMAC_MAC_RXQ_CTRL2_PSRQ0_WIDTH           EMAC_MAC_RXQ_CTRL2_PSRQ0_WIDTH
564 #define GMAC_MAC_RXQ_CTRL2_PSRQ0(x)              EMAC_MAC_RXQ_CTRL2_PSRQ0(x)
565 #define GMAC_MAC_RXQ_CTRL2_PSRQ1_MASK            EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK
566 #define GMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT           EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT
567 #define GMAC_MAC_RXQ_CTRL2_PSRQ1_WIDTH           EMAC_MAC_RXQ_CTRL2_PSRQ1_WIDTH
568 #define GMAC_MAC_RXQ_CTRL2_PSRQ1(x)              EMAC_MAC_RXQ_CTRL2_PSRQ1(x)
569 /*! @} */
570 
571 /*! @name MAC_INTERRUPT_STATUS -  */
572 /*! @{ */
573 #define GMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK     EMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK
574 #define GMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT    EMAC_MAC_INTERRUPT_STATUS_PHYIS_SHIFT
575 #define GMAC_MAC_INTERRUPT_STATUS_PHYIS_WIDTH    EMAC_MAC_INTERRUPT_STATUS_PHYIS_WIDTH
576 #define GMAC_MAC_INTERRUPT_STATUS_PHYIS(x)       EMAC_MAC_INTERRUPT_STATUS_PHYIS(x)
577 #define GMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK     EMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK
578 #define GMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT    EMAC_MAC_INTERRUPT_STATUS_MMCIS_SHIFT
579 #define GMAC_MAC_INTERRUPT_STATUS_MMCIS_WIDTH    EMAC_MAC_INTERRUPT_STATUS_MMCIS_WIDTH
580 #define GMAC_MAC_INTERRUPT_STATUS_MMCIS(x)       EMAC_MAC_INTERRUPT_STATUS_MMCIS(x)
581 #define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK   EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK
582 #define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT  EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT
583 #define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_WIDTH  EMAC_MAC_INTERRUPT_STATUS_MMCRXIS_WIDTH
584 #define GMAC_MAC_INTERRUPT_STATUS_MMCRXIS(x)     EMAC_MAC_INTERRUPT_STATUS_MMCRXIS(x)
585 #define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK   EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK
586 #define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT  EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT
587 #define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_WIDTH  EMAC_MAC_INTERRUPT_STATUS_MMCTXIS_WIDTH
588 #define GMAC_MAC_INTERRUPT_STATUS_MMCTXIS(x)     EMAC_MAC_INTERRUPT_STATUS_MMCTXIS(x)
589 #define GMAC_MAC_INTERRUPT_STATUS_TSIS_MASK      EMAC_MAC_INTERRUPT_STATUS_TSIS_MASK
590 #define GMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT     EMAC_MAC_INTERRUPT_STATUS_TSIS_SHIFT
591 #define GMAC_MAC_INTERRUPT_STATUS_TSIS_WIDTH     EMAC_MAC_INTERRUPT_STATUS_TSIS_WIDTH
592 #define GMAC_MAC_INTERRUPT_STATUS_TSIS(x)        EMAC_MAC_INTERRUPT_STATUS_TSIS(x)
593 #define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK   EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK
594 #define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT  EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT
595 #define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_WIDTH  EMAC_MAC_INTERRUPT_STATUS_TXSTSIS_WIDTH
596 #define GMAC_MAC_INTERRUPT_STATUS_TXSTSIS(x)     EMAC_MAC_INTERRUPT_STATUS_TXSTSIS(x)
597 #define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK   EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK
598 #define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT  EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT
599 #define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_WIDTH  EMAC_MAC_INTERRUPT_STATUS_RXSTSIS_WIDTH
600 #define GMAC_MAC_INTERRUPT_STATUS_RXSTSIS(x)     EMAC_MAC_INTERRUPT_STATUS_RXSTSIS(x)
601 #define GMAC_MAC_INTERRUPT_STATUS_FPEIS_MASK     EMAC_MAC_INTERRUPT_STATUS_FPEIS_MASK
602 #define GMAC_MAC_INTERRUPT_STATUS_FPEIS_SHIFT    EMAC_MAC_INTERRUPT_STATUS_FPEIS_SHIFT
603 #define GMAC_MAC_INTERRUPT_STATUS_FPEIS_WIDTH    EMAC_MAC_INTERRUPT_STATUS_FPEIS_WIDTH
604 #define GMAC_MAC_INTERRUPT_STATUS_FPEIS(x)       EMAC_MAC_INTERRUPT_STATUS_FPEIS(x)
605 #define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK    EMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK
606 #define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT   EMAC_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT
607 #define GMAC_MAC_INTERRUPT_STATUS_MDIOIS_WIDTH   EMAC_MAC_INTERRUPT_STATUS_MDIOIS_WIDTH
608 #define GMAC_MAC_INTERRUPT_STATUS_MDIOIS(x)      EMAC_MAC_INTERRUPT_STATUS_MDIOIS(x)
609 #define GMAC_MAC_INTERRUPT_STATUS_MFTIS_MASK     EMAC_MAC_INTERRUPT_STATUS_MFTIS_MASK
610 #define GMAC_MAC_INTERRUPT_STATUS_MFTIS_SHIFT    EMAC_MAC_INTERRUPT_STATUS_MFTIS_SHIFT
611 #define GMAC_MAC_INTERRUPT_STATUS_MFTIS_WIDTH    EMAC_MAC_INTERRUPT_STATUS_MFTIS_WIDTH
612 #define GMAC_MAC_INTERRUPT_STATUS_MFTIS(x)       EMAC_MAC_INTERRUPT_STATUS_MFTIS(x)
613 #define GMAC_MAC_INTERRUPT_STATUS_MFRIS_MASK     EMAC_MAC_INTERRUPT_STATUS_MFRIS_MASK
614 #define GMAC_MAC_INTERRUPT_STATUS_MFRIS_SHIFT    EMAC_MAC_INTERRUPT_STATUS_MFRIS_SHIFT
615 #define GMAC_MAC_INTERRUPT_STATUS_MFRIS_WIDTH    EMAC_MAC_INTERRUPT_STATUS_MFRIS_WIDTH
616 #define GMAC_MAC_INTERRUPT_STATUS_MFRIS(x)       EMAC_MAC_INTERRUPT_STATUS_MFRIS(x)
617 /*! @} */
618 
619 /*! @name MAC_INTERRUPT_ENABLE -  */
620 /*! @{ */
621 #define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_MASK     EMAC_MAC_INTERRUPT_ENABLE_PHYIE_MASK
622 #define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT    EMAC_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT
623 #define GMAC_MAC_INTERRUPT_ENABLE_PHYIE_WIDTH    EMAC_MAC_INTERRUPT_ENABLE_PHYIE_WIDTH
624 #define GMAC_MAC_INTERRUPT_ENABLE_PHYIE(x)       EMAC_MAC_INTERRUPT_ENABLE_PHYIE(x)
625 #define GMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK      EMAC_MAC_INTERRUPT_ENABLE_TSIE_MASK
626 #define GMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT     EMAC_MAC_INTERRUPT_ENABLE_TSIE_SHIFT
627 #define GMAC_MAC_INTERRUPT_ENABLE_TSIE_WIDTH     EMAC_MAC_INTERRUPT_ENABLE_TSIE_WIDTH
628 #define GMAC_MAC_INTERRUPT_ENABLE_TSIE(x)        EMAC_MAC_INTERRUPT_ENABLE_TSIE(x)
629 #define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK   EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK
630 #define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT  EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT
631 #define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_WIDTH  EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE_WIDTH
632 #define GMAC_MAC_INTERRUPT_ENABLE_TXSTSIE(x)     EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE(x)
633 #define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK   EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK
634 #define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT  EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT
635 #define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_WIDTH  EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE_WIDTH
636 #define GMAC_MAC_INTERRUPT_ENABLE_RXSTSIE(x)     EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE(x)
637 #define GMAC_MAC_INTERRUPT_ENABLE_FPEIE_MASK     EMAC_MAC_INTERRUPT_ENABLE_FPEIE_MASK
638 #define GMAC_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT    EMAC_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT
639 #define GMAC_MAC_INTERRUPT_ENABLE_FPEIE_WIDTH    EMAC_MAC_INTERRUPT_ENABLE_FPEIE_WIDTH
640 #define GMAC_MAC_INTERRUPT_ENABLE_FPEIE(x)       EMAC_MAC_INTERRUPT_ENABLE_FPEIE(x)
641 #define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_MASK    EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_MASK
642 #define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT   EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT
643 #define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE_WIDTH   EMAC_MAC_INTERRUPT_ENABLE_MDIOIE_WIDTH
644 #define GMAC_MAC_INTERRUPT_ENABLE_MDIOIE(x)      EMAC_MAC_INTERRUPT_ENABLE_MDIOIE(x)
645 /*! @} */
646 
647 /*! @name MAC_RX_TX_STATUS -  */
648 /*! @{ */
649 #define GMAC_MAC_RX_TX_STATUS_TJT_MASK           EMAC_MAC_RX_TX_STATUS_TJT_MASK
650 #define GMAC_MAC_RX_TX_STATUS_TJT_SHIFT          EMAC_MAC_RX_TX_STATUS_TJT_SHIFT
651 #define GMAC_MAC_RX_TX_STATUS_TJT_WIDTH          EMAC_MAC_RX_TX_STATUS_TJT_WIDTH
652 #define GMAC_MAC_RX_TX_STATUS_TJT(x)             EMAC_MAC_RX_TX_STATUS_TJT(x)
653 #define GMAC_MAC_RX_TX_STATUS_NCARR_MASK         EMAC_MAC_RX_TX_STATUS_NCARR_MASK
654 #define GMAC_MAC_RX_TX_STATUS_NCARR_SHIFT        EMAC_MAC_RX_TX_STATUS_NCARR_SHIFT
655 #define GMAC_MAC_RX_TX_STATUS_NCARR_WIDTH        EMAC_MAC_RX_TX_STATUS_NCARR_WIDTH
656 #define GMAC_MAC_RX_TX_STATUS_NCARR(x)           EMAC_MAC_RX_TX_STATUS_NCARR(x)
657 #define GMAC_MAC_RX_TX_STATUS_LCARR_MASK         EMAC_MAC_RX_TX_STATUS_LCARR_MASK
658 #define GMAC_MAC_RX_TX_STATUS_LCARR_SHIFT        EMAC_MAC_RX_TX_STATUS_LCARR_SHIFT
659 #define GMAC_MAC_RX_TX_STATUS_LCARR_WIDTH        EMAC_MAC_RX_TX_STATUS_LCARR_WIDTH
660 #define GMAC_MAC_RX_TX_STATUS_LCARR(x)           EMAC_MAC_RX_TX_STATUS_LCARR(x)
661 #define GMAC_MAC_RX_TX_STATUS_EXDEF_MASK         EMAC_MAC_RX_TX_STATUS_EXDEF_MASK
662 #define GMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT        EMAC_MAC_RX_TX_STATUS_EXDEF_SHIFT
663 #define GMAC_MAC_RX_TX_STATUS_EXDEF_WIDTH        EMAC_MAC_RX_TX_STATUS_EXDEF_WIDTH
664 #define GMAC_MAC_RX_TX_STATUS_EXDEF(x)           EMAC_MAC_RX_TX_STATUS_EXDEF(x)
665 #define GMAC_MAC_RX_TX_STATUS_LCOL_MASK          EMAC_MAC_RX_TX_STATUS_LCOL_MASK
666 #define GMAC_MAC_RX_TX_STATUS_LCOL_SHIFT         EMAC_MAC_RX_TX_STATUS_LCOL_SHIFT
667 #define GMAC_MAC_RX_TX_STATUS_LCOL_WIDTH         EMAC_MAC_RX_TX_STATUS_LCOL_WIDTH
668 #define GMAC_MAC_RX_TX_STATUS_LCOL(x)            EMAC_MAC_RX_TX_STATUS_LCOL(x)
669 #define GMAC_MAC_RX_TX_STATUS_EXCOL_MASK         EMAC_MAC_RX_TX_STATUS_EXCOL_MASK
670 #define GMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT        EMAC_MAC_RX_TX_STATUS_EXCOL_SHIFT
671 #define GMAC_MAC_RX_TX_STATUS_EXCOL_WIDTH        EMAC_MAC_RX_TX_STATUS_EXCOL_WIDTH
672 #define GMAC_MAC_RX_TX_STATUS_EXCOL(x)           EMAC_MAC_RX_TX_STATUS_EXCOL(x)
673 #define GMAC_MAC_RX_TX_STATUS_RWT_MASK           EMAC_MAC_RX_TX_STATUS_RWT_MASK
674 #define GMAC_MAC_RX_TX_STATUS_RWT_SHIFT          EMAC_MAC_RX_TX_STATUS_RWT_SHIFT
675 #define GMAC_MAC_RX_TX_STATUS_RWT_WIDTH          EMAC_MAC_RX_TX_STATUS_RWT_WIDTH
676 #define GMAC_MAC_RX_TX_STATUS_RWT(x)             EMAC_MAC_RX_TX_STATUS_RWT(x)
677 /*! @} */
678 
679 /*! @name MAC_VERSION -  */
680 /*! @{ */
681 #define GMAC_MAC_VERSION_IPVER_MASK              EMAC_MAC_VERSION_IPVER_MASK
682 #define GMAC_MAC_VERSION_IPVER_SHIFT             EMAC_MAC_VERSION_IPVER_SHIFT
683 #define GMAC_MAC_VERSION_IPVER_WIDTH             EMAC_MAC_VERSION_IPVER_WIDTH
684 #define GMAC_MAC_VERSION_IPVER(x)                EMAC_MAC_VERSION_IPVER(x)
685 #define GMAC_MAC_VERSION_CFGVER_MASK             EMAC_MAC_VERSION_CFGVER_MASK
686 #define GMAC_MAC_VERSION_CFGVER_SHIFT            EMAC_MAC_VERSION_CFGVER_SHIFT
687 #define GMAC_MAC_VERSION_CFGVER_WIDTH            EMAC_MAC_VERSION_CFGVER_WIDTH
688 #define GMAC_MAC_VERSION_CFGVER(x)               EMAC_MAC_VERSION_CFGVER(x)
689 /*! @} */
690 
691 /*! @name MAC_DEBUG -  */
692 /*! @{ */
693 #define GMAC_MAC_DEBUG_RPESTS_MASK               EMAC_MAC_DEBUG_RPESTS_MASK
694 #define GMAC_MAC_DEBUG_RPESTS_SHIFT              EMAC_MAC_DEBUG_RPESTS_SHIFT
695 #define GMAC_MAC_DEBUG_RPESTS_WIDTH              EMAC_MAC_DEBUG_RPESTS_WIDTH
696 #define GMAC_MAC_DEBUG_RPESTS(x)                 EMAC_MAC_DEBUG_RPESTS(x)
697 #define GMAC_MAC_DEBUG_RFCFCSTS_MASK             EMAC_MAC_DEBUG_RFCFCSTS_MASK
698 #define GMAC_MAC_DEBUG_RFCFCSTS_SHIFT            EMAC_MAC_DEBUG_RFCFCSTS_SHIFT
699 #define GMAC_MAC_DEBUG_RFCFCSTS_WIDTH            EMAC_MAC_DEBUG_RFCFCSTS_WIDTH
700 #define GMAC_MAC_DEBUG_RFCFCSTS(x)               EMAC_MAC_DEBUG_RFCFCSTS(x)
701 #define GMAC_MAC_DEBUG_TPESTS_MASK               EMAC_MAC_DEBUG_TPESTS_MASK
702 #define GMAC_MAC_DEBUG_TPESTS_SHIFT              EMAC_MAC_DEBUG_TPESTS_SHIFT
703 #define GMAC_MAC_DEBUG_TPESTS_WIDTH              EMAC_MAC_DEBUG_TPESTS_WIDTH
704 #define GMAC_MAC_DEBUG_TPESTS(x)                 EMAC_MAC_DEBUG_TPESTS(x)
705 #define GMAC_MAC_DEBUG_TFCSTS_MASK               EMAC_MAC_DEBUG_TFCSTS_MASK
706 #define GMAC_MAC_DEBUG_TFCSTS_SHIFT              EMAC_MAC_DEBUG_TFCSTS_SHIFT
707 #define GMAC_MAC_DEBUG_TFCSTS_WIDTH              EMAC_MAC_DEBUG_TFCSTS_WIDTH
708 #define GMAC_MAC_DEBUG_TFCSTS(x)                 EMAC_MAC_DEBUG_TFCSTS(x)
709 /*! @} */
710 
711 /*! @name MAC_HW_FEATURE0 -  */
712 /*! @{ */
713 #define GMAC_MAC_HW_FEATURE0_MIISEL_MASK         EMAC_MAC_HW_FEATURE0_MIISEL_MASK
714 #define GMAC_MAC_HW_FEATURE0_MIISEL_SHIFT        EMAC_MAC_HW_FEATURE0_MIISEL_SHIFT
715 #define GMAC_MAC_HW_FEATURE0_MIISEL_WIDTH        EMAC_MAC_HW_FEATURE0_MIISEL_WIDTH
716 #define GMAC_MAC_HW_FEATURE0_MIISEL(x)           EMAC_MAC_HW_FEATURE0_MIISEL(x)
717 #define GMAC_MAC_HW_FEATURE0_GMIISEL_MASK        EMAC_MAC_HW_FEATURE0_GMIISEL_MASK
718 #define GMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT       EMAC_MAC_HW_FEATURE0_GMIISEL_SHIFT
719 #define GMAC_MAC_HW_FEATURE0_GMIISEL_WIDTH       EMAC_MAC_HW_FEATURE0_GMIISEL_WIDTH
720 #define GMAC_MAC_HW_FEATURE0_GMIISEL(x)          EMAC_MAC_HW_FEATURE0_GMIISEL(x)
721 #define GMAC_MAC_HW_FEATURE0_HDSEL_MASK          EMAC_MAC_HW_FEATURE0_HDSEL_MASK
722 #define GMAC_MAC_HW_FEATURE0_HDSEL_SHIFT         EMAC_MAC_HW_FEATURE0_HDSEL_SHIFT
723 #define GMAC_MAC_HW_FEATURE0_HDSEL_WIDTH         EMAC_MAC_HW_FEATURE0_HDSEL_WIDTH
724 #define GMAC_MAC_HW_FEATURE0_HDSEL(x)            EMAC_MAC_HW_FEATURE0_HDSEL(x)
725 #define GMAC_MAC_HW_FEATURE0_PCSSEL_MASK         EMAC_MAC_HW_FEATURE0_PCSSEL_MASK
726 #define GMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT        EMAC_MAC_HW_FEATURE0_PCSSEL_SHIFT
727 #define GMAC_MAC_HW_FEATURE0_PCSSEL_WIDTH        EMAC_MAC_HW_FEATURE0_PCSSEL_WIDTH
728 #define GMAC_MAC_HW_FEATURE0_PCSSEL(x)           EMAC_MAC_HW_FEATURE0_PCSSEL(x)
729 #define GMAC_MAC_HW_FEATURE0_VLHASH_MASK         EMAC_MAC_HW_FEATURE0_VLHASH_MASK
730 #define GMAC_MAC_HW_FEATURE0_VLHASH_SHIFT        EMAC_MAC_HW_FEATURE0_VLHASH_SHIFT
731 #define GMAC_MAC_HW_FEATURE0_VLHASH_WIDTH        EMAC_MAC_HW_FEATURE0_VLHASH_WIDTH
732 #define GMAC_MAC_HW_FEATURE0_VLHASH(x)           EMAC_MAC_HW_FEATURE0_VLHASH(x)
733 #define GMAC_MAC_HW_FEATURE0_SMASEL_MASK         EMAC_MAC_HW_FEATURE0_SMASEL_MASK
734 #define GMAC_MAC_HW_FEATURE0_SMASEL_SHIFT        EMAC_MAC_HW_FEATURE0_SMASEL_SHIFT
735 #define GMAC_MAC_HW_FEATURE0_SMASEL_WIDTH        EMAC_MAC_HW_FEATURE0_SMASEL_WIDTH
736 #define GMAC_MAC_HW_FEATURE0_SMASEL(x)           EMAC_MAC_HW_FEATURE0_SMASEL(x)
737 #define GMAC_MAC_HW_FEATURE0_RWKSEL_MASK         EMAC_MAC_HW_FEATURE0_RWKSEL_MASK
738 #define GMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT        EMAC_MAC_HW_FEATURE0_RWKSEL_SHIFT
739 #define GMAC_MAC_HW_FEATURE0_RWKSEL_WIDTH        EMAC_MAC_HW_FEATURE0_RWKSEL_WIDTH
740 #define GMAC_MAC_HW_FEATURE0_RWKSEL(x)           EMAC_MAC_HW_FEATURE0_RWKSEL(x)
741 #define GMAC_MAC_HW_FEATURE0_MGKSEL_MASK         EMAC_MAC_HW_FEATURE0_MGKSEL_MASK
742 #define GMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT        EMAC_MAC_HW_FEATURE0_MGKSEL_SHIFT
743 #define GMAC_MAC_HW_FEATURE0_MGKSEL_WIDTH        EMAC_MAC_HW_FEATURE0_MGKSEL_WIDTH
744 #define GMAC_MAC_HW_FEATURE0_MGKSEL(x)           EMAC_MAC_HW_FEATURE0_MGKSEL(x)
745 #define GMAC_MAC_HW_FEATURE0_MMCSEL_MASK         EMAC_MAC_HW_FEATURE0_MMCSEL_MASK
746 #define GMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT        EMAC_MAC_HW_FEATURE0_MMCSEL_SHIFT
747 #define GMAC_MAC_HW_FEATURE0_MMCSEL_WIDTH        EMAC_MAC_HW_FEATURE0_MMCSEL_WIDTH
748 #define GMAC_MAC_HW_FEATURE0_MMCSEL(x)           EMAC_MAC_HW_FEATURE0_MMCSEL(x)
749 #define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK      EMAC_MAC_HW_FEATURE0_ARPOFFSEL_MASK
750 #define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT     EMAC_MAC_HW_FEATURE0_ARPOFFSEL_SHIFT
751 #define GMAC_MAC_HW_FEATURE0_ARPOFFSEL_WIDTH     EMAC_MAC_HW_FEATURE0_ARPOFFSEL_WIDTH
752 #define GMAC_MAC_HW_FEATURE0_ARPOFFSEL(x)        EMAC_MAC_HW_FEATURE0_ARPOFFSEL(x)
753 #define GMAC_MAC_HW_FEATURE0_TSSEL_MASK          EMAC_MAC_HW_FEATURE0_TSSEL_MASK
754 #define GMAC_MAC_HW_FEATURE0_TSSEL_SHIFT         EMAC_MAC_HW_FEATURE0_TSSEL_SHIFT
755 #define GMAC_MAC_HW_FEATURE0_TSSEL_WIDTH         EMAC_MAC_HW_FEATURE0_TSSEL_WIDTH
756 #define GMAC_MAC_HW_FEATURE0_TSSEL(x)            EMAC_MAC_HW_FEATURE0_TSSEL(x)
757 #define GMAC_MAC_HW_FEATURE0_EEESEL_MASK         EMAC_MAC_HW_FEATURE0_EEESEL_MASK
758 #define GMAC_MAC_HW_FEATURE0_EEESEL_SHIFT        EMAC_MAC_HW_FEATURE0_EEESEL_SHIFT
759 #define GMAC_MAC_HW_FEATURE0_EEESEL_WIDTH        EMAC_MAC_HW_FEATURE0_EEESEL_WIDTH
760 #define GMAC_MAC_HW_FEATURE0_EEESEL(x)           EMAC_MAC_HW_FEATURE0_EEESEL(x)
761 #define GMAC_MAC_HW_FEATURE0_TXCOESEL_MASK       EMAC_MAC_HW_FEATURE0_TXCOESEL_MASK
762 #define GMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT      EMAC_MAC_HW_FEATURE0_TXCOESEL_SHIFT
763 #define GMAC_MAC_HW_FEATURE0_TXCOESEL_WIDTH      EMAC_MAC_HW_FEATURE0_TXCOESEL_WIDTH
764 #define GMAC_MAC_HW_FEATURE0_TXCOESEL(x)         EMAC_MAC_HW_FEATURE0_TXCOESEL(x)
765 #define GMAC_MAC_HW_FEATURE0_RXCOESEL_MASK       EMAC_MAC_HW_FEATURE0_RXCOESEL_MASK
766 #define GMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT      EMAC_MAC_HW_FEATURE0_RXCOESEL_SHIFT
767 #define GMAC_MAC_HW_FEATURE0_RXCOESEL_WIDTH      EMAC_MAC_HW_FEATURE0_RXCOESEL_WIDTH
768 #define GMAC_MAC_HW_FEATURE0_RXCOESEL(x)         EMAC_MAC_HW_FEATURE0_RXCOESEL(x)
769 #define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK   EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK
770 #define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT  EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT
771 #define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL_WIDTH  EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_WIDTH
772 #define GMAC_MAC_HW_FEATURE0_ADDMACADRSEL(x)     EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(x)
773 #define GMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK    EMAC_MAC_HW_FEATURE0_MACADR32SEL_MASK
774 #define GMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT   EMAC_MAC_HW_FEATURE0_MACADR32SEL_SHIFT
775 #define GMAC_MAC_HW_FEATURE0_MACADR32SEL_WIDTH   EMAC_MAC_HW_FEATURE0_MACADR32SEL_WIDTH
776 #define GMAC_MAC_HW_FEATURE0_MACADR32SEL(x)      EMAC_MAC_HW_FEATURE0_MACADR32SEL(x)
777 #define GMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK    EMAC_MAC_HW_FEATURE0_MACADR64SEL_MASK
778 #define GMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT   EMAC_MAC_HW_FEATURE0_MACADR64SEL_SHIFT
779 #define GMAC_MAC_HW_FEATURE0_MACADR64SEL_WIDTH   EMAC_MAC_HW_FEATURE0_MACADR64SEL_WIDTH
780 #define GMAC_MAC_HW_FEATURE0_MACADR64SEL(x)      EMAC_MAC_HW_FEATURE0_MACADR64SEL(x)
781 #define GMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK       EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK
782 #define GMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT      EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT
783 #define GMAC_MAC_HW_FEATURE0_TSSTSSEL_WIDTH      EMAC_MAC_HW_FEATURE0_TSSTSSEL_WIDTH
784 #define GMAC_MAC_HW_FEATURE0_TSSTSSEL(x)         EMAC_MAC_HW_FEATURE0_TSSTSSEL(x)
785 #define GMAC_MAC_HW_FEATURE0_SAVLANINS_MASK      EMAC_MAC_HW_FEATURE0_SAVLANINS_MASK
786 #define GMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT     EMAC_MAC_HW_FEATURE0_SAVLANINS_SHIFT
787 #define GMAC_MAC_HW_FEATURE0_SAVLANINS_WIDTH     EMAC_MAC_HW_FEATURE0_SAVLANINS_WIDTH
788 #define GMAC_MAC_HW_FEATURE0_SAVLANINS(x)        EMAC_MAC_HW_FEATURE0_SAVLANINS(x)
789 #define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK      EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK
790 #define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT     EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT
791 #define GMAC_MAC_HW_FEATURE0_ACTPHYSEL_WIDTH     EMAC_MAC_HW_FEATURE0_ACTPHYSEL_WIDTH
792 #define GMAC_MAC_HW_FEATURE0_ACTPHYSEL(x)        EMAC_MAC_HW_FEATURE0_ACTPHYSEL(x)
793 /*! @} */
794 
795 /*! @name MAC_HW_FEATURE1 -  */
796 /*! @{ */
797 #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK     EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK
798 #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT    EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT
799 #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE_WIDTH    EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_WIDTH
800 #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x)       EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x)
801 #define GMAC_MAC_HW_FEATURE1_SPRAM_MASK          EMAC_MAC_HW_FEATURE1_SPRAM_MASK
802 #define GMAC_MAC_HW_FEATURE1_SPRAM_SHIFT         EMAC_MAC_HW_FEATURE1_SPRAM_SHIFT
803 #define GMAC_MAC_HW_FEATURE1_SPRAM_WIDTH         EMAC_MAC_HW_FEATURE1_SPRAM_WIDTH
804 #define GMAC_MAC_HW_FEATURE1_SPRAM(x)            EMAC_MAC_HW_FEATURE1_SPRAM(x)
805 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK     EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK
806 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT    EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT
807 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE_WIDTH    EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_WIDTH
808 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x)       EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x)
809 #define GMAC_MAC_HW_FEATURE1_OSTEN_MASK          EMAC_MAC_HW_FEATURE1_OSTEN_MASK
810 #define GMAC_MAC_HW_FEATURE1_OSTEN_SHIFT         EMAC_MAC_HW_FEATURE1_OSTEN_SHIFT
811 #define GMAC_MAC_HW_FEATURE1_OSTEN_WIDTH         EMAC_MAC_HW_FEATURE1_OSTEN_WIDTH
812 #define GMAC_MAC_HW_FEATURE1_OSTEN(x)            EMAC_MAC_HW_FEATURE1_OSTEN(x)
813 #define GMAC_MAC_HW_FEATURE1_PTOEN_MASK          EMAC_MAC_HW_FEATURE1_PTOEN_MASK
814 #define GMAC_MAC_HW_FEATURE1_PTOEN_SHIFT         EMAC_MAC_HW_FEATURE1_PTOEN_SHIFT
815 #define GMAC_MAC_HW_FEATURE1_PTOEN_WIDTH         EMAC_MAC_HW_FEATURE1_PTOEN_WIDTH
816 #define GMAC_MAC_HW_FEATURE1_PTOEN(x)            EMAC_MAC_HW_FEATURE1_PTOEN(x)
817 #define GMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK      EMAC_MAC_HW_FEATURE1_ADVTHWORD_MASK
818 #define GMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT     EMAC_MAC_HW_FEATURE1_ADVTHWORD_SHIFT
819 #define GMAC_MAC_HW_FEATURE1_ADVTHWORD_WIDTH     EMAC_MAC_HW_FEATURE1_ADVTHWORD_WIDTH
820 #define GMAC_MAC_HW_FEATURE1_ADVTHWORD(x)        EMAC_MAC_HW_FEATURE1_ADVTHWORD(x)
821 #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK         EMAC_MAC_HW_FEATURE1_ADDR64_MASK
822 #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT        EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT
823 #define GMAC_MAC_HW_FEATURE1_ADDR64_WIDTH        EMAC_MAC_HW_FEATURE1_ADDR64_WIDTH
824 #define GMAC_MAC_HW_FEATURE1_ADDR64(x)           EMAC_MAC_HW_FEATURE1_ADDR64(x)
825 #define GMAC_MAC_HW_FEATURE1_DCBEN_MASK          EMAC_MAC_HW_FEATURE1_DCBEN_MASK
826 #define GMAC_MAC_HW_FEATURE1_DCBEN_SHIFT         EMAC_MAC_HW_FEATURE1_DCBEN_SHIFT
827 #define GMAC_MAC_HW_FEATURE1_DCBEN_WIDTH         EMAC_MAC_HW_FEATURE1_DCBEN_WIDTH
828 #define GMAC_MAC_HW_FEATURE1_DCBEN(x)            EMAC_MAC_HW_FEATURE1_DCBEN(x)
829 #define GMAC_MAC_HW_FEATURE1_SPHEN_MASK          EMAC_MAC_HW_FEATURE1_SPHEN_MASK
830 #define GMAC_MAC_HW_FEATURE1_SPHEN_SHIFT         EMAC_MAC_HW_FEATURE1_SPHEN_SHIFT
831 #define GMAC_MAC_HW_FEATURE1_SPHEN_WIDTH         EMAC_MAC_HW_FEATURE1_SPHEN_WIDTH
832 #define GMAC_MAC_HW_FEATURE1_SPHEN(x)            EMAC_MAC_HW_FEATURE1_SPHEN(x)
833 #define GMAC_MAC_HW_FEATURE1_TSOEN_MASK          EMAC_MAC_HW_FEATURE1_TSOEN_MASK
834 #define GMAC_MAC_HW_FEATURE1_TSOEN_SHIFT         EMAC_MAC_HW_FEATURE1_TSOEN_SHIFT
835 #define GMAC_MAC_HW_FEATURE1_TSOEN_WIDTH         EMAC_MAC_HW_FEATURE1_TSOEN_WIDTH
836 #define GMAC_MAC_HW_FEATURE1_TSOEN(x)            EMAC_MAC_HW_FEATURE1_TSOEN(x)
837 #define GMAC_MAC_HW_FEATURE1_DBGMEMA_MASK        EMAC_MAC_HW_FEATURE1_DBGMEMA_MASK
838 #define GMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT       EMAC_MAC_HW_FEATURE1_DBGMEMA_SHIFT
839 #define GMAC_MAC_HW_FEATURE1_DBGMEMA_WIDTH       EMAC_MAC_HW_FEATURE1_DBGMEMA_WIDTH
840 #define GMAC_MAC_HW_FEATURE1_DBGMEMA(x)          EMAC_MAC_HW_FEATURE1_DBGMEMA(x)
841 #define GMAC_MAC_HW_FEATURE1_AVSEL_MASK          EMAC_MAC_HW_FEATURE1_AVSEL_MASK
842 #define GMAC_MAC_HW_FEATURE1_AVSEL_SHIFT         EMAC_MAC_HW_FEATURE1_AVSEL_SHIFT
843 #define GMAC_MAC_HW_FEATURE1_AVSEL_WIDTH         EMAC_MAC_HW_FEATURE1_AVSEL_WIDTH
844 #define GMAC_MAC_HW_FEATURE1_AVSEL(x)            EMAC_MAC_HW_FEATURE1_AVSEL(x)
845 #define GMAC_MAC_HW_FEATURE1_RAVSEL_MASK         EMAC_MAC_HW_FEATURE1_RAVSEL_MASK
846 #define GMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT        EMAC_MAC_HW_FEATURE1_RAVSEL_SHIFT
847 #define GMAC_MAC_HW_FEATURE1_RAVSEL_WIDTH        EMAC_MAC_HW_FEATURE1_RAVSEL_WIDTH
848 #define GMAC_MAC_HW_FEATURE1_RAVSEL(x)           EMAC_MAC_HW_FEATURE1_RAVSEL(x)
849 #define GMAC_MAC_HW_FEATURE1_POUOST_MASK         EMAC_MAC_HW_FEATURE1_POUOST_MASK
850 #define GMAC_MAC_HW_FEATURE1_POUOST_SHIFT        EMAC_MAC_HW_FEATURE1_POUOST_SHIFT
851 #define GMAC_MAC_HW_FEATURE1_POUOST_WIDTH        EMAC_MAC_HW_FEATURE1_POUOST_WIDTH
852 #define GMAC_MAC_HW_FEATURE1_POUOST(x)           EMAC_MAC_HW_FEATURE1_POUOST(x)
853 #define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK      EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK
854 #define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT     EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT
855 #define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_WIDTH     EMAC_MAC_HW_FEATURE1_HASHTBLSZ_WIDTH
856 #define GMAC_MAC_HW_FEATURE1_HASHTBLSZ(x)        EMAC_MAC_HW_FEATURE1_HASHTBLSZ(x)
857 #define GMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK       EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK
858 #define GMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT      EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT
859 #define GMAC_MAC_HW_FEATURE1_L3L4FNUM_WIDTH      EMAC_MAC_HW_FEATURE1_L3L4FNUM_WIDTH
860 #define GMAC_MAC_HW_FEATURE1_L3L4FNUM(x)         EMAC_MAC_HW_FEATURE1_L3L4FNUM(x)
861 /*! @} */
862 
863 /*! @name MAC_HW_FEATURE2 -  */
864 /*! @{ */
865 #define GMAC_MAC_HW_FEATURE2_RXQCNT_MASK         EMAC_MAC_HW_FEATURE2_RXQCNT_MASK
866 #define GMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT        EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT
867 #define GMAC_MAC_HW_FEATURE2_RXQCNT_WIDTH        EMAC_MAC_HW_FEATURE2_RXQCNT_WIDTH
868 #define GMAC_MAC_HW_FEATURE2_RXQCNT(x)           EMAC_MAC_HW_FEATURE2_RXQCNT(x)
869 #define GMAC_MAC_HW_FEATURE2_TXQCNT_MASK         EMAC_MAC_HW_FEATURE2_TXQCNT_MASK
870 #define GMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT        EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT
871 #define GMAC_MAC_HW_FEATURE2_TXQCNT_WIDTH        EMAC_MAC_HW_FEATURE2_TXQCNT_WIDTH
872 #define GMAC_MAC_HW_FEATURE2_TXQCNT(x)           EMAC_MAC_HW_FEATURE2_TXQCNT(x)
873 #define GMAC_MAC_HW_FEATURE2_RXCHCNT_MASK        EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK
874 #define GMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT       EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT
875 #define GMAC_MAC_HW_FEATURE2_RXCHCNT_WIDTH       EMAC_MAC_HW_FEATURE2_RXCHCNT_WIDTH
876 #define GMAC_MAC_HW_FEATURE2_RXCHCNT(x)          EMAC_MAC_HW_FEATURE2_RXCHCNT(x)
877 #define GMAC_MAC_HW_FEATURE2_TXCHCNT_MASK        EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK
878 #define GMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT       EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT
879 #define GMAC_MAC_HW_FEATURE2_TXCHCNT_WIDTH       EMAC_MAC_HW_FEATURE2_TXCHCNT_WIDTH
880 #define GMAC_MAC_HW_FEATURE2_TXCHCNT(x)          EMAC_MAC_HW_FEATURE2_TXCHCNT(x)
881 #define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK      EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK
882 #define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT     EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT
883 #define GMAC_MAC_HW_FEATURE2_PPSOUTNUM_WIDTH     EMAC_MAC_HW_FEATURE2_PPSOUTNUM_WIDTH
884 #define GMAC_MAC_HW_FEATURE2_PPSOUTNUM(x)        EMAC_MAC_HW_FEATURE2_PPSOUTNUM(x)
885 #define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK     EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK
886 #define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT    EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT
887 #define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM_WIDTH    EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_WIDTH
888 #define GMAC_MAC_HW_FEATURE2_AUXSNAPNUM(x)       EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(x)
889 /*! @} */
890 
891 /*! @name MAC_HW_FEATURE3 -  */
892 /*! @{ */
893 #define GMAC_MAC_HW_FEATURE3_NRVF_MASK           EMAC_MAC_HW_FEATURE3_NRVF_MASK
894 #define GMAC_MAC_HW_FEATURE3_NRVF_SHIFT          EMAC_MAC_HW_FEATURE3_NRVF_SHIFT
895 #define GMAC_MAC_HW_FEATURE3_NRVF_WIDTH          EMAC_MAC_HW_FEATURE3_NRVF_WIDTH
896 #define GMAC_MAC_HW_FEATURE3_NRVF(x)             EMAC_MAC_HW_FEATURE3_NRVF(x)
897 #define GMAC_MAC_HW_FEATURE3_CBTISEL_MASK        EMAC_MAC_HW_FEATURE3_CBTISEL_MASK
898 #define GMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT       EMAC_MAC_HW_FEATURE3_CBTISEL_SHIFT
899 #define GMAC_MAC_HW_FEATURE3_CBTISEL_WIDTH       EMAC_MAC_HW_FEATURE3_CBTISEL_WIDTH
900 #define GMAC_MAC_HW_FEATURE3_CBTISEL(x)          EMAC_MAC_HW_FEATURE3_CBTISEL(x)
901 #define GMAC_MAC_HW_FEATURE3_DVLAN_MASK          EMAC_MAC_HW_FEATURE3_DVLAN_MASK
902 #define GMAC_MAC_HW_FEATURE3_DVLAN_SHIFT         EMAC_MAC_HW_FEATURE3_DVLAN_SHIFT
903 #define GMAC_MAC_HW_FEATURE3_DVLAN_WIDTH         EMAC_MAC_HW_FEATURE3_DVLAN_WIDTH
904 #define GMAC_MAC_HW_FEATURE3_DVLAN(x)            EMAC_MAC_HW_FEATURE3_DVLAN(x)
905 #define GMAC_MAC_HW_FEATURE3_PDUPSEL_MASK        EMAC_MAC_HW_FEATURE3_PDUPSEL_MASK
906 #define GMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT       EMAC_MAC_HW_FEATURE3_PDUPSEL_SHIFT
907 #define GMAC_MAC_HW_FEATURE3_PDUPSEL_WIDTH       EMAC_MAC_HW_FEATURE3_PDUPSEL_WIDTH
908 #define GMAC_MAC_HW_FEATURE3_PDUPSEL(x)          EMAC_MAC_HW_FEATURE3_PDUPSEL(x)
909 #define GMAC_MAC_HW_FEATURE3_FRPSEL_MASK         EMAC_MAC_HW_FEATURE3_FRPSEL_MASK
910 #define GMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT        EMAC_MAC_HW_FEATURE3_FRPSEL_SHIFT
911 #define GMAC_MAC_HW_FEATURE3_FRPSEL_WIDTH        EMAC_MAC_HW_FEATURE3_FRPSEL_WIDTH
912 #define GMAC_MAC_HW_FEATURE3_FRPSEL(x)           EMAC_MAC_HW_FEATURE3_FRPSEL(x)
913 #define GMAC_MAC_HW_FEATURE3_FRPBS_MASK          EMAC_MAC_HW_FEATURE3_FRPBS_MASK
914 #define GMAC_MAC_HW_FEATURE3_FRPBS_SHIFT         EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT
915 #define GMAC_MAC_HW_FEATURE3_FRPBS_WIDTH         EMAC_MAC_HW_FEATURE3_FRPBS_WIDTH
916 #define GMAC_MAC_HW_FEATURE3_FRPBS(x)            EMAC_MAC_HW_FEATURE3_FRPBS(x)
917 #define GMAC_MAC_HW_FEATURE3_FRPES_MASK          EMAC_MAC_HW_FEATURE3_FRPES_MASK
918 #define GMAC_MAC_HW_FEATURE3_FRPES_SHIFT         EMAC_MAC_HW_FEATURE3_FRPES_SHIFT
919 #define GMAC_MAC_HW_FEATURE3_FRPES_WIDTH         EMAC_MAC_HW_FEATURE3_FRPES_WIDTH
920 #define GMAC_MAC_HW_FEATURE3_FRPES(x)            EMAC_MAC_HW_FEATURE3_FRPES(x)
921 #define GMAC_MAC_HW_FEATURE3_ESTSEL_MASK         EMAC_MAC_HW_FEATURE3_ESTSEL_MASK
922 #define GMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT        EMAC_MAC_HW_FEATURE3_ESTSEL_SHIFT
923 #define GMAC_MAC_HW_FEATURE3_ESTSEL_WIDTH        EMAC_MAC_HW_FEATURE3_ESTSEL_WIDTH
924 #define GMAC_MAC_HW_FEATURE3_ESTSEL(x)           EMAC_MAC_HW_FEATURE3_ESTSEL(x)
925 #define GMAC_MAC_HW_FEATURE3_ESTDEP_MASK         EMAC_MAC_HW_FEATURE3_ESTDEP_MASK
926 #define GMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT        EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT
927 #define GMAC_MAC_HW_FEATURE3_ESTDEP_WIDTH        EMAC_MAC_HW_FEATURE3_ESTDEP_WIDTH
928 #define GMAC_MAC_HW_FEATURE3_ESTDEP(x)           EMAC_MAC_HW_FEATURE3_ESTDEP(x)
929 #define GMAC_MAC_HW_FEATURE3_ESTWID_MASK         EMAC_MAC_HW_FEATURE3_ESTWID_MASK
930 #define GMAC_MAC_HW_FEATURE3_ESTWID_SHIFT        EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT
931 #define GMAC_MAC_HW_FEATURE3_ESTWID_WIDTH        EMAC_MAC_HW_FEATURE3_ESTWID_WIDTH
932 #define GMAC_MAC_HW_FEATURE3_ESTWID(x)           EMAC_MAC_HW_FEATURE3_ESTWID(x)
933 #define GMAC_MAC_HW_FEATURE3_FPESEL_MASK         EMAC_MAC_HW_FEATURE3_FPESEL_MASK
934 #define GMAC_MAC_HW_FEATURE3_FPESEL_SHIFT        EMAC_MAC_HW_FEATURE3_FPESEL_SHIFT
935 #define GMAC_MAC_HW_FEATURE3_FPESEL_WIDTH        EMAC_MAC_HW_FEATURE3_FPESEL_WIDTH
936 #define GMAC_MAC_HW_FEATURE3_FPESEL(x)           EMAC_MAC_HW_FEATURE3_FPESEL(x)
937 #define GMAC_MAC_HW_FEATURE3_TBSSEL_MASK         EMAC_MAC_HW_FEATURE3_TBSSEL_MASK
938 #define GMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT        EMAC_MAC_HW_FEATURE3_TBSSEL_SHIFT
939 #define GMAC_MAC_HW_FEATURE3_TBSSEL_WIDTH        EMAC_MAC_HW_FEATURE3_TBSSEL_WIDTH
940 #define GMAC_MAC_HW_FEATURE3_TBSSEL(x)           EMAC_MAC_HW_FEATURE3_TBSSEL(x)
941 #define GMAC_MAC_HW_FEATURE3_ASP_MASK            EMAC_MAC_HW_FEATURE3_ASP_MASK
942 #define GMAC_MAC_HW_FEATURE3_ASP_SHIFT           EMAC_MAC_HW_FEATURE3_ASP_SHIFT
943 #define GMAC_MAC_HW_FEATURE3_ASP_WIDTH           EMAC_MAC_HW_FEATURE3_ASP_WIDTH
944 #define GMAC_MAC_HW_FEATURE3_ASP(x)              EMAC_MAC_HW_FEATURE3_ASP(x)
945 /*! @} */
946 
947 /*! @name MAC_DPP_FSM_INTERRUPT_STATUS -  */
948 /*! @{ */
949 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_MASK
950 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_SHIFT
951 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_WIDTH
952 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES(x)
953 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_MASK
954 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_SHIFT
955 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_WIDTH
956 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES(x)
957 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_MASK
958 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_SHIFT
959 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_WIDTH
960 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES(x)
961 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_MASK
962 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_SHIFT
963 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_WIDTH
964 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES(x)
965 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_MASK
966 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_SHIFT
967 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_WIDTH
968 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES(x)
969 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_MASK
970 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_SHIFT
971 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_WIDTH
972 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES(x)
973 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_MASK
974 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_SHIFT
975 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_WIDTH
976 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES(x)
977 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_MASK
978 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_SHIFT
979 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_WIDTH
980 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES(x)
981 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_MASK
982 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_SHIFT
983 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES_WIDTH
984 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES(x)
985 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_MASK EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_MASK
986 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_SHIFT EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_SHIFT
987 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_WIDTH EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_WIDTH
988 #define GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES(x) EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES(x)
989 /*! @} */
990 
991 /*! @name MAC_FSM_CONTROL -  */
992 /*! @{ */
993 #define GMAC_MAC_FSM_CONTROL_TMOUTEN_MASK        EMAC_MAC_FSM_CONTROL_TMOUTEN_MASK
994 #define GMAC_MAC_FSM_CONTROL_TMOUTEN_SHIFT       EMAC_MAC_FSM_CONTROL_TMOUTEN_SHIFT
995 #define GMAC_MAC_FSM_CONTROL_TMOUTEN_WIDTH       EMAC_MAC_FSM_CONTROL_TMOUTEN_WIDTH
996 #define GMAC_MAC_FSM_CONTROL_TMOUTEN(x)          EMAC_MAC_FSM_CONTROL_TMOUTEN(x)
997 #define GMAC_MAC_FSM_CONTROL_PRTYEN_MASK         EMAC_MAC_FSM_CONTROL_PRTYEN_MASK
998 #define GMAC_MAC_FSM_CONTROL_PRTYEN_SHIFT        EMAC_MAC_FSM_CONTROL_PRTYEN_SHIFT
999 #define GMAC_MAC_FSM_CONTROL_PRTYEN_WIDTH        EMAC_MAC_FSM_CONTROL_PRTYEN_WIDTH
1000 #define GMAC_MAC_FSM_CONTROL_PRTYEN(x)           EMAC_MAC_FSM_CONTROL_PRTYEN(x)
1001 #define GMAC_MAC_FSM_CONTROL_TTEIN_MASK          EMAC_MAC_FSM_CONTROL_TTEIN_MASK
1002 #define GMAC_MAC_FSM_CONTROL_TTEIN_SHIFT         EMAC_MAC_FSM_CONTROL_TTEIN_SHIFT
1003 #define GMAC_MAC_FSM_CONTROL_TTEIN_WIDTH         EMAC_MAC_FSM_CONTROL_TTEIN_WIDTH
1004 #define GMAC_MAC_FSM_CONTROL_TTEIN(x)            EMAC_MAC_FSM_CONTROL_TTEIN(x)
1005 #define GMAC_MAC_FSM_CONTROL_RTEIN_MASK          EMAC_MAC_FSM_CONTROL_RTEIN_MASK
1006 #define GMAC_MAC_FSM_CONTROL_RTEIN_SHIFT         EMAC_MAC_FSM_CONTROL_RTEIN_SHIFT
1007 #define GMAC_MAC_FSM_CONTROL_RTEIN_WIDTH         EMAC_MAC_FSM_CONTROL_RTEIN_WIDTH
1008 #define GMAC_MAC_FSM_CONTROL_RTEIN(x)            EMAC_MAC_FSM_CONTROL_RTEIN(x)
1009 #define GMAC_MAC_FSM_CONTROL_ATEIN_MASK          EMAC_MAC_FSM_CONTROL_ATEIN_MASK
1010 #define GMAC_MAC_FSM_CONTROL_ATEIN_SHIFT         EMAC_MAC_FSM_CONTROL_ATEIN_SHIFT
1011 #define GMAC_MAC_FSM_CONTROL_ATEIN_WIDTH         EMAC_MAC_FSM_CONTROL_ATEIN_WIDTH
1012 #define GMAC_MAC_FSM_CONTROL_ATEIN(x)            EMAC_MAC_FSM_CONTROL_ATEIN(x)
1013 #define GMAC_MAC_FSM_CONTROL_PTEIN_MASK          EMAC_MAC_FSM_CONTROL_PTEIN_MASK
1014 #define GMAC_MAC_FSM_CONTROL_PTEIN_SHIFT         EMAC_MAC_FSM_CONTROL_PTEIN_SHIFT
1015 #define GMAC_MAC_FSM_CONTROL_PTEIN_WIDTH         EMAC_MAC_FSM_CONTROL_PTEIN_WIDTH
1016 #define GMAC_MAC_FSM_CONTROL_PTEIN(x)            EMAC_MAC_FSM_CONTROL_PTEIN(x)
1017 #define GMAC_MAC_FSM_CONTROL_TPEIN_MASK          EMAC_MAC_FSM_CONTROL_TPEIN_MASK
1018 #define GMAC_MAC_FSM_CONTROL_TPEIN_SHIFT         EMAC_MAC_FSM_CONTROL_TPEIN_SHIFT
1019 #define GMAC_MAC_FSM_CONTROL_TPEIN_WIDTH         EMAC_MAC_FSM_CONTROL_TPEIN_WIDTH
1020 #define GMAC_MAC_FSM_CONTROL_TPEIN(x)            EMAC_MAC_FSM_CONTROL_TPEIN(x)
1021 #define GMAC_MAC_FSM_CONTROL_RPEIN_MASK          EMAC_MAC_FSM_CONTROL_RPEIN_MASK
1022 #define GMAC_MAC_FSM_CONTROL_RPEIN_SHIFT         EMAC_MAC_FSM_CONTROL_RPEIN_SHIFT
1023 #define GMAC_MAC_FSM_CONTROL_RPEIN_WIDTH         EMAC_MAC_FSM_CONTROL_RPEIN_WIDTH
1024 #define GMAC_MAC_FSM_CONTROL_RPEIN(x)            EMAC_MAC_FSM_CONTROL_RPEIN(x)
1025 #define GMAC_MAC_FSM_CONTROL_APEIN_MASK          EMAC_MAC_FSM_CONTROL_APEIN_MASK
1026 #define GMAC_MAC_FSM_CONTROL_APEIN_SHIFT         EMAC_MAC_FSM_CONTROL_APEIN_SHIFT
1027 #define GMAC_MAC_FSM_CONTROL_APEIN_WIDTH         EMAC_MAC_FSM_CONTROL_APEIN_WIDTH
1028 #define GMAC_MAC_FSM_CONTROL_APEIN(x)            EMAC_MAC_FSM_CONTROL_APEIN(x)
1029 #define GMAC_MAC_FSM_CONTROL_PPEIN_MASK          EMAC_MAC_FSM_CONTROL_PPEIN_MASK
1030 #define GMAC_MAC_FSM_CONTROL_PPEIN_SHIFT         EMAC_MAC_FSM_CONTROL_PPEIN_SHIFT
1031 #define GMAC_MAC_FSM_CONTROL_PPEIN_WIDTH         EMAC_MAC_FSM_CONTROL_PPEIN_WIDTH
1032 #define GMAC_MAC_FSM_CONTROL_PPEIN(x)            EMAC_MAC_FSM_CONTROL_PPEIN(x)
1033 #define GMAC_MAC_FSM_CONTROL_TLGRNML_MASK        EMAC_MAC_FSM_CONTROL_TLGRNML_MASK
1034 #define GMAC_MAC_FSM_CONTROL_TLGRNML_SHIFT       EMAC_MAC_FSM_CONTROL_TLGRNML_SHIFT
1035 #define GMAC_MAC_FSM_CONTROL_TLGRNML_WIDTH       EMAC_MAC_FSM_CONTROL_TLGRNML_WIDTH
1036 #define GMAC_MAC_FSM_CONTROL_TLGRNML(x)          EMAC_MAC_FSM_CONTROL_TLGRNML(x)
1037 #define GMAC_MAC_FSM_CONTROL_RLGRNML_MASK        EMAC_MAC_FSM_CONTROL_RLGRNML_MASK
1038 #define GMAC_MAC_FSM_CONTROL_RLGRNML_SHIFT       EMAC_MAC_FSM_CONTROL_RLGRNML_SHIFT
1039 #define GMAC_MAC_FSM_CONTROL_RLGRNML_WIDTH       EMAC_MAC_FSM_CONTROL_RLGRNML_WIDTH
1040 #define GMAC_MAC_FSM_CONTROL_RLGRNML(x)          EMAC_MAC_FSM_CONTROL_RLGRNML(x)
1041 #define GMAC_MAC_FSM_CONTROL_ALGRNML_MASK        EMAC_MAC_FSM_CONTROL_ALGRNML_MASK
1042 #define GMAC_MAC_FSM_CONTROL_ALGRNML_SHIFT       EMAC_MAC_FSM_CONTROL_ALGRNML_SHIFT
1043 #define GMAC_MAC_FSM_CONTROL_ALGRNML_WIDTH       EMAC_MAC_FSM_CONTROL_ALGRNML_WIDTH
1044 #define GMAC_MAC_FSM_CONTROL_ALGRNML(x)          EMAC_MAC_FSM_CONTROL_ALGRNML(x)
1045 #define GMAC_MAC_FSM_CONTROL_PLGRNML_MASK        EMAC_MAC_FSM_CONTROL_PLGRNML_MASK
1046 #define GMAC_MAC_FSM_CONTROL_PLGRNML_SHIFT       EMAC_MAC_FSM_CONTROL_PLGRNML_SHIFT
1047 #define GMAC_MAC_FSM_CONTROL_PLGRNML_WIDTH       EMAC_MAC_FSM_CONTROL_PLGRNML_WIDTH
1048 #define GMAC_MAC_FSM_CONTROL_PLGRNML(x)          EMAC_MAC_FSM_CONTROL_PLGRNML(x)
1049 /*! @} */
1050 
1051 /*! @name MAC_FSM_ACT_TIMER -  */
1052 /*! @{ */
1053 #define GMAC_MAC_FSM_ACT_TIMER_TMR_MASK          EMAC_MAC_FSM_ACT_TIMER_TMR_MASK
1054 #define GMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT         EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT
1055 #define GMAC_MAC_FSM_ACT_TIMER_TMR_WIDTH         EMAC_MAC_FSM_ACT_TIMER_TMR_WIDTH
1056 #define GMAC_MAC_FSM_ACT_TIMER_TMR(x)            EMAC_MAC_FSM_ACT_TIMER_TMR(x)
1057 #define GMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK       EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK
1058 #define GMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT      EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT
1059 #define GMAC_MAC_FSM_ACT_TIMER_NTMRMD_WIDTH      EMAC_MAC_FSM_ACT_TIMER_NTMRMD_WIDTH
1060 #define GMAC_MAC_FSM_ACT_TIMER_NTMRMD(x)         EMAC_MAC_FSM_ACT_TIMER_NTMRMD(x)
1061 #define GMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK       EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK
1062 #define GMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT      EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT
1063 #define GMAC_MAC_FSM_ACT_TIMER_LTMRMD_WIDTH      EMAC_MAC_FSM_ACT_TIMER_LTMRMD_WIDTH
1064 #define GMAC_MAC_FSM_ACT_TIMER_LTMRMD(x)         EMAC_MAC_FSM_ACT_TIMER_LTMRMD(x)
1065 /*! @} */
1066 
1067 /*! @name SCS_REG1 -  */
1068 /*! @{ */
1069 #define GMAC_SCS_REG1_MAC_SCS1_MASK              EMAC_SCS_REG1_MAC_SCS1_MASK
1070 #define GMAC_SCS_REG1_MAC_SCS1_SHIFT             EMAC_SCS_REG1_MAC_SCS1_SHIFT
1071 #define GMAC_SCS_REG1_MAC_SCS1_WIDTH             EMAC_SCS_REG1_MAC_SCS1_WIDTH
1072 #define GMAC_SCS_REG1_MAC_SCS1(x)                EMAC_SCS_REG1_MAC_SCS1(x)
1073 /*! @} */
1074 
1075 /*! @name MAC_MDIO_ADDRESS -  */
1076 /*! @{ */
1077 #define GMAC_MAC_MDIO_ADDRESS_GB_MASK            EMAC_MAC_MDIO_ADDRESS_GB_MASK
1078 #define GMAC_MAC_MDIO_ADDRESS_GB_SHIFT           EMAC_MAC_MDIO_ADDRESS_GB_SHIFT
1079 #define GMAC_MAC_MDIO_ADDRESS_GB_WIDTH           EMAC_MAC_MDIO_ADDRESS_GB_WIDTH
1080 #define GMAC_MAC_MDIO_ADDRESS_GB(x)              EMAC_MAC_MDIO_ADDRESS_GB(x)
1081 #define GMAC_MAC_MDIO_ADDRESS_C45E_MASK          EMAC_MAC_MDIO_ADDRESS_C45E_MASK
1082 #define GMAC_MAC_MDIO_ADDRESS_C45E_SHIFT         EMAC_MAC_MDIO_ADDRESS_C45E_SHIFT
1083 #define GMAC_MAC_MDIO_ADDRESS_C45E_WIDTH         EMAC_MAC_MDIO_ADDRESS_C45E_WIDTH
1084 #define GMAC_MAC_MDIO_ADDRESS_C45E(x)            EMAC_MAC_MDIO_ADDRESS_C45E(x)
1085 #define GMAC_MAC_MDIO_ADDRESS_GOC_0_MASK         EMAC_MAC_MDIO_ADDRESS_GOC_0_MASK
1086 #define GMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT        EMAC_MAC_MDIO_ADDRESS_GOC_0_SHIFT
1087 #define GMAC_MAC_MDIO_ADDRESS_GOC_0_WIDTH        EMAC_MAC_MDIO_ADDRESS_GOC_0_WIDTH
1088 #define GMAC_MAC_MDIO_ADDRESS_GOC_0(x)           EMAC_MAC_MDIO_ADDRESS_GOC_0(x)
1089 #define GMAC_MAC_MDIO_ADDRESS_GOC_1_MASK         EMAC_MAC_MDIO_ADDRESS_GOC_1_MASK
1090 #define GMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT        EMAC_MAC_MDIO_ADDRESS_GOC_1_SHIFT
1091 #define GMAC_MAC_MDIO_ADDRESS_GOC_1_WIDTH        EMAC_MAC_MDIO_ADDRESS_GOC_1_WIDTH
1092 #define GMAC_MAC_MDIO_ADDRESS_GOC_1(x)           EMAC_MAC_MDIO_ADDRESS_GOC_1(x)
1093 #define GMAC_MAC_MDIO_ADDRESS_SKAP_MASK          EMAC_MAC_MDIO_ADDRESS_SKAP_MASK
1094 #define GMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT         EMAC_MAC_MDIO_ADDRESS_SKAP_SHIFT
1095 #define GMAC_MAC_MDIO_ADDRESS_SKAP_WIDTH         EMAC_MAC_MDIO_ADDRESS_SKAP_WIDTH
1096 #define GMAC_MAC_MDIO_ADDRESS_SKAP(x)            EMAC_MAC_MDIO_ADDRESS_SKAP(x)
1097 #define GMAC_MAC_MDIO_ADDRESS_CR_MASK            EMAC_MAC_MDIO_ADDRESS_CR_MASK
1098 #define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT           EMAC_MAC_MDIO_ADDRESS_CR_SHIFT
1099 #define GMAC_MAC_MDIO_ADDRESS_CR_WIDTH           EMAC_MAC_MDIO_ADDRESS_CR_WIDTH
1100 #define GMAC_MAC_MDIO_ADDRESS_CR(x)              EMAC_MAC_MDIO_ADDRESS_CR(x)
1101 #define GMAC_MAC_MDIO_ADDRESS_NTC_MASK           EMAC_MAC_MDIO_ADDRESS_NTC_MASK
1102 #define GMAC_MAC_MDIO_ADDRESS_NTC_SHIFT          EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT
1103 #define GMAC_MAC_MDIO_ADDRESS_NTC_WIDTH          EMAC_MAC_MDIO_ADDRESS_NTC_WIDTH
1104 #define GMAC_MAC_MDIO_ADDRESS_NTC(x)             EMAC_MAC_MDIO_ADDRESS_NTC(x)
1105 #define GMAC_MAC_MDIO_ADDRESS_RDA_MASK           EMAC_MAC_MDIO_ADDRESS_RDA_MASK
1106 #define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT          EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT
1107 #define GMAC_MAC_MDIO_ADDRESS_RDA_WIDTH          EMAC_MAC_MDIO_ADDRESS_RDA_WIDTH
1108 #define GMAC_MAC_MDIO_ADDRESS_RDA(x)             EMAC_MAC_MDIO_ADDRESS_RDA(x)
1109 #define GMAC_MAC_MDIO_ADDRESS_PA_MASK            EMAC_MAC_MDIO_ADDRESS_PA_MASK
1110 #define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT           EMAC_MAC_MDIO_ADDRESS_PA_SHIFT
1111 #define GMAC_MAC_MDIO_ADDRESS_PA_WIDTH           EMAC_MAC_MDIO_ADDRESS_PA_WIDTH
1112 #define GMAC_MAC_MDIO_ADDRESS_PA(x)              EMAC_MAC_MDIO_ADDRESS_PA(x)
1113 #define GMAC_MAC_MDIO_ADDRESS_BTB_MASK           EMAC_MAC_MDIO_ADDRESS_BTB_MASK
1114 #define GMAC_MAC_MDIO_ADDRESS_BTB_SHIFT          EMAC_MAC_MDIO_ADDRESS_BTB_SHIFT
1115 #define GMAC_MAC_MDIO_ADDRESS_BTB_WIDTH          EMAC_MAC_MDIO_ADDRESS_BTB_WIDTH
1116 #define GMAC_MAC_MDIO_ADDRESS_BTB(x)             EMAC_MAC_MDIO_ADDRESS_BTB(x)
1117 #define GMAC_MAC_MDIO_ADDRESS_PSE_MASK           EMAC_MAC_MDIO_ADDRESS_PSE_MASK
1118 #define GMAC_MAC_MDIO_ADDRESS_PSE_SHIFT          EMAC_MAC_MDIO_ADDRESS_PSE_SHIFT
1119 #define GMAC_MAC_MDIO_ADDRESS_PSE_WIDTH          EMAC_MAC_MDIO_ADDRESS_PSE_WIDTH
1120 #define GMAC_MAC_MDIO_ADDRESS_PSE(x)             EMAC_MAC_MDIO_ADDRESS_PSE(x)
1121 /*! @} */
1122 
1123 /*! @name MAC_MDIO_DATA -  */
1124 /*! @{ */
1125 #define GMAC_MAC_MDIO_DATA_GD_MASK               EMAC_MAC_MDIO_DATA_GD_MASK
1126 #define GMAC_MAC_MDIO_DATA_GD_SHIFT              EMAC_MAC_MDIO_DATA_GD_SHIFT
1127 #define GMAC_MAC_MDIO_DATA_GD_WIDTH              EMAC_MAC_MDIO_DATA_GD_WIDTH
1128 #define GMAC_MAC_MDIO_DATA_GD(x)                 EMAC_MAC_MDIO_DATA_GD(x)
1129 #define GMAC_MAC_MDIO_DATA_RA_MASK               EMAC_MAC_MDIO_DATA_RA_MASK
1130 #define GMAC_MAC_MDIO_DATA_RA_SHIFT              EMAC_MAC_MDIO_DATA_RA_SHIFT
1131 #define GMAC_MAC_MDIO_DATA_RA_WIDTH              EMAC_MAC_MDIO_DATA_RA_WIDTH
1132 #define GMAC_MAC_MDIO_DATA_RA(x)                 EMAC_MAC_MDIO_DATA_RA(x)
1133 /*! @} */
1134 
1135 /*! @name MAC_CSR_SW_CTRL -  */
1136 /*! @{ */
1137 #define GMAC_MAC_CSR_SW_CTRL_RCWE_MASK           EMAC_MAC_CSR_SW_CTRL_RCWE_MASK
1138 #define GMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT          EMAC_MAC_CSR_SW_CTRL_RCWE_SHIFT
1139 #define GMAC_MAC_CSR_SW_CTRL_RCWE_WIDTH          EMAC_MAC_CSR_SW_CTRL_RCWE_WIDTH
1140 #define GMAC_MAC_CSR_SW_CTRL_RCWE(x)             EMAC_MAC_CSR_SW_CTRL_RCWE(x)
1141 #define GMAC_MAC_CSR_SW_CTRL_SEEN_MASK           EMAC_MAC_CSR_SW_CTRL_SEEN_MASK
1142 #define GMAC_MAC_CSR_SW_CTRL_SEEN_SHIFT          EMAC_MAC_CSR_SW_CTRL_SEEN_SHIFT
1143 #define GMAC_MAC_CSR_SW_CTRL_SEEN_WIDTH          EMAC_MAC_CSR_SW_CTRL_SEEN_WIDTH
1144 #define GMAC_MAC_CSR_SW_CTRL_SEEN(x)             EMAC_MAC_CSR_SW_CTRL_SEEN(x)
1145 /*! @} */
1146 
1147 /*! @name MAC_FPE_CTRL_STS -  */
1148 /*! @{ */
1149 #define GMAC_MAC_FPE_CTRL_STS_EFPE_MASK          EMAC_MAC_FPE_CTRL_STS_EFPE_MASK
1150 #define GMAC_MAC_FPE_CTRL_STS_EFPE_SHIFT         EMAC_MAC_FPE_CTRL_STS_EFPE_SHIFT
1151 #define GMAC_MAC_FPE_CTRL_STS_EFPE_WIDTH         EMAC_MAC_FPE_CTRL_STS_EFPE_WIDTH
1152 #define GMAC_MAC_FPE_CTRL_STS_EFPE(x)            EMAC_MAC_FPE_CTRL_STS_EFPE(x)
1153 #define GMAC_MAC_FPE_CTRL_STS_SVER_MASK          EMAC_MAC_FPE_CTRL_STS_SVER_MASK
1154 #define GMAC_MAC_FPE_CTRL_STS_SVER_SHIFT         EMAC_MAC_FPE_CTRL_STS_SVER_SHIFT
1155 #define GMAC_MAC_FPE_CTRL_STS_SVER_WIDTH         EMAC_MAC_FPE_CTRL_STS_SVER_WIDTH
1156 #define GMAC_MAC_FPE_CTRL_STS_SVER(x)            EMAC_MAC_FPE_CTRL_STS_SVER(x)
1157 #define GMAC_MAC_FPE_CTRL_STS_SRSP_MASK          EMAC_MAC_FPE_CTRL_STS_SRSP_MASK
1158 #define GMAC_MAC_FPE_CTRL_STS_SRSP_SHIFT         EMAC_MAC_FPE_CTRL_STS_SRSP_SHIFT
1159 #define GMAC_MAC_FPE_CTRL_STS_SRSP_WIDTH         EMAC_MAC_FPE_CTRL_STS_SRSP_WIDTH
1160 #define GMAC_MAC_FPE_CTRL_STS_SRSP(x)            EMAC_MAC_FPE_CTRL_STS_SRSP(x)
1161 #define GMAC_MAC_FPE_CTRL_STS_S1_SET_0_MASK      EMAC_MAC_FPE_CTRL_STS_S1_SET_0_MASK
1162 #define GMAC_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT     EMAC_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT
1163 #define GMAC_MAC_FPE_CTRL_STS_S1_SET_0_WIDTH     EMAC_MAC_FPE_CTRL_STS_S1_SET_0_WIDTH
1164 #define GMAC_MAC_FPE_CTRL_STS_S1_SET_0(x)        EMAC_MAC_FPE_CTRL_STS_S1_SET_0(x)
1165 #define GMAC_MAC_FPE_CTRL_STS_RVER_MASK          EMAC_MAC_FPE_CTRL_STS_RVER_MASK
1166 #define GMAC_MAC_FPE_CTRL_STS_RVER_SHIFT         EMAC_MAC_FPE_CTRL_STS_RVER_SHIFT
1167 #define GMAC_MAC_FPE_CTRL_STS_RVER_WIDTH         EMAC_MAC_FPE_CTRL_STS_RVER_WIDTH
1168 #define GMAC_MAC_FPE_CTRL_STS_RVER(x)            EMAC_MAC_FPE_CTRL_STS_RVER(x)
1169 #define GMAC_MAC_FPE_CTRL_STS_RRSP_MASK          EMAC_MAC_FPE_CTRL_STS_RRSP_MASK
1170 #define GMAC_MAC_FPE_CTRL_STS_RRSP_SHIFT         EMAC_MAC_FPE_CTRL_STS_RRSP_SHIFT
1171 #define GMAC_MAC_FPE_CTRL_STS_RRSP_WIDTH         EMAC_MAC_FPE_CTRL_STS_RRSP_WIDTH
1172 #define GMAC_MAC_FPE_CTRL_STS_RRSP(x)            EMAC_MAC_FPE_CTRL_STS_RRSP(x)
1173 #define GMAC_MAC_FPE_CTRL_STS_TVER_MASK          EMAC_MAC_FPE_CTRL_STS_TVER_MASK
1174 #define GMAC_MAC_FPE_CTRL_STS_TVER_SHIFT         EMAC_MAC_FPE_CTRL_STS_TVER_SHIFT
1175 #define GMAC_MAC_FPE_CTRL_STS_TVER_WIDTH         EMAC_MAC_FPE_CTRL_STS_TVER_WIDTH
1176 #define GMAC_MAC_FPE_CTRL_STS_TVER(x)            EMAC_MAC_FPE_CTRL_STS_TVER(x)
1177 #define GMAC_MAC_FPE_CTRL_STS_TRSP_MASK          EMAC_MAC_FPE_CTRL_STS_TRSP_MASK
1178 #define GMAC_MAC_FPE_CTRL_STS_TRSP_SHIFT         EMAC_MAC_FPE_CTRL_STS_TRSP_SHIFT
1179 #define GMAC_MAC_FPE_CTRL_STS_TRSP_WIDTH         EMAC_MAC_FPE_CTRL_STS_TRSP_WIDTH
1180 #define GMAC_MAC_FPE_CTRL_STS_TRSP(x)            EMAC_MAC_FPE_CTRL_STS_TRSP(x)
1181 /*! @} */
1182 
1183 /*! @name MAC_PRESN_TIME_NS -  */
1184 /*! @{ */
1185 #define GMAC_MAC_PRESN_TIME_NS_MPTN_MASK         EMAC_MAC_PRESN_TIME_NS_MPTN_MASK
1186 #define GMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT        EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT
1187 #define GMAC_MAC_PRESN_TIME_NS_MPTN_WIDTH        EMAC_MAC_PRESN_TIME_NS_MPTN_WIDTH
1188 #define GMAC_MAC_PRESN_TIME_NS_MPTN(x)           EMAC_MAC_PRESN_TIME_NS_MPTN(x)
1189 /*! @} */
1190 
1191 /*! @name MAC_PRESN_TIME_UPDT -  */
1192 /*! @{ */
1193 #define GMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK       EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK
1194 #define GMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT      EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT
1195 #define GMAC_MAC_PRESN_TIME_UPDT_MPTU_WIDTH      EMAC_MAC_PRESN_TIME_UPDT_MPTU_WIDTH
1196 #define GMAC_MAC_PRESN_TIME_UPDT_MPTU(x)         EMAC_MAC_PRESN_TIME_UPDT_MPTU(x)
1197 /*! @} */
1198 
1199 /*! @name MAC_ADDRESS0_HIGH -  */
1200 /*! @{ */
1201 #define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK       EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK
1202 #define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT      EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT
1203 #define GMAC_MAC_ADDRESS0_HIGH_ADDRHI_WIDTH      EMAC_MAC_ADDRESS0_HIGH_ADDRHI_WIDTH
1204 #define GMAC_MAC_ADDRESS0_HIGH_ADDRHI(x)         EMAC_MAC_ADDRESS0_HIGH_ADDRHI(x)
1205 #define GMAC_MAC_ADDRESS0_HIGH_DCS_MASK          EMAC_MAC_ADDRESS0_HIGH_DCS_MASK
1206 #define GMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT         EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT
1207 #define GMAC_MAC_ADDRESS0_HIGH_DCS_WIDTH         EMAC_MAC_ADDRESS0_HIGH_DCS_WIDTH
1208 #define GMAC_MAC_ADDRESS0_HIGH_DCS(x)            EMAC_MAC_ADDRESS0_HIGH_DCS(x)
1209 #define GMAC_MAC_ADDRESS0_HIGH_AE_MASK           EMAC_MAC_ADDRESS0_HIGH_AE_MASK
1210 #define GMAC_MAC_ADDRESS0_HIGH_AE_SHIFT          EMAC_MAC_ADDRESS0_HIGH_AE_SHIFT
1211 #define GMAC_MAC_ADDRESS0_HIGH_AE_WIDTH          EMAC_MAC_ADDRESS0_HIGH_AE_WIDTH
1212 #define GMAC_MAC_ADDRESS0_HIGH_AE(x)             EMAC_MAC_ADDRESS0_HIGH_AE(x)
1213 /*! @} */
1214 
1215 /*! @name MAC_ADDRESS0_LOW -  */
1216 /*! @{ */
1217 #define GMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK        EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK
1218 #define GMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT       EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT
1219 #define GMAC_MAC_ADDRESS0_LOW_ADDRLO_WIDTH       EMAC_MAC_ADDRESS0_LOW_ADDRLO_WIDTH
1220 #define GMAC_MAC_ADDRESS0_LOW_ADDRLO(x)          EMAC_MAC_ADDRESS0_LOW_ADDRLO(x)
1221 /*! @} */
1222 
1223 /*! @name MAC_ADDRESS1_HIGH -  */
1224 /*! @{ */
1225 #define GMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK       EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK
1226 #define GMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT      EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT
1227 #define GMAC_MAC_ADDRESS1_HIGH_ADDRHI_WIDTH      EMAC_MAC_ADDRESS1_HIGH_ADDRHI_WIDTH
1228 #define GMAC_MAC_ADDRESS1_HIGH_ADDRHI(x)         EMAC_MAC_ADDRESS1_HIGH_ADDRHI(x)
1229 #define GMAC_MAC_ADDRESS1_HIGH_DCS_MASK          EMAC_MAC_ADDRESS1_HIGH_DCS_MASK
1230 #define GMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT         EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT
1231 #define GMAC_MAC_ADDRESS1_HIGH_DCS_WIDTH         EMAC_MAC_ADDRESS1_HIGH_DCS_WIDTH
1232 #define GMAC_MAC_ADDRESS1_HIGH_DCS(x)            EMAC_MAC_ADDRESS1_HIGH_DCS(x)
1233 #define GMAC_MAC_ADDRESS1_HIGH_MBC_MASK          EMAC_MAC_ADDRESS1_HIGH_MBC_MASK
1234 #define GMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT         EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT
1235 #define GMAC_MAC_ADDRESS1_HIGH_MBC_WIDTH         EMAC_MAC_ADDRESS1_HIGH_MBC_WIDTH
1236 #define GMAC_MAC_ADDRESS1_HIGH_MBC(x)            EMAC_MAC_ADDRESS1_HIGH_MBC(x)
1237 #define GMAC_MAC_ADDRESS1_HIGH_SA_MASK           EMAC_MAC_ADDRESS1_HIGH_SA_MASK
1238 #define GMAC_MAC_ADDRESS1_HIGH_SA_SHIFT          EMAC_MAC_ADDRESS1_HIGH_SA_SHIFT
1239 #define GMAC_MAC_ADDRESS1_HIGH_SA_WIDTH          EMAC_MAC_ADDRESS1_HIGH_SA_WIDTH
1240 #define GMAC_MAC_ADDRESS1_HIGH_SA(x)             EMAC_MAC_ADDRESS1_HIGH_SA(x)
1241 #define GMAC_MAC_ADDRESS1_HIGH_AE_MASK           EMAC_MAC_ADDRESS1_HIGH_AE_MASK
1242 #define GMAC_MAC_ADDRESS1_HIGH_AE_SHIFT          EMAC_MAC_ADDRESS1_HIGH_AE_SHIFT
1243 #define GMAC_MAC_ADDRESS1_HIGH_AE_WIDTH          EMAC_MAC_ADDRESS1_HIGH_AE_WIDTH
1244 #define GMAC_MAC_ADDRESS1_HIGH_AE(x)             EMAC_MAC_ADDRESS1_HIGH_AE(x)
1245 /*! @} */
1246 
1247 /*! @name MAC_ADDRESS1_LOW -  */
1248 /*! @{ */
1249 #define GMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK        EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK
1250 #define GMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT       EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT
1251 #define GMAC_MAC_ADDRESS1_LOW_ADDRLO_WIDTH       EMAC_MAC_ADDRESS1_LOW_ADDRLO_WIDTH
1252 #define GMAC_MAC_ADDRESS1_LOW_ADDRLO(x)          EMAC_MAC_ADDRESS1_LOW_ADDRLO(x)
1253 /*! @} */
1254 
1255 /*! @name MAC_ADDRESS2_HIGH -  */
1256 /*! @{ */
1257 #define GMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK       EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK
1258 #define GMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT      EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT
1259 #define GMAC_MAC_ADDRESS2_HIGH_ADDRHI_WIDTH      EMAC_MAC_ADDRESS2_HIGH_ADDRHI_WIDTH
1260 #define GMAC_MAC_ADDRESS2_HIGH_ADDRHI(x)         EMAC_MAC_ADDRESS2_HIGH_ADDRHI(x)
1261 #define GMAC_MAC_ADDRESS2_HIGH_DCS_MASK          EMAC_MAC_ADDRESS2_HIGH_DCS_MASK
1262 #define GMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT         EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT
1263 #define GMAC_MAC_ADDRESS2_HIGH_DCS_WIDTH         EMAC_MAC_ADDRESS2_HIGH_DCS_WIDTH
1264 #define GMAC_MAC_ADDRESS2_HIGH_DCS(x)            EMAC_MAC_ADDRESS2_HIGH_DCS(x)
1265 #define GMAC_MAC_ADDRESS2_HIGH_MBC_MASK          EMAC_MAC_ADDRESS2_HIGH_MBC_MASK
1266 #define GMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT         EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT
1267 #define GMAC_MAC_ADDRESS2_HIGH_MBC_WIDTH         EMAC_MAC_ADDRESS2_HIGH_MBC_WIDTH
1268 #define GMAC_MAC_ADDRESS2_HIGH_MBC(x)            EMAC_MAC_ADDRESS2_HIGH_MBC(x)
1269 #define GMAC_MAC_ADDRESS2_HIGH_SA_MASK           EMAC_MAC_ADDRESS2_HIGH_SA_MASK
1270 #define GMAC_MAC_ADDRESS2_HIGH_SA_SHIFT          EMAC_MAC_ADDRESS2_HIGH_SA_SHIFT
1271 #define GMAC_MAC_ADDRESS2_HIGH_SA_WIDTH          EMAC_MAC_ADDRESS2_HIGH_SA_WIDTH
1272 #define GMAC_MAC_ADDRESS2_HIGH_SA(x)             EMAC_MAC_ADDRESS2_HIGH_SA(x)
1273 #define GMAC_MAC_ADDRESS2_HIGH_AE_MASK           EMAC_MAC_ADDRESS2_HIGH_AE_MASK
1274 #define GMAC_MAC_ADDRESS2_HIGH_AE_SHIFT          EMAC_MAC_ADDRESS2_HIGH_AE_SHIFT
1275 #define GMAC_MAC_ADDRESS2_HIGH_AE_WIDTH          EMAC_MAC_ADDRESS2_HIGH_AE_WIDTH
1276 #define GMAC_MAC_ADDRESS2_HIGH_AE(x)             EMAC_MAC_ADDRESS2_HIGH_AE(x)
1277 /*! @} */
1278 
1279 /*! @name MAC_ADDRESS2_LOW -  */
1280 /*! @{ */
1281 #define GMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK        EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK
1282 #define GMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT       EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT
1283 #define GMAC_MAC_ADDRESS2_LOW_ADDRLO_WIDTH       EMAC_MAC_ADDRESS2_LOW_ADDRLO_WIDTH
1284 #define GMAC_MAC_ADDRESS2_LOW_ADDRLO(x)          EMAC_MAC_ADDRESS2_LOW_ADDRLO(x)
1285 /*! @} */
1286 
1287 /*! @name MMC_CONTROL -  */
1288 /*! @{ */
1289 #define GMAC_MMC_CONTROL_CNTRST_MASK             EMAC_MMC_CONTROL_CNTRST_MASK
1290 #define GMAC_MMC_CONTROL_CNTRST_SHIFT            EMAC_MMC_CONTROL_CNTRST_SHIFT
1291 #define GMAC_MMC_CONTROL_CNTRST_WIDTH            EMAC_MMC_CONTROL_CNTRST_WIDTH
1292 #define GMAC_MMC_CONTROL_CNTRST(x)               EMAC_MMC_CONTROL_CNTRST(x)
1293 #define GMAC_MMC_CONTROL_CNTSTOPRO_MASK          EMAC_MMC_CONTROL_CNTSTOPRO_MASK
1294 #define GMAC_MMC_CONTROL_CNTSTOPRO_SHIFT         EMAC_MMC_CONTROL_CNTSTOPRO_SHIFT
1295 #define GMAC_MMC_CONTROL_CNTSTOPRO_WIDTH         EMAC_MMC_CONTROL_CNTSTOPRO_WIDTH
1296 #define GMAC_MMC_CONTROL_CNTSTOPRO(x)            EMAC_MMC_CONTROL_CNTSTOPRO(x)
1297 #define GMAC_MMC_CONTROL_RSTONRD_MASK            EMAC_MMC_CONTROL_RSTONRD_MASK
1298 #define GMAC_MMC_CONTROL_RSTONRD_SHIFT           EMAC_MMC_CONTROL_RSTONRD_SHIFT
1299 #define GMAC_MMC_CONTROL_RSTONRD_WIDTH           EMAC_MMC_CONTROL_RSTONRD_WIDTH
1300 #define GMAC_MMC_CONTROL_RSTONRD(x)              EMAC_MMC_CONTROL_RSTONRD(x)
1301 #define GMAC_MMC_CONTROL_CNTFREEZ_MASK           EMAC_MMC_CONTROL_CNTFREEZ_MASK
1302 #define GMAC_MMC_CONTROL_CNTFREEZ_SHIFT          EMAC_MMC_CONTROL_CNTFREEZ_SHIFT
1303 #define GMAC_MMC_CONTROL_CNTFREEZ_WIDTH          EMAC_MMC_CONTROL_CNTFREEZ_WIDTH
1304 #define GMAC_MMC_CONTROL_CNTFREEZ(x)             EMAC_MMC_CONTROL_CNTFREEZ(x)
1305 #define GMAC_MMC_CONTROL_CNTPRST_MASK            EMAC_MMC_CONTROL_CNTPRST_MASK
1306 #define GMAC_MMC_CONTROL_CNTPRST_SHIFT           EMAC_MMC_CONTROL_CNTPRST_SHIFT
1307 #define GMAC_MMC_CONTROL_CNTPRST_WIDTH           EMAC_MMC_CONTROL_CNTPRST_WIDTH
1308 #define GMAC_MMC_CONTROL_CNTPRST(x)              EMAC_MMC_CONTROL_CNTPRST(x)
1309 #define GMAC_MMC_CONTROL_CNTPRSTLVL_MASK         EMAC_MMC_CONTROL_CNTPRSTLVL_MASK
1310 #define GMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT        EMAC_MMC_CONTROL_CNTPRSTLVL_SHIFT
1311 #define GMAC_MMC_CONTROL_CNTPRSTLVL_WIDTH        EMAC_MMC_CONTROL_CNTPRSTLVL_WIDTH
1312 #define GMAC_MMC_CONTROL_CNTPRSTLVL(x)           EMAC_MMC_CONTROL_CNTPRSTLVL(x)
1313 #define GMAC_MMC_CONTROL_UCDBC_MASK              EMAC_MMC_CONTROL_UCDBC_MASK
1314 #define GMAC_MMC_CONTROL_UCDBC_SHIFT             EMAC_MMC_CONTROL_UCDBC_SHIFT
1315 #define GMAC_MMC_CONTROL_UCDBC_WIDTH             EMAC_MMC_CONTROL_UCDBC_WIDTH
1316 #define GMAC_MMC_CONTROL_UCDBC(x)                EMAC_MMC_CONTROL_UCDBC(x)
1317 /*! @} */
1318 
1319 /*! @name MMC_RX_INTERRUPT -  */
1320 /*! @{ */
1321 #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK     EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK
1322 #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT    EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT
1323 #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS_WIDTH    EMAC_MMC_RX_INTERRUPT_RXGBPKTIS_WIDTH
1324 #define GMAC_MMC_RX_INTERRUPT_RXGBPKTIS(x)       EMAC_MMC_RX_INTERRUPT_RXGBPKTIS(x)
1325 #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK     EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK
1326 #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT    EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT
1327 #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS_WIDTH    EMAC_MMC_RX_INTERRUPT_RXGBOCTIS_WIDTH
1328 #define GMAC_MMC_RX_INTERRUPT_RXGBOCTIS(x)       EMAC_MMC_RX_INTERRUPT_RXGBOCTIS(x)
1329 #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK      EMAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK
1330 #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT     EMAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT
1331 #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS_WIDTH     EMAC_MMC_RX_INTERRUPT_RXGOCTIS_WIDTH
1332 #define GMAC_MMC_RX_INTERRUPT_RXGOCTIS(x)        EMAC_MMC_RX_INTERRUPT_RXGOCTIS(x)
1333 #define GMAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK      EMAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK
1334 #define GMAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT     EMAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT
1335 #define GMAC_MMC_RX_INTERRUPT_RXBCGPIS_WIDTH     EMAC_MMC_RX_INTERRUPT_RXBCGPIS_WIDTH
1336 #define GMAC_MMC_RX_INTERRUPT_RXBCGPIS(x)        EMAC_MMC_RX_INTERRUPT_RXBCGPIS(x)
1337 #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK      EMAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK
1338 #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT     EMAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT
1339 #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS_WIDTH     EMAC_MMC_RX_INTERRUPT_RXMCGPIS_WIDTH
1340 #define GMAC_MMC_RX_INTERRUPT_RXMCGPIS(x)        EMAC_MMC_RX_INTERRUPT_RXMCGPIS(x)
1341 #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK    EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK
1342 #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT   EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT
1343 #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS_WIDTH   EMAC_MMC_RX_INTERRUPT_RXCRCERPIS_WIDTH
1344 #define GMAC_MMC_RX_INTERRUPT_RXCRCERPIS(x)      EMAC_MMC_RX_INTERRUPT_RXCRCERPIS(x)
1345 #define GMAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK   EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK
1346 #define GMAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT  EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT
1347 #define GMAC_MMC_RX_INTERRUPT_RXALGNERPIS_WIDTH  EMAC_MMC_RX_INTERRUPT_RXALGNERPIS_WIDTH
1348 #define GMAC_MMC_RX_INTERRUPT_RXALGNERPIS(x)     EMAC_MMC_RX_INTERRUPT_RXALGNERPIS(x)
1349 #define GMAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK     EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK
1350 #define GMAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT    EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT
1351 #define GMAC_MMC_RX_INTERRUPT_RXRUNTPIS_WIDTH    EMAC_MMC_RX_INTERRUPT_RXRUNTPIS_WIDTH
1352 #define GMAC_MMC_RX_INTERRUPT_RXRUNTPIS(x)       EMAC_MMC_RX_INTERRUPT_RXRUNTPIS(x)
1353 #define GMAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK    EMAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK
1354 #define GMAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT   EMAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT
1355 #define GMAC_MMC_RX_INTERRUPT_RXJABERPIS_WIDTH   EMAC_MMC_RX_INTERRUPT_RXJABERPIS_WIDTH
1356 #define GMAC_MMC_RX_INTERRUPT_RXJABERPIS(x)      EMAC_MMC_RX_INTERRUPT_RXJABERPIS(x)
1357 #define GMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK   EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK
1358 #define GMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT  EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT
1359 #define GMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_WIDTH  EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_WIDTH
1360 #define GMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x)     EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x)
1361 #define GMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK   EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK
1362 #define GMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT  EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT
1363 #define GMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_WIDTH  EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_WIDTH
1364 #define GMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x)     EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x)
1365 #define GMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK  EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK
1366 #define GMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT
1367 #define GMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_WIDTH
1368 #define GMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x)    EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x)
1369 #define GMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK
1370 #define GMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT
1371 #define GMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_WIDTH
1372 #define GMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x)
1373 #define GMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK
1374 #define GMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT
1375 #define GMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_WIDTH
1376 #define GMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x)
1377 #define GMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK
1378 #define GMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT
1379 #define GMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_WIDTH
1380 #define GMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x)
1381 #define GMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK
1382 #define GMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT
1383 #define GMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_WIDTH
1384 #define GMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x)
1385 #define GMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK
1386 #define GMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT
1387 #define GMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_WIDTH EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_WIDTH
1388 #define GMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x)
1389 #define GMAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK      EMAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK
1390 #define GMAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT     EMAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT
1391 #define GMAC_MMC_RX_INTERRUPT_RXUCGPIS_WIDTH     EMAC_MMC_RX_INTERRUPT_RXUCGPIS_WIDTH
1392 #define GMAC_MMC_RX_INTERRUPT_RXUCGPIS(x)        EMAC_MMC_RX_INTERRUPT_RXUCGPIS(x)
1393 #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK    EMAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK
1394 #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT   EMAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT
1395 #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS_WIDTH   EMAC_MMC_RX_INTERRUPT_RXLENERPIS_WIDTH
1396 #define GMAC_MMC_RX_INTERRUPT_RXLENERPIS(x)      EMAC_MMC_RX_INTERRUPT_RXLENERPIS(x)
1397 #define GMAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK   EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK
1398 #define GMAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT  EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT
1399 #define GMAC_MMC_RX_INTERRUPT_RXORANGEPIS_WIDTH  EMAC_MMC_RX_INTERRUPT_RXORANGEPIS_WIDTH
1400 #define GMAC_MMC_RX_INTERRUPT_RXORANGEPIS(x)     EMAC_MMC_RX_INTERRUPT_RXORANGEPIS(x)
1401 #define GMAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK     EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK
1402 #define GMAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT    EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT
1403 #define GMAC_MMC_RX_INTERRUPT_RXPAUSPIS_WIDTH    EMAC_MMC_RX_INTERRUPT_RXPAUSPIS_WIDTH
1404 #define GMAC_MMC_RX_INTERRUPT_RXPAUSPIS(x)       EMAC_MMC_RX_INTERRUPT_RXPAUSPIS(x)
1405 #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK      EMAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK
1406 #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT     EMAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT
1407 #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS_WIDTH     EMAC_MMC_RX_INTERRUPT_RXFOVPIS_WIDTH
1408 #define GMAC_MMC_RX_INTERRUPT_RXFOVPIS(x)        EMAC_MMC_RX_INTERRUPT_RXFOVPIS(x)
1409 #define GMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK   EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK
1410 #define GMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT  EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT
1411 #define GMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_WIDTH  EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS_WIDTH
1412 #define GMAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x)     EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x)
1413 #define GMAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK     EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK
1414 #define GMAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT    EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT
1415 #define GMAC_MMC_RX_INTERRUPT_RXWDOGPIS_WIDTH    EMAC_MMC_RX_INTERRUPT_RXWDOGPIS_WIDTH
1416 #define GMAC_MMC_RX_INTERRUPT_RXWDOGPIS(x)       EMAC_MMC_RX_INTERRUPT_RXWDOGPIS(x)
1417 #define GMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK   EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK
1418 #define GMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT  EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT
1419 #define GMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_WIDTH  EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS_WIDTH
1420 #define GMAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x)     EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x)
1421 #define GMAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK     EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK
1422 #define GMAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT    EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT
1423 #define GMAC_MMC_RX_INTERRUPT_RXCTRLPIS_WIDTH    EMAC_MMC_RX_INTERRUPT_RXCTRLPIS_WIDTH
1424 #define GMAC_MMC_RX_INTERRUPT_RXCTRLPIS(x)       EMAC_MMC_RX_INTERRUPT_RXCTRLPIS(x)
1425 /*! @} */
1426 
1427 /*! @name MMC_TX_INTERRUPT -  */
1428 /*! @{ */
1429 #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK     EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK
1430 #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT    EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT
1431 #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS_WIDTH    EMAC_MMC_TX_INTERRUPT_TXGBOCTIS_WIDTH
1432 #define GMAC_MMC_TX_INTERRUPT_TXGBOCTIS(x)       EMAC_MMC_TX_INTERRUPT_TXGBOCTIS(x)
1433 #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK     EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK
1434 #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT    EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT
1435 #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS_WIDTH    EMAC_MMC_TX_INTERRUPT_TXGBPKTIS_WIDTH
1436 #define GMAC_MMC_TX_INTERRUPT_TXGBPKTIS(x)       EMAC_MMC_TX_INTERRUPT_TXGBPKTIS(x)
1437 #define GMAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK      EMAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK
1438 #define GMAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT     EMAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT
1439 #define GMAC_MMC_TX_INTERRUPT_TXBCGPIS_WIDTH     EMAC_MMC_TX_INTERRUPT_TXBCGPIS_WIDTH
1440 #define GMAC_MMC_TX_INTERRUPT_TXBCGPIS(x)        EMAC_MMC_TX_INTERRUPT_TXBCGPIS(x)
1441 #define GMAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK      EMAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK
1442 #define GMAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT     EMAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT
1443 #define GMAC_MMC_TX_INTERRUPT_TXMCGPIS_WIDTH     EMAC_MMC_TX_INTERRUPT_TXMCGPIS_WIDTH
1444 #define GMAC_MMC_TX_INTERRUPT_TXMCGPIS(x)        EMAC_MMC_TX_INTERRUPT_TXMCGPIS(x)
1445 #define GMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK  EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK
1446 #define GMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT
1447 #define GMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_WIDTH
1448 #define GMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x)    EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x)
1449 #define GMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK
1450 #define GMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT
1451 #define GMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_WIDTH
1452 #define GMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x)
1453 #define GMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK
1454 #define GMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT
1455 #define GMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_WIDTH
1456 #define GMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x)
1457 #define GMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK
1458 #define GMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT
1459 #define GMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_WIDTH
1460 #define GMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x)
1461 #define GMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK
1462 #define GMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT
1463 #define GMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_WIDTH
1464 #define GMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x)
1465 #define GMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK
1466 #define GMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT
1467 #define GMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_WIDTH
1468 #define GMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x)
1469 #define GMAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK     EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK
1470 #define GMAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT    EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT
1471 #define GMAC_MMC_TX_INTERRUPT_TXUCGBPIS_WIDTH    EMAC_MMC_TX_INTERRUPT_TXUCGBPIS_WIDTH
1472 #define GMAC_MMC_TX_INTERRUPT_TXUCGBPIS(x)       EMAC_MMC_TX_INTERRUPT_TXUCGBPIS(x)
1473 #define GMAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK     EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK
1474 #define GMAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT    EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT
1475 #define GMAC_MMC_TX_INTERRUPT_TXMCGBPIS_WIDTH    EMAC_MMC_TX_INTERRUPT_TXMCGBPIS_WIDTH
1476 #define GMAC_MMC_TX_INTERRUPT_TXMCGBPIS(x)       EMAC_MMC_TX_INTERRUPT_TXMCGBPIS(x)
1477 #define GMAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK     EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK
1478 #define GMAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT    EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT
1479 #define GMAC_MMC_TX_INTERRUPT_TXBCGBPIS_WIDTH    EMAC_MMC_TX_INTERRUPT_TXBCGBPIS_WIDTH
1480 #define GMAC_MMC_TX_INTERRUPT_TXBCGBPIS(x)       EMAC_MMC_TX_INTERRUPT_TXBCGBPIS(x)
1481 #define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK  EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK
1482 #define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT
1483 #define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_WIDTH EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_WIDTH
1484 #define GMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x)    EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x)
1485 #define GMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK    EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK
1486 #define GMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT   EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT
1487 #define GMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_WIDTH   EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS_WIDTH
1488 #define GMAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x)      EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x)
1489 #define GMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK    EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK
1490 #define GMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT   EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT
1491 #define GMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_WIDTH   EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS_WIDTH
1492 #define GMAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x)      EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x)
1493 #define GMAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK      EMAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK
1494 #define GMAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT     EMAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT
1495 #define GMAC_MMC_TX_INTERRUPT_TXDEFPIS_WIDTH     EMAC_MMC_TX_INTERRUPT_TXDEFPIS_WIDTH
1496 #define GMAC_MMC_TX_INTERRUPT_TXDEFPIS(x)        EMAC_MMC_TX_INTERRUPT_TXDEFPIS(x)
1497 #define GMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK   EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK
1498 #define GMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT  EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT
1499 #define GMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_WIDTH  EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS_WIDTH
1500 #define GMAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x)     EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x)
1501 #define GMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK    EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK
1502 #define GMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT   EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT
1503 #define GMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_WIDTH   EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS_WIDTH
1504 #define GMAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x)      EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x)
1505 #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK    EMAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK
1506 #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT   EMAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT
1507 #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS_WIDTH   EMAC_MMC_TX_INTERRUPT_TXCARERPIS_WIDTH
1508 #define GMAC_MMC_TX_INTERRUPT_TXCARERPIS(x)      EMAC_MMC_TX_INTERRUPT_TXCARERPIS(x)
1509 #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK      EMAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK
1510 #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT     EMAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT
1511 #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS_WIDTH     EMAC_MMC_TX_INTERRUPT_TXGOCTIS_WIDTH
1512 #define GMAC_MMC_TX_INTERRUPT_TXGOCTIS(x)        EMAC_MMC_TX_INTERRUPT_TXGOCTIS(x)
1513 #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK      EMAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK
1514 #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT     EMAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT
1515 #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS_WIDTH     EMAC_MMC_TX_INTERRUPT_TXGPKTIS_WIDTH
1516 #define GMAC_MMC_TX_INTERRUPT_TXGPKTIS(x)        EMAC_MMC_TX_INTERRUPT_TXGPKTIS(x)
1517 #define GMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK    EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK
1518 #define GMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT   EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT
1519 #define GMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_WIDTH   EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS_WIDTH
1520 #define GMAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x)      EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x)
1521 #define GMAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK     EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK
1522 #define GMAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT    EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT
1523 #define GMAC_MMC_TX_INTERRUPT_TXPAUSPIS_WIDTH    EMAC_MMC_TX_INTERRUPT_TXPAUSPIS_WIDTH
1524 #define GMAC_MMC_TX_INTERRUPT_TXPAUSPIS(x)       EMAC_MMC_TX_INTERRUPT_TXPAUSPIS(x)
1525 #define GMAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK    EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK
1526 #define GMAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT   EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT
1527 #define GMAC_MMC_TX_INTERRUPT_TXVLANGPIS_WIDTH   EMAC_MMC_TX_INTERRUPT_TXVLANGPIS_WIDTH
1528 #define GMAC_MMC_TX_INTERRUPT_TXVLANGPIS(x)      EMAC_MMC_TX_INTERRUPT_TXVLANGPIS(x)
1529 #define GMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK   EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK
1530 #define GMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT  EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT
1531 #define GMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_WIDTH  EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_WIDTH
1532 #define GMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x)     EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x)
1533 /*! @} */
1534 
1535 /*! @name MMC_RX_INTERRUPT_MASK -  */
1536 /*! @{ */
1537 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK
1538 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT
1539 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_WIDTH
1540 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x)  EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x)
1541 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK
1542 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT
1543 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_WIDTH
1544 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x)  EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x)
1545 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK
1546 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT
1547 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_WIDTH
1548 #define GMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x)   EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x)
1549 #define GMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK
1550 #define GMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT
1551 #define GMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_WIDTH
1552 #define GMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x)   EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x)
1553 #define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK
1554 #define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT
1555 #define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_WIDTH
1556 #define GMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x)   EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x)
1557 #define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK
1558 #define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT
1559 #define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_WIDTH
1560 #define GMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x)
1561 #define GMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK
1562 #define GMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT
1563 #define GMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_WIDTH
1564 #define GMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x)
1565 #define GMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK
1566 #define GMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT
1567 #define GMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_WIDTH
1568 #define GMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x)  EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x)
1569 #define GMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK
1570 #define GMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT
1571 #define GMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_WIDTH
1572 #define GMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x)
1573 #define GMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK
1574 #define GMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT
1575 #define GMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_WIDTH
1576 #define GMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x)
1577 #define GMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK
1578 #define GMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT
1579 #define GMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_WIDTH
1580 #define GMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x)
1581 #define GMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK
1582 #define GMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT
1583 #define GMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_WIDTH
1584 #define GMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x)
1585 #define GMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK
1586 #define GMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT
1587 #define GMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_WIDTH
1588 #define GMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x)
1589 #define GMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK
1590 #define GMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT
1591 #define GMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_WIDTH
1592 #define GMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x)
1593 #define GMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK
1594 #define GMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT
1595 #define GMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_WIDTH
1596 #define GMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x)
1597 #define GMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK
1598 #define GMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT
1599 #define GMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_WIDTH
1600 #define GMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x)
1601 #define GMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK
1602 #define GMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT
1603 #define GMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_WIDTH
1604 #define GMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x)
1605 #define GMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK
1606 #define GMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT
1607 #define GMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_WIDTH
1608 #define GMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x)   EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x)
1609 #define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK
1610 #define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT
1611 #define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_WIDTH
1612 #define GMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x)
1613 #define GMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK
1614 #define GMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT
1615 #define GMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_WIDTH
1616 #define GMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x)
1617 #define GMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK
1618 #define GMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT
1619 #define GMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_WIDTH
1620 #define GMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x)  EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x)
1621 #define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK
1622 #define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT
1623 #define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_WIDTH
1624 #define GMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x)   EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x)
1625 #define GMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK
1626 #define GMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT
1627 #define GMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_WIDTH
1628 #define GMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x)
1629 #define GMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK
1630 #define GMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT
1631 #define GMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_WIDTH
1632 #define GMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x)  EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x)
1633 #define GMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK
1634 #define GMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT
1635 #define GMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_WIDTH
1636 #define GMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x)
1637 #define GMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK
1638 #define GMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT
1639 #define GMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_WIDTH EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_WIDTH
1640 #define GMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x)  EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x)
1641 /*! @} */
1642 
1643 /*! @name MMC_TX_INTERRUPT_MASK -  */
1644 /*! @{ */
1645 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK
1646 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT
1647 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_WIDTH
1648 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x)  EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x)
1649 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK
1650 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT
1651 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_WIDTH
1652 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x)  EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x)
1653 #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK
1654 #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT
1655 #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_WIDTH
1656 #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x)   EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x)
1657 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK
1658 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT
1659 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_WIDTH
1660 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x)   EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x)
1661 #define GMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK
1662 #define GMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT
1663 #define GMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_WIDTH
1664 #define GMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x)
1665 #define GMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK
1666 #define GMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT
1667 #define GMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_WIDTH
1668 #define GMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x)
1669 #define GMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK
1670 #define GMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT
1671 #define GMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_WIDTH
1672 #define GMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x)
1673 #define GMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK
1674 #define GMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT
1675 #define GMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_WIDTH
1676 #define GMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x)
1677 #define GMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK
1678 #define GMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT
1679 #define GMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_WIDTH
1680 #define GMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x)
1681 #define GMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK
1682 #define GMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT
1683 #define GMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_WIDTH
1684 #define GMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x)
1685 #define GMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK
1686 #define GMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT
1687 #define GMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_WIDTH
1688 #define GMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x)  EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x)
1689 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK
1690 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT
1691 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_WIDTH
1692 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x)  EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x)
1693 #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK
1694 #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT
1695 #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_WIDTH
1696 #define GMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x)  EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x)
1697 #define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK
1698 #define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT
1699 #define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_WIDTH
1700 #define GMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x)
1701 #define GMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK
1702 #define GMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT
1703 #define GMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_WIDTH
1704 #define GMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x)
1705 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK
1706 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT
1707 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_WIDTH
1708 #define GMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x)
1709 #define GMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK
1710 #define GMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT
1711 #define GMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_WIDTH
1712 #define GMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x)   EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x)
1713 #define GMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK
1714 #define GMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT
1715 #define GMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_WIDTH
1716 #define GMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x)
1717 #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK
1718 #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT
1719 #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_WIDTH
1720 #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x)
1721 #define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK
1722 #define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT
1723 #define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_WIDTH
1724 #define GMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x)
1725 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK
1726 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT
1727 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_WIDTH
1728 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x)   EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x)
1729 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK
1730 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT
1731 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_WIDTH
1732 #define GMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x)   EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x)
1733 #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK
1734 #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT
1735 #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_WIDTH
1736 #define GMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x)
1737 #define GMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK
1738 #define GMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT
1739 #define GMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_WIDTH
1740 #define GMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x)  EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x)
1741 #define GMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK
1742 #define GMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT
1743 #define GMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_WIDTH
1744 #define GMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x)
1745 #define GMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK
1746 #define GMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT
1747 #define GMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_WIDTH EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_WIDTH
1748 #define GMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x)
1749 /*! @} */
1750 
1751 /*! @name TX_OCTET_COUNT_GOOD_BAD -  */
1752 /*! @{ */
1753 #define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK
1754 #define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT
1755 #define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_WIDTH EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_WIDTH
1756 #define GMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x)  EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x)
1757 /*! @} */
1758 
1759 /*! @name TX_PACKET_COUNT_GOOD_BAD -  */
1760 /*! @{ */
1761 #define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK
1762 #define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT
1763 #define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_WIDTH EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_WIDTH
1764 #define GMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x)
1765 /*! @} */
1766 
1767 /*! @name TX_BROADCAST_PACKETS_GOOD -  */
1768 /*! @{ */
1769 #define GMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK
1770 #define GMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT
1771 #define GMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_WIDTH EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_WIDTH
1772 #define GMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x)
1773 /*! @} */
1774 
1775 /*! @name TX_MULTICAST_PACKETS_GOOD -  */
1776 /*! @{ */
1777 #define GMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK
1778 #define GMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT
1779 #define GMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_WIDTH EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_WIDTH
1780 #define GMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x)
1781 /*! @} */
1782 
1783 /*! @name TX_64OCTETS_PACKETS_GOOD_BAD -  */
1784 /*! @{ */
1785 #define GMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK
1786 #define GMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT
1787 #define GMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_WIDTH EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_WIDTH
1788 #define GMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x)
1789 /*! @} */
1790 
1791 /*! @name TX_65TO127OCTETS_PACKETS_GOOD_BAD -  */
1792 /*! @{ */
1793 #define GMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK
1794 #define GMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT
1795 #define GMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_WIDTH EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_WIDTH
1796 #define GMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x)
1797 /*! @} */
1798 
1799 /*! @name TX_128TO255OCTETS_PACKETS_GOOD_BAD -  */
1800 /*! @{ */
1801 #define GMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK
1802 #define GMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT
1803 #define GMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_WIDTH EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_WIDTH
1804 #define GMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x)
1805 /*! @} */
1806 
1807 /*! @name TX_256TO511OCTETS_PACKETS_GOOD_BAD -  */
1808 /*! @{ */
1809 #define GMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK
1810 #define GMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT
1811 #define GMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_WIDTH EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_WIDTH
1812 #define GMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x)
1813 /*! @} */
1814 
1815 /*! @name TX_512TO1023OCTETS_PACKETS_GOOD_BAD -  */
1816 /*! @{ */
1817 #define GMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK
1818 #define GMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT
1819 #define GMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_WIDTH EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_WIDTH
1820 #define GMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x)
1821 /*! @} */
1822 
1823 /*! @name TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD -  */
1824 /*! @{ */
1825 #define GMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK
1826 #define GMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT
1827 #define GMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_WIDTH EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_WIDTH
1828 #define GMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x)
1829 /*! @} */
1830 
1831 /*! @name TX_UNICAST_PACKETS_GOOD_BAD -  */
1832 /*! @{ */
1833 #define GMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK
1834 #define GMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT
1835 #define GMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_WIDTH EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_WIDTH
1836 #define GMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x)
1837 /*! @} */
1838 
1839 /*! @name TX_MULTICAST_PACKETS_GOOD_BAD -  */
1840 /*! @{ */
1841 #define GMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK
1842 #define GMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT
1843 #define GMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_WIDTH EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_WIDTH
1844 #define GMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x)
1845 /*! @} */
1846 
1847 /*! @name TX_BROADCAST_PACKETS_GOOD_BAD -  */
1848 /*! @{ */
1849 #define GMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK
1850 #define GMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT
1851 #define GMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_WIDTH EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_WIDTH
1852 #define GMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x)
1853 /*! @} */
1854 
1855 /*! @name TX_UNDERFLOW_ERROR_PACKETS -  */
1856 /*! @{ */
1857 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK
1858 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT
1859 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_WIDTH EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_WIDTH
1860 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x)
1861 /*! @} */
1862 
1863 /*! @name TX_SINGLE_COLLISION_GOOD_PACKETS -  */
1864 /*! @{ */
1865 #define GMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK
1866 #define GMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT
1867 #define GMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_WIDTH EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_WIDTH
1868 #define GMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x)
1869 /*! @} */
1870 
1871 /*! @name TX_MULTIPLE_COLLISION_GOOD_PACKETS -  */
1872 /*! @{ */
1873 #define GMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK
1874 #define GMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT
1875 #define GMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_WIDTH EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_WIDTH
1876 #define GMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x)
1877 /*! @} */
1878 
1879 /*! @name TX_DEFERRED_PACKETS -  */
1880 /*! @{ */
1881 #define GMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK    EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK
1882 #define GMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT   EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT
1883 #define GMAC_TX_DEFERRED_PACKETS_TXDEFRD_WIDTH   EMAC_TX_DEFERRED_PACKETS_TXDEFRD_WIDTH
1884 #define GMAC_TX_DEFERRED_PACKETS_TXDEFRD(x)      EMAC_TX_DEFERRED_PACKETS_TXDEFRD(x)
1885 /*! @} */
1886 
1887 /*! @name TX_LATE_COLLISION_PACKETS -  */
1888 /*! @{ */
1889 #define GMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK
1890 #define GMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT
1891 #define GMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_WIDTH EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_WIDTH
1892 #define GMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x)
1893 /*! @} */
1894 
1895 /*! @name TX_EXCESSIVE_COLLISION_PACKETS -  */
1896 /*! @{ */
1897 #define GMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK
1898 #define GMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT
1899 #define GMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_WIDTH EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_WIDTH
1900 #define GMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x)
1901 /*! @} */
1902 
1903 /*! @name TX_CARRIER_ERROR_PACKETS -  */
1904 /*! @{ */
1905 #define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK
1906 #define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT
1907 #define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_WIDTH EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_WIDTH
1908 #define GMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x)  EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x)
1909 /*! @} */
1910 
1911 /*! @name TX_OCTET_COUNT_GOOD -  */
1912 /*! @{ */
1913 #define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK     EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK
1914 #define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT    EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT
1915 #define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG_WIDTH    EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_WIDTH
1916 #define GMAC_TX_OCTET_COUNT_GOOD_TXOCTG(x)       EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(x)
1917 /*! @} */
1918 
1919 /*! @name TX_PACKET_COUNT_GOOD -  */
1920 /*! @{ */
1921 #define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK    EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK
1922 #define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT   EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT
1923 #define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG_WIDTH   EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_WIDTH
1924 #define GMAC_TX_PACKET_COUNT_GOOD_TXPKTG(x)      EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(x)
1925 /*! @} */
1926 
1927 /*! @name TX_EXCESSIVE_DEFERRAL_ERROR -  */
1928 /*! @{ */
1929 #define GMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK
1930 #define GMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT
1931 #define GMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_WIDTH EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_WIDTH
1932 #define GMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x)
1933 /*! @} */
1934 
1935 /*! @name TX_PAUSE_PACKETS -  */
1936 /*! @{ */
1937 #define GMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK       EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK
1938 #define GMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT      EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT
1939 #define GMAC_TX_PAUSE_PACKETS_TXPAUSE_WIDTH      EMAC_TX_PAUSE_PACKETS_TXPAUSE_WIDTH
1940 #define GMAC_TX_PAUSE_PACKETS_TXPAUSE(x)         EMAC_TX_PAUSE_PACKETS_TXPAUSE(x)
1941 /*! @} */
1942 
1943 /*! @name TX_VLAN_PACKETS_GOOD -  */
1944 /*! @{ */
1945 #define GMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK   EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK
1946 #define GMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT  EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT
1947 #define GMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_WIDTH  EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_WIDTH
1948 #define GMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x)     EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x)
1949 /*! @} */
1950 
1951 /*! @name TX_OSIZE_PACKETS_GOOD -  */
1952 /*! @{ */
1953 #define GMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK  EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK
1954 #define GMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT
1955 #define GMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_WIDTH EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_WIDTH
1956 #define GMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x)    EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x)
1957 /*! @} */
1958 
1959 /*! @name RX_PACKETS_COUNT_GOOD_BAD -  */
1960 /*! @{ */
1961 #define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK
1962 #define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT
1963 #define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_WIDTH EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_WIDTH
1964 #define GMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x)
1965 /*! @} */
1966 
1967 /*! @name RX_OCTET_COUNT_GOOD_BAD -  */
1968 /*! @{ */
1969 #define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK
1970 #define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT
1971 #define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_WIDTH EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_WIDTH
1972 #define GMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x)  EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x)
1973 /*! @} */
1974 
1975 /*! @name RX_OCTET_COUNT_GOOD -  */
1976 /*! @{ */
1977 #define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK     EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK
1978 #define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT    EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT
1979 #define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG_WIDTH    EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_WIDTH
1980 #define GMAC_RX_OCTET_COUNT_GOOD_RXOCTG(x)       EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(x)
1981 /*! @} */
1982 
1983 /*! @name RX_BROADCAST_PACKETS_GOOD -  */
1984 /*! @{ */
1985 #define GMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK
1986 #define GMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT
1987 #define GMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_WIDTH EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_WIDTH
1988 #define GMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x)
1989 /*! @} */
1990 
1991 /*! @name RX_MULTICAST_PACKETS_GOOD -  */
1992 /*! @{ */
1993 #define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK
1994 #define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT
1995 #define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_WIDTH EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_WIDTH
1996 #define GMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x)
1997 /*! @} */
1998 
1999 /*! @name RX_CRC_ERROR_PACKETS -  */
2000 /*! @{ */
2001 #define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK  EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK
2002 #define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT
2003 #define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_WIDTH EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_WIDTH
2004 #define GMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x)    EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x)
2005 /*! @} */
2006 
2007 /*! @name RX_ALIGNMENT_ERROR_PACKETS -  */
2008 /*! @{ */
2009 #define GMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK
2010 #define GMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT
2011 #define GMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_WIDTH EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_WIDTH
2012 #define GMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x)
2013 /*! @} */
2014 
2015 /*! @name RX_RUNT_ERROR_PACKETS -  */
2016 /*! @{ */
2017 #define GMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK
2018 #define GMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT
2019 #define GMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_WIDTH EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_WIDTH
2020 #define GMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x)  EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x)
2021 /*! @} */
2022 
2023 /*! @name RX_JABBER_ERROR_PACKETS -  */
2024 /*! @{ */
2025 #define GMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK
2026 #define GMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT
2027 #define GMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_WIDTH EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_WIDTH
2028 #define GMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x)
2029 /*! @} */
2030 
2031 /*! @name RX_UNDERSIZE_PACKETS_GOOD -  */
2032 /*! @{ */
2033 #define GMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK
2034 #define GMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT
2035 #define GMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_WIDTH EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_WIDTH
2036 #define GMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x)
2037 /*! @} */
2038 
2039 /*! @name RX_OVERSIZE_PACKETS_GOOD -  */
2040 /*! @{ */
2041 #define GMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK
2042 #define GMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT
2043 #define GMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_WIDTH EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_WIDTH
2044 #define GMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x)
2045 /*! @} */
2046 
2047 /*! @name RX_64OCTETS_PACKETS_GOOD_BAD -  */
2048 /*! @{ */
2049 #define GMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK
2050 #define GMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT
2051 #define GMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_WIDTH EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_WIDTH
2052 #define GMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x)
2053 /*! @} */
2054 
2055 /*! @name RX_65TO127OCTETS_PACKETS_GOOD_BAD -  */
2056 /*! @{ */
2057 #define GMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK
2058 #define GMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT
2059 #define GMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_WIDTH EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_WIDTH
2060 #define GMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x)
2061 /*! @} */
2062 
2063 /*! @name RX_128TO255OCTETS_PACKETS_GOOD_BAD -  */
2064 /*! @{ */
2065 #define GMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK
2066 #define GMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT
2067 #define GMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_WIDTH EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_WIDTH
2068 #define GMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x)
2069 /*! @} */
2070 
2071 /*! @name RX_256TO511OCTETS_PACKETS_GOOD_BAD -  */
2072 /*! @{ */
2073 #define GMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK
2074 #define GMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT
2075 #define GMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_WIDTH EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_WIDTH
2076 #define GMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x)
2077 /*! @} */
2078 
2079 /*! @name RX_512TO1023OCTETS_PACKETS_GOOD_BAD -  */
2080 /*! @{ */
2081 #define GMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK
2082 #define GMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT
2083 #define GMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_WIDTH EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_WIDTH
2084 #define GMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x)
2085 /*! @} */
2086 
2087 /*! @name RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD -  */
2088 /*! @{ */
2089 #define GMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK
2090 #define GMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT
2091 #define GMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_WIDTH EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_WIDTH
2092 #define GMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x)
2093 /*! @} */
2094 
2095 /*! @name RX_UNICAST_PACKETS_GOOD -  */
2096 /*! @{ */
2097 #define GMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK
2098 #define GMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT
2099 #define GMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_WIDTH EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_WIDTH
2100 #define GMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x)
2101 /*! @} */
2102 
2103 /*! @name RX_LENGTH_ERROR_PACKETS -  */
2104 /*! @{ */
2105 #define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK
2106 #define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT
2107 #define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_WIDTH EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_WIDTH
2108 #define GMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x)
2109 /*! @} */
2110 
2111 /*! @name RX_OUT_OF_RANGE_TYPE_PACKETS -  */
2112 /*! @{ */
2113 #define GMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK
2114 #define GMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT
2115 #define GMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_WIDTH EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_WIDTH
2116 #define GMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x)
2117 /*! @} */
2118 
2119 /*! @name RX_PAUSE_PACKETS -  */
2120 /*! @{ */
2121 #define GMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK    EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK
2122 #define GMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT   EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT
2123 #define GMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_WIDTH   EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_WIDTH
2124 #define GMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x)      EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x)
2125 /*! @} */
2126 
2127 /*! @name RX_FIFO_OVERFLOW_PACKETS -  */
2128 /*! @{ */
2129 #define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK
2130 #define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT
2131 #define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_WIDTH EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_WIDTH
2132 #define GMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x)
2133 /*! @} */
2134 
2135 /*! @name RX_VLAN_PACKETS_GOOD_BAD -  */
2136 /*! @{ */
2137 #define GMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK
2138 #define GMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT
2139 #define GMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_WIDTH EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_WIDTH
2140 #define GMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x)
2141 /*! @} */
2142 
2143 /*! @name RX_WATCHDOG_ERROR_PACKETS -  */
2144 /*! @{ */
2145 #define GMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK
2146 #define GMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT
2147 #define GMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_WIDTH EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_WIDTH
2148 #define GMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x)
2149 /*! @} */
2150 
2151 /*! @name RX_RECEIVE_ERROR_PACKETS -  */
2152 /*! @{ */
2153 #define GMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK
2154 #define GMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT
2155 #define GMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_WIDTH EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_WIDTH
2156 #define GMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x)
2157 /*! @} */
2158 
2159 /*! @name RX_CONTROL_PACKETS_GOOD -  */
2160 /*! @{ */
2161 #define GMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK
2162 #define GMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT
2163 #define GMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_WIDTH EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_WIDTH
2164 #define GMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x)  EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x)
2165 /*! @} */
2166 
2167 /*! @name MMC_FPE_TX_INTERRUPT -  */
2168 /*! @{ */
2169 #define GMAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK      EMAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK
2170 #define GMAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT     EMAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT
2171 #define GMAC_MMC_FPE_TX_INTERRUPT_FCIS_WIDTH     EMAC_MMC_FPE_TX_INTERRUPT_FCIS_WIDTH
2172 #define GMAC_MMC_FPE_TX_INTERRUPT_FCIS(x)        EMAC_MMC_FPE_TX_INTERRUPT_FCIS(x)
2173 #define GMAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK     EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK
2174 #define GMAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT    EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT
2175 #define GMAC_MMC_FPE_TX_INTERRUPT_HRCIS_WIDTH    EMAC_MMC_FPE_TX_INTERRUPT_HRCIS_WIDTH
2176 #define GMAC_MMC_FPE_TX_INTERRUPT_HRCIS(x)       EMAC_MMC_FPE_TX_INTERRUPT_HRCIS(x)
2177 /*! @} */
2178 
2179 /*! @name MMC_FPE_TX_INTERRUPT_MASK -  */
2180 /*! @{ */
2181 #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK
2182 #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT
2183 #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_WIDTH EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_WIDTH
2184 #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x)   EMAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x)
2185 #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK
2186 #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT
2187 #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_WIDTH EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_WIDTH
2188 #define GMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x)  EMAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x)
2189 /*! @} */
2190 
2191 /*! @name MMC_TX_FPE_FRAGMENT_CNTR -  */
2192 /*! @{ */
2193 #define GMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK
2194 #define GMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT
2195 #define GMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_WIDTH EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_WIDTH
2196 #define GMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x)   EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x)
2197 /*! @} */
2198 
2199 /*! @name MMC_TX_HOLD_REQ_CNTR -  */
2200 /*! @{ */
2201 #define GMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK     EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK
2202 #define GMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT    EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT
2203 #define GMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_WIDTH    EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_WIDTH
2204 #define GMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x)       EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x)
2205 /*! @} */
2206 
2207 /*! @name MMC_FPE_RX_INTERRUPT -  */
2208 /*! @{ */
2209 #define GMAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK    EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK
2210 #define GMAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT   EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT
2211 #define GMAC_MMC_FPE_RX_INTERRUPT_PAECIS_WIDTH   EMAC_MMC_FPE_RX_INTERRUPT_PAECIS_WIDTH
2212 #define GMAC_MMC_FPE_RX_INTERRUPT_PAECIS(x)      EMAC_MMC_FPE_RX_INTERRUPT_PAECIS(x)
2213 #define GMAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK    EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK
2214 #define GMAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT   EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT
2215 #define GMAC_MMC_FPE_RX_INTERRUPT_PSECIS_WIDTH   EMAC_MMC_FPE_RX_INTERRUPT_PSECIS_WIDTH
2216 #define GMAC_MMC_FPE_RX_INTERRUPT_PSECIS(x)      EMAC_MMC_FPE_RX_INTERRUPT_PSECIS(x)
2217 #define GMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK    EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK
2218 #define GMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT   EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT
2219 #define GMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_WIDTH   EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS_WIDTH
2220 #define GMAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x)      EMAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x)
2221 #define GMAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK      EMAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK
2222 #define GMAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT     EMAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT
2223 #define GMAC_MMC_FPE_RX_INTERRUPT_FCIS_WIDTH     EMAC_MMC_FPE_RX_INTERRUPT_FCIS_WIDTH
2224 #define GMAC_MMC_FPE_RX_INTERRUPT_FCIS(x)        EMAC_MMC_FPE_RX_INTERRUPT_FCIS(x)
2225 /*! @} */
2226 
2227 /*! @name MMC_FPE_RX_INTERRUPT_MASK -  */
2228 /*! @{ */
2229 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK
2230 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT
2231 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_WIDTH
2232 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x)
2233 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK
2234 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT
2235 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_WIDTH
2236 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) EMAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x)
2237 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK
2238 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT
2239 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_WIDTH
2240 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) EMAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x)
2241 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK
2242 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT
2243 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_WIDTH EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_WIDTH
2244 #define GMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x)   EMAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x)
2245 /*! @} */
2246 
2247 /*! @name MMC_RX_PACKET_ASSEMBLY_ERR_CNTR -  */
2248 /*! @{ */
2249 #define GMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK
2250 #define GMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT
2251 #define GMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_WIDTH EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_WIDTH
2252 #define GMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x)
2253 /*! @} */
2254 
2255 /*! @name MMC_RX_PACKET_SMD_ERR_CNTR -  */
2256 /*! @{ */
2257 #define GMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK
2258 #define GMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT
2259 #define GMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_WIDTH EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_WIDTH
2260 #define GMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x)  EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x)
2261 /*! @} */
2262 
2263 /*! @name MMC_RX_PACKET_ASSEMBLY_OK_CNTR -  */
2264 /*! @{ */
2265 #define GMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK
2266 #define GMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT
2267 #define GMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_WIDTH EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_WIDTH
2268 #define GMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x)
2269 /*! @} */
2270 
2271 /*! @name MMC_RX_FPE_FRAGMENT_CNTR -  */
2272 /*! @{ */
2273 #define GMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK   EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK
2274 #define GMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT  EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT
2275 #define GMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_WIDTH  EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_WIDTH
2276 #define GMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x)     EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x)
2277 /*! @} */
2278 
2279 /*! @name MAC_L3_L4_CONTROL0 -  */
2280 /*! @{ */
2281 #define GMAC_MAC_L3_L4_CONTROL0_L3PEN0_MASK      EMAC_MAC_L3_L4_CONTROL0_L3PEN0_MASK
2282 #define GMAC_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT     EMAC_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT
2283 #define GMAC_MAC_L3_L4_CONTROL0_L3PEN0_WIDTH     EMAC_MAC_L3_L4_CONTROL0_L3PEN0_WIDTH
2284 #define GMAC_MAC_L3_L4_CONTROL0_L3PEN0(x)        EMAC_MAC_L3_L4_CONTROL0_L3PEN0(x)
2285 #define GMAC_MAC_L3_L4_CONTROL0_L3SAM0_MASK      EMAC_MAC_L3_L4_CONTROL0_L3SAM0_MASK
2286 #define GMAC_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT     EMAC_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT
2287 #define GMAC_MAC_L3_L4_CONTROL0_L3SAM0_WIDTH     EMAC_MAC_L3_L4_CONTROL0_L3SAM0_WIDTH
2288 #define GMAC_MAC_L3_L4_CONTROL0_L3SAM0(x)        EMAC_MAC_L3_L4_CONTROL0_L3SAM0(x)
2289 #define GMAC_MAC_L3_L4_CONTROL0_L3SAIM0_MASK     EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_MASK
2290 #define GMAC_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT    EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT
2291 #define GMAC_MAC_L3_L4_CONTROL0_L3SAIM0_WIDTH    EMAC_MAC_L3_L4_CONTROL0_L3SAIM0_WIDTH
2292 #define GMAC_MAC_L3_L4_CONTROL0_L3SAIM0(x)       EMAC_MAC_L3_L4_CONTROL0_L3SAIM0(x)
2293 #define GMAC_MAC_L3_L4_CONTROL0_L3DAM0_MASK      EMAC_MAC_L3_L4_CONTROL0_L3DAM0_MASK
2294 #define GMAC_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT     EMAC_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT
2295 #define GMAC_MAC_L3_L4_CONTROL0_L3DAM0_WIDTH     EMAC_MAC_L3_L4_CONTROL0_L3DAM0_WIDTH
2296 #define GMAC_MAC_L3_L4_CONTROL0_L3DAM0(x)        EMAC_MAC_L3_L4_CONTROL0_L3DAM0(x)
2297 #define GMAC_MAC_L3_L4_CONTROL0_L3DAIM0_MASK     EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_MASK
2298 #define GMAC_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT    EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT
2299 #define GMAC_MAC_L3_L4_CONTROL0_L3DAIM0_WIDTH    EMAC_MAC_L3_L4_CONTROL0_L3DAIM0_WIDTH
2300 #define GMAC_MAC_L3_L4_CONTROL0_L3DAIM0(x)       EMAC_MAC_L3_L4_CONTROL0_L3DAIM0(x)
2301 #define GMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK     EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK
2302 #define GMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT    EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT
2303 #define GMAC_MAC_L3_L4_CONTROL0_L3HSBM0_WIDTH    EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_WIDTH
2304 #define GMAC_MAC_L3_L4_CONTROL0_L3HSBM0(x)       EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(x)
2305 #define GMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK     EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK
2306 #define GMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT    EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT
2307 #define GMAC_MAC_L3_L4_CONTROL0_L3HDBM0_WIDTH    EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_WIDTH
2308 #define GMAC_MAC_L3_L4_CONTROL0_L3HDBM0(x)       EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(x)
2309 #define GMAC_MAC_L3_L4_CONTROL0_L4PEN0_MASK      EMAC_MAC_L3_L4_CONTROL0_L4PEN0_MASK
2310 #define GMAC_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT     EMAC_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT
2311 #define GMAC_MAC_L3_L4_CONTROL0_L4PEN0_WIDTH     EMAC_MAC_L3_L4_CONTROL0_L4PEN0_WIDTH
2312 #define GMAC_MAC_L3_L4_CONTROL0_L4PEN0(x)        EMAC_MAC_L3_L4_CONTROL0_L4PEN0(x)
2313 #define GMAC_MAC_L3_L4_CONTROL0_L4SPM0_MASK      EMAC_MAC_L3_L4_CONTROL0_L4SPM0_MASK
2314 #define GMAC_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT     EMAC_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT
2315 #define GMAC_MAC_L3_L4_CONTROL0_L4SPM0_WIDTH     EMAC_MAC_L3_L4_CONTROL0_L4SPM0_WIDTH
2316 #define GMAC_MAC_L3_L4_CONTROL0_L4SPM0(x)        EMAC_MAC_L3_L4_CONTROL0_L4SPM0(x)
2317 #define GMAC_MAC_L3_L4_CONTROL0_L4SPIM0_MASK     EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_MASK
2318 #define GMAC_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT    EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT
2319 #define GMAC_MAC_L3_L4_CONTROL0_L4SPIM0_WIDTH    EMAC_MAC_L3_L4_CONTROL0_L4SPIM0_WIDTH
2320 #define GMAC_MAC_L3_L4_CONTROL0_L4SPIM0(x)       EMAC_MAC_L3_L4_CONTROL0_L4SPIM0(x)
2321 #define GMAC_MAC_L3_L4_CONTROL0_L4DPM0_MASK      EMAC_MAC_L3_L4_CONTROL0_L4DPM0_MASK
2322 #define GMAC_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT     EMAC_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT
2323 #define GMAC_MAC_L3_L4_CONTROL0_L4DPM0_WIDTH     EMAC_MAC_L3_L4_CONTROL0_L4DPM0_WIDTH
2324 #define GMAC_MAC_L3_L4_CONTROL0_L4DPM0(x)        EMAC_MAC_L3_L4_CONTROL0_L4DPM0(x)
2325 #define GMAC_MAC_L3_L4_CONTROL0_L4DPIM0_MASK     EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_MASK
2326 #define GMAC_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT    EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT
2327 #define GMAC_MAC_L3_L4_CONTROL0_L4DPIM0_WIDTH    EMAC_MAC_L3_L4_CONTROL0_L4DPIM0_WIDTH
2328 #define GMAC_MAC_L3_L4_CONTROL0_L4DPIM0(x)       EMAC_MAC_L3_L4_CONTROL0_L4DPIM0(x)
2329 #define GMAC_MAC_L3_L4_CONTROL0_DMCHN0_MASK      EMAC_MAC_L3_L4_CONTROL0_DMCHN0_MASK
2330 #define GMAC_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT     EMAC_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT
2331 #define GMAC_MAC_L3_L4_CONTROL0_DMCHN0_WIDTH     EMAC_MAC_L3_L4_CONTROL0_DMCHN0_WIDTH
2332 #define GMAC_MAC_L3_L4_CONTROL0_DMCHN0(x)        EMAC_MAC_L3_L4_CONTROL0_DMCHN0(x)
2333 #define GMAC_MAC_L3_L4_CONTROL0_DMCHEN0_MASK     EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_MASK
2334 #define GMAC_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT    EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT
2335 #define GMAC_MAC_L3_L4_CONTROL0_DMCHEN0_WIDTH    EMAC_MAC_L3_L4_CONTROL0_DMCHEN0_WIDTH
2336 #define GMAC_MAC_L3_L4_CONTROL0_DMCHEN0(x)       EMAC_MAC_L3_L4_CONTROL0_DMCHEN0(x)
2337 /*! @} */
2338 
2339 /*! @name MAC_LAYER4_ADDRESS0 -  */
2340 /*! @{ */
2341 #define GMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK      EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK
2342 #define GMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT     EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT
2343 #define GMAC_MAC_LAYER4_ADDRESS0_L4SP0_WIDTH     EMAC_MAC_LAYER4_ADDRESS0_L4SP0_WIDTH
2344 #define GMAC_MAC_LAYER4_ADDRESS0_L4SP0(x)        EMAC_MAC_LAYER4_ADDRESS0_L4SP0(x)
2345 #define GMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK      EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK
2346 #define GMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT     EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT
2347 #define GMAC_MAC_LAYER4_ADDRESS0_L4DP0_WIDTH     EMAC_MAC_LAYER4_ADDRESS0_L4DP0_WIDTH
2348 #define GMAC_MAC_LAYER4_ADDRESS0_L4DP0(x)        EMAC_MAC_LAYER4_ADDRESS0_L4DP0(x)
2349 /*! @} */
2350 
2351 /*! @name MAC_LAYER3_ADDR0_REG0 -  */
2352 /*! @{ */
2353 #define GMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK    EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK
2354 #define GMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT   EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT
2355 #define GMAC_MAC_LAYER3_ADDR0_REG0_L3A00_WIDTH   EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_WIDTH
2356 #define GMAC_MAC_LAYER3_ADDR0_REG0_L3A00(x)      EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(x)
2357 /*! @} */
2358 
2359 /*! @name MAC_LAYER3_ADDR1_REG0 -  */
2360 /*! @{ */
2361 #define GMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK    EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK
2362 #define GMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT   EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT
2363 #define GMAC_MAC_LAYER3_ADDR1_REG0_L3A10_WIDTH   EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_WIDTH
2364 #define GMAC_MAC_LAYER3_ADDR1_REG0_L3A10(x)      EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(x)
2365 /*! @} */
2366 
2367 /*! @name MAC_LAYER3_ADDR2_REG0 -  */
2368 /*! @{ */
2369 #define GMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK    EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK
2370 #define GMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT   EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT
2371 #define GMAC_MAC_LAYER3_ADDR2_REG0_L3A20_WIDTH   EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_WIDTH
2372 #define GMAC_MAC_LAYER3_ADDR2_REG0_L3A20(x)      EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(x)
2373 /*! @} */
2374 
2375 /*! @name MAC_LAYER3_ADDR3_REG0 -  */
2376 /*! @{ */
2377 #define GMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK    EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK
2378 #define GMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT   EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT
2379 #define GMAC_MAC_LAYER3_ADDR3_REG0_L3A30_WIDTH   EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_WIDTH
2380 #define GMAC_MAC_LAYER3_ADDR3_REG0_L3A30(x)      EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(x)
2381 /*! @} */
2382 
2383 /*! @name MAC_L3_L4_CONTROL1 -  */
2384 /*! @{ */
2385 #define GMAC_MAC_L3_L4_CONTROL1_L3PEN1_MASK      EMAC_MAC_L3_L4_CONTROL1_L3PEN1_MASK
2386 #define GMAC_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT     EMAC_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT
2387 #define GMAC_MAC_L3_L4_CONTROL1_L3PEN1_WIDTH     EMAC_MAC_L3_L4_CONTROL1_L3PEN1_WIDTH
2388 #define GMAC_MAC_L3_L4_CONTROL1_L3PEN1(x)        EMAC_MAC_L3_L4_CONTROL1_L3PEN1(x)
2389 #define GMAC_MAC_L3_L4_CONTROL1_L3SAM1_MASK      EMAC_MAC_L3_L4_CONTROL1_L3SAM1_MASK
2390 #define GMAC_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT     EMAC_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT
2391 #define GMAC_MAC_L3_L4_CONTROL1_L3SAM1_WIDTH     EMAC_MAC_L3_L4_CONTROL1_L3SAM1_WIDTH
2392 #define GMAC_MAC_L3_L4_CONTROL1_L3SAM1(x)        EMAC_MAC_L3_L4_CONTROL1_L3SAM1(x)
2393 #define GMAC_MAC_L3_L4_CONTROL1_L3SAIM1_MASK     EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_MASK
2394 #define GMAC_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT    EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT
2395 #define GMAC_MAC_L3_L4_CONTROL1_L3SAIM1_WIDTH    EMAC_MAC_L3_L4_CONTROL1_L3SAIM1_WIDTH
2396 #define GMAC_MAC_L3_L4_CONTROL1_L3SAIM1(x)       EMAC_MAC_L3_L4_CONTROL1_L3SAIM1(x)
2397 #define GMAC_MAC_L3_L4_CONTROL1_L3DAM1_MASK      EMAC_MAC_L3_L4_CONTROL1_L3DAM1_MASK
2398 #define GMAC_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT     EMAC_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT
2399 #define GMAC_MAC_L3_L4_CONTROL1_L3DAM1_WIDTH     EMAC_MAC_L3_L4_CONTROL1_L3DAM1_WIDTH
2400 #define GMAC_MAC_L3_L4_CONTROL1_L3DAM1(x)        EMAC_MAC_L3_L4_CONTROL1_L3DAM1(x)
2401 #define GMAC_MAC_L3_L4_CONTROL1_L3DAIM1_MASK     EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_MASK
2402 #define GMAC_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT    EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT
2403 #define GMAC_MAC_L3_L4_CONTROL1_L3DAIM1_WIDTH    EMAC_MAC_L3_L4_CONTROL1_L3DAIM1_WIDTH
2404 #define GMAC_MAC_L3_L4_CONTROL1_L3DAIM1(x)       EMAC_MAC_L3_L4_CONTROL1_L3DAIM1(x)
2405 #define GMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK     EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK
2406 #define GMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT    EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT
2407 #define GMAC_MAC_L3_L4_CONTROL1_L3HSBM1_WIDTH    EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_WIDTH
2408 #define GMAC_MAC_L3_L4_CONTROL1_L3HSBM1(x)       EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(x)
2409 #define GMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK     EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK
2410 #define GMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT    EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT
2411 #define GMAC_MAC_L3_L4_CONTROL1_L3HDBM1_WIDTH    EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_WIDTH
2412 #define GMAC_MAC_L3_L4_CONTROL1_L3HDBM1(x)       EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(x)
2413 #define GMAC_MAC_L3_L4_CONTROL1_L4PEN1_MASK      EMAC_MAC_L3_L4_CONTROL1_L4PEN1_MASK
2414 #define GMAC_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT     EMAC_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT
2415 #define GMAC_MAC_L3_L4_CONTROL1_L4PEN1_WIDTH     EMAC_MAC_L3_L4_CONTROL1_L4PEN1_WIDTH
2416 #define GMAC_MAC_L3_L4_CONTROL1_L4PEN1(x)        EMAC_MAC_L3_L4_CONTROL1_L4PEN1(x)
2417 #define GMAC_MAC_L3_L4_CONTROL1_L4SPM1_MASK      EMAC_MAC_L3_L4_CONTROL1_L4SPM1_MASK
2418 #define GMAC_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT     EMAC_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT
2419 #define GMAC_MAC_L3_L4_CONTROL1_L4SPM1_WIDTH     EMAC_MAC_L3_L4_CONTROL1_L4SPM1_WIDTH
2420 #define GMAC_MAC_L3_L4_CONTROL1_L4SPM1(x)        EMAC_MAC_L3_L4_CONTROL1_L4SPM1(x)
2421 #define GMAC_MAC_L3_L4_CONTROL1_L4SPIM1_MASK     EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_MASK
2422 #define GMAC_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT    EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT
2423 #define GMAC_MAC_L3_L4_CONTROL1_L4SPIM1_WIDTH    EMAC_MAC_L3_L4_CONTROL1_L4SPIM1_WIDTH
2424 #define GMAC_MAC_L3_L4_CONTROL1_L4SPIM1(x)       EMAC_MAC_L3_L4_CONTROL1_L4SPIM1(x)
2425 #define GMAC_MAC_L3_L4_CONTROL1_L4DPM1_MASK      EMAC_MAC_L3_L4_CONTROL1_L4DPM1_MASK
2426 #define GMAC_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT     EMAC_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT
2427 #define GMAC_MAC_L3_L4_CONTROL1_L4DPM1_WIDTH     EMAC_MAC_L3_L4_CONTROL1_L4DPM1_WIDTH
2428 #define GMAC_MAC_L3_L4_CONTROL1_L4DPM1(x)        EMAC_MAC_L3_L4_CONTROL1_L4DPM1(x)
2429 #define GMAC_MAC_L3_L4_CONTROL1_L4DPIM1_MASK     EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_MASK
2430 #define GMAC_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT    EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT
2431 #define GMAC_MAC_L3_L4_CONTROL1_L4DPIM1_WIDTH    EMAC_MAC_L3_L4_CONTROL1_L4DPIM1_WIDTH
2432 #define GMAC_MAC_L3_L4_CONTROL1_L4DPIM1(x)       EMAC_MAC_L3_L4_CONTROL1_L4DPIM1(x)
2433 #define GMAC_MAC_L3_L4_CONTROL1_DMCHN1_MASK      EMAC_MAC_L3_L4_CONTROL1_DMCHN1_MASK
2434 #define GMAC_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT     EMAC_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT
2435 #define GMAC_MAC_L3_L4_CONTROL1_DMCHN1_WIDTH     EMAC_MAC_L3_L4_CONTROL1_DMCHN1_WIDTH
2436 #define GMAC_MAC_L3_L4_CONTROL1_DMCHN1(x)        EMAC_MAC_L3_L4_CONTROL1_DMCHN1(x)
2437 #define GMAC_MAC_L3_L4_CONTROL1_DMCHEN1_MASK     EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_MASK
2438 #define GMAC_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT    EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT
2439 #define GMAC_MAC_L3_L4_CONTROL1_DMCHEN1_WIDTH    EMAC_MAC_L3_L4_CONTROL1_DMCHEN1_WIDTH
2440 #define GMAC_MAC_L3_L4_CONTROL1_DMCHEN1(x)       EMAC_MAC_L3_L4_CONTROL1_DMCHEN1(x)
2441 /*! @} */
2442 
2443 /*! @name MAC_LAYER4_ADDRESS1 -  */
2444 /*! @{ */
2445 #define GMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK      EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK
2446 #define GMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT     EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT
2447 #define GMAC_MAC_LAYER4_ADDRESS1_L4SP1_WIDTH     EMAC_MAC_LAYER4_ADDRESS1_L4SP1_WIDTH
2448 #define GMAC_MAC_LAYER4_ADDRESS1_L4SP1(x)        EMAC_MAC_LAYER4_ADDRESS1_L4SP1(x)
2449 #define GMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK      EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK
2450 #define GMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT     EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT
2451 #define GMAC_MAC_LAYER4_ADDRESS1_L4DP1_WIDTH     EMAC_MAC_LAYER4_ADDRESS1_L4DP1_WIDTH
2452 #define GMAC_MAC_LAYER4_ADDRESS1_L4DP1(x)        EMAC_MAC_LAYER4_ADDRESS1_L4DP1(x)
2453 /*! @} */
2454 
2455 /*! @name MAC_LAYER3_ADDR0_REG1 -  */
2456 /*! @{ */
2457 #define GMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK    EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK
2458 #define GMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT   EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT
2459 #define GMAC_MAC_LAYER3_ADDR0_REG1_L3A01_WIDTH   EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_WIDTH
2460 #define GMAC_MAC_LAYER3_ADDR0_REG1_L3A01(x)      EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(x)
2461 /*! @} */
2462 
2463 /*! @name MAC_LAYER3_ADDR1_REG1 -  */
2464 /*! @{ */
2465 #define GMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK    EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK
2466 #define GMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT   EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT
2467 #define GMAC_MAC_LAYER3_ADDR1_REG1_L3A11_WIDTH   EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_WIDTH
2468 #define GMAC_MAC_LAYER3_ADDR1_REG1_L3A11(x)      EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(x)
2469 /*! @} */
2470 
2471 /*! @name MAC_LAYER3_ADDR2_REG1 -  */
2472 /*! @{ */
2473 #define GMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK    EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK
2474 #define GMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT   EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT
2475 #define GMAC_MAC_LAYER3_ADDR2_REG1_L3A21_WIDTH   EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_WIDTH
2476 #define GMAC_MAC_LAYER3_ADDR2_REG1_L3A21(x)      EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(x)
2477 /*! @} */
2478 
2479 /*! @name MAC_LAYER3_ADDR3_REG1 -  */
2480 /*! @{ */
2481 #define GMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK    EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK
2482 #define GMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT   EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT
2483 #define GMAC_MAC_LAYER3_ADDR3_REG1_L3A31_WIDTH   EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_WIDTH
2484 #define GMAC_MAC_LAYER3_ADDR3_REG1_L3A31(x)      EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(x)
2485 /*! @} */
2486 
2487 /*! @name MAC_L3_L4_CONTROL2 -  */
2488 /*! @{ */
2489 #define GMAC_MAC_L3_L4_CONTROL2_L3PEN2_MASK      EMAC_MAC_L3_L4_CONTROL2_L3PEN2_MASK
2490 #define GMAC_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT     EMAC_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT
2491 #define GMAC_MAC_L3_L4_CONTROL2_L3PEN2_WIDTH     EMAC_MAC_L3_L4_CONTROL2_L3PEN2_WIDTH
2492 #define GMAC_MAC_L3_L4_CONTROL2_L3PEN2(x)        EMAC_MAC_L3_L4_CONTROL2_L3PEN2(x)
2493 #define GMAC_MAC_L3_L4_CONTROL2_L3SAM2_MASK      EMAC_MAC_L3_L4_CONTROL2_L3SAM2_MASK
2494 #define GMAC_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT     EMAC_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT
2495 #define GMAC_MAC_L3_L4_CONTROL2_L3SAM2_WIDTH     EMAC_MAC_L3_L4_CONTROL2_L3SAM2_WIDTH
2496 #define GMAC_MAC_L3_L4_CONTROL2_L3SAM2(x)        EMAC_MAC_L3_L4_CONTROL2_L3SAM2(x)
2497 #define GMAC_MAC_L3_L4_CONTROL2_L3SAIM2_MASK     EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_MASK
2498 #define GMAC_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT    EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT
2499 #define GMAC_MAC_L3_L4_CONTROL2_L3SAIM2_WIDTH    EMAC_MAC_L3_L4_CONTROL2_L3SAIM2_WIDTH
2500 #define GMAC_MAC_L3_L4_CONTROL2_L3SAIM2(x)       EMAC_MAC_L3_L4_CONTROL2_L3SAIM2(x)
2501 #define GMAC_MAC_L3_L4_CONTROL2_L3DAM2_MASK      EMAC_MAC_L3_L4_CONTROL2_L3DAM2_MASK
2502 #define GMAC_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT     EMAC_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT
2503 #define GMAC_MAC_L3_L4_CONTROL2_L3DAM2_WIDTH     EMAC_MAC_L3_L4_CONTROL2_L3DAM2_WIDTH
2504 #define GMAC_MAC_L3_L4_CONTROL2_L3DAM2(x)        EMAC_MAC_L3_L4_CONTROL2_L3DAM2(x)
2505 #define GMAC_MAC_L3_L4_CONTROL2_L3DAIM2_MASK     EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_MASK
2506 #define GMAC_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT    EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT
2507 #define GMAC_MAC_L3_L4_CONTROL2_L3DAIM2_WIDTH    EMAC_MAC_L3_L4_CONTROL2_L3DAIM2_WIDTH
2508 #define GMAC_MAC_L3_L4_CONTROL2_L3DAIM2(x)       EMAC_MAC_L3_L4_CONTROL2_L3DAIM2(x)
2509 #define GMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK     EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK
2510 #define GMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT    EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT
2511 #define GMAC_MAC_L3_L4_CONTROL2_L3HSBM2_WIDTH    EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_WIDTH
2512 #define GMAC_MAC_L3_L4_CONTROL2_L3HSBM2(x)       EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(x)
2513 #define GMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK     EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK
2514 #define GMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT    EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT
2515 #define GMAC_MAC_L3_L4_CONTROL2_L3HDBM2_WIDTH    EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_WIDTH
2516 #define GMAC_MAC_L3_L4_CONTROL2_L3HDBM2(x)       EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(x)
2517 #define GMAC_MAC_L3_L4_CONTROL2_L4PEN2_MASK      EMAC_MAC_L3_L4_CONTROL2_L4PEN2_MASK
2518 #define GMAC_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT     EMAC_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT
2519 #define GMAC_MAC_L3_L4_CONTROL2_L4PEN2_WIDTH     EMAC_MAC_L3_L4_CONTROL2_L4PEN2_WIDTH
2520 #define GMAC_MAC_L3_L4_CONTROL2_L4PEN2(x)        EMAC_MAC_L3_L4_CONTROL2_L4PEN2(x)
2521 #define GMAC_MAC_L3_L4_CONTROL2_L4SPM2_MASK      EMAC_MAC_L3_L4_CONTROL2_L4SPM2_MASK
2522 #define GMAC_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT     EMAC_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT
2523 #define GMAC_MAC_L3_L4_CONTROL2_L4SPM2_WIDTH     EMAC_MAC_L3_L4_CONTROL2_L4SPM2_WIDTH
2524 #define GMAC_MAC_L3_L4_CONTROL2_L4SPM2(x)        EMAC_MAC_L3_L4_CONTROL2_L4SPM2(x)
2525 #define GMAC_MAC_L3_L4_CONTROL2_L4SPIM2_MASK     EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_MASK
2526 #define GMAC_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT    EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT
2527 #define GMAC_MAC_L3_L4_CONTROL2_L4SPIM2_WIDTH    EMAC_MAC_L3_L4_CONTROL2_L4SPIM2_WIDTH
2528 #define GMAC_MAC_L3_L4_CONTROL2_L4SPIM2(x)       EMAC_MAC_L3_L4_CONTROL2_L4SPIM2(x)
2529 #define GMAC_MAC_L3_L4_CONTROL2_L4DPM2_MASK      EMAC_MAC_L3_L4_CONTROL2_L4DPM2_MASK
2530 #define GMAC_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT     EMAC_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT
2531 #define GMAC_MAC_L3_L4_CONTROL2_L4DPM2_WIDTH     EMAC_MAC_L3_L4_CONTROL2_L4DPM2_WIDTH
2532 #define GMAC_MAC_L3_L4_CONTROL2_L4DPM2(x)        EMAC_MAC_L3_L4_CONTROL2_L4DPM2(x)
2533 #define GMAC_MAC_L3_L4_CONTROL2_L4DPIM2_MASK     EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_MASK
2534 #define GMAC_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT    EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT
2535 #define GMAC_MAC_L3_L4_CONTROL2_L4DPIM2_WIDTH    EMAC_MAC_L3_L4_CONTROL2_L4DPIM2_WIDTH
2536 #define GMAC_MAC_L3_L4_CONTROL2_L4DPIM2(x)       EMAC_MAC_L3_L4_CONTROL2_L4DPIM2(x)
2537 #define GMAC_MAC_L3_L4_CONTROL2_DMCHN2_MASK      EMAC_MAC_L3_L4_CONTROL2_DMCHN2_MASK
2538 #define GMAC_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT     EMAC_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT
2539 #define GMAC_MAC_L3_L4_CONTROL2_DMCHN2_WIDTH     EMAC_MAC_L3_L4_CONTROL2_DMCHN2_WIDTH
2540 #define GMAC_MAC_L3_L4_CONTROL2_DMCHN2(x)        EMAC_MAC_L3_L4_CONTROL2_DMCHN2(x)
2541 #define GMAC_MAC_L3_L4_CONTROL2_DMCHEN2_MASK     EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_MASK
2542 #define GMAC_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT    EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT
2543 #define GMAC_MAC_L3_L4_CONTROL2_DMCHEN2_WIDTH    EMAC_MAC_L3_L4_CONTROL2_DMCHEN2_WIDTH
2544 #define GMAC_MAC_L3_L4_CONTROL2_DMCHEN2(x)       EMAC_MAC_L3_L4_CONTROL2_DMCHEN2(x)
2545 /*! @} */
2546 
2547 /*! @name MAC_LAYER4_ADDRESS2 -  */
2548 /*! @{ */
2549 #define GMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK      EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK
2550 #define GMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT     EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT
2551 #define GMAC_MAC_LAYER4_ADDRESS2_L4SP2_WIDTH     EMAC_MAC_LAYER4_ADDRESS2_L4SP2_WIDTH
2552 #define GMAC_MAC_LAYER4_ADDRESS2_L4SP2(x)        EMAC_MAC_LAYER4_ADDRESS2_L4SP2(x)
2553 #define GMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK      EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK
2554 #define GMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT     EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT
2555 #define GMAC_MAC_LAYER4_ADDRESS2_L4DP2_WIDTH     EMAC_MAC_LAYER4_ADDRESS2_L4DP2_WIDTH
2556 #define GMAC_MAC_LAYER4_ADDRESS2_L4DP2(x)        EMAC_MAC_LAYER4_ADDRESS2_L4DP2(x)
2557 /*! @} */
2558 
2559 /*! @name MAC_LAYER3_ADDR0_REG2 -  */
2560 /*! @{ */
2561 #define GMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK    EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK
2562 #define GMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT   EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT
2563 #define GMAC_MAC_LAYER3_ADDR0_REG2_L3A02_WIDTH   EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_WIDTH
2564 #define GMAC_MAC_LAYER3_ADDR0_REG2_L3A02(x)      EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(x)
2565 /*! @} */
2566 
2567 /*! @name MAC_LAYER3_ADDR1_REG2 -  */
2568 /*! @{ */
2569 #define GMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK    EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK
2570 #define GMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT   EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT
2571 #define GMAC_MAC_LAYER3_ADDR1_REG2_L3A12_WIDTH   EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_WIDTH
2572 #define GMAC_MAC_LAYER3_ADDR1_REG2_L3A12(x)      EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(x)
2573 /*! @} */
2574 
2575 /*! @name MAC_LAYER3_ADDR2_REG2 -  */
2576 /*! @{ */
2577 #define GMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK    EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK
2578 #define GMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT   EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT
2579 #define GMAC_MAC_LAYER3_ADDR2_REG2_L3A22_WIDTH   EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_WIDTH
2580 #define GMAC_MAC_LAYER3_ADDR2_REG2_L3A22(x)      EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(x)
2581 /*! @} */
2582 
2583 /*! @name MAC_LAYER3_ADDR3_REG2 -  */
2584 /*! @{ */
2585 #define GMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK    EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK
2586 #define GMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT   EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT
2587 #define GMAC_MAC_LAYER3_ADDR3_REG2_L3A32_WIDTH   EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_WIDTH
2588 #define GMAC_MAC_LAYER3_ADDR3_REG2_L3A32(x)      EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(x)
2589 /*! @} */
2590 
2591 /*! @name MAC_L3_L4_CONTROL3 -  */
2592 /*! @{ */
2593 #define GMAC_MAC_L3_L4_CONTROL3_L3PEN3_MASK      EMAC_MAC_L3_L4_CONTROL3_L3PEN3_MASK
2594 #define GMAC_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT     EMAC_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT
2595 #define GMAC_MAC_L3_L4_CONTROL3_L3PEN3_WIDTH     EMAC_MAC_L3_L4_CONTROL3_L3PEN3_WIDTH
2596 #define GMAC_MAC_L3_L4_CONTROL3_L3PEN3(x)        EMAC_MAC_L3_L4_CONTROL3_L3PEN3(x)
2597 #define GMAC_MAC_L3_L4_CONTROL3_L3SAM3_MASK      EMAC_MAC_L3_L4_CONTROL3_L3SAM3_MASK
2598 #define GMAC_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT     EMAC_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT
2599 #define GMAC_MAC_L3_L4_CONTROL3_L3SAM3_WIDTH     EMAC_MAC_L3_L4_CONTROL3_L3SAM3_WIDTH
2600 #define GMAC_MAC_L3_L4_CONTROL3_L3SAM3(x)        EMAC_MAC_L3_L4_CONTROL3_L3SAM3(x)
2601 #define GMAC_MAC_L3_L4_CONTROL3_L3SAIM3_MASK     EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_MASK
2602 #define GMAC_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT    EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT
2603 #define GMAC_MAC_L3_L4_CONTROL3_L3SAIM3_WIDTH    EMAC_MAC_L3_L4_CONTROL3_L3SAIM3_WIDTH
2604 #define GMAC_MAC_L3_L4_CONTROL3_L3SAIM3(x)       EMAC_MAC_L3_L4_CONTROL3_L3SAIM3(x)
2605 #define GMAC_MAC_L3_L4_CONTROL3_L3DAM3_MASK      EMAC_MAC_L3_L4_CONTROL3_L3DAM3_MASK
2606 #define GMAC_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT     EMAC_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT
2607 #define GMAC_MAC_L3_L4_CONTROL3_L3DAM3_WIDTH     EMAC_MAC_L3_L4_CONTROL3_L3DAM3_WIDTH
2608 #define GMAC_MAC_L3_L4_CONTROL3_L3DAM3(x)        EMAC_MAC_L3_L4_CONTROL3_L3DAM3(x)
2609 #define GMAC_MAC_L3_L4_CONTROL3_L3DAIM3_MASK     EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_MASK
2610 #define GMAC_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT    EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT
2611 #define GMAC_MAC_L3_L4_CONTROL3_L3DAIM3_WIDTH    EMAC_MAC_L3_L4_CONTROL3_L3DAIM3_WIDTH
2612 #define GMAC_MAC_L3_L4_CONTROL3_L3DAIM3(x)       EMAC_MAC_L3_L4_CONTROL3_L3DAIM3(x)
2613 #define GMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK     EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK
2614 #define GMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT    EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT
2615 #define GMAC_MAC_L3_L4_CONTROL3_L3HSBM3_WIDTH    EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_WIDTH
2616 #define GMAC_MAC_L3_L4_CONTROL3_L3HSBM3(x)       EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(x)
2617 #define GMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK     EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK
2618 #define GMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT    EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT
2619 #define GMAC_MAC_L3_L4_CONTROL3_L3HDBM3_WIDTH    EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_WIDTH
2620 #define GMAC_MAC_L3_L4_CONTROL3_L3HDBM3(x)       EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(x)
2621 #define GMAC_MAC_L3_L4_CONTROL3_L4PEN3_MASK      EMAC_MAC_L3_L4_CONTROL3_L4PEN3_MASK
2622 #define GMAC_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT     EMAC_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT
2623 #define GMAC_MAC_L3_L4_CONTROL3_L4PEN3_WIDTH     EMAC_MAC_L3_L4_CONTROL3_L4PEN3_WIDTH
2624 #define GMAC_MAC_L3_L4_CONTROL3_L4PEN3(x)        EMAC_MAC_L3_L4_CONTROL3_L4PEN3(x)
2625 #define GMAC_MAC_L3_L4_CONTROL3_L4SPM3_MASK      EMAC_MAC_L3_L4_CONTROL3_L4SPM3_MASK
2626 #define GMAC_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT     EMAC_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT
2627 #define GMAC_MAC_L3_L4_CONTROL3_L4SPM3_WIDTH     EMAC_MAC_L3_L4_CONTROL3_L4SPM3_WIDTH
2628 #define GMAC_MAC_L3_L4_CONTROL3_L4SPM3(x)        EMAC_MAC_L3_L4_CONTROL3_L4SPM3(x)
2629 #define GMAC_MAC_L3_L4_CONTROL3_L4SPIM3_MASK     EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_MASK
2630 #define GMAC_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT    EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT
2631 #define GMAC_MAC_L3_L4_CONTROL3_L4SPIM3_WIDTH    EMAC_MAC_L3_L4_CONTROL3_L4SPIM3_WIDTH
2632 #define GMAC_MAC_L3_L4_CONTROL3_L4SPIM3(x)       EMAC_MAC_L3_L4_CONTROL3_L4SPIM3(x)
2633 #define GMAC_MAC_L3_L4_CONTROL3_L4DPM3_MASK      EMAC_MAC_L3_L4_CONTROL3_L4DPM3_MASK
2634 #define GMAC_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT     EMAC_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT
2635 #define GMAC_MAC_L3_L4_CONTROL3_L4DPM3_WIDTH     EMAC_MAC_L3_L4_CONTROL3_L4DPM3_WIDTH
2636 #define GMAC_MAC_L3_L4_CONTROL3_L4DPM3(x)        EMAC_MAC_L3_L4_CONTROL3_L4DPM3(x)
2637 #define GMAC_MAC_L3_L4_CONTROL3_L4DPIM3_MASK     EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_MASK
2638 #define GMAC_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT    EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT
2639 #define GMAC_MAC_L3_L4_CONTROL3_L4DPIM3_WIDTH    EMAC_MAC_L3_L4_CONTROL3_L4DPIM3_WIDTH
2640 #define GMAC_MAC_L3_L4_CONTROL3_L4DPIM3(x)       EMAC_MAC_L3_L4_CONTROL3_L4DPIM3(x)
2641 #define GMAC_MAC_L3_L4_CONTROL3_DMCHN3_MASK      EMAC_MAC_L3_L4_CONTROL3_DMCHN3_MASK
2642 #define GMAC_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT     EMAC_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT
2643 #define GMAC_MAC_L3_L4_CONTROL3_DMCHN3_WIDTH     EMAC_MAC_L3_L4_CONTROL3_DMCHN3_WIDTH
2644 #define GMAC_MAC_L3_L4_CONTROL3_DMCHN3(x)        EMAC_MAC_L3_L4_CONTROL3_DMCHN3(x)
2645 #define GMAC_MAC_L3_L4_CONTROL3_DMCHEN3_MASK     EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_MASK
2646 #define GMAC_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT    EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT
2647 #define GMAC_MAC_L3_L4_CONTROL3_DMCHEN3_WIDTH    EMAC_MAC_L3_L4_CONTROL3_DMCHEN3_WIDTH
2648 #define GMAC_MAC_L3_L4_CONTROL3_DMCHEN3(x)       EMAC_MAC_L3_L4_CONTROL3_DMCHEN3(x)
2649 /*! @} */
2650 
2651 /*! @name MAC_LAYER4_ADDRESS3 -  */
2652 /*! @{ */
2653 #define GMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK      EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK
2654 #define GMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT     EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT
2655 #define GMAC_MAC_LAYER4_ADDRESS3_L4SP3_WIDTH     EMAC_MAC_LAYER4_ADDRESS3_L4SP3_WIDTH
2656 #define GMAC_MAC_LAYER4_ADDRESS3_L4SP3(x)        EMAC_MAC_LAYER4_ADDRESS3_L4SP3(x)
2657 #define GMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK      EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK
2658 #define GMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT     EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT
2659 #define GMAC_MAC_LAYER4_ADDRESS3_L4DP3_WIDTH     EMAC_MAC_LAYER4_ADDRESS3_L4DP3_WIDTH
2660 #define GMAC_MAC_LAYER4_ADDRESS3_L4DP3(x)        EMAC_MAC_LAYER4_ADDRESS3_L4DP3(x)
2661 /*! @} */
2662 
2663 /*! @name MAC_LAYER3_ADDR0_REG3 -  */
2664 /*! @{ */
2665 #define GMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK    EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK
2666 #define GMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT   EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT
2667 #define GMAC_MAC_LAYER3_ADDR0_REG3_L3A03_WIDTH   EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_WIDTH
2668 #define GMAC_MAC_LAYER3_ADDR0_REG3_L3A03(x)      EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(x)
2669 /*! @} */
2670 
2671 /*! @name MAC_LAYER3_ADDR1_REG3 -  */
2672 /*! @{ */
2673 #define GMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK    EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK
2674 #define GMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT   EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT
2675 #define GMAC_MAC_LAYER3_ADDR1_REG3_L3A13_WIDTH   EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_WIDTH
2676 #define GMAC_MAC_LAYER3_ADDR1_REG3_L3A13(x)      EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(x)
2677 /*! @} */
2678 
2679 /*! @name MAC_LAYER3_ADDR2_REG3 -  */
2680 /*! @{ */
2681 #define GMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK    EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK
2682 #define GMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT   EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT
2683 #define GMAC_MAC_LAYER3_ADDR2_REG3_L3A23_WIDTH   EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_WIDTH
2684 #define GMAC_MAC_LAYER3_ADDR2_REG3_L3A23(x)      EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(x)
2685 /*! @} */
2686 
2687 /*! @name MAC_LAYER3_ADDR3_REG3 -  */
2688 /*! @{ */
2689 #define GMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK    EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK
2690 #define GMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT   EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT
2691 #define GMAC_MAC_LAYER3_ADDR3_REG3_L3A33_WIDTH   EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_WIDTH
2692 #define GMAC_MAC_LAYER3_ADDR3_REG3_L3A33(x)      EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(x)
2693 /*! @} */
2694 
2695 /*! @name MAC_TIMESTAMP_CONTROL -  */
2696 /*! @{ */
2697 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK    EMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK
2698 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT   EMAC_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT
2699 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENA_WIDTH   EMAC_MAC_TIMESTAMP_CONTROL_TSENA_WIDTH
2700 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENA(x)      EMAC_MAC_TIMESTAMP_CONTROL_TSENA(x)
2701 #define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK
2702 #define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT
2703 #define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_WIDTH
2704 #define GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x)   EMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x)
2705 #define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK   EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK
2706 #define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT  EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT
2707 #define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_WIDTH  EMAC_MAC_TIMESTAMP_CONTROL_TSINIT_WIDTH
2708 #define GMAC_MAC_TIMESTAMP_CONTROL_TSINIT(x)     EMAC_MAC_TIMESTAMP_CONTROL_TSINIT(x)
2709 #define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK   EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK
2710 #define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT  EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT
2711 #define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_WIDTH  EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_WIDTH
2712 #define GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT(x)     EMAC_MAC_TIMESTAMP_CONTROL_TSUPDT(x)
2713 #define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK
2714 #define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT
2715 #define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_WIDTH
2716 #define GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG(x)   EMAC_MAC_TIMESTAMP_CONTROL_TSADDREG(x)
2717 #define GMAC_MAC_TIMESTAMP_CONTROL_PTGE_MASK     EMAC_MAC_TIMESTAMP_CONTROL_PTGE_MASK
2718 #define GMAC_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT    EMAC_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT
2719 #define GMAC_MAC_TIMESTAMP_CONTROL_PTGE_WIDTH    EMAC_MAC_TIMESTAMP_CONTROL_PTGE_WIDTH
2720 #define GMAC_MAC_TIMESTAMP_CONTROL_PTGE(x)       EMAC_MAC_TIMESTAMP_CONTROL_PTGE(x)
2721 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK  EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK
2722 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT
2723 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSENALL_WIDTH
2724 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENALL(x)    EMAC_MAC_TIMESTAMP_CONTROL_TSENALL(x)
2725 #define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK
2726 #define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT
2727 #define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_WIDTH
2728 #define GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x)  EMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x)
2729 #define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK
2730 #define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT
2731 #define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA_WIDTH
2732 #define GMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x)  EMAC_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x)
2733 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK  EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK
2734 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT
2735 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA_WIDTH
2736 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPENA(x)    EMAC_MAC_TIMESTAMP_CONTROL_TSIPENA(x)
2737 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK
2738 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT
2739 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_WIDTH
2740 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x)  EMAC_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x)
2741 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK
2742 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT
2743 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_WIDTH
2744 #define GMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x)  EMAC_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x)
2745 #define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK
2746 #define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT
2747 #define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA_WIDTH
2748 #define GMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x)  EMAC_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x)
2749 #define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK
2750 #define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT
2751 #define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA_WIDTH
2752 #define GMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x)  EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x)
2753 #define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK
2754 #define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT
2755 #define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_WIDTH
2756 #define GMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x)
2757 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK
2758 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT
2759 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR_WIDTH
2760 #define GMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x)
2761 #define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_MASK     EMAC_MAC_TIMESTAMP_CONTROL_ESTI_MASK
2762 #define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT    EMAC_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT
2763 #define GMAC_MAC_TIMESTAMP_CONTROL_ESTI_WIDTH    EMAC_MAC_TIMESTAMP_CONTROL_ESTI_WIDTH
2764 #define GMAC_MAC_TIMESTAMP_CONTROL_ESTI(x)       EMAC_MAC_TIMESTAMP_CONTROL_ESTI(x)
2765 #define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK
2766 #define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT
2767 #define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM_WIDTH
2768 #define GMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x)   EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x)
2769 #define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK
2770 #define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT
2771 #define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_WIDTH EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_WIDTH
2772 #define GMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) EMAC_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x)
2773 /*! @} */
2774 
2775 /*! @name MAC_SUB_SECOND_INCREMENT -  */
2776 /*! @{ */
2777 #define GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK
2778 #define GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT
2779 #define GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_WIDTH EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_WIDTH
2780 #define GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(x)  EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(x)
2781 #define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK
2782 #define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT
2783 #define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC_WIDTH EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_WIDTH
2784 #define GMAC_MAC_SUB_SECOND_INCREMENT_SSINC(x)   EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(x)
2785 /*! @} */
2786 
2787 /*! @name MAC_SYSTEM_TIME_SECONDS -  */
2788 /*! @{ */
2789 #define GMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK    EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK
2790 #define GMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT   EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT
2791 #define GMAC_MAC_SYSTEM_TIME_SECONDS_TSS_WIDTH   EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_WIDTH
2792 #define GMAC_MAC_SYSTEM_TIME_SECONDS_TSS(x)      EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(x)
2793 /*! @} */
2794 
2795 /*! @name MAC_SYSTEM_TIME_NANOSECONDS -  */
2796 /*! @{ */
2797 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK
2798 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT
2799 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_WIDTH EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_WIDTH
2800 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x)
2801 /*! @} */
2802 
2803 /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE -  */
2804 /*! @{ */
2805 #define GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK
2806 #define GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT
2807 #define GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_WIDTH EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_WIDTH
2808 #define GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x)
2809 /*! @} */
2810 
2811 /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE -  */
2812 /*! @{ */
2813 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK
2814 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT
2815 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_WIDTH EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_WIDTH
2816 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x)
2817 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK
2818 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT
2819 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_WIDTH EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_WIDTH
2820 #define GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x)
2821 /*! @} */
2822 
2823 /*! @name MAC_TIMESTAMP_ADDEND -  */
2824 /*! @{ */
2825 #define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK      EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK
2826 #define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT     EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT
2827 #define GMAC_MAC_TIMESTAMP_ADDEND_TSAR_WIDTH     EMAC_MAC_TIMESTAMP_ADDEND_TSAR_WIDTH
2828 #define GMAC_MAC_TIMESTAMP_ADDEND_TSAR(x)        EMAC_MAC_TIMESTAMP_ADDEND_TSAR(x)
2829 /*! @} */
2830 
2831 /*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS -  */
2832 /*! @{ */
2833 #define GMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK
2834 #define GMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT
2835 #define GMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_WIDTH EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_WIDTH
2836 #define GMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x)
2837 /*! @} */
2838 
2839 /*! @name MAC_TIMESTAMP_STATUS -  */
2840 /*! @{ */
2841 #define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_MASK    EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_MASK
2842 #define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT   EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT
2843 #define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF_WIDTH   EMAC_MAC_TIMESTAMP_STATUS_TSSOVF_WIDTH
2844 #define GMAC_MAC_TIMESTAMP_STATUS_TSSOVF(x)      EMAC_MAC_TIMESTAMP_STATUS_TSSOVF(x)
2845 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK  EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK
2846 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT
2847 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0_WIDTH
2848 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT0(x)    EMAC_MAC_TIMESTAMP_STATUS_TSTARGT0(x)
2849 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK
2850 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT
2851 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0_WIDTH
2852 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x)  EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x)
2853 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK  EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK
2854 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT
2855 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1_WIDTH
2856 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT1(x)    EMAC_MAC_TIMESTAMP_STATUS_TSTARGT1(x)
2857 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK
2858 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT
2859 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1_WIDTH
2860 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x)  EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x)
2861 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK  EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK
2862 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT
2863 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2_WIDTH
2864 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT2(x)    EMAC_MAC_TIMESTAMP_STATUS_TSTARGT2(x)
2865 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK
2866 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT
2867 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2_WIDTH
2868 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x)  EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x)
2869 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK  EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK
2870 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT
2871 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3_WIDTH
2872 #define GMAC_MAC_TIMESTAMP_STATUS_TSTARGT3(x)    EMAC_MAC_TIMESTAMP_STATUS_TSTARGT3(x)
2873 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK
2874 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT
2875 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_WIDTH EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3_WIDTH
2876 #define GMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x)  EMAC_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x)
2877 #define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK   EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK
2878 #define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT  EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT
2879 #define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_WIDTH  EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS_WIDTH
2880 #define GMAC_MAC_TIMESTAMP_STATUS_TXTSSIS(x)     EMAC_MAC_TIMESTAMP_STATUS_TXTSSIS(x)
2881 /*! @} */
2882 
2883 /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS -  */
2884 /*! @{ */
2885 #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK
2886 #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT
2887 #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_WIDTH EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_WIDTH
2888 #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x)
2889 #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK
2890 #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT
2891 #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_WIDTH EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_WIDTH
2892 #define GMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x)
2893 /*! @} */
2894 
2895 /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS -  */
2896 /*! @{ */
2897 #define GMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK
2898 #define GMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT
2899 #define GMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_WIDTH EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_WIDTH
2900 #define GMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x)
2901 /*! @} */
2902 
2903 /*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR -  */
2904 /*! @{ */
2905 #define GMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK
2906 #define GMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT
2907 #define GMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_WIDTH
2908 #define GMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x)
2909 /*! @} */
2910 
2911 /*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR -  */
2912 /*! @{ */
2913 #define GMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK
2914 #define GMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT
2915 #define GMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_WIDTH
2916 #define GMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x)
2917 /*! @} */
2918 
2919 /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND -  */
2920 /*! @{ */
2921 #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK
2922 #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT
2923 #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_WIDTH
2924 #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x)
2925 /*! @} */
2926 
2927 /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND -  */
2928 /*! @{ */
2929 #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK
2930 #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT
2931 #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_WIDTH
2932 #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x)
2933 /*! @} */
2934 
2935 /*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC -  */
2936 /*! @{ */
2937 #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK
2938 #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT
2939 #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_WIDTH
2940 #define GMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x)
2941 /*! @} */
2942 
2943 /*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC -  */
2944 /*! @{ */
2945 #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK
2946 #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT
2947 #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_WIDTH
2948 #define GMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x)
2949 /*! @} */
2950 
2951 /*! @name MAC_TIMESTAMP_INGRESS_LATENCY -  */
2952 /*! @{ */
2953 #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK
2954 #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT
2955 #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_WIDTH
2956 #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x)
2957 #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK
2958 #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT
2959 #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_WIDTH EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_WIDTH
2960 #define GMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x)
2961 /*! @} */
2962 
2963 /*! @name MAC_TIMESTAMP_EGRESS_LATENCY -  */
2964 /*! @{ */
2965 #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK
2966 #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT
2967 #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_WIDTH
2968 #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x)
2969 #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK
2970 #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT
2971 #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_WIDTH EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_WIDTH
2972 #define GMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x)
2973 /*! @} */
2974 
2975 /*! @name MAC_PPS_CONTROL -  */
2976 /*! @{ */
2977 #define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK
2978 #define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT
2979 #define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_WIDTH EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_WIDTH
2980 #define GMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x)   EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x)
2981 #define GMAC_MAC_PPS_CONTROL_PPSEN0_MASK         EMAC_MAC_PPS_CONTROL_PPSEN0_MASK
2982 #define GMAC_MAC_PPS_CONTROL_PPSEN0_SHIFT        EMAC_MAC_PPS_CONTROL_PPSEN0_SHIFT
2983 #define GMAC_MAC_PPS_CONTROL_PPSEN0_WIDTH        EMAC_MAC_PPS_CONTROL_PPSEN0_WIDTH
2984 #define GMAC_MAC_PPS_CONTROL_PPSEN0(x)           EMAC_MAC_PPS_CONTROL_PPSEN0(x)
2985 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK    EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK
2986 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT   EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT
2987 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL0_WIDTH   EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_WIDTH
2988 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL0(x)      EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(x)
2989 #define GMAC_MAC_PPS_CONTROL_MCGREN0_MASK        EMAC_MAC_PPS_CONTROL_MCGREN0_MASK
2990 #define GMAC_MAC_PPS_CONTROL_MCGREN0_SHIFT       EMAC_MAC_PPS_CONTROL_MCGREN0_SHIFT
2991 #define GMAC_MAC_PPS_CONTROL_MCGREN0_WIDTH       EMAC_MAC_PPS_CONTROL_MCGREN0_WIDTH
2992 #define GMAC_MAC_PPS_CONTROL_MCGREN0(x)          EMAC_MAC_PPS_CONTROL_MCGREN0(x)
2993 #define GMAC_MAC_PPS_CONTROL_PPSCMD1_MASK        EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK
2994 #define GMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT       EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT
2995 #define GMAC_MAC_PPS_CONTROL_PPSCMD1_WIDTH       EMAC_MAC_PPS_CONTROL_PPSCMD1_WIDTH
2996 #define GMAC_MAC_PPS_CONTROL_PPSCMD1(x)          EMAC_MAC_PPS_CONTROL_PPSCMD1(x)
2997 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK    EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK
2998 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT   EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT
2999 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL1_WIDTH   EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_WIDTH
3000 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL1(x)      EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(x)
3001 #define GMAC_MAC_PPS_CONTROL_MCGREN1_MASK        EMAC_MAC_PPS_CONTROL_MCGREN1_MASK
3002 #define GMAC_MAC_PPS_CONTROL_MCGREN1_SHIFT       EMAC_MAC_PPS_CONTROL_MCGREN1_SHIFT
3003 #define GMAC_MAC_PPS_CONTROL_MCGREN1_WIDTH       EMAC_MAC_PPS_CONTROL_MCGREN1_WIDTH
3004 #define GMAC_MAC_PPS_CONTROL_MCGREN1(x)          EMAC_MAC_PPS_CONTROL_MCGREN1(x)
3005 #define GMAC_MAC_PPS_CONTROL_PPSCMD2_MASK        EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK
3006 #define GMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT       EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT
3007 #define GMAC_MAC_PPS_CONTROL_PPSCMD2_WIDTH       EMAC_MAC_PPS_CONTROL_PPSCMD2_WIDTH
3008 #define GMAC_MAC_PPS_CONTROL_PPSCMD2(x)          EMAC_MAC_PPS_CONTROL_PPSCMD2(x)
3009 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK    EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK
3010 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT   EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT
3011 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL2_WIDTH   EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_WIDTH
3012 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL2(x)      EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(x)
3013 #define GMAC_MAC_PPS_CONTROL_MCGREN2_MASK        EMAC_MAC_PPS_CONTROL_MCGREN2_MASK
3014 #define GMAC_MAC_PPS_CONTROL_MCGREN2_SHIFT       EMAC_MAC_PPS_CONTROL_MCGREN2_SHIFT
3015 #define GMAC_MAC_PPS_CONTROL_MCGREN2_WIDTH       EMAC_MAC_PPS_CONTROL_MCGREN2_WIDTH
3016 #define GMAC_MAC_PPS_CONTROL_MCGREN2(x)          EMAC_MAC_PPS_CONTROL_MCGREN2(x)
3017 #define GMAC_MAC_PPS_CONTROL_PPSCMD3_MASK        EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK
3018 #define GMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT       EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT
3019 #define GMAC_MAC_PPS_CONTROL_PPSCMD3_WIDTH       EMAC_MAC_PPS_CONTROL_PPSCMD3_WIDTH
3020 #define GMAC_MAC_PPS_CONTROL_PPSCMD3(x)          EMAC_MAC_PPS_CONTROL_PPSCMD3(x)
3021 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK    EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK
3022 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT   EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT
3023 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL3_WIDTH   EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_WIDTH
3024 #define GMAC_MAC_PPS_CONTROL_TRGTMODSEL3(x)      EMAC_MAC_PPS_CONTROL_TRGTMODSEL3(x)
3025 #define GMAC_MAC_PPS_CONTROL_MCGREN3_MASK        EMAC_MAC_PPS_CONTROL_MCGREN3_MASK
3026 #define GMAC_MAC_PPS_CONTROL_MCGREN3_SHIFT       EMAC_MAC_PPS_CONTROL_MCGREN3_SHIFT
3027 #define GMAC_MAC_PPS_CONTROL_MCGREN3_WIDTH       EMAC_MAC_PPS_CONTROL_MCGREN3_WIDTH
3028 #define GMAC_MAC_PPS_CONTROL_MCGREN3(x)          EMAC_MAC_PPS_CONTROL_MCGREN3(x)
3029 /*! @} */
3030 
3031 /*! @name MAC_PPS0_TARGET_TIME_SECONDS -  */
3032 /*! @{ */
3033 #define GMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK
3034 #define GMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT
3035 #define GMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_WIDTH EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_WIDTH
3036 #define GMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x)
3037 /*! @} */
3038 
3039 /*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS -  */
3040 /*! @{ */
3041 #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK
3042 #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT
3043 #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_WIDTH EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_WIDTH
3044 #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x)
3045 #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK
3046 #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT
3047 #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_WIDTH EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_WIDTH
3048 #define GMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x)
3049 /*! @} */
3050 
3051 /*! @name MAC_PPS0_INTERVAL -  */
3052 /*! @{ */
3053 #define GMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK      EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK
3054 #define GMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT     EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT
3055 #define GMAC_MAC_PPS0_INTERVAL_PPSINT0_WIDTH     EMAC_MAC_PPS0_INTERVAL_PPSINT0_WIDTH
3056 #define GMAC_MAC_PPS0_INTERVAL_PPSINT0(x)        EMAC_MAC_PPS0_INTERVAL_PPSINT0(x)
3057 /*! @} */
3058 
3059 /*! @name MAC_PPS0_WIDTH -  */
3060 /*! @{ */
3061 #define GMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK       EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK
3062 #define GMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT      EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT
3063 #define GMAC_MAC_PPS0_WIDTH_PPSWIDTH0_WIDTH      EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_WIDTH
3064 #define GMAC_MAC_PPS0_WIDTH_PPSWIDTH0(x)         EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(x)
3065 /*! @} */
3066 
3067 /*! @name MAC_PPS1_TARGET_TIME_SECONDS -  */
3068 /*! @{ */
3069 #define GMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK
3070 #define GMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT
3071 #define GMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_WIDTH EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_WIDTH
3072 #define GMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x)
3073 /*! @} */
3074 
3075 /*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS -  */
3076 /*! @{ */
3077 #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK
3078 #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT
3079 #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_WIDTH EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_WIDTH
3080 #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x)
3081 #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK
3082 #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT
3083 #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_WIDTH EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_WIDTH
3084 #define GMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x)
3085 /*! @} */
3086 
3087 /*! @name MAC_PPS1_INTERVAL -  */
3088 /*! @{ */
3089 #define GMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK      EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK
3090 #define GMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT     EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT
3091 #define GMAC_MAC_PPS1_INTERVAL_PPSINT1_WIDTH     EMAC_MAC_PPS1_INTERVAL_PPSINT1_WIDTH
3092 #define GMAC_MAC_PPS1_INTERVAL_PPSINT1(x)        EMAC_MAC_PPS1_INTERVAL_PPSINT1(x)
3093 /*! @} */
3094 
3095 /*! @name MAC_PPS1_WIDTH -  */
3096 /*! @{ */
3097 #define GMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK       EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK
3098 #define GMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT      EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT
3099 #define GMAC_MAC_PPS1_WIDTH_PPSWIDTH1_WIDTH      EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_WIDTH
3100 #define GMAC_MAC_PPS1_WIDTH_PPSWIDTH1(x)         EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(x)
3101 /*! @} */
3102 
3103 /*! @name MAC_PPS2_TARGET_TIME_SECONDS -  */
3104 /*! @{ */
3105 #define GMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK
3106 #define GMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT
3107 #define GMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_WIDTH EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_WIDTH
3108 #define GMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x)
3109 /*! @} */
3110 
3111 /*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS -  */
3112 /*! @{ */
3113 #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK
3114 #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT
3115 #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_WIDTH EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_WIDTH
3116 #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x)
3117 #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK
3118 #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT
3119 #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_WIDTH EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_WIDTH
3120 #define GMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x)
3121 /*! @} */
3122 
3123 /*! @name MAC_PPS2_INTERVAL -  */
3124 /*! @{ */
3125 #define GMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK      EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK
3126 #define GMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT     EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT
3127 #define GMAC_MAC_PPS2_INTERVAL_PPSINT2_WIDTH     EMAC_MAC_PPS2_INTERVAL_PPSINT2_WIDTH
3128 #define GMAC_MAC_PPS2_INTERVAL_PPSINT2(x)        EMAC_MAC_PPS2_INTERVAL_PPSINT2(x)
3129 /*! @} */
3130 
3131 /*! @name MAC_PPS2_WIDTH -  */
3132 /*! @{ */
3133 #define GMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK       EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK
3134 #define GMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT      EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT
3135 #define GMAC_MAC_PPS2_WIDTH_PPSWIDTH2_WIDTH      EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_WIDTH
3136 #define GMAC_MAC_PPS2_WIDTH_PPSWIDTH2(x)         EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(x)
3137 /*! @} */
3138 
3139 /*! @name MAC_PPS3_TARGET_TIME_SECONDS -  */
3140 /*! @{ */
3141 #define GMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK
3142 #define GMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT
3143 #define GMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_WIDTH EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_WIDTH
3144 #define GMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x)
3145 /*! @} */
3146 
3147 /*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS -  */
3148 /*! @{ */
3149 #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK
3150 #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT
3151 #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_WIDTH EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_WIDTH
3152 #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x)
3153 #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK
3154 #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT
3155 #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_WIDTH EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_WIDTH
3156 #define GMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x)
3157 /*! @} */
3158 
3159 /*! @name MAC_PPS3_INTERVAL -  */
3160 /*! @{ */
3161 #define GMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK      EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK
3162 #define GMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT     EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT
3163 #define GMAC_MAC_PPS3_INTERVAL_PPSINT3_WIDTH     EMAC_MAC_PPS3_INTERVAL_PPSINT3_WIDTH
3164 #define GMAC_MAC_PPS3_INTERVAL_PPSINT3(x)        EMAC_MAC_PPS3_INTERVAL_PPSINT3(x)
3165 /*! @} */
3166 
3167 /*! @name MAC_PPS3_WIDTH -  */
3168 /*! @{ */
3169 #define GMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK       EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK
3170 #define GMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT      EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT
3171 #define GMAC_MAC_PPS3_WIDTH_PPSWIDTH3_WIDTH      EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_WIDTH
3172 #define GMAC_MAC_PPS3_WIDTH_PPSWIDTH3(x)         EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(x)
3173 /*! @} */
3174 
3175 /*! @name MTL_OPERATION_MODE -  */
3176 /*! @{ */
3177 #define GMAC_MTL_OPERATION_MODE_DTXSTS_MASK      EMAC_MTL_OPERATION_MODE_DTXSTS_MASK
3178 #define GMAC_MTL_OPERATION_MODE_DTXSTS_SHIFT     EMAC_MTL_OPERATION_MODE_DTXSTS_SHIFT
3179 #define GMAC_MTL_OPERATION_MODE_DTXSTS_WIDTH     EMAC_MTL_OPERATION_MODE_DTXSTS_WIDTH
3180 #define GMAC_MTL_OPERATION_MODE_DTXSTS(x)        EMAC_MTL_OPERATION_MODE_DTXSTS(x)
3181 #define GMAC_MTL_OPERATION_MODE_RAA_MASK         EMAC_MTL_OPERATION_MODE_RAA_MASK
3182 #define GMAC_MTL_OPERATION_MODE_RAA_SHIFT        EMAC_MTL_OPERATION_MODE_RAA_SHIFT
3183 #define GMAC_MTL_OPERATION_MODE_RAA_WIDTH        EMAC_MTL_OPERATION_MODE_RAA_WIDTH
3184 #define GMAC_MTL_OPERATION_MODE_RAA(x)           EMAC_MTL_OPERATION_MODE_RAA(x)
3185 #define GMAC_MTL_OPERATION_MODE_SCHALG_MASK      EMAC_MTL_OPERATION_MODE_SCHALG_MASK
3186 #define GMAC_MTL_OPERATION_MODE_SCHALG_SHIFT     EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT
3187 #define GMAC_MTL_OPERATION_MODE_SCHALG_WIDTH     EMAC_MTL_OPERATION_MODE_SCHALG_WIDTH
3188 #define GMAC_MTL_OPERATION_MODE_SCHALG(x)        EMAC_MTL_OPERATION_MODE_SCHALG(x)
3189 #define GMAC_MTL_OPERATION_MODE_CNTPRST_MASK     EMAC_MTL_OPERATION_MODE_CNTPRST_MASK
3190 #define GMAC_MTL_OPERATION_MODE_CNTPRST_SHIFT    EMAC_MTL_OPERATION_MODE_CNTPRST_SHIFT
3191 #define GMAC_MTL_OPERATION_MODE_CNTPRST_WIDTH    EMAC_MTL_OPERATION_MODE_CNTPRST_WIDTH
3192 #define GMAC_MTL_OPERATION_MODE_CNTPRST(x)       EMAC_MTL_OPERATION_MODE_CNTPRST(x)
3193 #define GMAC_MTL_OPERATION_MODE_CNTCLR_MASK      EMAC_MTL_OPERATION_MODE_CNTCLR_MASK
3194 #define GMAC_MTL_OPERATION_MODE_CNTCLR_SHIFT     EMAC_MTL_OPERATION_MODE_CNTCLR_SHIFT
3195 #define GMAC_MTL_OPERATION_MODE_CNTCLR_WIDTH     EMAC_MTL_OPERATION_MODE_CNTCLR_WIDTH
3196 #define GMAC_MTL_OPERATION_MODE_CNTCLR(x)        EMAC_MTL_OPERATION_MODE_CNTCLR(x)
3197 #define GMAC_MTL_OPERATION_MODE_FRPE_MASK        EMAC_MTL_OPERATION_MODE_FRPE_MASK
3198 #define GMAC_MTL_OPERATION_MODE_FRPE_SHIFT       EMAC_MTL_OPERATION_MODE_FRPE_SHIFT
3199 #define GMAC_MTL_OPERATION_MODE_FRPE_WIDTH       EMAC_MTL_OPERATION_MODE_FRPE_WIDTH
3200 #define GMAC_MTL_OPERATION_MODE_FRPE(x)          EMAC_MTL_OPERATION_MODE_FRPE(x)
3201 /*! @} */
3202 
3203 /*! @name MTL_DBG_CTL -  */
3204 /*! @{ */
3205 #define GMAC_MTL_DBG_CTL_FDBGEN_MASK             EMAC_MTL_DBG_CTL_FDBGEN_MASK
3206 #define GMAC_MTL_DBG_CTL_FDBGEN_SHIFT            EMAC_MTL_DBG_CTL_FDBGEN_SHIFT
3207 #define GMAC_MTL_DBG_CTL_FDBGEN_WIDTH            EMAC_MTL_DBG_CTL_FDBGEN_WIDTH
3208 #define GMAC_MTL_DBG_CTL_FDBGEN(x)               EMAC_MTL_DBG_CTL_FDBGEN(x)
3209 #define GMAC_MTL_DBG_CTL_DBGMOD_MASK             EMAC_MTL_DBG_CTL_DBGMOD_MASK
3210 #define GMAC_MTL_DBG_CTL_DBGMOD_SHIFT            EMAC_MTL_DBG_CTL_DBGMOD_SHIFT
3211 #define GMAC_MTL_DBG_CTL_DBGMOD_WIDTH            EMAC_MTL_DBG_CTL_DBGMOD_WIDTH
3212 #define GMAC_MTL_DBG_CTL_DBGMOD(x)               EMAC_MTL_DBG_CTL_DBGMOD(x)
3213 #define GMAC_MTL_DBG_CTL_BYTEEN_MASK             EMAC_MTL_DBG_CTL_BYTEEN_MASK
3214 #define GMAC_MTL_DBG_CTL_BYTEEN_SHIFT            EMAC_MTL_DBG_CTL_BYTEEN_SHIFT
3215 #define GMAC_MTL_DBG_CTL_BYTEEN_WIDTH            EMAC_MTL_DBG_CTL_BYTEEN_WIDTH
3216 #define GMAC_MTL_DBG_CTL_BYTEEN(x)               EMAC_MTL_DBG_CTL_BYTEEN(x)
3217 #define GMAC_MTL_DBG_CTL_PKTSTATE_MASK           EMAC_MTL_DBG_CTL_PKTSTATE_MASK
3218 #define GMAC_MTL_DBG_CTL_PKTSTATE_SHIFT          EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT
3219 #define GMAC_MTL_DBG_CTL_PKTSTATE_WIDTH          EMAC_MTL_DBG_CTL_PKTSTATE_WIDTH
3220 #define GMAC_MTL_DBG_CTL_PKTSTATE(x)             EMAC_MTL_DBG_CTL_PKTSTATE(x)
3221 #define GMAC_MTL_DBG_CTL_RSTALL_MASK             EMAC_MTL_DBG_CTL_RSTALL_MASK
3222 #define GMAC_MTL_DBG_CTL_RSTALL_SHIFT            EMAC_MTL_DBG_CTL_RSTALL_SHIFT
3223 #define GMAC_MTL_DBG_CTL_RSTALL_WIDTH            EMAC_MTL_DBG_CTL_RSTALL_WIDTH
3224 #define GMAC_MTL_DBG_CTL_RSTALL(x)               EMAC_MTL_DBG_CTL_RSTALL(x)
3225 #define GMAC_MTL_DBG_CTL_RSTSEL_MASK             EMAC_MTL_DBG_CTL_RSTSEL_MASK
3226 #define GMAC_MTL_DBG_CTL_RSTSEL_SHIFT            EMAC_MTL_DBG_CTL_RSTSEL_SHIFT
3227 #define GMAC_MTL_DBG_CTL_RSTSEL_WIDTH            EMAC_MTL_DBG_CTL_RSTSEL_WIDTH
3228 #define GMAC_MTL_DBG_CTL_RSTSEL(x)               EMAC_MTL_DBG_CTL_RSTSEL(x)
3229 #define GMAC_MTL_DBG_CTL_FIFORDEN_MASK           EMAC_MTL_DBG_CTL_FIFORDEN_MASK
3230 #define GMAC_MTL_DBG_CTL_FIFORDEN_SHIFT          EMAC_MTL_DBG_CTL_FIFORDEN_SHIFT
3231 #define GMAC_MTL_DBG_CTL_FIFORDEN_WIDTH          EMAC_MTL_DBG_CTL_FIFORDEN_WIDTH
3232 #define GMAC_MTL_DBG_CTL_FIFORDEN(x)             EMAC_MTL_DBG_CTL_FIFORDEN(x)
3233 #define GMAC_MTL_DBG_CTL_FIFOWREN_MASK           EMAC_MTL_DBG_CTL_FIFOWREN_MASK
3234 #define GMAC_MTL_DBG_CTL_FIFOWREN_SHIFT          EMAC_MTL_DBG_CTL_FIFOWREN_SHIFT
3235 #define GMAC_MTL_DBG_CTL_FIFOWREN_WIDTH          EMAC_MTL_DBG_CTL_FIFOWREN_WIDTH
3236 #define GMAC_MTL_DBG_CTL_FIFOWREN(x)             EMAC_MTL_DBG_CTL_FIFOWREN(x)
3237 #define GMAC_MTL_DBG_CTL_FIFOSEL_MASK            EMAC_MTL_DBG_CTL_FIFOSEL_MASK
3238 #define GMAC_MTL_DBG_CTL_FIFOSEL_SHIFT           EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT
3239 #define GMAC_MTL_DBG_CTL_FIFOSEL_WIDTH           EMAC_MTL_DBG_CTL_FIFOSEL_WIDTH
3240 #define GMAC_MTL_DBG_CTL_FIFOSEL(x)              EMAC_MTL_DBG_CTL_FIFOSEL(x)
3241 #define GMAC_MTL_DBG_CTL_PKTIE_MASK              EMAC_MTL_DBG_CTL_PKTIE_MASK
3242 #define GMAC_MTL_DBG_CTL_PKTIE_SHIFT             EMAC_MTL_DBG_CTL_PKTIE_SHIFT
3243 #define GMAC_MTL_DBG_CTL_PKTIE_WIDTH             EMAC_MTL_DBG_CTL_PKTIE_WIDTH
3244 #define GMAC_MTL_DBG_CTL_PKTIE(x)                EMAC_MTL_DBG_CTL_PKTIE(x)
3245 #define GMAC_MTL_DBG_CTL_STSIE_MASK              EMAC_MTL_DBG_CTL_STSIE_MASK
3246 #define GMAC_MTL_DBG_CTL_STSIE_SHIFT             EMAC_MTL_DBG_CTL_STSIE_SHIFT
3247 #define GMAC_MTL_DBG_CTL_STSIE_WIDTH             EMAC_MTL_DBG_CTL_STSIE_WIDTH
3248 #define GMAC_MTL_DBG_CTL_STSIE(x)                EMAC_MTL_DBG_CTL_STSIE(x)
3249 #define GMAC_MTL_DBG_CTL_EIEE_MASK               EMAC_MTL_DBG_CTL_EIEE_MASK
3250 #define GMAC_MTL_DBG_CTL_EIEE_SHIFT              EMAC_MTL_DBG_CTL_EIEE_SHIFT
3251 #define GMAC_MTL_DBG_CTL_EIEE_WIDTH              EMAC_MTL_DBG_CTL_EIEE_WIDTH
3252 #define GMAC_MTL_DBG_CTL_EIEE(x)                 EMAC_MTL_DBG_CTL_EIEE(x)
3253 #define GMAC_MTL_DBG_CTL_EIEC_MASK               EMAC_MTL_DBG_CTL_EIEC_MASK
3254 #define GMAC_MTL_DBG_CTL_EIEC_SHIFT              EMAC_MTL_DBG_CTL_EIEC_SHIFT
3255 #define GMAC_MTL_DBG_CTL_EIEC_WIDTH              EMAC_MTL_DBG_CTL_EIEC_WIDTH
3256 #define GMAC_MTL_DBG_CTL_EIEC(x)                 EMAC_MTL_DBG_CTL_EIEC(x)
3257 /*! @} */
3258 
3259 /*! @name MTL_DBG_STS -  */
3260 /*! @{ */
3261 #define GMAC_MTL_DBG_STS_FIFOBUSY_MASK           EMAC_MTL_DBG_STS_FIFOBUSY_MASK
3262 #define GMAC_MTL_DBG_STS_FIFOBUSY_SHIFT          EMAC_MTL_DBG_STS_FIFOBUSY_SHIFT
3263 #define GMAC_MTL_DBG_STS_FIFOBUSY_WIDTH          EMAC_MTL_DBG_STS_FIFOBUSY_WIDTH
3264 #define GMAC_MTL_DBG_STS_FIFOBUSY(x)             EMAC_MTL_DBG_STS_FIFOBUSY(x)
3265 #define GMAC_MTL_DBG_STS_PKTSTATE_MASK           EMAC_MTL_DBG_STS_PKTSTATE_MASK
3266 #define GMAC_MTL_DBG_STS_PKTSTATE_SHIFT          EMAC_MTL_DBG_STS_PKTSTATE_SHIFT
3267 #define GMAC_MTL_DBG_STS_PKTSTATE_WIDTH          EMAC_MTL_DBG_STS_PKTSTATE_WIDTH
3268 #define GMAC_MTL_DBG_STS_PKTSTATE(x)             EMAC_MTL_DBG_STS_PKTSTATE(x)
3269 #define GMAC_MTL_DBG_STS_BYTEEN_MASK             EMAC_MTL_DBG_STS_BYTEEN_MASK
3270 #define GMAC_MTL_DBG_STS_BYTEEN_SHIFT            EMAC_MTL_DBG_STS_BYTEEN_SHIFT
3271 #define GMAC_MTL_DBG_STS_BYTEEN_WIDTH            EMAC_MTL_DBG_STS_BYTEEN_WIDTH
3272 #define GMAC_MTL_DBG_STS_BYTEEN(x)               EMAC_MTL_DBG_STS_BYTEEN(x)
3273 #define GMAC_MTL_DBG_STS_PKTI_MASK               EMAC_MTL_DBG_STS_PKTI_MASK
3274 #define GMAC_MTL_DBG_STS_PKTI_SHIFT              EMAC_MTL_DBG_STS_PKTI_SHIFT
3275 #define GMAC_MTL_DBG_STS_PKTI_WIDTH              EMAC_MTL_DBG_STS_PKTI_WIDTH
3276 #define GMAC_MTL_DBG_STS_PKTI(x)                 EMAC_MTL_DBG_STS_PKTI(x)
3277 #define GMAC_MTL_DBG_STS_STSI_MASK               EMAC_MTL_DBG_STS_STSI_MASK
3278 #define GMAC_MTL_DBG_STS_STSI_SHIFT              EMAC_MTL_DBG_STS_STSI_SHIFT
3279 #define GMAC_MTL_DBG_STS_STSI_WIDTH              EMAC_MTL_DBG_STS_STSI_WIDTH
3280 #define GMAC_MTL_DBG_STS_STSI(x)                 EMAC_MTL_DBG_STS_STSI(x)
3281 #define GMAC_MTL_DBG_STS_LOCR_MASK               EMAC_MTL_DBG_STS_LOCR_MASK
3282 #define GMAC_MTL_DBG_STS_LOCR_SHIFT              EMAC_MTL_DBG_STS_LOCR_SHIFT
3283 #define GMAC_MTL_DBG_STS_LOCR_WIDTH              EMAC_MTL_DBG_STS_LOCR_WIDTH
3284 #define GMAC_MTL_DBG_STS_LOCR(x)                 EMAC_MTL_DBG_STS_LOCR(x)
3285 /*! @} */
3286 
3287 /*! @name MTL_FIFO_DEBUG_DATA -  */
3288 /*! @{ */
3289 #define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK   EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK
3290 #define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT  EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT
3291 #define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_WIDTH  EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_WIDTH
3292 #define GMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(x)     EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(x)
3293 /*! @} */
3294 
3295 /*! @name MTL_INTERRUPT_STATUS -  */
3296 /*! @{ */
3297 #define GMAC_MTL_INTERRUPT_STATUS_Q0IS_MASK      EMAC_MTL_INTERRUPT_STATUS_Q0IS_MASK
3298 #define GMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT     EMAC_MTL_INTERRUPT_STATUS_Q0IS_SHIFT
3299 #define GMAC_MTL_INTERRUPT_STATUS_Q0IS_WIDTH     EMAC_MTL_INTERRUPT_STATUS_Q0IS_WIDTH
3300 #define GMAC_MTL_INTERRUPT_STATUS_Q0IS(x)        EMAC_MTL_INTERRUPT_STATUS_Q0IS(x)
3301 #define GMAC_MTL_INTERRUPT_STATUS_Q1IS_MASK      EMAC_MTL_INTERRUPT_STATUS_Q1IS_MASK
3302 #define GMAC_MTL_INTERRUPT_STATUS_Q1IS_SHIFT     EMAC_MTL_INTERRUPT_STATUS_Q1IS_SHIFT
3303 #define GMAC_MTL_INTERRUPT_STATUS_Q1IS_WIDTH     EMAC_MTL_INTERRUPT_STATUS_Q1IS_WIDTH
3304 #define GMAC_MTL_INTERRUPT_STATUS_Q1IS(x)        EMAC_MTL_INTERRUPT_STATUS_Q1IS(x)
3305 #define GMAC_MTL_INTERRUPT_STATUS_DBGIS_MASK     EMAC_MTL_INTERRUPT_STATUS_DBGIS_MASK
3306 #define GMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT    EMAC_MTL_INTERRUPT_STATUS_DBGIS_SHIFT
3307 #define GMAC_MTL_INTERRUPT_STATUS_DBGIS_WIDTH    EMAC_MTL_INTERRUPT_STATUS_DBGIS_WIDTH
3308 #define GMAC_MTL_INTERRUPT_STATUS_DBGIS(x)       EMAC_MTL_INTERRUPT_STATUS_DBGIS(x)
3309 #define GMAC_MTL_INTERRUPT_STATUS_ESTIS_MASK     EMAC_MTL_INTERRUPT_STATUS_ESTIS_MASK
3310 #define GMAC_MTL_INTERRUPT_STATUS_ESTIS_SHIFT    EMAC_MTL_INTERRUPT_STATUS_ESTIS_SHIFT
3311 #define GMAC_MTL_INTERRUPT_STATUS_ESTIS_WIDTH    EMAC_MTL_INTERRUPT_STATUS_ESTIS_WIDTH
3312 #define GMAC_MTL_INTERRUPT_STATUS_ESTIS(x)       EMAC_MTL_INTERRUPT_STATUS_ESTIS(x)
3313 #define GMAC_MTL_INTERRUPT_STATUS_MTLPIS_MASK    EMAC_MTL_INTERRUPT_STATUS_MTLPIS_MASK
3314 #define GMAC_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT   EMAC_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT
3315 #define GMAC_MTL_INTERRUPT_STATUS_MTLPIS_WIDTH   EMAC_MTL_INTERRUPT_STATUS_MTLPIS_WIDTH
3316 #define GMAC_MTL_INTERRUPT_STATUS_MTLPIS(x)      EMAC_MTL_INTERRUPT_STATUS_MTLPIS(x)
3317 /*! @} */
3318 
3319 /*! @name MTL_RXQ_DMA_MAP0 -  */
3320 /*! @{ */
3321 #define GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK      EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK
3322 #define GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT     EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT
3323 #define GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_WIDTH     EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH_WIDTH
3324 #define GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH(x)        EMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH(x)
3325 #define GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK      EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK
3326 #define GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT     EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT
3327 #define GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_WIDTH     EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH_WIDTH
3328 #define GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH(x)        EMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH(x)
3329 #define GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK      EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK
3330 #define GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT     EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT
3331 #define GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_WIDTH     EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH_WIDTH
3332 #define GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH(x)        EMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH(x)
3333 #define GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK      EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK
3334 #define GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT     EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT
3335 #define GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_WIDTH     EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH_WIDTH
3336 #define GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH(x)        EMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH(x)
3337 /*! @} */
3338 
3339 /*! @name MTL_TBS_CTRL -  */
3340 /*! @{ */
3341 #define GMAC_MTL_TBS_CTRL_ESTM_MASK              EMAC_MTL_TBS_CTRL_ESTM_MASK
3342 #define GMAC_MTL_TBS_CTRL_ESTM_SHIFT             EMAC_MTL_TBS_CTRL_ESTM_SHIFT
3343 #define GMAC_MTL_TBS_CTRL_ESTM_WIDTH             EMAC_MTL_TBS_CTRL_ESTM_WIDTH
3344 #define GMAC_MTL_TBS_CTRL_ESTM(x)                EMAC_MTL_TBS_CTRL_ESTM(x)
3345 #define GMAC_MTL_TBS_CTRL_LEOV_MASK              EMAC_MTL_TBS_CTRL_LEOV_MASK
3346 #define GMAC_MTL_TBS_CTRL_LEOV_SHIFT             EMAC_MTL_TBS_CTRL_LEOV_SHIFT
3347 #define GMAC_MTL_TBS_CTRL_LEOV_WIDTH             EMAC_MTL_TBS_CTRL_LEOV_WIDTH
3348 #define GMAC_MTL_TBS_CTRL_LEOV(x)                EMAC_MTL_TBS_CTRL_LEOV(x)
3349 #define GMAC_MTL_TBS_CTRL_LEGOS_MASK             EMAC_MTL_TBS_CTRL_LEGOS_MASK
3350 #define GMAC_MTL_TBS_CTRL_LEGOS_SHIFT            EMAC_MTL_TBS_CTRL_LEGOS_SHIFT
3351 #define GMAC_MTL_TBS_CTRL_LEGOS_WIDTH            EMAC_MTL_TBS_CTRL_LEGOS_WIDTH
3352 #define GMAC_MTL_TBS_CTRL_LEGOS(x)               EMAC_MTL_TBS_CTRL_LEGOS(x)
3353 #define GMAC_MTL_TBS_CTRL_LEOS_MASK              EMAC_MTL_TBS_CTRL_LEOS_MASK
3354 #define GMAC_MTL_TBS_CTRL_LEOS_SHIFT             EMAC_MTL_TBS_CTRL_LEOS_SHIFT
3355 #define GMAC_MTL_TBS_CTRL_LEOS_WIDTH             EMAC_MTL_TBS_CTRL_LEOS_WIDTH
3356 #define GMAC_MTL_TBS_CTRL_LEOS(x)                EMAC_MTL_TBS_CTRL_LEOS(x)
3357 /*! @} */
3358 
3359 /*! @name MTL_EST_CONTROL -  */
3360 /*! @{ */
3361 #define GMAC_MTL_EST_CONTROL_EEST_MASK           EMAC_MTL_EST_CONTROL_EEST_MASK
3362 #define GMAC_MTL_EST_CONTROL_EEST_SHIFT          EMAC_MTL_EST_CONTROL_EEST_SHIFT
3363 #define GMAC_MTL_EST_CONTROL_EEST_WIDTH          EMAC_MTL_EST_CONTROL_EEST_WIDTH
3364 #define GMAC_MTL_EST_CONTROL_EEST(x)             EMAC_MTL_EST_CONTROL_EEST(x)
3365 #define GMAC_MTL_EST_CONTROL_SSWL_MASK           EMAC_MTL_EST_CONTROL_SSWL_MASK
3366 #define GMAC_MTL_EST_CONTROL_SSWL_SHIFT          EMAC_MTL_EST_CONTROL_SSWL_SHIFT
3367 #define GMAC_MTL_EST_CONTROL_SSWL_WIDTH          EMAC_MTL_EST_CONTROL_SSWL_WIDTH
3368 #define GMAC_MTL_EST_CONTROL_SSWL(x)             EMAC_MTL_EST_CONTROL_SSWL(x)
3369 #define GMAC_MTL_EST_CONTROL_DDBF_MASK           EMAC_MTL_EST_CONTROL_DDBF_MASK
3370 #define GMAC_MTL_EST_CONTROL_DDBF_SHIFT          EMAC_MTL_EST_CONTROL_DDBF_SHIFT
3371 #define GMAC_MTL_EST_CONTROL_DDBF_WIDTH          EMAC_MTL_EST_CONTROL_DDBF_WIDTH
3372 #define GMAC_MTL_EST_CONTROL_DDBF(x)             EMAC_MTL_EST_CONTROL_DDBF(x)
3373 #define GMAC_MTL_EST_CONTROL_DFBS_MASK           EMAC_MTL_EST_CONTROL_DFBS_MASK
3374 #define GMAC_MTL_EST_CONTROL_DFBS_SHIFT          EMAC_MTL_EST_CONTROL_DFBS_SHIFT
3375 #define GMAC_MTL_EST_CONTROL_DFBS_WIDTH          EMAC_MTL_EST_CONTROL_DFBS_WIDTH
3376 #define GMAC_MTL_EST_CONTROL_DFBS(x)             EMAC_MTL_EST_CONTROL_DFBS(x)
3377 #define GMAC_MTL_EST_CONTROL_LCSE_MASK           EMAC_MTL_EST_CONTROL_LCSE_MASK
3378 #define GMAC_MTL_EST_CONTROL_LCSE_SHIFT          EMAC_MTL_EST_CONTROL_LCSE_SHIFT
3379 #define GMAC_MTL_EST_CONTROL_LCSE_WIDTH          EMAC_MTL_EST_CONTROL_LCSE_WIDTH
3380 #define GMAC_MTL_EST_CONTROL_LCSE(x)             EMAC_MTL_EST_CONTROL_LCSE(x)
3381 #define GMAC_MTL_EST_CONTROL_TILS_MASK           EMAC_MTL_EST_CONTROL_TILS_MASK
3382 #define GMAC_MTL_EST_CONTROL_TILS_SHIFT          EMAC_MTL_EST_CONTROL_TILS_SHIFT
3383 #define GMAC_MTL_EST_CONTROL_TILS_WIDTH          EMAC_MTL_EST_CONTROL_TILS_WIDTH
3384 #define GMAC_MTL_EST_CONTROL_TILS(x)             EMAC_MTL_EST_CONTROL_TILS(x)
3385 #define GMAC_MTL_EST_CONTROL_CTOV_MASK           EMAC_MTL_EST_CONTROL_CTOV_MASK
3386 #define GMAC_MTL_EST_CONTROL_CTOV_SHIFT          EMAC_MTL_EST_CONTROL_CTOV_SHIFT
3387 #define GMAC_MTL_EST_CONTROL_CTOV_WIDTH          EMAC_MTL_EST_CONTROL_CTOV_WIDTH
3388 #define GMAC_MTL_EST_CONTROL_CTOV(x)             EMAC_MTL_EST_CONTROL_CTOV(x)
3389 #define GMAC_MTL_EST_CONTROL_PTOV_MASK           EMAC_MTL_EST_CONTROL_PTOV_MASK
3390 #define GMAC_MTL_EST_CONTROL_PTOV_SHIFT          EMAC_MTL_EST_CONTROL_PTOV_SHIFT
3391 #define GMAC_MTL_EST_CONTROL_PTOV_WIDTH          EMAC_MTL_EST_CONTROL_PTOV_WIDTH
3392 #define GMAC_MTL_EST_CONTROL_PTOV(x)             EMAC_MTL_EST_CONTROL_PTOV(x)
3393 /*! @} */
3394 
3395 /*! @name MTL_EST_STATUS -  */
3396 /*! @{ */
3397 #define GMAC_MTL_EST_STATUS_SWLC_MASK            EMAC_MTL_EST_STATUS_SWLC_MASK
3398 #define GMAC_MTL_EST_STATUS_SWLC_SHIFT           EMAC_MTL_EST_STATUS_SWLC_SHIFT
3399 #define GMAC_MTL_EST_STATUS_SWLC_WIDTH           EMAC_MTL_EST_STATUS_SWLC_WIDTH
3400 #define GMAC_MTL_EST_STATUS_SWLC(x)              EMAC_MTL_EST_STATUS_SWLC(x)
3401 #define GMAC_MTL_EST_STATUS_BTRE_MASK            EMAC_MTL_EST_STATUS_BTRE_MASK
3402 #define GMAC_MTL_EST_STATUS_BTRE_SHIFT           EMAC_MTL_EST_STATUS_BTRE_SHIFT
3403 #define GMAC_MTL_EST_STATUS_BTRE_WIDTH           EMAC_MTL_EST_STATUS_BTRE_WIDTH
3404 #define GMAC_MTL_EST_STATUS_BTRE(x)              EMAC_MTL_EST_STATUS_BTRE(x)
3405 #define GMAC_MTL_EST_STATUS_HLBF_MASK            EMAC_MTL_EST_STATUS_HLBF_MASK
3406 #define GMAC_MTL_EST_STATUS_HLBF_SHIFT           EMAC_MTL_EST_STATUS_HLBF_SHIFT
3407 #define GMAC_MTL_EST_STATUS_HLBF_WIDTH           EMAC_MTL_EST_STATUS_HLBF_WIDTH
3408 #define GMAC_MTL_EST_STATUS_HLBF(x)              EMAC_MTL_EST_STATUS_HLBF(x)
3409 #define GMAC_MTL_EST_STATUS_HLBS_MASK            EMAC_MTL_EST_STATUS_HLBS_MASK
3410 #define GMAC_MTL_EST_STATUS_HLBS_SHIFT           EMAC_MTL_EST_STATUS_HLBS_SHIFT
3411 #define GMAC_MTL_EST_STATUS_HLBS_WIDTH           EMAC_MTL_EST_STATUS_HLBS_WIDTH
3412 #define GMAC_MTL_EST_STATUS_HLBS(x)              EMAC_MTL_EST_STATUS_HLBS(x)
3413 #define GMAC_MTL_EST_STATUS_CGCE_MASK            EMAC_MTL_EST_STATUS_CGCE_MASK
3414 #define GMAC_MTL_EST_STATUS_CGCE_SHIFT           EMAC_MTL_EST_STATUS_CGCE_SHIFT
3415 #define GMAC_MTL_EST_STATUS_CGCE_WIDTH           EMAC_MTL_EST_STATUS_CGCE_WIDTH
3416 #define GMAC_MTL_EST_STATUS_CGCE(x)              EMAC_MTL_EST_STATUS_CGCE(x)
3417 #define GMAC_MTL_EST_STATUS_SWOL_MASK            EMAC_MTL_EST_STATUS_SWOL_MASK
3418 #define GMAC_MTL_EST_STATUS_SWOL_SHIFT           EMAC_MTL_EST_STATUS_SWOL_SHIFT
3419 #define GMAC_MTL_EST_STATUS_SWOL_WIDTH           EMAC_MTL_EST_STATUS_SWOL_WIDTH
3420 #define GMAC_MTL_EST_STATUS_SWOL(x)              EMAC_MTL_EST_STATUS_SWOL(x)
3421 #define GMAC_MTL_EST_STATUS_BTRL_MASK            EMAC_MTL_EST_STATUS_BTRL_MASK
3422 #define GMAC_MTL_EST_STATUS_BTRL_SHIFT           EMAC_MTL_EST_STATUS_BTRL_SHIFT
3423 #define GMAC_MTL_EST_STATUS_BTRL_WIDTH           EMAC_MTL_EST_STATUS_BTRL_WIDTH
3424 #define GMAC_MTL_EST_STATUS_BTRL(x)              EMAC_MTL_EST_STATUS_BTRL(x)
3425 #define GMAC_MTL_EST_STATUS_CGSN_MASK            EMAC_MTL_EST_STATUS_CGSN_MASK
3426 #define GMAC_MTL_EST_STATUS_CGSN_SHIFT           EMAC_MTL_EST_STATUS_CGSN_SHIFT
3427 #define GMAC_MTL_EST_STATUS_CGSN_WIDTH           EMAC_MTL_EST_STATUS_CGSN_WIDTH
3428 #define GMAC_MTL_EST_STATUS_CGSN(x)              EMAC_MTL_EST_STATUS_CGSN(x)
3429 /*! @} */
3430 
3431 /*! @name MTL_EST_SCH_ERROR -  */
3432 /*! @{ */
3433 #define GMAC_MTL_EST_SCH_ERROR_SEQN_MASK         EMAC_MTL_EST_SCH_ERROR_SEQN_MASK
3434 #define GMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT        EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT
3435 #define GMAC_MTL_EST_SCH_ERROR_SEQN_WIDTH        EMAC_MTL_EST_SCH_ERROR_SEQN_WIDTH
3436 #define GMAC_MTL_EST_SCH_ERROR_SEQN(x)           EMAC_MTL_EST_SCH_ERROR_SEQN(x)
3437 /*! @} */
3438 
3439 /*! @name MTL_EST_FRM_SIZE_ERROR -  */
3440 /*! @{ */
3441 #define GMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK    EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK
3442 #define GMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT   EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT
3443 #define GMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_WIDTH   EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_WIDTH
3444 #define GMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(x)      EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(x)
3445 /*! @} */
3446 
3447 /*! @name MTL_EST_FRM_SIZE_CAPTURE -  */
3448 /*! @{ */
3449 #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK  EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK
3450 #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT
3451 #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_WIDTH EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_WIDTH
3452 #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x)    EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x)
3453 #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK  EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK
3454 #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT
3455 #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_WIDTH EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_WIDTH
3456 #define GMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x)    EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x)
3457 /*! @} */
3458 
3459 /*! @name MTL_EST_INTR_ENABLE -  */
3460 /*! @{ */
3461 #define GMAC_MTL_EST_INTR_ENABLE_IECC_MASK       EMAC_MTL_EST_INTR_ENABLE_IECC_MASK
3462 #define GMAC_MTL_EST_INTR_ENABLE_IECC_SHIFT      EMAC_MTL_EST_INTR_ENABLE_IECC_SHIFT
3463 #define GMAC_MTL_EST_INTR_ENABLE_IECC_WIDTH      EMAC_MTL_EST_INTR_ENABLE_IECC_WIDTH
3464 #define GMAC_MTL_EST_INTR_ENABLE_IECC(x)         EMAC_MTL_EST_INTR_ENABLE_IECC(x)
3465 #define GMAC_MTL_EST_INTR_ENABLE_IEBE_MASK       EMAC_MTL_EST_INTR_ENABLE_IEBE_MASK
3466 #define GMAC_MTL_EST_INTR_ENABLE_IEBE_SHIFT      EMAC_MTL_EST_INTR_ENABLE_IEBE_SHIFT
3467 #define GMAC_MTL_EST_INTR_ENABLE_IEBE_WIDTH      EMAC_MTL_EST_INTR_ENABLE_IEBE_WIDTH
3468 #define GMAC_MTL_EST_INTR_ENABLE_IEBE(x)         EMAC_MTL_EST_INTR_ENABLE_IEBE(x)
3469 #define GMAC_MTL_EST_INTR_ENABLE_IEHF_MASK       EMAC_MTL_EST_INTR_ENABLE_IEHF_MASK
3470 #define GMAC_MTL_EST_INTR_ENABLE_IEHF_SHIFT      EMAC_MTL_EST_INTR_ENABLE_IEHF_SHIFT
3471 #define GMAC_MTL_EST_INTR_ENABLE_IEHF_WIDTH      EMAC_MTL_EST_INTR_ENABLE_IEHF_WIDTH
3472 #define GMAC_MTL_EST_INTR_ENABLE_IEHF(x)         EMAC_MTL_EST_INTR_ENABLE_IEHF(x)
3473 #define GMAC_MTL_EST_INTR_ENABLE_IEHS_MASK       EMAC_MTL_EST_INTR_ENABLE_IEHS_MASK
3474 #define GMAC_MTL_EST_INTR_ENABLE_IEHS_SHIFT      EMAC_MTL_EST_INTR_ENABLE_IEHS_SHIFT
3475 #define GMAC_MTL_EST_INTR_ENABLE_IEHS_WIDTH      EMAC_MTL_EST_INTR_ENABLE_IEHS_WIDTH
3476 #define GMAC_MTL_EST_INTR_ENABLE_IEHS(x)         EMAC_MTL_EST_INTR_ENABLE_IEHS(x)
3477 #define GMAC_MTL_EST_INTR_ENABLE_CGCE_MASK       EMAC_MTL_EST_INTR_ENABLE_CGCE_MASK
3478 #define GMAC_MTL_EST_INTR_ENABLE_CGCE_SHIFT      EMAC_MTL_EST_INTR_ENABLE_CGCE_SHIFT
3479 #define GMAC_MTL_EST_INTR_ENABLE_CGCE_WIDTH      EMAC_MTL_EST_INTR_ENABLE_CGCE_WIDTH
3480 #define GMAC_MTL_EST_INTR_ENABLE_CGCE(x)         EMAC_MTL_EST_INTR_ENABLE_CGCE(x)
3481 /*! @} */
3482 
3483 /*! @name MTL_EST_GCL_CONTROL -  */
3484 /*! @{ */
3485 #define GMAC_MTL_EST_GCL_CONTROL_SRWO_MASK       EMAC_MTL_EST_GCL_CONTROL_SRWO_MASK
3486 #define GMAC_MTL_EST_GCL_CONTROL_SRWO_SHIFT      EMAC_MTL_EST_GCL_CONTROL_SRWO_SHIFT
3487 #define GMAC_MTL_EST_GCL_CONTROL_SRWO_WIDTH      EMAC_MTL_EST_GCL_CONTROL_SRWO_WIDTH
3488 #define GMAC_MTL_EST_GCL_CONTROL_SRWO(x)         EMAC_MTL_EST_GCL_CONTROL_SRWO(x)
3489 #define GMAC_MTL_EST_GCL_CONTROL_R1W0_MASK       EMAC_MTL_EST_GCL_CONTROL_R1W0_MASK
3490 #define GMAC_MTL_EST_GCL_CONTROL_R1W0_SHIFT      EMAC_MTL_EST_GCL_CONTROL_R1W0_SHIFT
3491 #define GMAC_MTL_EST_GCL_CONTROL_R1W0_WIDTH      EMAC_MTL_EST_GCL_CONTROL_R1W0_WIDTH
3492 #define GMAC_MTL_EST_GCL_CONTROL_R1W0(x)         EMAC_MTL_EST_GCL_CONTROL_R1W0(x)
3493 #define GMAC_MTL_EST_GCL_CONTROL_GCRR_MASK       EMAC_MTL_EST_GCL_CONTROL_GCRR_MASK
3494 #define GMAC_MTL_EST_GCL_CONTROL_GCRR_SHIFT      EMAC_MTL_EST_GCL_CONTROL_GCRR_SHIFT
3495 #define GMAC_MTL_EST_GCL_CONTROL_GCRR_WIDTH      EMAC_MTL_EST_GCL_CONTROL_GCRR_WIDTH
3496 #define GMAC_MTL_EST_GCL_CONTROL_GCRR(x)         EMAC_MTL_EST_GCL_CONTROL_GCRR(x)
3497 #define GMAC_MTL_EST_GCL_CONTROL_DBGM_MASK       EMAC_MTL_EST_GCL_CONTROL_DBGM_MASK
3498 #define GMAC_MTL_EST_GCL_CONTROL_DBGM_SHIFT      EMAC_MTL_EST_GCL_CONTROL_DBGM_SHIFT
3499 #define GMAC_MTL_EST_GCL_CONTROL_DBGM_WIDTH      EMAC_MTL_EST_GCL_CONTROL_DBGM_WIDTH
3500 #define GMAC_MTL_EST_GCL_CONTROL_DBGM(x)         EMAC_MTL_EST_GCL_CONTROL_DBGM(x)
3501 #define GMAC_MTL_EST_GCL_CONTROL_DBGB_MASK       EMAC_MTL_EST_GCL_CONTROL_DBGB_MASK
3502 #define GMAC_MTL_EST_GCL_CONTROL_DBGB_SHIFT      EMAC_MTL_EST_GCL_CONTROL_DBGB_SHIFT
3503 #define GMAC_MTL_EST_GCL_CONTROL_DBGB_WIDTH      EMAC_MTL_EST_GCL_CONTROL_DBGB_WIDTH
3504 #define GMAC_MTL_EST_GCL_CONTROL_DBGB(x)         EMAC_MTL_EST_GCL_CONTROL_DBGB(x)
3505 #define GMAC_MTL_EST_GCL_CONTROL_ADDR_MASK       EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK
3506 #define GMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT      EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT
3507 #define GMAC_MTL_EST_GCL_CONTROL_ADDR_WIDTH      EMAC_MTL_EST_GCL_CONTROL_ADDR_WIDTH
3508 #define GMAC_MTL_EST_GCL_CONTROL_ADDR(x)         EMAC_MTL_EST_GCL_CONTROL_ADDR(x)
3509 #define GMAC_MTL_EST_GCL_CONTROL_ERR0_MASK       EMAC_MTL_EST_GCL_CONTROL_ERR0_MASK
3510 #define GMAC_MTL_EST_GCL_CONTROL_ERR0_SHIFT      EMAC_MTL_EST_GCL_CONTROL_ERR0_SHIFT
3511 #define GMAC_MTL_EST_GCL_CONTROL_ERR0_WIDTH      EMAC_MTL_EST_GCL_CONTROL_ERR0_WIDTH
3512 #define GMAC_MTL_EST_GCL_CONTROL_ERR0(x)         EMAC_MTL_EST_GCL_CONTROL_ERR0(x)
3513 #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEE_MASK    EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_MASK
3514 #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT   EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT
3515 #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEE_WIDTH   EMAC_MTL_EST_GCL_CONTROL_ESTEIEE_WIDTH
3516 #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEE(x)      EMAC_MTL_EST_GCL_CONTROL_ESTEIEE(x)
3517 #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK    EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK
3518 #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT   EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT
3519 #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEC_WIDTH   EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_WIDTH
3520 #define GMAC_MTL_EST_GCL_CONTROL_ESTEIEC(x)      EMAC_MTL_EST_GCL_CONTROL_ESTEIEC(x)
3521 /*! @} */
3522 
3523 /*! @name MTL_EST_GCL_DATA -  */
3524 /*! @{ */
3525 #define GMAC_MTL_EST_GCL_DATA_GCD_MASK           EMAC_MTL_EST_GCL_DATA_GCD_MASK
3526 #define GMAC_MTL_EST_GCL_DATA_GCD_SHIFT          EMAC_MTL_EST_GCL_DATA_GCD_SHIFT
3527 #define GMAC_MTL_EST_GCL_DATA_GCD_WIDTH          EMAC_MTL_EST_GCL_DATA_GCD_WIDTH
3528 #define GMAC_MTL_EST_GCL_DATA_GCD(x)             EMAC_MTL_EST_GCL_DATA_GCD(x)
3529 /*! @} */
3530 
3531 /*! @name MTL_FPE_CTRL_STS -  */
3532 /*! @{ */
3533 #define GMAC_MTL_FPE_CTRL_STS_AFSZ_MASK          EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK
3534 #define GMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT         EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT
3535 #define GMAC_MTL_FPE_CTRL_STS_AFSZ_WIDTH         EMAC_MTL_FPE_CTRL_STS_AFSZ_WIDTH
3536 #define GMAC_MTL_FPE_CTRL_STS_AFSZ(x)            EMAC_MTL_FPE_CTRL_STS_AFSZ(x)
3537 #define GMAC_MTL_FPE_CTRL_STS_PEC_MASK           EMAC_MTL_FPE_CTRL_STS_PEC_MASK
3538 #define GMAC_MTL_FPE_CTRL_STS_PEC_SHIFT          EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT
3539 #define GMAC_MTL_FPE_CTRL_STS_PEC_WIDTH          EMAC_MTL_FPE_CTRL_STS_PEC_WIDTH
3540 #define GMAC_MTL_FPE_CTRL_STS_PEC(x)             EMAC_MTL_FPE_CTRL_STS_PEC(x)
3541 #define GMAC_MTL_FPE_CTRL_STS_HRS_MASK           EMAC_MTL_FPE_CTRL_STS_HRS_MASK
3542 #define GMAC_MTL_FPE_CTRL_STS_HRS_SHIFT          EMAC_MTL_FPE_CTRL_STS_HRS_SHIFT
3543 #define GMAC_MTL_FPE_CTRL_STS_HRS_WIDTH          EMAC_MTL_FPE_CTRL_STS_HRS_WIDTH
3544 #define GMAC_MTL_FPE_CTRL_STS_HRS(x)             EMAC_MTL_FPE_CTRL_STS_HRS(x)
3545 /*! @} */
3546 
3547 /*! @name MTL_FPE_ADVANCE -  */
3548 /*! @{ */
3549 #define GMAC_MTL_FPE_ADVANCE_HADV_MASK           EMAC_MTL_FPE_ADVANCE_HADV_MASK
3550 #define GMAC_MTL_FPE_ADVANCE_HADV_SHIFT          EMAC_MTL_FPE_ADVANCE_HADV_SHIFT
3551 #define GMAC_MTL_FPE_ADVANCE_HADV_WIDTH          EMAC_MTL_FPE_ADVANCE_HADV_WIDTH
3552 #define GMAC_MTL_FPE_ADVANCE_HADV(x)             EMAC_MTL_FPE_ADVANCE_HADV(x)
3553 #define GMAC_MTL_FPE_ADVANCE_RADV_MASK           EMAC_MTL_FPE_ADVANCE_RADV_MASK
3554 #define GMAC_MTL_FPE_ADVANCE_RADV_SHIFT          EMAC_MTL_FPE_ADVANCE_RADV_SHIFT
3555 #define GMAC_MTL_FPE_ADVANCE_RADV_WIDTH          EMAC_MTL_FPE_ADVANCE_RADV_WIDTH
3556 #define GMAC_MTL_FPE_ADVANCE_RADV(x)             EMAC_MTL_FPE_ADVANCE_RADV(x)
3557 /*! @} */
3558 
3559 /*! @name MTL_RXP_CONTROL_STATUS -  */
3560 /*! @{ */
3561 #define GMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK     EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK
3562 #define GMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT    EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT
3563 #define GMAC_MTL_RXP_CONTROL_STATUS_NVE_WIDTH    EMAC_MTL_RXP_CONTROL_STATUS_NVE_WIDTH
3564 #define GMAC_MTL_RXP_CONTROL_STATUS_NVE(x)       EMAC_MTL_RXP_CONTROL_STATUS_NVE(x)
3565 #define GMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_MASK EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_MASK
3566 #define GMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_SHIFT EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_SHIFT
3567 #define GMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_WIDTH EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1_WIDTH
3568 #define GMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1(x)  EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1(x)
3569 #define GMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK     EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK
3570 #define GMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT    EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT
3571 #define GMAC_MTL_RXP_CONTROL_STATUS_NPE_WIDTH    EMAC_MTL_RXP_CONTROL_STATUS_NPE_WIDTH
3572 #define GMAC_MTL_RXP_CONTROL_STATUS_NPE(x)       EMAC_MTL_RXP_CONTROL_STATUS_NPE(x)
3573 #define GMAC_MTL_RXP_CONTROL_STATUS_RXPI_MASK    EMAC_MTL_RXP_CONTROL_STATUS_RXPI_MASK
3574 #define GMAC_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT   EMAC_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT
3575 #define GMAC_MTL_RXP_CONTROL_STATUS_RXPI_WIDTH   EMAC_MTL_RXP_CONTROL_STATUS_RXPI_WIDTH
3576 #define GMAC_MTL_RXP_CONTROL_STATUS_RXPI(x)      EMAC_MTL_RXP_CONTROL_STATUS_RXPI(x)
3577 /*! @} */
3578 
3579 /*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS -  */
3580 /*! @{ */
3581 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK
3582 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT
3583 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_WIDTH
3584 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x)
3585 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK
3586 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT
3587 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_WIDTH
3588 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x)
3589 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK
3590 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT
3591 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_WIDTH
3592 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x)
3593 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK
3594 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT
3595 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_WIDTH
3596 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x)
3597 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK
3598 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT
3599 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_WIDTH
3600 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x)
3601 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK
3602 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT
3603 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_WIDTH
3604 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x)
3605 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK
3606 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT
3607 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_WIDTH
3608 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x)
3609 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK
3610 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT
3611 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_WIDTH EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_WIDTH
3612 #define GMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x)
3613 /*! @} */
3614 
3615 /*! @name MTL_RXP_DROP_CNT -  */
3616 /*! @{ */
3617 #define GMAC_MTL_RXP_DROP_CNT_RXPDC_MASK         EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK
3618 #define GMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT        EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT
3619 #define GMAC_MTL_RXP_DROP_CNT_RXPDC_WIDTH        EMAC_MTL_RXP_DROP_CNT_RXPDC_WIDTH
3620 #define GMAC_MTL_RXP_DROP_CNT_RXPDC(x)           EMAC_MTL_RXP_DROP_CNT_RXPDC(x)
3621 #define GMAC_MTL_RXP_DROP_CNT_RXPDCOVF_MASK      EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_MASK
3622 #define GMAC_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT     EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT
3623 #define GMAC_MTL_RXP_DROP_CNT_RXPDCOVF_WIDTH     EMAC_MTL_RXP_DROP_CNT_RXPDCOVF_WIDTH
3624 #define GMAC_MTL_RXP_DROP_CNT_RXPDCOVF(x)        EMAC_MTL_RXP_DROP_CNT_RXPDCOVF(x)
3625 /*! @} */
3626 
3627 /*! @name MTL_RXP_ERROR_CNT -  */
3628 /*! @{ */
3629 #define GMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK        EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK
3630 #define GMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT       EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT
3631 #define GMAC_MTL_RXP_ERROR_CNT_RXPEC_WIDTH       EMAC_MTL_RXP_ERROR_CNT_RXPEC_WIDTH
3632 #define GMAC_MTL_RXP_ERROR_CNT_RXPEC(x)          EMAC_MTL_RXP_ERROR_CNT_RXPEC(x)
3633 #define GMAC_MTL_RXP_ERROR_CNT_RXPECOVF_MASK     EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_MASK
3634 #define GMAC_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT    EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT
3635 #define GMAC_MTL_RXP_ERROR_CNT_RXPECOVF_WIDTH    EMAC_MTL_RXP_ERROR_CNT_RXPECOVF_WIDTH
3636 #define GMAC_MTL_RXP_ERROR_CNT_RXPECOVF(x)       EMAC_MTL_RXP_ERROR_CNT_RXPECOVF(x)
3637 /*! @} */
3638 
3639 /*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS -  */
3640 /*! @{ */
3641 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK
3642 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT
3643 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_WIDTH
3644 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x)
3645 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK
3646 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT
3647 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_WIDTH
3648 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x)
3649 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_MASK
3650 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_SHIFT
3651 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE_WIDTH
3652 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE(x)
3653 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK
3654 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT
3655 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_WIDTH
3656 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(x)
3657 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK
3658 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT
3659 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_WIDTH
3660 #define GMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x)
3661 /*! @} */
3662 
3663 /*! @name MTL_RXP_INDIRECT_ACC_DATA -  */
3664 /*! @{ */
3665 #define GMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK
3666 #define GMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT
3667 #define GMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_WIDTH EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_WIDTH
3668 #define GMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(x)   EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(x)
3669 /*! @} */
3670 
3671 /*! @name MTL_ECC_CONTROL -  */
3672 /*! @{ */
3673 #define GMAC_MTL_ECC_CONTROL_MTXEE_MASK          EMAC_MTL_ECC_CONTROL_MTXEE_MASK
3674 #define GMAC_MTL_ECC_CONTROL_MTXEE_SHIFT         EMAC_MTL_ECC_CONTROL_MTXEE_SHIFT
3675 #define GMAC_MTL_ECC_CONTROL_MTXEE_WIDTH         EMAC_MTL_ECC_CONTROL_MTXEE_WIDTH
3676 #define GMAC_MTL_ECC_CONTROL_MTXEE(x)            EMAC_MTL_ECC_CONTROL_MTXEE(x)
3677 #define GMAC_MTL_ECC_CONTROL_MRXEE_MASK          EMAC_MTL_ECC_CONTROL_MRXEE_MASK
3678 #define GMAC_MTL_ECC_CONTROL_MRXEE_SHIFT         EMAC_MTL_ECC_CONTROL_MRXEE_SHIFT
3679 #define GMAC_MTL_ECC_CONTROL_MRXEE_WIDTH         EMAC_MTL_ECC_CONTROL_MRXEE_WIDTH
3680 #define GMAC_MTL_ECC_CONTROL_MRXEE(x)            EMAC_MTL_ECC_CONTROL_MRXEE(x)
3681 #define GMAC_MTL_ECC_CONTROL_MESTEE_MASK         EMAC_MTL_ECC_CONTROL_MESTEE_MASK
3682 #define GMAC_MTL_ECC_CONTROL_MESTEE_SHIFT        EMAC_MTL_ECC_CONTROL_MESTEE_SHIFT
3683 #define GMAC_MTL_ECC_CONTROL_MESTEE_WIDTH        EMAC_MTL_ECC_CONTROL_MESTEE_WIDTH
3684 #define GMAC_MTL_ECC_CONTROL_MESTEE(x)           EMAC_MTL_ECC_CONTROL_MESTEE(x)
3685 #define GMAC_MTL_ECC_CONTROL_MRXPEE_MASK         EMAC_MTL_ECC_CONTROL_MRXPEE_MASK
3686 #define GMAC_MTL_ECC_CONTROL_MRXPEE_SHIFT        EMAC_MTL_ECC_CONTROL_MRXPEE_SHIFT
3687 #define GMAC_MTL_ECC_CONTROL_MRXPEE_WIDTH        EMAC_MTL_ECC_CONTROL_MRXPEE_WIDTH
3688 #define GMAC_MTL_ECC_CONTROL_MRXPEE(x)           EMAC_MTL_ECC_CONTROL_MRXPEE(x)
3689 #define GMAC_MTL_ECC_CONTROL_MEEAO_MASK          EMAC_MTL_ECC_CONTROL_MEEAO_MASK
3690 #define GMAC_MTL_ECC_CONTROL_MEEAO_SHIFT         EMAC_MTL_ECC_CONTROL_MEEAO_SHIFT
3691 #define GMAC_MTL_ECC_CONTROL_MEEAO_WIDTH         EMAC_MTL_ECC_CONTROL_MEEAO_WIDTH
3692 #define GMAC_MTL_ECC_CONTROL_MEEAO(x)            EMAC_MTL_ECC_CONTROL_MEEAO(x)
3693 /*! @} */
3694 
3695 /*! @name MTL_SAFETY_INTERRUPT_STATUS -  */
3696 /*! @{ */
3697 #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_MASK EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_MASK
3698 #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_SHIFT EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_SHIFT
3699 #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_WIDTH EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS_WIDTH
3700 #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS(x) EMAC_MTL_SAFETY_INTERRUPT_STATUS_MECIS(x)
3701 #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_MASK EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_MASK
3702 #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_SHIFT EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_SHIFT
3703 #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_WIDTH EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS_WIDTH
3704 #define GMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS(x) EMAC_MTL_SAFETY_INTERRUPT_STATUS_MEUIS(x)
3705 /*! @} */
3706 
3707 /*! @name MTL_ECC_INTERRUPT_ENABLE -  */
3708 /*! @{ */
3709 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_MASK EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_MASK
3710 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_SHIFT EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_SHIFT
3711 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_WIDTH EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE_WIDTH
3712 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE(x)  EMAC_MTL_ECC_INTERRUPT_ENABLE_TXCEIE(x)
3713 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_MASK EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_MASK
3714 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_SHIFT EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_SHIFT
3715 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_WIDTH EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE_WIDTH
3716 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE(x)  EMAC_MTL_ECC_INTERRUPT_ENABLE_RXCEIE(x)
3717 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_MASK EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_MASK
3718 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_SHIFT EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_SHIFT
3719 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_WIDTH EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE_WIDTH
3720 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE(x)   EMAC_MTL_ECC_INTERRUPT_ENABLE_ECEIE(x)
3721 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_MASK EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_MASK
3722 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_SHIFT EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_SHIFT
3723 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_WIDTH EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE_WIDTH
3724 #define GMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE(x)  EMAC_MTL_ECC_INTERRUPT_ENABLE_RPCEIE(x)
3725 /*! @} */
3726 
3727 /*! @name MTL_ECC_INTERRUPT_STATUS -  */
3728 /*! @{ */
3729 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_MASK
3730 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_SHIFT
3731 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES_WIDTH
3732 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXCES(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_TXCES(x)
3733 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_MASK
3734 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_SHIFT
3735 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_WIDTH
3736 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS(x)
3737 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_MASK
3738 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_SHIFT
3739 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_WIDTH
3740 #define GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_TXUES(x)
3741 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_MASK
3742 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_SHIFT
3743 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES_WIDTH
3744 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXCES(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_RXCES(x)
3745 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_MASK
3746 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_SHIFT
3747 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_WIDTH
3748 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS(x)
3749 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_MASK
3750 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_SHIFT
3751 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_WIDTH
3752 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_RXUES(x)
3753 #define GMAC_MTL_ECC_INTERRUPT_STATUS_ECES_MASK  EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_MASK
3754 #define GMAC_MTL_ECC_INTERRUPT_STATUS_ECES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_SHIFT
3755 #define GMAC_MTL_ECC_INTERRUPT_STATUS_ECES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_ECES_WIDTH
3756 #define GMAC_MTL_ECC_INTERRUPT_STATUS_ECES(x)    EMAC_MTL_ECC_INTERRUPT_STATUS_ECES(x)
3757 #define GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_MASK  EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_MASK
3758 #define GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_SHIFT
3759 #define GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_WIDTH
3760 #define GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS(x)    EMAC_MTL_ECC_INTERRUPT_STATUS_EAMS(x)
3761 #define GMAC_MTL_ECC_INTERRUPT_STATUS_EUES_MASK  EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_MASK
3762 #define GMAC_MTL_ECC_INTERRUPT_STATUS_EUES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_SHIFT
3763 #define GMAC_MTL_ECC_INTERRUPT_STATUS_EUES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_EUES_WIDTH
3764 #define GMAC_MTL_ECC_INTERRUPT_STATUS_EUES(x)    EMAC_MTL_ECC_INTERRUPT_STATUS_EUES(x)
3765 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_MASK
3766 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_SHIFT
3767 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES_WIDTH
3768 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPCES(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_RPCES(x)
3769 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_MASK
3770 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_SHIFT
3771 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS_WIDTH
3772 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_RPAMS(x)
3773 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_MASK EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_MASK
3774 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_SHIFT EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_SHIFT
3775 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_WIDTH EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES_WIDTH
3776 #define GMAC_MTL_ECC_INTERRUPT_STATUS_RPUES(x)   EMAC_MTL_ECC_INTERRUPT_STATUS_RPUES(x)
3777 /*! @} */
3778 
3779 /*! @name MTL_ECC_ERR_STS_RCTL -  */
3780 /*! @{ */
3781 #define GMAC_MTL_ECC_ERR_STS_RCTL_EESRE_MASK     EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_MASK
3782 #define GMAC_MTL_ECC_ERR_STS_RCTL_EESRE_SHIFT    EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_SHIFT
3783 #define GMAC_MTL_ECC_ERR_STS_RCTL_EESRE_WIDTH    EMAC_MTL_ECC_ERR_STS_RCTL_EESRE_WIDTH
3784 #define GMAC_MTL_ECC_ERR_STS_RCTL_EESRE(x)       EMAC_MTL_ECC_ERR_STS_RCTL_EESRE(x)
3785 #define GMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK       EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK
3786 #define GMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT      EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT
3787 #define GMAC_MTL_ECC_ERR_STS_RCTL_EMS_WIDTH      EMAC_MTL_ECC_ERR_STS_RCTL_EMS_WIDTH
3788 #define GMAC_MTL_ECC_ERR_STS_RCTL_EMS(x)         EMAC_MTL_ECC_ERR_STS_RCTL_EMS(x)
3789 #define GMAC_MTL_ECC_ERR_STS_RCTL_CCES_MASK      EMAC_MTL_ECC_ERR_STS_RCTL_CCES_MASK
3790 #define GMAC_MTL_ECC_ERR_STS_RCTL_CCES_SHIFT     EMAC_MTL_ECC_ERR_STS_RCTL_CCES_SHIFT
3791 #define GMAC_MTL_ECC_ERR_STS_RCTL_CCES_WIDTH     EMAC_MTL_ECC_ERR_STS_RCTL_CCES_WIDTH
3792 #define GMAC_MTL_ECC_ERR_STS_RCTL_CCES(x)        EMAC_MTL_ECC_ERR_STS_RCTL_CCES(x)
3793 #define GMAC_MTL_ECC_ERR_STS_RCTL_CUES_MASK      EMAC_MTL_ECC_ERR_STS_RCTL_CUES_MASK
3794 #define GMAC_MTL_ECC_ERR_STS_RCTL_CUES_SHIFT     EMAC_MTL_ECC_ERR_STS_RCTL_CUES_SHIFT
3795 #define GMAC_MTL_ECC_ERR_STS_RCTL_CUES_WIDTH     EMAC_MTL_ECC_ERR_STS_RCTL_CUES_WIDTH
3796 #define GMAC_MTL_ECC_ERR_STS_RCTL_CUES(x)        EMAC_MTL_ECC_ERR_STS_RCTL_CUES(x)
3797 /*! @} */
3798 
3799 /*! @name MTL_ECC_ERR_ADDR_STATUS -  */
3800 /*! @{ */
3801 #define GMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK  EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK
3802 #define GMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT
3803 #define GMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_WIDTH EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_WIDTH
3804 #define GMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(x)    EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(x)
3805 #define GMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK  EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK
3806 #define GMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT
3807 #define GMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_WIDTH EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_WIDTH
3808 #define GMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(x)    EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(x)
3809 /*! @} */
3810 
3811 /*! @name MTL_ECC_ERR_CNTR_STATUS -  */
3812 /*! @{ */
3813 #define GMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK  EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK
3814 #define GMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT
3815 #define GMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_WIDTH EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_WIDTH
3816 #define GMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(x)    EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(x)
3817 #define GMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK  EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK
3818 #define GMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT
3819 #define GMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_WIDTH EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_WIDTH
3820 #define GMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(x)    EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(x)
3821 /*! @} */
3822 
3823 /*! @name MTL_DPP_CONTROL -  */
3824 /*! @{ */
3825 #define GMAC_MTL_DPP_CONTROL_EDPP_MASK           EMAC_MTL_DPP_CONTROL_EDPP_MASK
3826 #define GMAC_MTL_DPP_CONTROL_EDPP_SHIFT          EMAC_MTL_DPP_CONTROL_EDPP_SHIFT
3827 #define GMAC_MTL_DPP_CONTROL_EDPP_WIDTH          EMAC_MTL_DPP_CONTROL_EDPP_WIDTH
3828 #define GMAC_MTL_DPP_CONTROL_EDPP(x)             EMAC_MTL_DPP_CONTROL_EDPP(x)
3829 #define GMAC_MTL_DPP_CONTROL_OPE_MASK            EMAC_MTL_DPP_CONTROL_OPE_MASK
3830 #define GMAC_MTL_DPP_CONTROL_OPE_SHIFT           EMAC_MTL_DPP_CONTROL_OPE_SHIFT
3831 #define GMAC_MTL_DPP_CONTROL_OPE_WIDTH           EMAC_MTL_DPP_CONTROL_OPE_WIDTH
3832 #define GMAC_MTL_DPP_CONTROL_OPE(x)              EMAC_MTL_DPP_CONTROL_OPE(x)
3833 #define GMAC_MTL_DPP_CONTROL_IPEID_MASK          EMAC_MTL_DPP_CONTROL_IPEID_MASK
3834 #define GMAC_MTL_DPP_CONTROL_IPEID_SHIFT         EMAC_MTL_DPP_CONTROL_IPEID_SHIFT
3835 #define GMAC_MTL_DPP_CONTROL_IPEID_WIDTH         EMAC_MTL_DPP_CONTROL_IPEID_WIDTH
3836 #define GMAC_MTL_DPP_CONTROL_IPEID(x)            EMAC_MTL_DPP_CONTROL_IPEID(x)
3837 #define GMAC_MTL_DPP_CONTROL_IPEMC_MASK          EMAC_MTL_DPP_CONTROL_IPEMC_MASK
3838 #define GMAC_MTL_DPP_CONTROL_IPEMC_SHIFT         EMAC_MTL_DPP_CONTROL_IPEMC_SHIFT
3839 #define GMAC_MTL_DPP_CONTROL_IPEMC_WIDTH         EMAC_MTL_DPP_CONTROL_IPEMC_WIDTH
3840 #define GMAC_MTL_DPP_CONTROL_IPEMC(x)            EMAC_MTL_DPP_CONTROL_IPEMC(x)
3841 #define GMAC_MTL_DPP_CONTROL_IPEMTS_MASK         EMAC_MTL_DPP_CONTROL_IPEMTS_MASK
3842 #define GMAC_MTL_DPP_CONTROL_IPEMTS_SHIFT        EMAC_MTL_DPP_CONTROL_IPEMTS_SHIFT
3843 #define GMAC_MTL_DPP_CONTROL_IPEMTS_WIDTH        EMAC_MTL_DPP_CONTROL_IPEMTS_WIDTH
3844 #define GMAC_MTL_DPP_CONTROL_IPEMTS(x)           EMAC_MTL_DPP_CONTROL_IPEMTS(x)
3845 #define GMAC_MTL_DPP_CONTROL_IPEMRF_MASK         EMAC_MTL_DPP_CONTROL_IPEMRF_MASK
3846 #define GMAC_MTL_DPP_CONTROL_IPEMRF_SHIFT        EMAC_MTL_DPP_CONTROL_IPEMRF_SHIFT
3847 #define GMAC_MTL_DPP_CONTROL_IPEMRF_WIDTH        EMAC_MTL_DPP_CONTROL_IPEMRF_WIDTH
3848 #define GMAC_MTL_DPP_CONTROL_IPEMRF(x)           EMAC_MTL_DPP_CONTROL_IPEMRF(x)
3849 #define GMAC_MTL_DPP_CONTROL_IPEDDC_MASK         EMAC_MTL_DPP_CONTROL_IPEDDC_MASK
3850 #define GMAC_MTL_DPP_CONTROL_IPEDDC_SHIFT        EMAC_MTL_DPP_CONTROL_IPEDDC_SHIFT
3851 #define GMAC_MTL_DPP_CONTROL_IPEDDC_WIDTH        EMAC_MTL_DPP_CONTROL_IPEDDC_WIDTH
3852 #define GMAC_MTL_DPP_CONTROL_IPEDDC(x)           EMAC_MTL_DPP_CONTROL_IPEDDC(x)
3853 #define GMAC_MTL_DPP_CONTROL_IPETD_MASK          EMAC_MTL_DPP_CONTROL_IPETD_MASK
3854 #define GMAC_MTL_DPP_CONTROL_IPETD_SHIFT         EMAC_MTL_DPP_CONTROL_IPETD_SHIFT
3855 #define GMAC_MTL_DPP_CONTROL_IPETD_WIDTH         EMAC_MTL_DPP_CONTROL_IPETD_WIDTH
3856 #define GMAC_MTL_DPP_CONTROL_IPETD(x)            EMAC_MTL_DPP_CONTROL_IPETD(x)
3857 #define GMAC_MTL_DPP_CONTROL_IPERD_MASK          EMAC_MTL_DPP_CONTROL_IPERD_MASK
3858 #define GMAC_MTL_DPP_CONTROL_IPERD_SHIFT         EMAC_MTL_DPP_CONTROL_IPERD_SHIFT
3859 #define GMAC_MTL_DPP_CONTROL_IPERD_WIDTH         EMAC_MTL_DPP_CONTROL_IPERD_WIDTH
3860 #define GMAC_MTL_DPP_CONTROL_IPERD(x)            EMAC_MTL_DPP_CONTROL_IPERD(x)
3861 /*! @} */
3862 
3863 /*! @name MTL_TXQ0_OPERATION_MODE -  */
3864 /*! @{ */
3865 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK    EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK
3866 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT   EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_SHIFT
3867 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_WIDTH   EMAC_MTL_TXQ0_OPERATION_MODE_FTQ_WIDTH
3868 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ(x)      EMAC_MTL_TXQ0_OPERATION_MODE_FTQ(x)
3869 #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK    EMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK
3870 #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT   EMAC_MTL_TXQ0_OPERATION_MODE_TSF_SHIFT
3871 #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF_WIDTH   EMAC_MTL_TXQ0_OPERATION_MODE_TSF_WIDTH
3872 #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF(x)      EMAC_MTL_TXQ0_OPERATION_MODE_TSF(x)
3873 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK  EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK
3874 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT
3875 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_WIDTH EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_WIDTH
3876 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(x)    EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(x)
3877 #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK    EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK
3878 #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT   EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT
3879 #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC_WIDTH   EMAC_MTL_TXQ0_OPERATION_MODE_TTC_WIDTH
3880 #define GMAC_MTL_TXQ0_OPERATION_MODE_TTC(x)      EMAC_MTL_TXQ0_OPERATION_MODE_TTC(x)
3881 #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK    EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK
3882 #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT   EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT
3883 #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS_WIDTH   EMAC_MTL_TXQ0_OPERATION_MODE_TQS_WIDTH
3884 #define GMAC_MTL_TXQ0_OPERATION_MODE_TQS(x)      EMAC_MTL_TXQ0_OPERATION_MODE_TQS(x)
3885 /*! @} */
3886 
3887 /*! @name MTL_TXQ0_UNDERFLOW -  */
3888 /*! @{ */
3889 #define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK    EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK
3890 #define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT   EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT
3891 #define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_WIDTH   EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_WIDTH
3892 #define GMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(x)      EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(x)
3893 #define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK    EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MASK
3894 #define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT   EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_SHIFT
3895 #define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_WIDTH   EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF_WIDTH
3896 #define GMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF(x)      EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF(x)
3897 /*! @} */
3898 
3899 /*! @name MTL_TXQ0_DEBUG -  */
3900 /*! @{ */
3901 #define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK       EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_MASK
3902 #define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT      EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_SHIFT
3903 #define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED_WIDTH      EMAC_MTL_TXQ0_DEBUG_TXQPAUSED_WIDTH
3904 #define GMAC_MTL_TXQ0_DEBUG_TXQPAUSED(x)         EMAC_MTL_TXQ0_DEBUG_TXQPAUSED(x)
3905 #define GMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK          EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK
3906 #define GMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT         EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT
3907 #define GMAC_MTL_TXQ0_DEBUG_TRCSTS_WIDTH         EMAC_MTL_TXQ0_DEBUG_TRCSTS_WIDTH
3908 #define GMAC_MTL_TXQ0_DEBUG_TRCSTS(x)            EMAC_MTL_TXQ0_DEBUG_TRCSTS(x)
3909 #define GMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK          EMAC_MTL_TXQ0_DEBUG_TWCSTS_MASK
3910 #define GMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT         EMAC_MTL_TXQ0_DEBUG_TWCSTS_SHIFT
3911 #define GMAC_MTL_TXQ0_DEBUG_TWCSTS_WIDTH         EMAC_MTL_TXQ0_DEBUG_TWCSTS_WIDTH
3912 #define GMAC_MTL_TXQ0_DEBUG_TWCSTS(x)            EMAC_MTL_TXQ0_DEBUG_TWCSTS(x)
3913 #define GMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK          EMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK
3914 #define GMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT         EMAC_MTL_TXQ0_DEBUG_TXQSTS_SHIFT
3915 #define GMAC_MTL_TXQ0_DEBUG_TXQSTS_WIDTH         EMAC_MTL_TXQ0_DEBUG_TXQSTS_WIDTH
3916 #define GMAC_MTL_TXQ0_DEBUG_TXQSTS(x)            EMAC_MTL_TXQ0_DEBUG_TXQSTS(x)
3917 #define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK       EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_MASK
3918 #define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT      EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_SHIFT
3919 #define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_WIDTH      EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS_WIDTH
3920 #define GMAC_MTL_TXQ0_DEBUG_TXSTSFSTS(x)         EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS(x)
3921 #define GMAC_MTL_TXQ0_DEBUG_PTXQ_MASK            EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK
3922 #define GMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT           EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT
3923 #define GMAC_MTL_TXQ0_DEBUG_PTXQ_WIDTH           EMAC_MTL_TXQ0_DEBUG_PTXQ_WIDTH
3924 #define GMAC_MTL_TXQ0_DEBUG_PTXQ(x)              EMAC_MTL_TXQ0_DEBUG_PTXQ(x)
3925 #define GMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK         EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK
3926 #define GMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT        EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT
3927 #define GMAC_MTL_TXQ0_DEBUG_STXSTSF_WIDTH        EMAC_MTL_TXQ0_DEBUG_STXSTSF_WIDTH
3928 #define GMAC_MTL_TXQ0_DEBUG_STXSTSF(x)           EMAC_MTL_TXQ0_DEBUG_STXSTSF(x)
3929 /*! @} */
3930 
3931 /*! @name MTL_TXQ0_ETS_STATUS -  */
3932 /*! @{ */
3933 #define GMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK        EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK
3934 #define GMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT       EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT
3935 #define GMAC_MTL_TXQ0_ETS_STATUS_ABS_WIDTH       EMAC_MTL_TXQ0_ETS_STATUS_ABS_WIDTH
3936 #define GMAC_MTL_TXQ0_ETS_STATUS_ABS(x)          EMAC_MTL_TXQ0_ETS_STATUS_ABS(x)
3937 /*! @} */
3938 
3939 /*! @name MTL_TXQ0_QUANTUM_WEIGHT -  */
3940 /*! @{ */
3941 #define GMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK  EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK
3942 #define GMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT
3943 #define GMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_WIDTH EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_WIDTH
3944 #define GMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(x)    EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(x)
3945 /*! @} */
3946 
3947 /*! @name MTL_Q0_INTERRUPT_CONTROL_STATUS -  */
3948 /*! @{ */
3949 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK
3950 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT
3951 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH
3952 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS(x)
3953 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK
3954 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT
3955 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH
3956 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS(x)
3957 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MASK
3958 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT
3959 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH
3960 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE(x)
3961 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK
3962 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT
3963 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH
3964 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE(x)
3965 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK
3966 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT
3967 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH
3968 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS(x)
3969 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MASK EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MASK
3970 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT
3971 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH
3972 #define GMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE(x) EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE(x)
3973 /*! @} */
3974 
3975 /*! @name MTL_RXQ0_OPERATION_MODE -  */
3976 /*! @{ */
3977 #define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK    EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK
3978 #define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT   EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT
3979 #define GMAC_MTL_RXQ0_OPERATION_MODE_RTC_WIDTH   EMAC_MTL_RXQ0_OPERATION_MODE_RTC_WIDTH
3980 #define GMAC_MTL_RXQ0_OPERATION_MODE_RTC(x)      EMAC_MTL_RXQ0_OPERATION_MODE_RTC(x)
3981 #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK    EMAC_MTL_RXQ0_OPERATION_MODE_FUP_MASK
3982 #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT   EMAC_MTL_RXQ0_OPERATION_MODE_FUP_SHIFT
3983 #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP_WIDTH   EMAC_MTL_RXQ0_OPERATION_MODE_FUP_WIDTH
3984 #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP(x)      EMAC_MTL_RXQ0_OPERATION_MODE_FUP(x)
3985 #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK    EMAC_MTL_RXQ0_OPERATION_MODE_FEP_MASK
3986 #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT   EMAC_MTL_RXQ0_OPERATION_MODE_FEP_SHIFT
3987 #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP_WIDTH   EMAC_MTL_RXQ0_OPERATION_MODE_FEP_WIDTH
3988 #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP(x)      EMAC_MTL_RXQ0_OPERATION_MODE_FEP(x)
3989 #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK    EMAC_MTL_RXQ0_OPERATION_MODE_RSF_MASK
3990 #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT   EMAC_MTL_RXQ0_OPERATION_MODE_RSF_SHIFT
3991 #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF_WIDTH   EMAC_MTL_RXQ0_OPERATION_MODE_RSF_WIDTH
3992 #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF(x)      EMAC_MTL_RXQ0_OPERATION_MODE_RSF(x)
3993 #define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MASK
3994 #define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_SHIFT
3995 #define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_WIDTH EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_WIDTH
3996 #define GMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF(x) EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF(x)
3997 #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK   EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_MASK
3998 #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT  EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_SHIFT
3999 #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC_WIDTH  EMAC_MTL_RXQ0_OPERATION_MODE_EHFC_WIDTH
4000 #define GMAC_MTL_RXQ0_OPERATION_MODE_EHFC(x)     EMAC_MTL_RXQ0_OPERATION_MODE_EHFC(x)
4001 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK    EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK
4002 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT   EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT
4003 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA_WIDTH   EMAC_MTL_RXQ0_OPERATION_MODE_RFA_WIDTH
4004 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFA(x)      EMAC_MTL_RXQ0_OPERATION_MODE_RFA(x)
4005 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK    EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK
4006 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT   EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT
4007 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD_WIDTH   EMAC_MTL_RXQ0_OPERATION_MODE_RFD_WIDTH
4008 #define GMAC_MTL_RXQ0_OPERATION_MODE_RFD(x)      EMAC_MTL_RXQ0_OPERATION_MODE_RFD(x)
4009 #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK    EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK
4010 #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT   EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT
4011 #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS_WIDTH   EMAC_MTL_RXQ0_OPERATION_MODE_RQS_WIDTH
4012 #define GMAC_MTL_RXQ0_OPERATION_MODE_RQS(x)      EMAC_MTL_RXQ0_OPERATION_MODE_RQS(x)
4013 /*! @} */
4014 
4015 /*! @name MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT -  */
4016 /*! @{ */
4017 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK
4018 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT
4019 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH
4020 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x)
4021 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK
4022 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT
4023 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH
4024 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x)
4025 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK
4026 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT
4027 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH
4028 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x)
4029 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK
4030 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT
4031 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH
4032 #define GMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x)
4033 /*! @} */
4034 
4035 /*! @name MTL_RXQ0_DEBUG -  */
4036 /*! @{ */
4037 #define GMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK          EMAC_MTL_RXQ0_DEBUG_RWCSTS_MASK
4038 #define GMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT         EMAC_MTL_RXQ0_DEBUG_RWCSTS_SHIFT
4039 #define GMAC_MTL_RXQ0_DEBUG_RWCSTS_WIDTH         EMAC_MTL_RXQ0_DEBUG_RWCSTS_WIDTH
4040 #define GMAC_MTL_RXQ0_DEBUG_RWCSTS(x)            EMAC_MTL_RXQ0_DEBUG_RWCSTS(x)
4041 #define GMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK          EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK
4042 #define GMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT         EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT
4043 #define GMAC_MTL_RXQ0_DEBUG_RRCSTS_WIDTH         EMAC_MTL_RXQ0_DEBUG_RRCSTS_WIDTH
4044 #define GMAC_MTL_RXQ0_DEBUG_RRCSTS(x)            EMAC_MTL_RXQ0_DEBUG_RRCSTS(x)
4045 #define GMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK          EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK
4046 #define GMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT         EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT
4047 #define GMAC_MTL_RXQ0_DEBUG_RXQSTS_WIDTH         EMAC_MTL_RXQ0_DEBUG_RXQSTS_WIDTH
4048 #define GMAC_MTL_RXQ0_DEBUG_RXQSTS(x)            EMAC_MTL_RXQ0_DEBUG_RXQSTS(x)
4049 #define GMAC_MTL_RXQ0_DEBUG_PRXQ_MASK            EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK
4050 #define GMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT           EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT
4051 #define GMAC_MTL_RXQ0_DEBUG_PRXQ_WIDTH           EMAC_MTL_RXQ0_DEBUG_PRXQ_WIDTH
4052 #define GMAC_MTL_RXQ0_DEBUG_PRXQ(x)              EMAC_MTL_RXQ0_DEBUG_PRXQ(x)
4053 /*! @} */
4054 
4055 /*! @name MTL_RXQ0_CONTROL -  */
4056 /*! @{ */
4057 #define GMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK      EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK
4058 #define GMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT     EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT
4059 #define GMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_WIDTH     EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_WIDTH
4060 #define GMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(x)        EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(x)
4061 #define GMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MASK EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MASK
4062 #define GMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_SHIFT EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_SHIFT
4063 #define GMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_WIDTH EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_WIDTH
4064 #define GMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT(x)   EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT(x)
4065 /*! @} */
4066 
4067 /*! @name MTL_TXQ1_OPERATION_MODE -  */
4068 /*! @{ */
4069 #define GMAC_MTL_TXQ1_OPERATION_MODE_FTQ_MASK    EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_MASK
4070 #define GMAC_MTL_TXQ1_OPERATION_MODE_FTQ_SHIFT   EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_SHIFT
4071 #define GMAC_MTL_TXQ1_OPERATION_MODE_FTQ_WIDTH   EMAC_MTL_TXQ1_OPERATION_MODE_FTQ_WIDTH
4072 #define GMAC_MTL_TXQ1_OPERATION_MODE_FTQ(x)      EMAC_MTL_TXQ1_OPERATION_MODE_FTQ(x)
4073 #define GMAC_MTL_TXQ1_OPERATION_MODE_TSF_MASK    EMAC_MTL_TXQ1_OPERATION_MODE_TSF_MASK
4074 #define GMAC_MTL_TXQ1_OPERATION_MODE_TSF_SHIFT   EMAC_MTL_TXQ1_OPERATION_MODE_TSF_SHIFT
4075 #define GMAC_MTL_TXQ1_OPERATION_MODE_TSF_WIDTH   EMAC_MTL_TXQ1_OPERATION_MODE_TSF_WIDTH
4076 #define GMAC_MTL_TXQ1_OPERATION_MODE_TSF(x)      EMAC_MTL_TXQ1_OPERATION_MODE_TSF(x)
4077 #define GMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK  EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK
4078 #define GMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT
4079 #define GMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_WIDTH EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_WIDTH
4080 #define GMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(x)    EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(x)
4081 #define GMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK    EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK
4082 #define GMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT   EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT
4083 #define GMAC_MTL_TXQ1_OPERATION_MODE_TTC_WIDTH   EMAC_MTL_TXQ1_OPERATION_MODE_TTC_WIDTH
4084 #define GMAC_MTL_TXQ1_OPERATION_MODE_TTC(x)      EMAC_MTL_TXQ1_OPERATION_MODE_TTC(x)
4085 #define GMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK    EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK
4086 #define GMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT   EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT
4087 #define GMAC_MTL_TXQ1_OPERATION_MODE_TQS_WIDTH   EMAC_MTL_TXQ1_OPERATION_MODE_TQS_WIDTH
4088 #define GMAC_MTL_TXQ1_OPERATION_MODE_TQS(x)      EMAC_MTL_TXQ1_OPERATION_MODE_TQS(x)
4089 /*! @} */
4090 
4091 /*! @name MTL_TXQ1_UNDERFLOW -  */
4092 /*! @{ */
4093 #define GMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK    EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK
4094 #define GMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT   EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT
4095 #define GMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_WIDTH   EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_WIDTH
4096 #define GMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(x)      EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(x)
4097 #define GMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_MASK    EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_MASK
4098 #define GMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_SHIFT   EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_SHIFT
4099 #define GMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_WIDTH   EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF_WIDTH
4100 #define GMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF(x)      EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF(x)
4101 /*! @} */
4102 
4103 /*! @name MTL_TXQ1_DEBUG -  */
4104 /*! @{ */
4105 #define GMAC_MTL_TXQ1_DEBUG_TXQPAUSED_MASK       EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_MASK
4106 #define GMAC_MTL_TXQ1_DEBUG_TXQPAUSED_SHIFT      EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_SHIFT
4107 #define GMAC_MTL_TXQ1_DEBUG_TXQPAUSED_WIDTH      EMAC_MTL_TXQ1_DEBUG_TXQPAUSED_WIDTH
4108 #define GMAC_MTL_TXQ1_DEBUG_TXQPAUSED(x)         EMAC_MTL_TXQ1_DEBUG_TXQPAUSED(x)
4109 #define GMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK          EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK
4110 #define GMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT         EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT
4111 #define GMAC_MTL_TXQ1_DEBUG_TRCSTS_WIDTH         EMAC_MTL_TXQ1_DEBUG_TRCSTS_WIDTH
4112 #define GMAC_MTL_TXQ1_DEBUG_TRCSTS(x)            EMAC_MTL_TXQ1_DEBUG_TRCSTS(x)
4113 #define GMAC_MTL_TXQ1_DEBUG_TWCSTS_MASK          EMAC_MTL_TXQ1_DEBUG_TWCSTS_MASK
4114 #define GMAC_MTL_TXQ1_DEBUG_TWCSTS_SHIFT         EMAC_MTL_TXQ1_DEBUG_TWCSTS_SHIFT
4115 #define GMAC_MTL_TXQ1_DEBUG_TWCSTS_WIDTH         EMAC_MTL_TXQ1_DEBUG_TWCSTS_WIDTH
4116 #define GMAC_MTL_TXQ1_DEBUG_TWCSTS(x)            EMAC_MTL_TXQ1_DEBUG_TWCSTS(x)
4117 #define GMAC_MTL_TXQ1_DEBUG_TXQSTS_MASK          EMAC_MTL_TXQ1_DEBUG_TXQSTS_MASK
4118 #define GMAC_MTL_TXQ1_DEBUG_TXQSTS_SHIFT         EMAC_MTL_TXQ1_DEBUG_TXQSTS_SHIFT
4119 #define GMAC_MTL_TXQ1_DEBUG_TXQSTS_WIDTH         EMAC_MTL_TXQ1_DEBUG_TXQSTS_WIDTH
4120 #define GMAC_MTL_TXQ1_DEBUG_TXQSTS(x)            EMAC_MTL_TXQ1_DEBUG_TXQSTS(x)
4121 #define GMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_MASK       EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_MASK
4122 #define GMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_SHIFT      EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_SHIFT
4123 #define GMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_WIDTH      EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS_WIDTH
4124 #define GMAC_MTL_TXQ1_DEBUG_TXSTSFSTS(x)         EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS(x)
4125 #define GMAC_MTL_TXQ1_DEBUG_PTXQ_MASK            EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK
4126 #define GMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT           EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT
4127 #define GMAC_MTL_TXQ1_DEBUG_PTXQ_WIDTH           EMAC_MTL_TXQ1_DEBUG_PTXQ_WIDTH
4128 #define GMAC_MTL_TXQ1_DEBUG_PTXQ(x)              EMAC_MTL_TXQ1_DEBUG_PTXQ(x)
4129 #define GMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK         EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK
4130 #define GMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT        EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT
4131 #define GMAC_MTL_TXQ1_DEBUG_STXSTSF_WIDTH        EMAC_MTL_TXQ1_DEBUG_STXSTSF_WIDTH
4132 #define GMAC_MTL_TXQ1_DEBUG_STXSTSF(x)           EMAC_MTL_TXQ1_DEBUG_STXSTSF(x)
4133 /*! @} */
4134 
4135 /*! @name MTL_TXQ1_ETS_CONTROL -  */
4136 /*! @{ */
4137 #define GMAC_MTL_TXQ1_ETS_CONTROL_AVALG_MASK     EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_MASK
4138 #define GMAC_MTL_TXQ1_ETS_CONTROL_AVALG_SHIFT    EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_SHIFT
4139 #define GMAC_MTL_TXQ1_ETS_CONTROL_AVALG_WIDTH    EMAC_MTL_TXQ1_ETS_CONTROL_AVALG_WIDTH
4140 #define GMAC_MTL_TXQ1_ETS_CONTROL_AVALG(x)       EMAC_MTL_TXQ1_ETS_CONTROL_AVALG(x)
4141 #define GMAC_MTL_TXQ1_ETS_CONTROL_CC_MASK        EMAC_MTL_TXQ1_ETS_CONTROL_CC_MASK
4142 #define GMAC_MTL_TXQ1_ETS_CONTROL_CC_SHIFT       EMAC_MTL_TXQ1_ETS_CONTROL_CC_SHIFT
4143 #define GMAC_MTL_TXQ1_ETS_CONTROL_CC_WIDTH       EMAC_MTL_TXQ1_ETS_CONTROL_CC_WIDTH
4144 #define GMAC_MTL_TXQ1_ETS_CONTROL_CC(x)          EMAC_MTL_TXQ1_ETS_CONTROL_CC(x)
4145 #define GMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK       EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK
4146 #define GMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT      EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT
4147 #define GMAC_MTL_TXQ1_ETS_CONTROL_SLC_WIDTH      EMAC_MTL_TXQ1_ETS_CONTROL_SLC_WIDTH
4148 #define GMAC_MTL_TXQ1_ETS_CONTROL_SLC(x)         EMAC_MTL_TXQ1_ETS_CONTROL_SLC(x)
4149 /*! @} */
4150 
4151 /*! @name MTL_TXQ1_ETS_STATUS -  */
4152 /*! @{ */
4153 #define GMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK        EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK
4154 #define GMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT       EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT
4155 #define GMAC_MTL_TXQ1_ETS_STATUS_ABS_WIDTH       EMAC_MTL_TXQ1_ETS_STATUS_ABS_WIDTH
4156 #define GMAC_MTL_TXQ1_ETS_STATUS_ABS(x)          EMAC_MTL_TXQ1_ETS_STATUS_ABS(x)
4157 /*! @} */
4158 
4159 /*! @name MTL_TXQ1_QUANTUM_WEIGHT -  */
4160 /*! @{ */
4161 #define GMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK  EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK
4162 #define GMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT
4163 #define GMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_WIDTH EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_WIDTH
4164 #define GMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(x)    EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(x)
4165 /*! @} */
4166 
4167 /*! @name MTL_TXQ1_SENDSLOPECREDIT -  */
4168 /*! @{ */
4169 #define GMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK   EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK
4170 #define GMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT  EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT
4171 #define GMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_WIDTH  EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_WIDTH
4172 #define GMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(x)     EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(x)
4173 /*! @} */
4174 
4175 /*! @name MTL_TXQ1_HICREDIT -  */
4176 /*! @{ */
4177 #define GMAC_MTL_TXQ1_HICREDIT_HC_MASK           EMAC_MTL_TXQ1_HICREDIT_HC_MASK
4178 #define GMAC_MTL_TXQ1_HICREDIT_HC_SHIFT          EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT
4179 #define GMAC_MTL_TXQ1_HICREDIT_HC_WIDTH          EMAC_MTL_TXQ1_HICREDIT_HC_WIDTH
4180 #define GMAC_MTL_TXQ1_HICREDIT_HC(x)             EMAC_MTL_TXQ1_HICREDIT_HC(x)
4181 /*! @} */
4182 
4183 /*! @name MTL_TXQ1_LOCREDIT -  */
4184 /*! @{ */
4185 #define GMAC_MTL_TXQ1_LOCREDIT_LC_MASK           EMAC_MTL_TXQ1_LOCREDIT_LC_MASK
4186 #define GMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT          EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT
4187 #define GMAC_MTL_TXQ1_LOCREDIT_LC_WIDTH          EMAC_MTL_TXQ1_LOCREDIT_LC_WIDTH
4188 #define GMAC_MTL_TXQ1_LOCREDIT_LC(x)             EMAC_MTL_TXQ1_LOCREDIT_LC(x)
4189 /*! @} */
4190 
4191 /*! @name MTL_Q1_INTERRUPT_CONTROL_STATUS -  */
4192 /*! @{ */
4193 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_MASK
4194 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_SHIFT
4195 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS_WIDTH
4196 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS(x)
4197 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_MASK
4198 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_SHIFT
4199 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS_WIDTH
4200 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIS(x)
4201 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_MASK
4202 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_SHIFT
4203 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE_WIDTH
4204 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUIE(x)
4205 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_MASK
4206 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_SHIFT
4207 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE_WIDTH
4208 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_ABPSIE(x)
4209 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_MASK
4210 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_SHIFT
4211 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS_WIDTH
4212 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOVFIS(x)
4213 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_MASK EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_MASK
4214 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_SHIFT
4215 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE_WIDTH
4216 #define GMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE(x) EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_RXOIE(x)
4217 /*! @} */
4218 
4219 /*! @name MTL_RXQ1_OPERATION_MODE -  */
4220 /*! @{ */
4221 #define GMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK    EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK
4222 #define GMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT   EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT
4223 #define GMAC_MTL_RXQ1_OPERATION_MODE_RTC_WIDTH   EMAC_MTL_RXQ1_OPERATION_MODE_RTC_WIDTH
4224 #define GMAC_MTL_RXQ1_OPERATION_MODE_RTC(x)      EMAC_MTL_RXQ1_OPERATION_MODE_RTC(x)
4225 #define GMAC_MTL_RXQ1_OPERATION_MODE_FUP_MASK    EMAC_MTL_RXQ1_OPERATION_MODE_FUP_MASK
4226 #define GMAC_MTL_RXQ1_OPERATION_MODE_FUP_SHIFT   EMAC_MTL_RXQ1_OPERATION_MODE_FUP_SHIFT
4227 #define GMAC_MTL_RXQ1_OPERATION_MODE_FUP_WIDTH   EMAC_MTL_RXQ1_OPERATION_MODE_FUP_WIDTH
4228 #define GMAC_MTL_RXQ1_OPERATION_MODE_FUP(x)      EMAC_MTL_RXQ1_OPERATION_MODE_FUP(x)
4229 #define GMAC_MTL_RXQ1_OPERATION_MODE_FEP_MASK    EMAC_MTL_RXQ1_OPERATION_MODE_FEP_MASK
4230 #define GMAC_MTL_RXQ1_OPERATION_MODE_FEP_SHIFT   EMAC_MTL_RXQ1_OPERATION_MODE_FEP_SHIFT
4231 #define GMAC_MTL_RXQ1_OPERATION_MODE_FEP_WIDTH   EMAC_MTL_RXQ1_OPERATION_MODE_FEP_WIDTH
4232 #define GMAC_MTL_RXQ1_OPERATION_MODE_FEP(x)      EMAC_MTL_RXQ1_OPERATION_MODE_FEP(x)
4233 #define GMAC_MTL_RXQ1_OPERATION_MODE_RSF_MASK    EMAC_MTL_RXQ1_OPERATION_MODE_RSF_MASK
4234 #define GMAC_MTL_RXQ1_OPERATION_MODE_RSF_SHIFT   EMAC_MTL_RXQ1_OPERATION_MODE_RSF_SHIFT
4235 #define GMAC_MTL_RXQ1_OPERATION_MODE_RSF_WIDTH   EMAC_MTL_RXQ1_OPERATION_MODE_RSF_WIDTH
4236 #define GMAC_MTL_RXQ1_OPERATION_MODE_RSF(x)      EMAC_MTL_RXQ1_OPERATION_MODE_RSF(x)
4237 #define GMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_MASK EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_MASK
4238 #define GMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_SHIFT EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_SHIFT
4239 #define GMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_WIDTH EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF_WIDTH
4240 #define GMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF(x) EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF(x)
4241 #define GMAC_MTL_RXQ1_OPERATION_MODE_EHFC_MASK   EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_MASK
4242 #define GMAC_MTL_RXQ1_OPERATION_MODE_EHFC_SHIFT  EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_SHIFT
4243 #define GMAC_MTL_RXQ1_OPERATION_MODE_EHFC_WIDTH  EMAC_MTL_RXQ1_OPERATION_MODE_EHFC_WIDTH
4244 #define GMAC_MTL_RXQ1_OPERATION_MODE_EHFC(x)     EMAC_MTL_RXQ1_OPERATION_MODE_EHFC(x)
4245 #define GMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK    EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK
4246 #define GMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT   EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT
4247 #define GMAC_MTL_RXQ1_OPERATION_MODE_RFA_WIDTH   EMAC_MTL_RXQ1_OPERATION_MODE_RFA_WIDTH
4248 #define GMAC_MTL_RXQ1_OPERATION_MODE_RFA(x)      EMAC_MTL_RXQ1_OPERATION_MODE_RFA(x)
4249 #define GMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK    EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK
4250 #define GMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT   EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT
4251 #define GMAC_MTL_RXQ1_OPERATION_MODE_RFD_WIDTH   EMAC_MTL_RXQ1_OPERATION_MODE_RFD_WIDTH
4252 #define GMAC_MTL_RXQ1_OPERATION_MODE_RFD(x)      EMAC_MTL_RXQ1_OPERATION_MODE_RFD(x)
4253 #define GMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK    EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK
4254 #define GMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT   EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT
4255 #define GMAC_MTL_RXQ1_OPERATION_MODE_RQS_WIDTH   EMAC_MTL_RXQ1_OPERATION_MODE_RQS_WIDTH
4256 #define GMAC_MTL_RXQ1_OPERATION_MODE_RQS(x)      EMAC_MTL_RXQ1_OPERATION_MODE_RQS(x)
4257 /*! @} */
4258 
4259 /*! @name MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT -  */
4260 /*! @{ */
4261 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK
4262 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT
4263 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_WIDTH
4264 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x) EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(x)
4265 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MASK
4266 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_SHIFT
4267 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_WIDTH
4268 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x) EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF(x)
4269 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK
4270 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT
4271 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_WIDTH
4272 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x) EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(x)
4273 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MASK
4274 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_SHIFT
4275 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_WIDTH
4276 #define GMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x) EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF(x)
4277 /*! @} */
4278 
4279 /*! @name MTL_RXQ1_DEBUG -  */
4280 /*! @{ */
4281 #define GMAC_MTL_RXQ1_DEBUG_RWCSTS_MASK          EMAC_MTL_RXQ1_DEBUG_RWCSTS_MASK
4282 #define GMAC_MTL_RXQ1_DEBUG_RWCSTS_SHIFT         EMAC_MTL_RXQ1_DEBUG_RWCSTS_SHIFT
4283 #define GMAC_MTL_RXQ1_DEBUG_RWCSTS_WIDTH         EMAC_MTL_RXQ1_DEBUG_RWCSTS_WIDTH
4284 #define GMAC_MTL_RXQ1_DEBUG_RWCSTS(x)            EMAC_MTL_RXQ1_DEBUG_RWCSTS(x)
4285 #define GMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK          EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK
4286 #define GMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT         EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT
4287 #define GMAC_MTL_RXQ1_DEBUG_RRCSTS_WIDTH         EMAC_MTL_RXQ1_DEBUG_RRCSTS_WIDTH
4288 #define GMAC_MTL_RXQ1_DEBUG_RRCSTS(x)            EMAC_MTL_RXQ1_DEBUG_RRCSTS(x)
4289 #define GMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK          EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK
4290 #define GMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT         EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT
4291 #define GMAC_MTL_RXQ1_DEBUG_RXQSTS_WIDTH         EMAC_MTL_RXQ1_DEBUG_RXQSTS_WIDTH
4292 #define GMAC_MTL_RXQ1_DEBUG_RXQSTS(x)            EMAC_MTL_RXQ1_DEBUG_RXQSTS(x)
4293 #define GMAC_MTL_RXQ1_DEBUG_PRXQ_MASK            EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK
4294 #define GMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT           EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT
4295 #define GMAC_MTL_RXQ1_DEBUG_PRXQ_WIDTH           EMAC_MTL_RXQ1_DEBUG_PRXQ_WIDTH
4296 #define GMAC_MTL_RXQ1_DEBUG_PRXQ(x)              EMAC_MTL_RXQ1_DEBUG_PRXQ(x)
4297 /*! @} */
4298 
4299 /*! @name MTL_RXQ1_CONTROL -  */
4300 /*! @{ */
4301 #define GMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK      EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK
4302 #define GMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT     EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT
4303 #define GMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_WIDTH     EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_WIDTH
4304 #define GMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(x)        EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(x)
4305 #define GMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_MASK EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_MASK
4306 #define GMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_SHIFT EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_SHIFT
4307 #define GMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_WIDTH EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT_WIDTH
4308 #define GMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT(x)   EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT(x)
4309 /*! @} */
4310 
4311 /*! @name DMA_MODE -  */
4312 /*! @{ */
4313 #define GMAC_DMA_MODE_SWR_MASK                   EMAC_DMA_MODE_SWR_MASK
4314 #define GMAC_DMA_MODE_SWR_SHIFT                  EMAC_DMA_MODE_SWR_SHIFT
4315 #define GMAC_DMA_MODE_SWR_WIDTH                  EMAC_DMA_MODE_SWR_WIDTH
4316 #define GMAC_DMA_MODE_SWR(x)                     EMAC_DMA_MODE_SWR(x)
4317 #define GMAC_DMA_MODE_DA_MASK                    EMAC_DMA_MODE_DA_MASK
4318 #define GMAC_DMA_MODE_DA_SHIFT                   EMAC_DMA_MODE_DA_SHIFT
4319 #define GMAC_DMA_MODE_DA_WIDTH                   EMAC_DMA_MODE_DA_WIDTH
4320 #define GMAC_DMA_MODE_DA(x)                      EMAC_DMA_MODE_DA(x)
4321 #define GMAC_DMA_MODE_TAA_MASK                   EMAC_DMA_MODE_TAA_MASK
4322 #define GMAC_DMA_MODE_TAA_SHIFT                  EMAC_DMA_MODE_TAA_SHIFT
4323 #define GMAC_DMA_MODE_TAA_WIDTH                  EMAC_DMA_MODE_TAA_WIDTH
4324 #define GMAC_DMA_MODE_TAA(x)                     EMAC_DMA_MODE_TAA(x)
4325 #define GMAC_DMA_MODE_ARBC_MASK                  EMAC_DMA_MODE_ARBC_MASK
4326 #define GMAC_DMA_MODE_ARBC_SHIFT                 EMAC_DMA_MODE_ARBC_SHIFT
4327 #define GMAC_DMA_MODE_ARBC_WIDTH                 EMAC_DMA_MODE_ARBC_WIDTH
4328 #define GMAC_DMA_MODE_ARBC(x)                    EMAC_DMA_MODE_ARBC(x)
4329 #define GMAC_DMA_MODE_TXPR_MASK                  EMAC_DMA_MODE_TXPR_MASK
4330 #define GMAC_DMA_MODE_TXPR_SHIFT                 EMAC_DMA_MODE_TXPR_SHIFT
4331 #define GMAC_DMA_MODE_TXPR_WIDTH                 EMAC_DMA_MODE_TXPR_WIDTH
4332 #define GMAC_DMA_MODE_TXPR(x)                    EMAC_DMA_MODE_TXPR(x)
4333 #define GMAC_DMA_MODE_PR_MASK                    EMAC_DMA_MODE_PR_MASK
4334 #define GMAC_DMA_MODE_PR_SHIFT                   EMAC_DMA_MODE_PR_SHIFT
4335 #define GMAC_DMA_MODE_PR_WIDTH                   EMAC_DMA_MODE_PR_WIDTH
4336 #define GMAC_DMA_MODE_PR(x)                      EMAC_DMA_MODE_PR(x)
4337 #define GMAC_DMA_MODE_INTM_MASK                  EMAC_DMA_MODE_INTM_MASK
4338 #define GMAC_DMA_MODE_INTM_SHIFT                 EMAC_DMA_MODE_INTM_SHIFT
4339 #define GMAC_DMA_MODE_INTM_WIDTH                 EMAC_DMA_MODE_INTM_WIDTH
4340 #define GMAC_DMA_MODE_INTM(x)                    EMAC_DMA_MODE_INTM(x)
4341 /*! @} */
4342 
4343 /*! @name DMA_SYSBUS_MODE -  */
4344 /*! @{ */
4345 #define GMAC_DMA_SYSBUS_MODE_FB_MASK             EMAC_DMA_SYSBUS_MODE_FB_MASK
4346 #define GMAC_DMA_SYSBUS_MODE_FB_SHIFT            EMAC_DMA_SYSBUS_MODE_FB_SHIFT
4347 #define GMAC_DMA_SYSBUS_MODE_FB_WIDTH            EMAC_DMA_SYSBUS_MODE_FB_WIDTH
4348 #define GMAC_DMA_SYSBUS_MODE_FB(x)               EMAC_DMA_SYSBUS_MODE_FB(x)
4349 #define GMAC_DMA_SYSBUS_MODE_AAL_MASK            EMAC_DMA_SYSBUS_MODE_AAL_MASK
4350 #define GMAC_DMA_SYSBUS_MODE_AAL_SHIFT           EMAC_DMA_SYSBUS_MODE_AAL_SHIFT
4351 #define GMAC_DMA_SYSBUS_MODE_AAL_WIDTH           EMAC_DMA_SYSBUS_MODE_AAL_WIDTH
4352 #define GMAC_DMA_SYSBUS_MODE_AAL(x)              EMAC_DMA_SYSBUS_MODE_AAL(x)
4353 #define GMAC_DMA_SYSBUS_MODE_MB_MASK             EMAC_DMA_SYSBUS_MODE_MB_MASK
4354 #define GMAC_DMA_SYSBUS_MODE_MB_SHIFT            EMAC_DMA_SYSBUS_MODE_MB_SHIFT
4355 #define GMAC_DMA_SYSBUS_MODE_MB_WIDTH            EMAC_DMA_SYSBUS_MODE_MB_WIDTH
4356 #define GMAC_DMA_SYSBUS_MODE_MB(x)               EMAC_DMA_SYSBUS_MODE_MB(x)
4357 #define GMAC_DMA_SYSBUS_MODE_RB_MASK             EMAC_DMA_SYSBUS_MODE_RB_MASK
4358 #define GMAC_DMA_SYSBUS_MODE_RB_SHIFT            EMAC_DMA_SYSBUS_MODE_RB_SHIFT
4359 #define GMAC_DMA_SYSBUS_MODE_RB_WIDTH            EMAC_DMA_SYSBUS_MODE_RB_WIDTH
4360 #define GMAC_DMA_SYSBUS_MODE_RB(x)               EMAC_DMA_SYSBUS_MODE_RB(x)
4361 /*! @} */
4362 
4363 /*! @name DMA_INTERRUPT_STATUS -  */
4364 /*! @{ */
4365 #define GMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK     EMAC_DMA_INTERRUPT_STATUS_DC0IS_MASK
4366 #define GMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT    EMAC_DMA_INTERRUPT_STATUS_DC0IS_SHIFT
4367 #define GMAC_DMA_INTERRUPT_STATUS_DC0IS_WIDTH    EMAC_DMA_INTERRUPT_STATUS_DC0IS_WIDTH
4368 #define GMAC_DMA_INTERRUPT_STATUS_DC0IS(x)       EMAC_DMA_INTERRUPT_STATUS_DC0IS(x)
4369 #define GMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK     EMAC_DMA_INTERRUPT_STATUS_DC1IS_MASK
4370 #define GMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT    EMAC_DMA_INTERRUPT_STATUS_DC1IS_SHIFT
4371 #define GMAC_DMA_INTERRUPT_STATUS_DC1IS_WIDTH    EMAC_DMA_INTERRUPT_STATUS_DC1IS_WIDTH
4372 #define GMAC_DMA_INTERRUPT_STATUS_DC1IS(x)       EMAC_DMA_INTERRUPT_STATUS_DC1IS(x)
4373 #define GMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK     EMAC_DMA_INTERRUPT_STATUS_MTLIS_MASK
4374 #define GMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT    EMAC_DMA_INTERRUPT_STATUS_MTLIS_SHIFT
4375 #define GMAC_DMA_INTERRUPT_STATUS_MTLIS_WIDTH    EMAC_DMA_INTERRUPT_STATUS_MTLIS_WIDTH
4376 #define GMAC_DMA_INTERRUPT_STATUS_MTLIS(x)       EMAC_DMA_INTERRUPT_STATUS_MTLIS(x)
4377 #define GMAC_DMA_INTERRUPT_STATUS_MACIS_MASK     EMAC_DMA_INTERRUPT_STATUS_MACIS_MASK
4378 #define GMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT    EMAC_DMA_INTERRUPT_STATUS_MACIS_SHIFT
4379 #define GMAC_DMA_INTERRUPT_STATUS_MACIS_WIDTH    EMAC_DMA_INTERRUPT_STATUS_MACIS_WIDTH
4380 #define GMAC_DMA_INTERRUPT_STATUS_MACIS(x)       EMAC_DMA_INTERRUPT_STATUS_MACIS(x)
4381 /*! @} */
4382 
4383 /*! @name DMA_DEBUG_STATUS0 -  */
4384 /*! @{ */
4385 #define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK      EMAC_DMA_DEBUG_STATUS0_AXWHSTS_MASK
4386 #define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT     EMAC_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT
4387 #define GMAC_DMA_DEBUG_STATUS0_AXWHSTS_WIDTH     EMAC_DMA_DEBUG_STATUS0_AXWHSTS_WIDTH
4388 #define GMAC_DMA_DEBUG_STATUS0_AXWHSTS(x)        EMAC_DMA_DEBUG_STATUS0_AXWHSTS(x)
4389 #define GMAC_DMA_DEBUG_STATUS0_RPS0_MASK         EMAC_DMA_DEBUG_STATUS0_RPS0_MASK
4390 #define GMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT        EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT
4391 #define GMAC_DMA_DEBUG_STATUS0_RPS0_WIDTH        EMAC_DMA_DEBUG_STATUS0_RPS0_WIDTH
4392 #define GMAC_DMA_DEBUG_STATUS0_RPS0(x)           EMAC_DMA_DEBUG_STATUS0_RPS0(x)
4393 #define GMAC_DMA_DEBUG_STATUS0_TPS0_MASK         EMAC_DMA_DEBUG_STATUS0_TPS0_MASK
4394 #define GMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT        EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT
4395 #define GMAC_DMA_DEBUG_STATUS0_TPS0_WIDTH        EMAC_DMA_DEBUG_STATUS0_TPS0_WIDTH
4396 #define GMAC_DMA_DEBUG_STATUS0_TPS0(x)           EMAC_DMA_DEBUG_STATUS0_TPS0(x)
4397 #define GMAC_DMA_DEBUG_STATUS0_RPS1_MASK         EMAC_DMA_DEBUG_STATUS0_RPS1_MASK
4398 #define GMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT        EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT
4399 #define GMAC_DMA_DEBUG_STATUS0_RPS1_WIDTH        EMAC_DMA_DEBUG_STATUS0_RPS1_WIDTH
4400 #define GMAC_DMA_DEBUG_STATUS0_RPS1(x)           EMAC_DMA_DEBUG_STATUS0_RPS1(x)
4401 #define GMAC_DMA_DEBUG_STATUS0_TPS1_MASK         EMAC_DMA_DEBUG_STATUS0_TPS1_MASK
4402 #define GMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT        EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT
4403 #define GMAC_DMA_DEBUG_STATUS0_TPS1_WIDTH        EMAC_DMA_DEBUG_STATUS0_TPS1_WIDTH
4404 #define GMAC_DMA_DEBUG_STATUS0_TPS1(x)           EMAC_DMA_DEBUG_STATUS0_TPS1(x)
4405 /*! @} */
4406 
4407 /*! @name DMA_TBS_CTRL -  */
4408 /*! @{ */
4409 #define GMAC_DMA_TBS_CTRL_FTOV_MASK              EMAC_DMA_TBS_CTRL_FTOV_MASK
4410 #define GMAC_DMA_TBS_CTRL_FTOV_SHIFT             EMAC_DMA_TBS_CTRL_FTOV_SHIFT
4411 #define GMAC_DMA_TBS_CTRL_FTOV_WIDTH             EMAC_DMA_TBS_CTRL_FTOV_WIDTH
4412 #define GMAC_DMA_TBS_CTRL_FTOV(x)                EMAC_DMA_TBS_CTRL_FTOV(x)
4413 #define GMAC_DMA_TBS_CTRL_FGOS_MASK              EMAC_DMA_TBS_CTRL_FGOS_MASK
4414 #define GMAC_DMA_TBS_CTRL_FGOS_SHIFT             EMAC_DMA_TBS_CTRL_FGOS_SHIFT
4415 #define GMAC_DMA_TBS_CTRL_FGOS_WIDTH             EMAC_DMA_TBS_CTRL_FGOS_WIDTH
4416 #define GMAC_DMA_TBS_CTRL_FGOS(x)                EMAC_DMA_TBS_CTRL_FGOS(x)
4417 #define GMAC_DMA_TBS_CTRL_FTOS_MASK              EMAC_DMA_TBS_CTRL_FTOS_MASK
4418 #define GMAC_DMA_TBS_CTRL_FTOS_SHIFT             EMAC_DMA_TBS_CTRL_FTOS_SHIFT
4419 #define GMAC_DMA_TBS_CTRL_FTOS_WIDTH             EMAC_DMA_TBS_CTRL_FTOS_WIDTH
4420 #define GMAC_DMA_TBS_CTRL_FTOS(x)                EMAC_DMA_TBS_CTRL_FTOS(x)
4421 /*! @} */
4422 
4423 /*! @name DMA_SAFETY_INTERRUPT_STATUS -  */
4424 /*! @{ */
4425 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_MASK
4426 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_SHIFT
4427 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS_WIDTH
4428 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS(x)
4429 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_MASK
4430 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_SHIFT
4431 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS_WIDTH
4432 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_DEUIS(x)
4433 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_MASK
4434 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_SHIFT
4435 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS_WIDTH
4436 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSCIS(x)
4437 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK
4438 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_SHIFT
4439 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_WIDTH
4440 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS(x)
4441 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK
4442 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_SHIFT
4443 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_WIDTH EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_WIDTH
4444 #define GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS(x) EMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS(x)
4445 /*! @} */
4446 
4447 /*! @name DMA_CH0_CONTROL -  */
4448 /*! @{ */
4449 #define GMAC_DMA_CH0_CONTROL_PBLx8_MASK          EMAC_DMA_CH0_CONTROL_PBLx8_MASK
4450 #define GMAC_DMA_CH0_CONTROL_PBLx8_SHIFT         EMAC_DMA_CH0_CONTROL_PBLx8_SHIFT
4451 #define GMAC_DMA_CH0_CONTROL_PBLx8_WIDTH         EMAC_DMA_CH0_CONTROL_PBLx8_WIDTH
4452 #define GMAC_DMA_CH0_CONTROL_PBLx8(x)            EMAC_DMA_CH0_CONTROL_PBLx8(x)
4453 #define GMAC_DMA_CH0_CONTROL_DSL_MASK            EMAC_DMA_CH0_CONTROL_DSL_MASK
4454 #define GMAC_DMA_CH0_CONTROL_DSL_SHIFT           EMAC_DMA_CH0_CONTROL_DSL_SHIFT
4455 #define GMAC_DMA_CH0_CONTROL_DSL_WIDTH           EMAC_DMA_CH0_CONTROL_DSL_WIDTH
4456 #define GMAC_DMA_CH0_CONTROL_DSL(x)              EMAC_DMA_CH0_CONTROL_DSL(x)
4457 /*! @} */
4458 
4459 /*! @name DMA_CH0_TX_CONTROL -  */
4460 /*! @{ */
4461 #define GMAC_DMA_CH0_TX_CONTROL_ST_MASK          EMAC_DMA_CH0_TX_CONTROL_ST_MASK
4462 #define GMAC_DMA_CH0_TX_CONTROL_ST_SHIFT         EMAC_DMA_CH0_TX_CONTROL_ST_SHIFT
4463 #define GMAC_DMA_CH0_TX_CONTROL_ST_WIDTH         EMAC_DMA_CH0_TX_CONTROL_ST_WIDTH
4464 #define GMAC_DMA_CH0_TX_CONTROL_ST(x)            EMAC_DMA_CH0_TX_CONTROL_ST(x)
4465 #define GMAC_DMA_CH0_TX_CONTROL_TCW_MASK         EMAC_DMA_CH0_TX_CONTROL_TCW_MASK
4466 #define GMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT        EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT
4467 #define GMAC_DMA_CH0_TX_CONTROL_TCW_WIDTH        EMAC_DMA_CH0_TX_CONTROL_TCW_WIDTH
4468 #define GMAC_DMA_CH0_TX_CONTROL_TCW(x)           EMAC_DMA_CH0_TX_CONTROL_TCW(x)
4469 #define GMAC_DMA_CH0_TX_CONTROL_OSF_MASK         EMAC_DMA_CH0_TX_CONTROL_OSF_MASK
4470 #define GMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT        EMAC_DMA_CH0_TX_CONTROL_OSF_SHIFT
4471 #define GMAC_DMA_CH0_TX_CONTROL_OSF_WIDTH        EMAC_DMA_CH0_TX_CONTROL_OSF_WIDTH
4472 #define GMAC_DMA_CH0_TX_CONTROL_OSF(x)           EMAC_DMA_CH0_TX_CONTROL_OSF(x)
4473 #define GMAC_DMA_CH0_TX_CONTROL_TxPBL_MASK       EMAC_DMA_CH0_TX_CONTROL_TxPBL_MASK
4474 #define GMAC_DMA_CH0_TX_CONTROL_TxPBL_SHIFT      EMAC_DMA_CH0_TX_CONTROL_TxPBL_SHIFT
4475 #define GMAC_DMA_CH0_TX_CONTROL_TxPBL_WIDTH      EMAC_DMA_CH0_TX_CONTROL_TxPBL_WIDTH
4476 #define GMAC_DMA_CH0_TX_CONTROL_TxPBL(x)         EMAC_DMA_CH0_TX_CONTROL_TxPBL(x)
4477 #define GMAC_DMA_CH0_TX_CONTROL_ETIC_MASK        EMAC_DMA_CH0_TX_CONTROL_ETIC_MASK
4478 #define GMAC_DMA_CH0_TX_CONTROL_ETIC_SHIFT       EMAC_DMA_CH0_TX_CONTROL_ETIC_SHIFT
4479 #define GMAC_DMA_CH0_TX_CONTROL_ETIC_WIDTH       EMAC_DMA_CH0_TX_CONTROL_ETIC_WIDTH
4480 #define GMAC_DMA_CH0_TX_CONTROL_ETIC(x)          EMAC_DMA_CH0_TX_CONTROL_ETIC(x)
4481 #define GMAC_DMA_CH0_TX_CONTROL_EDSE_MASK        EMAC_DMA_CH0_TX_CONTROL_EDSE_MASK
4482 #define GMAC_DMA_CH0_TX_CONTROL_EDSE_SHIFT       EMAC_DMA_CH0_TX_CONTROL_EDSE_SHIFT
4483 #define GMAC_DMA_CH0_TX_CONTROL_EDSE_WIDTH       EMAC_DMA_CH0_TX_CONTROL_EDSE_WIDTH
4484 #define GMAC_DMA_CH0_TX_CONTROL_EDSE(x)          EMAC_DMA_CH0_TX_CONTROL_EDSE(x)
4485 /*! @} */
4486 
4487 /*! @name DMA_CH0_RX_CONTROL -  */
4488 /*! @{ */
4489 #define GMAC_DMA_CH0_RX_CONTROL_SR_MASK          EMAC_DMA_CH0_RX_CONTROL_SR_MASK
4490 #define GMAC_DMA_CH0_RX_CONTROL_SR_SHIFT         EMAC_DMA_CH0_RX_CONTROL_SR_SHIFT
4491 #define GMAC_DMA_CH0_RX_CONTROL_SR_WIDTH         EMAC_DMA_CH0_RX_CONTROL_SR_WIDTH
4492 #define GMAC_DMA_CH0_RX_CONTROL_SR(x)            EMAC_DMA_CH0_RX_CONTROL_SR(x)
4493 #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_MASK    EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_MASK
4494 #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_SHIFT   EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_SHIFT
4495 #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_WIDTH   EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0_WIDTH
4496 #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0(x)      EMAC_DMA_CH0_RX_CONTROL_RBSZ_x_0(x)
4497 #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_MASK   EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_MASK
4498 #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_SHIFT  EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_SHIFT
4499 #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_WIDTH  EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y_WIDTH
4500 #define GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y(x)     EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y(x)
4501 #define GMAC_DMA_CH0_RX_CONTROL_RxPBL_MASK       EMAC_DMA_CH0_RX_CONTROL_RxPBL_MASK
4502 #define GMAC_DMA_CH0_RX_CONTROL_RxPBL_SHIFT      EMAC_DMA_CH0_RX_CONTROL_RxPBL_SHIFT
4503 #define GMAC_DMA_CH0_RX_CONTROL_RxPBL_WIDTH      EMAC_DMA_CH0_RX_CONTROL_RxPBL_WIDTH
4504 #define GMAC_DMA_CH0_RX_CONTROL_RxPBL(x)         EMAC_DMA_CH0_RX_CONTROL_RxPBL(x)
4505 #define GMAC_DMA_CH0_RX_CONTROL_ERIC_MASK        EMAC_DMA_CH0_RX_CONTROL_ERIC_MASK
4506 #define GMAC_DMA_CH0_RX_CONTROL_ERIC_SHIFT       EMAC_DMA_CH0_RX_CONTROL_ERIC_SHIFT
4507 #define GMAC_DMA_CH0_RX_CONTROL_ERIC_WIDTH       EMAC_DMA_CH0_RX_CONTROL_ERIC_WIDTH
4508 #define GMAC_DMA_CH0_RX_CONTROL_ERIC(x)          EMAC_DMA_CH0_RX_CONTROL_ERIC(x)
4509 #define GMAC_DMA_CH0_RX_CONTROL_RPF_MASK         EMAC_DMA_CH0_RX_CONTROL_RPF_MASK
4510 #define GMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT        EMAC_DMA_CH0_RX_CONTROL_RPF_SHIFT
4511 #define GMAC_DMA_CH0_RX_CONTROL_RPF_WIDTH        EMAC_DMA_CH0_RX_CONTROL_RPF_WIDTH
4512 #define GMAC_DMA_CH0_RX_CONTROL_RPF(x)           EMAC_DMA_CH0_RX_CONTROL_RPF(x)
4513 /*! @} */
4514 
4515 /*! @name DMA_CH0_TXDESC_LIST_ADDRESS -  */
4516 /*! @{ */
4517 #define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK
4518 #define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT
4519 #define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_WIDTH EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_WIDTH
4520 #define GMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(x) EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(x)
4521 /*! @} */
4522 
4523 /*! @name DMA_CH0_RXDESC_LIST_ADDRESS -  */
4524 /*! @{ */
4525 #define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK
4526 #define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT
4527 #define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_WIDTH EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_WIDTH
4528 #define GMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(x) EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(x)
4529 /*! @} */
4530 
4531 /*! @name DMA_CH0_TXDESC_TAIL_POINTER -  */
4532 /*! @{ */
4533 #define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK
4534 #define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT
4535 #define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_WIDTH EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_WIDTH
4536 #define GMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(x) EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(x)
4537 /*! @} */
4538 
4539 /*! @name DMA_CH0_RXDESC_TAIL_POINTER -  */
4540 /*! @{ */
4541 #define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK
4542 #define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT
4543 #define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_WIDTH EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_WIDTH
4544 #define GMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(x) EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(x)
4545 /*! @} */
4546 
4547 /*! @name DMA_CH0_TXDESC_RING_LENGTH -  */
4548 /*! @{ */
4549 #define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK
4550 #define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT
4551 #define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_WIDTH EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_WIDTH
4552 #define GMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(x)  EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(x)
4553 /*! @} */
4554 
4555 /*! @name DMA_CH0_RXDESC_RING_LENGTH -  */
4556 /*! @{ */
4557 #define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK
4558 #define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT
4559 #define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_WIDTH EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_WIDTH
4560 #define GMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(x)  EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(x)
4561 /*! @} */
4562 
4563 /*! @name DMA_CH0_INTERRUPT_ENABLE -  */
4564 /*! @{ */
4565 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK   EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK
4566 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT  EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_SHIFT
4567 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_WIDTH  EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_WIDTH
4568 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE(x)     EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE(x)
4569 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK  EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_MASK
4570 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_SHIFT
4571 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE_WIDTH
4572 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE(x)    EMAC_DMA_CH0_INTERRUPT_ENABLE_TXSE(x)
4573 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK  EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_MASK
4574 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_SHIFT
4575 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE_WIDTH
4576 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE(x)    EMAC_DMA_CH0_INTERRUPT_ENABLE_TBUE(x)
4577 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK   EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK
4578 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT  EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_SHIFT
4579 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_WIDTH  EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_WIDTH
4580 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE(x)     EMAC_DMA_CH0_INTERRUPT_ENABLE_RIE(x)
4581 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK  EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_MASK
4582 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_SHIFT
4583 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE_WIDTH
4584 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE(x)    EMAC_DMA_CH0_INTERRUPT_ENABLE_RBUE(x)
4585 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK   EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_MASK
4586 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT  EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_SHIFT
4587 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_WIDTH  EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE_WIDTH
4588 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RSE(x)     EMAC_DMA_CH0_INTERRUPT_ENABLE_RSE(x)
4589 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK  EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_MASK
4590 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_SHIFT
4591 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE_WIDTH
4592 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE(x)    EMAC_DMA_CH0_INTERRUPT_ENABLE_RWTE(x)
4593 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK  EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_MASK
4594 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_SHIFT
4595 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE_WIDTH
4596 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE(x)    EMAC_DMA_CH0_INTERRUPT_ENABLE_ETIE(x)
4597 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK  EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_MASK
4598 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_SHIFT
4599 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE_WIDTH
4600 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE(x)    EMAC_DMA_CH0_INTERRUPT_ENABLE_ERIE(x)
4601 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK  EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_MASK
4602 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_SHIFT
4603 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE_WIDTH
4604 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE(x)    EMAC_DMA_CH0_INTERRUPT_ENABLE_FBEE(x)
4605 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK  EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_MASK
4606 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_SHIFT
4607 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_WIDTH EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE_WIDTH
4608 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE(x)    EMAC_DMA_CH0_INTERRUPT_ENABLE_CDEE(x)
4609 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK   EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK
4610 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT  EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_SHIFT
4611 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_WIDTH  EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_WIDTH
4612 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE(x)     EMAC_DMA_CH0_INTERRUPT_ENABLE_AIE(x)
4613 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK   EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK
4614 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT  EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_SHIFT
4615 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_WIDTH  EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_WIDTH
4616 #define GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE(x)     EMAC_DMA_CH0_INTERRUPT_ENABLE_NIE(x)
4617 /*! @} */
4618 
4619 /*! @name DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER -  */
4620 /*! @{ */
4621 #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK
4622 #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT
4623 #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH
4624 #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x)
4625 #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK
4626 #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT
4627 #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH
4628 #define GMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x)
4629 /*! @} */
4630 
4631 /*! @name DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS -  */
4632 /*! @{ */
4633 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK
4634 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT
4635 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH
4636 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC(x)
4637 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK
4638 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT
4639 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH
4640 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC(x)
4641 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK
4642 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT
4643 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH
4644 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(x)
4645 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK
4646 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT
4647 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH
4648 #define GMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(x)
4649 /*! @} */
4650 
4651 /*! @name DMA_CH0_CURRENT_APP_TXDESC -  */
4652 /*! @{ */
4653 #define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK
4654 #define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT
4655 #define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH
4656 #define GMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(x) EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(x)
4657 /*! @} */
4658 
4659 /*! @name DMA_CH0_CURRENT_APP_RXDESC -  */
4660 /*! @{ */
4661 #define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK
4662 #define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT
4663 #define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH
4664 #define GMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(x) EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(x)
4665 /*! @} */
4666 
4667 /*! @name DMA_CH0_CURRENT_APP_TXBUFFER -  */
4668 /*! @{ */
4669 #define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK
4670 #define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT
4671 #define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH
4672 #define GMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x)
4673 /*! @} */
4674 
4675 /*! @name DMA_CH0_CURRENT_APP_RXBUFFER -  */
4676 /*! @{ */
4677 #define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK
4678 #define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT
4679 #define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH
4680 #define GMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x)
4681 /*! @} */
4682 
4683 /*! @name DMA_CH0_STATUS -  */
4684 /*! @{ */
4685 #define GMAC_DMA_CH0_STATUS_TI_MASK              EMAC_DMA_CH0_STATUS_TI_MASK
4686 #define GMAC_DMA_CH0_STATUS_TI_SHIFT             EMAC_DMA_CH0_STATUS_TI_SHIFT
4687 #define GMAC_DMA_CH0_STATUS_TI_WIDTH             EMAC_DMA_CH0_STATUS_TI_WIDTH
4688 #define GMAC_DMA_CH0_STATUS_TI(x)                EMAC_DMA_CH0_STATUS_TI(x)
4689 #define GMAC_DMA_CH0_STATUS_TPS_MASK             EMAC_DMA_CH0_STATUS_TPS_MASK
4690 #define GMAC_DMA_CH0_STATUS_TPS_SHIFT            EMAC_DMA_CH0_STATUS_TPS_SHIFT
4691 #define GMAC_DMA_CH0_STATUS_TPS_WIDTH            EMAC_DMA_CH0_STATUS_TPS_WIDTH
4692 #define GMAC_DMA_CH0_STATUS_TPS(x)               EMAC_DMA_CH0_STATUS_TPS(x)
4693 #define GMAC_DMA_CH0_STATUS_TBU_MASK             EMAC_DMA_CH0_STATUS_TBU_MASK
4694 #define GMAC_DMA_CH0_STATUS_TBU_SHIFT            EMAC_DMA_CH0_STATUS_TBU_SHIFT
4695 #define GMAC_DMA_CH0_STATUS_TBU_WIDTH            EMAC_DMA_CH0_STATUS_TBU_WIDTH
4696 #define GMAC_DMA_CH0_STATUS_TBU(x)               EMAC_DMA_CH0_STATUS_TBU(x)
4697 #define GMAC_DMA_CH0_STATUS_RI_MASK              EMAC_DMA_CH0_STATUS_RI_MASK
4698 #define GMAC_DMA_CH0_STATUS_RI_SHIFT             EMAC_DMA_CH0_STATUS_RI_SHIFT
4699 #define GMAC_DMA_CH0_STATUS_RI_WIDTH             EMAC_DMA_CH0_STATUS_RI_WIDTH
4700 #define GMAC_DMA_CH0_STATUS_RI(x)                EMAC_DMA_CH0_STATUS_RI(x)
4701 #define GMAC_DMA_CH0_STATUS_RBU_MASK             EMAC_DMA_CH0_STATUS_RBU_MASK
4702 #define GMAC_DMA_CH0_STATUS_RBU_SHIFT            EMAC_DMA_CH0_STATUS_RBU_SHIFT
4703 #define GMAC_DMA_CH0_STATUS_RBU_WIDTH            EMAC_DMA_CH0_STATUS_RBU_WIDTH
4704 #define GMAC_DMA_CH0_STATUS_RBU(x)               EMAC_DMA_CH0_STATUS_RBU(x)
4705 #define GMAC_DMA_CH0_STATUS_RPS_MASK             EMAC_DMA_CH0_STATUS_RPS_MASK
4706 #define GMAC_DMA_CH0_STATUS_RPS_SHIFT            EMAC_DMA_CH0_STATUS_RPS_SHIFT
4707 #define GMAC_DMA_CH0_STATUS_RPS_WIDTH            EMAC_DMA_CH0_STATUS_RPS_WIDTH
4708 #define GMAC_DMA_CH0_STATUS_RPS(x)               EMAC_DMA_CH0_STATUS_RPS(x)
4709 #define GMAC_DMA_CH0_STATUS_RWT_MASK             EMAC_DMA_CH0_STATUS_RWT_MASK
4710 #define GMAC_DMA_CH0_STATUS_RWT_SHIFT            EMAC_DMA_CH0_STATUS_RWT_SHIFT
4711 #define GMAC_DMA_CH0_STATUS_RWT_WIDTH            EMAC_DMA_CH0_STATUS_RWT_WIDTH
4712 #define GMAC_DMA_CH0_STATUS_RWT(x)               EMAC_DMA_CH0_STATUS_RWT(x)
4713 #define GMAC_DMA_CH0_STATUS_ETI_MASK             EMAC_DMA_CH0_STATUS_ETI_MASK
4714 #define GMAC_DMA_CH0_STATUS_ETI_SHIFT            EMAC_DMA_CH0_STATUS_ETI_SHIFT
4715 #define GMAC_DMA_CH0_STATUS_ETI_WIDTH            EMAC_DMA_CH0_STATUS_ETI_WIDTH
4716 #define GMAC_DMA_CH0_STATUS_ETI(x)               EMAC_DMA_CH0_STATUS_ETI(x)
4717 #define GMAC_DMA_CH0_STATUS_ERI_MASK             EMAC_DMA_CH0_STATUS_ERI_MASK
4718 #define GMAC_DMA_CH0_STATUS_ERI_SHIFT            EMAC_DMA_CH0_STATUS_ERI_SHIFT
4719 #define GMAC_DMA_CH0_STATUS_ERI_WIDTH            EMAC_DMA_CH0_STATUS_ERI_WIDTH
4720 #define GMAC_DMA_CH0_STATUS_ERI(x)               EMAC_DMA_CH0_STATUS_ERI(x)
4721 #define GMAC_DMA_CH0_STATUS_FBE_MASK             EMAC_DMA_CH0_STATUS_FBE_MASK
4722 #define GMAC_DMA_CH0_STATUS_FBE_SHIFT            EMAC_DMA_CH0_STATUS_FBE_SHIFT
4723 #define GMAC_DMA_CH0_STATUS_FBE_WIDTH            EMAC_DMA_CH0_STATUS_FBE_WIDTH
4724 #define GMAC_DMA_CH0_STATUS_FBE(x)               EMAC_DMA_CH0_STATUS_FBE(x)
4725 #define GMAC_DMA_CH0_STATUS_CDE_MASK             EMAC_DMA_CH0_STATUS_CDE_MASK
4726 #define GMAC_DMA_CH0_STATUS_CDE_SHIFT            EMAC_DMA_CH0_STATUS_CDE_SHIFT
4727 #define GMAC_DMA_CH0_STATUS_CDE_WIDTH            EMAC_DMA_CH0_STATUS_CDE_WIDTH
4728 #define GMAC_DMA_CH0_STATUS_CDE(x)               EMAC_DMA_CH0_STATUS_CDE(x)
4729 #define GMAC_DMA_CH0_STATUS_AIS_MASK             EMAC_DMA_CH0_STATUS_AIS_MASK
4730 #define GMAC_DMA_CH0_STATUS_AIS_SHIFT            EMAC_DMA_CH0_STATUS_AIS_SHIFT
4731 #define GMAC_DMA_CH0_STATUS_AIS_WIDTH            EMAC_DMA_CH0_STATUS_AIS_WIDTH
4732 #define GMAC_DMA_CH0_STATUS_AIS(x)               EMAC_DMA_CH0_STATUS_AIS(x)
4733 #define GMAC_DMA_CH0_STATUS_NIS_MASK             EMAC_DMA_CH0_STATUS_NIS_MASK
4734 #define GMAC_DMA_CH0_STATUS_NIS_SHIFT            EMAC_DMA_CH0_STATUS_NIS_SHIFT
4735 #define GMAC_DMA_CH0_STATUS_NIS_WIDTH            EMAC_DMA_CH0_STATUS_NIS_WIDTH
4736 #define GMAC_DMA_CH0_STATUS_NIS(x)               EMAC_DMA_CH0_STATUS_NIS(x)
4737 #define GMAC_DMA_CH0_STATUS_TEB_MASK             EMAC_DMA_CH0_STATUS_TEB_MASK
4738 #define GMAC_DMA_CH0_STATUS_TEB_SHIFT            EMAC_DMA_CH0_STATUS_TEB_SHIFT
4739 #define GMAC_DMA_CH0_STATUS_TEB_WIDTH            EMAC_DMA_CH0_STATUS_TEB_WIDTH
4740 #define GMAC_DMA_CH0_STATUS_TEB(x)               EMAC_DMA_CH0_STATUS_TEB(x)
4741 #define GMAC_DMA_CH0_STATUS_REB_MASK             EMAC_DMA_CH0_STATUS_REB_MASK
4742 #define GMAC_DMA_CH0_STATUS_REB_SHIFT            EMAC_DMA_CH0_STATUS_REB_SHIFT
4743 #define GMAC_DMA_CH0_STATUS_REB_WIDTH            EMAC_DMA_CH0_STATUS_REB_WIDTH
4744 #define GMAC_DMA_CH0_STATUS_REB(x)               EMAC_DMA_CH0_STATUS_REB(x)
4745 /*! @} */
4746 
4747 /*! @name DMA_CH0_MISS_FRAME_CNT -  */
4748 /*! @{ */
4749 #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK     EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK
4750 #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT    EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT
4751 #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC_WIDTH    EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_WIDTH
4752 #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFC(x)       EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(x)
4753 #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_MASK    EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_MASK
4754 #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_SHIFT   EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_SHIFT
4755 #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_WIDTH   EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO_WIDTH
4756 #define GMAC_DMA_CH0_MISS_FRAME_CNT_MFCO(x)      EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO(x)
4757 /*! @} */
4758 
4759 /*! @name DMA_CH0_RXP_ACCEPT_CNT -  */
4760 /*! @{ */
4761 #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK   EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK
4762 #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT  EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT
4763 #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_WIDTH  EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_WIDTH
4764 #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(x)     EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(x)
4765 #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_MASK EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_MASK
4766 #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_SHIFT EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_SHIFT
4767 #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_WIDTH EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF_WIDTH
4768 #define GMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF(x)   EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF(x)
4769 /*! @} */
4770 
4771 /*! @name DMA_CH0_RX_ERI_CNT -  */
4772 /*! @{ */
4773 #define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK        EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK
4774 #define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT       EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT
4775 #define GMAC_DMA_CH0_RX_ERI_CNT_ECNT_WIDTH       EMAC_DMA_CH0_RX_ERI_CNT_ECNT_WIDTH
4776 #define GMAC_DMA_CH0_RX_ERI_CNT_ECNT(x)          EMAC_DMA_CH0_RX_ERI_CNT_ECNT(x)
4777 /*! @} */
4778 
4779 /*! @name DMA_CH1_CONTROL -  */
4780 /*! @{ */
4781 #define GMAC_DMA_CH1_CONTROL_PBLx8_MASK          EMAC_DMA_CH1_CONTROL_PBLx8_MASK
4782 #define GMAC_DMA_CH1_CONTROL_PBLx8_SHIFT         EMAC_DMA_CH1_CONTROL_PBLx8_SHIFT
4783 #define GMAC_DMA_CH1_CONTROL_PBLx8_WIDTH         EMAC_DMA_CH1_CONTROL_PBLx8_WIDTH
4784 #define GMAC_DMA_CH1_CONTROL_PBLx8(x)            EMAC_DMA_CH1_CONTROL_PBLx8(x)
4785 #define GMAC_DMA_CH1_CONTROL_DSL_MASK            EMAC_DMA_CH1_CONTROL_DSL_MASK
4786 #define GMAC_DMA_CH1_CONTROL_DSL_SHIFT           EMAC_DMA_CH1_CONTROL_DSL_SHIFT
4787 #define GMAC_DMA_CH1_CONTROL_DSL_WIDTH           EMAC_DMA_CH1_CONTROL_DSL_WIDTH
4788 #define GMAC_DMA_CH1_CONTROL_DSL(x)              EMAC_DMA_CH1_CONTROL_DSL(x)
4789 /*! @} */
4790 
4791 /*! @name DMA_CH1_TX_CONTROL -  */
4792 /*! @{ */
4793 #define GMAC_DMA_CH1_TX_CONTROL_ST_MASK          EMAC_DMA_CH1_TX_CONTROL_ST_MASK
4794 #define GMAC_DMA_CH1_TX_CONTROL_ST_SHIFT         EMAC_DMA_CH1_TX_CONTROL_ST_SHIFT
4795 #define GMAC_DMA_CH1_TX_CONTROL_ST_WIDTH         EMAC_DMA_CH1_TX_CONTROL_ST_WIDTH
4796 #define GMAC_DMA_CH1_TX_CONTROL_ST(x)            EMAC_DMA_CH1_TX_CONTROL_ST(x)
4797 #define GMAC_DMA_CH1_TX_CONTROL_TCW_MASK         EMAC_DMA_CH1_TX_CONTROL_TCW_MASK
4798 #define GMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT        EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT
4799 #define GMAC_DMA_CH1_TX_CONTROL_TCW_WIDTH        EMAC_DMA_CH1_TX_CONTROL_TCW_WIDTH
4800 #define GMAC_DMA_CH1_TX_CONTROL_TCW(x)           EMAC_DMA_CH1_TX_CONTROL_TCW(x)
4801 #define GMAC_DMA_CH1_TX_CONTROL_OSF_MASK         EMAC_DMA_CH1_TX_CONTROL_OSF_MASK
4802 #define GMAC_DMA_CH1_TX_CONTROL_OSF_SHIFT        EMAC_DMA_CH1_TX_CONTROL_OSF_SHIFT
4803 #define GMAC_DMA_CH1_TX_CONTROL_OSF_WIDTH        EMAC_DMA_CH1_TX_CONTROL_OSF_WIDTH
4804 #define GMAC_DMA_CH1_TX_CONTROL_OSF(x)           EMAC_DMA_CH1_TX_CONTROL_OSF(x)
4805 #define GMAC_DMA_CH1_TX_CONTROL_TxPBL_MASK       EMAC_DMA_CH1_TX_CONTROL_TxPBL_MASK
4806 #define GMAC_DMA_CH1_TX_CONTROL_TxPBL_SHIFT      EMAC_DMA_CH1_TX_CONTROL_TxPBL_SHIFT
4807 #define GMAC_DMA_CH1_TX_CONTROL_TxPBL_WIDTH      EMAC_DMA_CH1_TX_CONTROL_TxPBL_WIDTH
4808 #define GMAC_DMA_CH1_TX_CONTROL_TxPBL(x)         EMAC_DMA_CH1_TX_CONTROL_TxPBL(x)
4809 #define GMAC_DMA_CH1_TX_CONTROL_ETIC_MASK        EMAC_DMA_CH1_TX_CONTROL_ETIC_MASK
4810 #define GMAC_DMA_CH1_TX_CONTROL_ETIC_SHIFT       EMAC_DMA_CH1_TX_CONTROL_ETIC_SHIFT
4811 #define GMAC_DMA_CH1_TX_CONTROL_ETIC_WIDTH       EMAC_DMA_CH1_TX_CONTROL_ETIC_WIDTH
4812 #define GMAC_DMA_CH1_TX_CONTROL_ETIC(x)          EMAC_DMA_CH1_TX_CONTROL_ETIC(x)
4813 #define GMAC_DMA_CH1_TX_CONTROL_EDSE_MASK        EMAC_DMA_CH1_TX_CONTROL_EDSE_MASK
4814 #define GMAC_DMA_CH1_TX_CONTROL_EDSE_SHIFT       EMAC_DMA_CH1_TX_CONTROL_EDSE_SHIFT
4815 #define GMAC_DMA_CH1_TX_CONTROL_EDSE_WIDTH       EMAC_DMA_CH1_TX_CONTROL_EDSE_WIDTH
4816 #define GMAC_DMA_CH1_TX_CONTROL_EDSE(x)          EMAC_DMA_CH1_TX_CONTROL_EDSE(x)
4817 /*! @} */
4818 
4819 /*! @name DMA_CH1_RX_CONTROL -  */
4820 /*! @{ */
4821 #define GMAC_DMA_CH1_RX_CONTROL_SR_MASK          EMAC_DMA_CH1_RX_CONTROL_SR_MASK
4822 #define GMAC_DMA_CH1_RX_CONTROL_SR_SHIFT         EMAC_DMA_CH1_RX_CONTROL_SR_SHIFT
4823 #define GMAC_DMA_CH1_RX_CONTROL_SR_WIDTH         EMAC_DMA_CH1_RX_CONTROL_SR_WIDTH
4824 #define GMAC_DMA_CH1_RX_CONTROL_SR(x)            EMAC_DMA_CH1_RX_CONTROL_SR(x)
4825 #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_MASK    EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_MASK
4826 #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_SHIFT   EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_SHIFT
4827 #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_WIDTH   EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0_WIDTH
4828 #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0(x)      EMAC_DMA_CH1_RX_CONTROL_RBSZ_x_0(x)
4829 #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_MASK   EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_MASK
4830 #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_SHIFT  EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_SHIFT
4831 #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_WIDTH  EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y_WIDTH
4832 #define GMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y(x)     EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_y(x)
4833 #define GMAC_DMA_CH1_RX_CONTROL_RxPBL_MASK       EMAC_DMA_CH1_RX_CONTROL_RxPBL_MASK
4834 #define GMAC_DMA_CH1_RX_CONTROL_RxPBL_SHIFT      EMAC_DMA_CH1_RX_CONTROL_RxPBL_SHIFT
4835 #define GMAC_DMA_CH1_RX_CONTROL_RxPBL_WIDTH      EMAC_DMA_CH1_RX_CONTROL_RxPBL_WIDTH
4836 #define GMAC_DMA_CH1_RX_CONTROL_RxPBL(x)         EMAC_DMA_CH1_RX_CONTROL_RxPBL(x)
4837 #define GMAC_DMA_CH1_RX_CONTROL_ERIC_MASK        EMAC_DMA_CH1_RX_CONTROL_ERIC_MASK
4838 #define GMAC_DMA_CH1_RX_CONTROL_ERIC_SHIFT       EMAC_DMA_CH1_RX_CONTROL_ERIC_SHIFT
4839 #define GMAC_DMA_CH1_RX_CONTROL_ERIC_WIDTH       EMAC_DMA_CH1_RX_CONTROL_ERIC_WIDTH
4840 #define GMAC_DMA_CH1_RX_CONTROL_ERIC(x)          EMAC_DMA_CH1_RX_CONTROL_ERIC(x)
4841 #define GMAC_DMA_CH1_RX_CONTROL_RPF_MASK         EMAC_DMA_CH1_RX_CONTROL_RPF_MASK
4842 #define GMAC_DMA_CH1_RX_CONTROL_RPF_SHIFT        EMAC_DMA_CH1_RX_CONTROL_RPF_SHIFT
4843 #define GMAC_DMA_CH1_RX_CONTROL_RPF_WIDTH        EMAC_DMA_CH1_RX_CONTROL_RPF_WIDTH
4844 #define GMAC_DMA_CH1_RX_CONTROL_RPF(x)           EMAC_DMA_CH1_RX_CONTROL_RPF(x)
4845 /*! @} */
4846 
4847 /*! @name DMA_CH1_TXDESC_LIST_ADDRESS -  */
4848 /*! @{ */
4849 #define GMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK
4850 #define GMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT
4851 #define GMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_WIDTH EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_WIDTH
4852 #define GMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(x) EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(x)
4853 /*! @} */
4854 
4855 /*! @name DMA_CH1_RXDESC_LIST_ADDRESS -  */
4856 /*! @{ */
4857 #define GMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK
4858 #define GMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT
4859 #define GMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_WIDTH EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_WIDTH
4860 #define GMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(x) EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(x)
4861 /*! @} */
4862 
4863 /*! @name DMA_CH1_TXDESC_TAIL_POINTER -  */
4864 /*! @{ */
4865 #define GMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK
4866 #define GMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT
4867 #define GMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_WIDTH EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_WIDTH
4868 #define GMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(x) EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(x)
4869 /*! @} */
4870 
4871 /*! @name DMA_CH1_RXDESC_TAIL_POINTER -  */
4872 /*! @{ */
4873 #define GMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK
4874 #define GMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT
4875 #define GMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_WIDTH EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_WIDTH
4876 #define GMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(x) EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(x)
4877 /*! @} */
4878 
4879 /*! @name DMA_CH1_TXDESC_RING_LENGTH -  */
4880 /*! @{ */
4881 #define GMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK
4882 #define GMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT
4883 #define GMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_WIDTH EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_WIDTH
4884 #define GMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(x)  EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(x)
4885 /*! @} */
4886 
4887 /*! @name DMA_CH1_RXDESC_RING_LENGTH -  */
4888 /*! @{ */
4889 #define GMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK
4890 #define GMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT
4891 #define GMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_WIDTH EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_WIDTH
4892 #define GMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(x)  EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(x)
4893 /*! @} */
4894 
4895 /*! @name DMA_CH1_INTERRUPT_ENABLE -  */
4896 /*! @{ */
4897 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_MASK   EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_MASK
4898 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_SHIFT  EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_SHIFT
4899 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_WIDTH  EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE_WIDTH
4900 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TIE(x)     EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE(x)
4901 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_MASK  EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_MASK
4902 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_SHIFT
4903 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE_WIDTH
4904 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE(x)    EMAC_DMA_CH1_INTERRUPT_ENABLE_TXSE(x)
4905 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_MASK  EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_MASK
4906 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_SHIFT
4907 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE_WIDTH
4908 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE(x)    EMAC_DMA_CH1_INTERRUPT_ENABLE_TBUE(x)
4909 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_MASK   EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_MASK
4910 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_SHIFT  EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_SHIFT
4911 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_WIDTH  EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE_WIDTH
4912 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RIE(x)     EMAC_DMA_CH1_INTERRUPT_ENABLE_RIE(x)
4913 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_MASK  EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_MASK
4914 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_SHIFT
4915 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE_WIDTH
4916 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE(x)    EMAC_DMA_CH1_INTERRUPT_ENABLE_RBUE(x)
4917 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_MASK   EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_MASK
4918 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_SHIFT  EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_SHIFT
4919 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_WIDTH  EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE_WIDTH
4920 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RSE(x)     EMAC_DMA_CH1_INTERRUPT_ENABLE_RSE(x)
4921 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_MASK  EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_MASK
4922 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_SHIFT
4923 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE_WIDTH
4924 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE(x)    EMAC_DMA_CH1_INTERRUPT_ENABLE_RWTE(x)
4925 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_MASK  EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_MASK
4926 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_SHIFT
4927 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE_WIDTH
4928 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE(x)    EMAC_DMA_CH1_INTERRUPT_ENABLE_ETIE(x)
4929 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_MASK  EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_MASK
4930 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_SHIFT
4931 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE_WIDTH
4932 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE(x)    EMAC_DMA_CH1_INTERRUPT_ENABLE_ERIE(x)
4933 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_MASK  EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_MASK
4934 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_SHIFT
4935 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE_WIDTH
4936 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE(x)    EMAC_DMA_CH1_INTERRUPT_ENABLE_FBEE(x)
4937 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_MASK  EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_MASK
4938 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_SHIFT EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_SHIFT
4939 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_WIDTH EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE_WIDTH
4940 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE(x)    EMAC_DMA_CH1_INTERRUPT_ENABLE_CDEE(x)
4941 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_MASK   EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_MASK
4942 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_SHIFT  EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_SHIFT
4943 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_WIDTH  EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE_WIDTH
4944 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_AIE(x)     EMAC_DMA_CH1_INTERRUPT_ENABLE_AIE(x)
4945 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_MASK   EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_MASK
4946 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_SHIFT  EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_SHIFT
4947 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_WIDTH  EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE_WIDTH
4948 #define GMAC_DMA_CH1_INTERRUPT_ENABLE_NIE(x)     EMAC_DMA_CH1_INTERRUPT_ENABLE_NIE(x)
4949 /*! @} */
4950 
4951 /*! @name DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER -  */
4952 /*! @{ */
4953 #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK
4954 #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT
4955 #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_WIDTH
4956 #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x) EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(x)
4957 #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK
4958 #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT
4959 #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_WIDTH
4960 #define GMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x) EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(x)
4961 /*! @} */
4962 
4963 /*! @name DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS -  */
4964 /*! @{ */
4965 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_MASK
4966 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_SHIFT
4967 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC_WIDTH
4968 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC(x) EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC(x)
4969 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_MASK
4970 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_SHIFT
4971 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC_WIDTH
4972 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC(x) EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC(x)
4973 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK
4974 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT
4975 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_WIDTH
4976 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(x) EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(x)
4977 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK
4978 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT
4979 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_WIDTH
4980 #define GMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(x) EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(x)
4981 /*! @} */
4982 
4983 /*! @name DMA_CH1_CURRENT_APP_TXDESC -  */
4984 /*! @{ */
4985 #define GMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK
4986 #define GMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT
4987 #define GMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_WIDTH
4988 #define GMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(x) EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(x)
4989 /*! @} */
4990 
4991 /*! @name DMA_CH1_CURRENT_APP_RXDESC -  */
4992 /*! @{ */
4993 #define GMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK
4994 #define GMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT
4995 #define GMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_WIDTH
4996 #define GMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(x) EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(x)
4997 /*! @} */
4998 
4999 /*! @name DMA_CH1_CURRENT_APP_TXBUFFER -  */
5000 /*! @{ */
5001 #define GMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK
5002 #define GMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT
5003 #define GMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_WIDTH
5004 #define GMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x) EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(x)
5005 /*! @} */
5006 
5007 /*! @name DMA_CH1_CURRENT_APP_RXBUFFER -  */
5008 /*! @{ */
5009 #define GMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK
5010 #define GMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT
5011 #define GMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_WIDTH
5012 #define GMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x) EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(x)
5013 /*! @} */
5014 
5015 /*! @name DMA_CH1_STATUS -  */
5016 /*! @{ */
5017 #define GMAC_DMA_CH1_STATUS_TI_MASK              EMAC_DMA_CH1_STATUS_TI_MASK
5018 #define GMAC_DMA_CH1_STATUS_TI_SHIFT             EMAC_DMA_CH1_STATUS_TI_SHIFT
5019 #define GMAC_DMA_CH1_STATUS_TI_WIDTH             EMAC_DMA_CH1_STATUS_TI_WIDTH
5020 #define GMAC_DMA_CH1_STATUS_TI(x)                EMAC_DMA_CH1_STATUS_TI(x)
5021 #define GMAC_DMA_CH1_STATUS_TPS_MASK             EMAC_DMA_CH1_STATUS_TPS_MASK
5022 #define GMAC_DMA_CH1_STATUS_TPS_SHIFT            EMAC_DMA_CH1_STATUS_TPS_SHIFT
5023 #define GMAC_DMA_CH1_STATUS_TPS_WIDTH            EMAC_DMA_CH1_STATUS_TPS_WIDTH
5024 #define GMAC_DMA_CH1_STATUS_TPS(x)               EMAC_DMA_CH1_STATUS_TPS(x)
5025 #define GMAC_DMA_CH1_STATUS_TBU_MASK             EMAC_DMA_CH1_STATUS_TBU_MASK
5026 #define GMAC_DMA_CH1_STATUS_TBU_SHIFT            EMAC_DMA_CH1_STATUS_TBU_SHIFT
5027 #define GMAC_DMA_CH1_STATUS_TBU_WIDTH            EMAC_DMA_CH1_STATUS_TBU_WIDTH
5028 #define GMAC_DMA_CH1_STATUS_TBU(x)               EMAC_DMA_CH1_STATUS_TBU(x)
5029 #define GMAC_DMA_CH1_STATUS_RI_MASK              EMAC_DMA_CH1_STATUS_RI_MASK
5030 #define GMAC_DMA_CH1_STATUS_RI_SHIFT             EMAC_DMA_CH1_STATUS_RI_SHIFT
5031 #define GMAC_DMA_CH1_STATUS_RI_WIDTH             EMAC_DMA_CH1_STATUS_RI_WIDTH
5032 #define GMAC_DMA_CH1_STATUS_RI(x)                EMAC_DMA_CH1_STATUS_RI(x)
5033 #define GMAC_DMA_CH1_STATUS_RBU_MASK             EMAC_DMA_CH1_STATUS_RBU_MASK
5034 #define GMAC_DMA_CH1_STATUS_RBU_SHIFT            EMAC_DMA_CH1_STATUS_RBU_SHIFT
5035 #define GMAC_DMA_CH1_STATUS_RBU_WIDTH            EMAC_DMA_CH1_STATUS_RBU_WIDTH
5036 #define GMAC_DMA_CH1_STATUS_RBU(x)               EMAC_DMA_CH1_STATUS_RBU(x)
5037 #define GMAC_DMA_CH1_STATUS_RPS_MASK             EMAC_DMA_CH1_STATUS_RPS_MASK
5038 #define GMAC_DMA_CH1_STATUS_RPS_SHIFT            EMAC_DMA_CH1_STATUS_RPS_SHIFT
5039 #define GMAC_DMA_CH1_STATUS_RPS_WIDTH            EMAC_DMA_CH1_STATUS_RPS_WIDTH
5040 #define GMAC_DMA_CH1_STATUS_RPS(x)               EMAC_DMA_CH1_STATUS_RPS(x)
5041 #define GMAC_DMA_CH1_STATUS_RWT_MASK             EMAC_DMA_CH1_STATUS_RWT_MASK
5042 #define GMAC_DMA_CH1_STATUS_RWT_SHIFT            EMAC_DMA_CH1_STATUS_RWT_SHIFT
5043 #define GMAC_DMA_CH1_STATUS_RWT_WIDTH            EMAC_DMA_CH1_STATUS_RWT_WIDTH
5044 #define GMAC_DMA_CH1_STATUS_RWT(x)               EMAC_DMA_CH1_STATUS_RWT(x)
5045 #define GMAC_DMA_CH1_STATUS_ETI_MASK             EMAC_DMA_CH1_STATUS_ETI_MASK
5046 #define GMAC_DMA_CH1_STATUS_ETI_SHIFT            EMAC_DMA_CH1_STATUS_ETI_SHIFT
5047 #define GMAC_DMA_CH1_STATUS_ETI_WIDTH            EMAC_DMA_CH1_STATUS_ETI_WIDTH
5048 #define GMAC_DMA_CH1_STATUS_ETI(x)               EMAC_DMA_CH1_STATUS_ETI(x)
5049 #define GMAC_DMA_CH1_STATUS_ERI_MASK             EMAC_DMA_CH1_STATUS_ERI_MASK
5050 #define GMAC_DMA_CH1_STATUS_ERI_SHIFT            EMAC_DMA_CH1_STATUS_ERI_SHIFT
5051 #define GMAC_DMA_CH1_STATUS_ERI_WIDTH            EMAC_DMA_CH1_STATUS_ERI_WIDTH
5052 #define GMAC_DMA_CH1_STATUS_ERI(x)               EMAC_DMA_CH1_STATUS_ERI(x)
5053 #define GMAC_DMA_CH1_STATUS_FBE_MASK             EMAC_DMA_CH1_STATUS_FBE_MASK
5054 #define GMAC_DMA_CH1_STATUS_FBE_SHIFT            EMAC_DMA_CH1_STATUS_FBE_SHIFT
5055 #define GMAC_DMA_CH1_STATUS_FBE_WIDTH            EMAC_DMA_CH1_STATUS_FBE_WIDTH
5056 #define GMAC_DMA_CH1_STATUS_FBE(x)               EMAC_DMA_CH1_STATUS_FBE(x)
5057 #define GMAC_DMA_CH1_STATUS_CDE_MASK             EMAC_DMA_CH1_STATUS_CDE_MASK
5058 #define GMAC_DMA_CH1_STATUS_CDE_SHIFT            EMAC_DMA_CH1_STATUS_CDE_SHIFT
5059 #define GMAC_DMA_CH1_STATUS_CDE_WIDTH            EMAC_DMA_CH1_STATUS_CDE_WIDTH
5060 #define GMAC_DMA_CH1_STATUS_CDE(x)               EMAC_DMA_CH1_STATUS_CDE(x)
5061 #define GMAC_DMA_CH1_STATUS_AIS_MASK             EMAC_DMA_CH1_STATUS_AIS_MASK
5062 #define GMAC_DMA_CH1_STATUS_AIS_SHIFT            EMAC_DMA_CH1_STATUS_AIS_SHIFT
5063 #define GMAC_DMA_CH1_STATUS_AIS_WIDTH            EMAC_DMA_CH1_STATUS_AIS_WIDTH
5064 #define GMAC_DMA_CH1_STATUS_AIS(x)               EMAC_DMA_CH1_STATUS_AIS(x)
5065 #define GMAC_DMA_CH1_STATUS_NIS_MASK             EMAC_DMA_CH1_STATUS_NIS_MASK
5066 #define GMAC_DMA_CH1_STATUS_NIS_SHIFT            EMAC_DMA_CH1_STATUS_NIS_SHIFT
5067 #define GMAC_DMA_CH1_STATUS_NIS_WIDTH            EMAC_DMA_CH1_STATUS_NIS_WIDTH
5068 #define GMAC_DMA_CH1_STATUS_NIS(x)               EMAC_DMA_CH1_STATUS_NIS(x)
5069 #define GMAC_DMA_CH1_STATUS_TEB_MASK             EMAC_DMA_CH1_STATUS_TEB_MASK
5070 #define GMAC_DMA_CH1_STATUS_TEB_SHIFT            EMAC_DMA_CH1_STATUS_TEB_SHIFT
5071 #define GMAC_DMA_CH1_STATUS_TEB_WIDTH            EMAC_DMA_CH1_STATUS_TEB_WIDTH
5072 #define GMAC_DMA_CH1_STATUS_TEB(x)               EMAC_DMA_CH1_STATUS_TEB(x)
5073 #define GMAC_DMA_CH1_STATUS_REB_MASK             EMAC_DMA_CH1_STATUS_REB_MASK
5074 #define GMAC_DMA_CH1_STATUS_REB_SHIFT            EMAC_DMA_CH1_STATUS_REB_SHIFT
5075 #define GMAC_DMA_CH1_STATUS_REB_WIDTH            EMAC_DMA_CH1_STATUS_REB_WIDTH
5076 #define GMAC_DMA_CH1_STATUS_REB(x)               EMAC_DMA_CH1_STATUS_REB(x)
5077 /*! @} */
5078 
5079 /*! @name DMA_CH1_MISS_FRAME_CNT -  */
5080 /*! @{ */
5081 #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK     EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK
5082 #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT    EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT
5083 #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFC_WIDTH    EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_WIDTH
5084 #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFC(x)       EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(x)
5085 #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_MASK    EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_MASK
5086 #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_SHIFT   EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_SHIFT
5087 #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_WIDTH   EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO_WIDTH
5088 #define GMAC_DMA_CH1_MISS_FRAME_CNT_MFCO(x)      EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO(x)
5089 /*! @} */
5090 
5091 /*! @name DMA_CH1_RXP_ACCEPT_CNT -  */
5092 /*! @{ */
5093 #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK   EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK
5094 #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT  EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT
5095 #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_WIDTH  EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_WIDTH
5096 #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(x)     EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(x)
5097 #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_MASK EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_MASK
5098 #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_SHIFT EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_SHIFT
5099 #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_WIDTH EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF_WIDTH
5100 #define GMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF(x)   EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF(x)
5101 /*! @} */
5102 
5103 /*! @name DMA_CH1_RX_ERI_CNT -  */
5104 /*! @{ */
5105 #define GMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK        EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK
5106 #define GMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT       EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT
5107 #define GMAC_DMA_CH1_RX_ERI_CNT_ECNT_WIDTH       EMAC_DMA_CH1_RX_ERI_CNT_ECNT_WIDTH
5108 #define GMAC_DMA_CH1_RX_ERI_CNT_ECNT(x)          EMAC_DMA_CH1_RX_ERI_CNT_ECNT(x)
5109 /*! @} */
5110 
5111 /*!
5112  * @}
5113  */ /* end of group GMAC_Register_Masks */
5114 
5115 
5116 #ifdef __cplusplus
5117 }
5118 #endif
5119 
5120 /** @} */
5121 
5122 #endif /* EMAC_IP_WRAPPER_H */
5123