1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GMAC_IP_TYPES_H 8 #define GMAC_IP_TYPES_H 9 10 /** 11 * @file 12 * 13 * @addtogroup GMAC_DRIVER GMAC Driver 14 * @{ 15 */ 16 17 #ifdef __cplusplus 18 extern "C"{ 19 #endif 20 21 /*================================================================================================== 22 * INCLUDE FILES 23 * 1) system and project includes 24 * 2) needed interfaces from external units 25 * 3) internal and external interfaces from this unit 26 ==================================================================================================*/ 27 #include "Gmac_Ip_Device_Registers.h" 28 #include "Gmac_Ip_Features.h" 29 #include "Gmac_Ip_Cfg.h" 30 31 /*================================================================================================== 32 * SOURCE FILE VERSION INFORMATION 33 ==================================================================================================*/ 34 #define GMAC_IP_TYPES_VENDOR_ID 43 35 #define GMAC_IP_TYPES_AR_RELEASE_MAJOR_VERSION 4 36 #define GMAC_IP_TYPES_AR_RELEASE_MINOR_VERSION 7 37 #define GMAC_IP_TYPES_AR_RELEASE_REVISION_VERSION 0 38 #define GMAC_IP_TYPES_SW_MAJOR_VERSION 3 39 #define GMAC_IP_TYPES_SW_MINOR_VERSION 0 40 #define GMAC_IP_TYPES_SW_PATCH_VERSION 0 41 42 /*================================================================================================== 43 * FILE VERSION CHECKS 44 ==================================================================================================*/ 45 /* Checks against Gmac_Ip_Device_Registers.h */ 46 #if (GMAC_IP_TYPES_VENDOR_ID != GMAC_IP_DEVICE_REGISTERS_VENDOR_ID) 47 #error "Gmac_Ip_Types.h and Gmac_Ip_Device_Registers.h have different vendor ids" 48 #endif 49 #if (( GMAC_IP_TYPES_AR_RELEASE_MAJOR_VERSION != GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_MAJOR_VERSION) || \ 50 ( GMAC_IP_TYPES_AR_RELEASE_MINOR_VERSION != GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_MINOR_VERSION) || \ 51 ( GMAC_IP_TYPES_AR_RELEASE_REVISION_VERSION != GMAC_IP_DEVICE_REGISTERS_AR_RELEASE_REVISION_VERSION)) 52 #error "AUTOSAR Version Numbers of Gmac_Ip_Types.h and Gmac_Ip_Device_Registers.h are different" 53 #endif 54 #if (( GMAC_IP_TYPES_SW_MAJOR_VERSION != GMAC_IP_DEVICE_REGISTERS_SW_MAJOR_VERSION) || \ 55 ( GMAC_IP_TYPES_SW_MINOR_VERSION != GMAC_IP_DEVICE_REGISTERS_SW_MINOR_VERSION) || \ 56 ( GMAC_IP_TYPES_SW_PATCH_VERSION != GMAC_IP_DEVICE_REGISTERS_SW_PATCH_VERSION)) 57 #error "Software Version Numbers of Gmac_Ip_Types.h and Gmac_Ip_Device_Registers.h are different" 58 #endif 59 60 /* Checks against Gmac_Ip_Features.h */ 61 #if (GMAC_IP_TYPES_VENDOR_ID != GMAC_IP_FEATURES_VENDOR_ID) 62 #error "Gmac_Ip_Types.h and Gmac_Ip_Features.h have different vendor ids" 63 #endif 64 #if (( GMAC_IP_TYPES_AR_RELEASE_MAJOR_VERSION != GMAC_IP_FEATURES_AR_RELEASE_MAJOR_VERSION) || \ 65 ( GMAC_IP_TYPES_AR_RELEASE_MINOR_VERSION != GMAC_IP_FEATURES_AR_RELEASE_MINOR_VERSION) || \ 66 ( GMAC_IP_TYPES_AR_RELEASE_REVISION_VERSION != GMAC_IP_FEATURES_AR_RELEASE_REVISION_VERSION)) 67 #error "AUTOSAR Version Numbers of Gmac_Ip_Types.h and Gmac_Ip_Features.h are different" 68 #endif 69 #if (( GMAC_IP_TYPES_SW_MAJOR_VERSION != GMAC_IP_FEATURES_SW_MAJOR_VERSION) || \ 70 ( GMAC_IP_TYPES_SW_MINOR_VERSION != GMAC_IP_FEATURES_SW_MINOR_VERSION) || \ 71 ( GMAC_IP_TYPES_SW_PATCH_VERSION != GMAC_IP_FEATURES_SW_PATCH_VERSION)) 72 #error "Software Version Numbers of Gmac_Ip_Types.h and Gmac_Ip_Features.h are different" 73 #endif 74 75 /******************************************************************************* 76 * Definitions 77 ******************************************************************************/ 78 79 /*! 80 * @brief Return values 81 * @implements Gmac_Ip_StatusType_structure 82 */ 83 typedef enum 84 { 85 /* Generic error codes */ 86 GMAC_STATUS_SUCCESS = 0x000U, /*!< Generic operation success status */ 87 GMAC_STATUS_ERROR = 0x001U, /*!< Generic operation failure status */ 88 GMAC_STATUS_BUSY = 0x002U, /*!< Generic operation busy status */ 89 GMAC_STATUS_TIMEOUT = 0x003U, /*!< Generic operation timeout status */ 90 GMAC_STATUS_UNSUPPORTED = 0x004U, /*!< Generic operation unsupported status */ 91 GMAC_STATUS_CACHE_ERROR = 0x005U, /*!< Generic operation cache operation failed */ 92 93 /* GMAC specific error codes */ 94 GMAC_STATUS_RX_QUEUE_EMPTY = 0xA01U, /*!< There is no available frame in the receive queue */ 95 GMAC_STATUS_TX_QUEUE_FULL = 0xA02U, /*!< There is no available space for the frame in the transmit queue */ 96 GMAC_STATUS_BUFF_NOT_FOUND = 0xA03U, /*!< The specified buffer was not found in the queue */ 97 GMAC_STATUS_TX_BUFF_BUSY = 0xA04U, /*!< All internal TX buffers are currently in use */ 98 GMAC_STATUS_TX_BUFF_OVERFLOW = 0xA05U /*!< The requested TX buffer length cannot*/ 99 } Gmac_Ip_StatusType; 100 101 /** @cond DRIVER_INTERNAL_USE_ONLY */ 102 /*! 103 * @brief Common interrupt sources 104 * @implements Gmac_Ip_InterruptType_structure 105 */ 106 typedef enum 107 { 108 #if FEATURE_GMAC_RGMII_EN || FEATURE_GMAC_SMII_EN 109 GMAC_MAC_INTERRUPT_RGSMIIIS = GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK, 110 #endif 111 GMAC_MAC_INTERRUPT_PHYIS = GMAC_MAC_INTERRUPT_STATUS_PHYIS_MASK, 112 #if FEATURE_GMAC_PMT_EN 113 GMAC_MAC_INTERRUPT_PMTIS = GMAC_MAC_INTERRUPT_STATUS_PMTIS_MASK, 114 #endif 115 GMAC_MAC_INTERRUPT_MMCIS = GMAC_MAC_INTERRUPT_STATUS_MMCIS_MASK, 116 GMAC_MAC_INTERRUPT_MMCRXIS = GMAC_MAC_INTERRUPT_STATUS_MMCRXIS_MASK, 117 GMAC_MAC_INTERRUPT_MMCTXIS = GMAC_MAC_INTERRUPT_STATUS_MMCTXIS_MASK, 118 GMAC_MAC_INTERRUPT_TSIS = GMAC_MAC_INTERRUPT_STATUS_TSIS_MASK, 119 GMAC_MAC_INTERRUPT_TXSTSIS = GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK, 120 GMAC_MAC_INTERRUPT_RXSTSIS = GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK, 121 GMAC_MAC_INTERRUPT_FPEIS = GMAC_MAC_INTERRUPT_STATUS_FPEIS_MASK, 122 GMAC_MAC_INTERRUPT_MDIOIS = GMAC_MAC_INTERRUPT_STATUS_MDIOIS_MASK, 123 GMAC_MAC_INTERRUPT_MFTIS = GMAC_MAC_INTERRUPT_STATUS_MFTIS_MASK, 124 GMAC_MAC_INTERRUPT_MFRIS = GMAC_MAC_INTERRUPT_STATUS_MFRIS_MASK 125 } Gmac_Ip_InterruptType; 126 /** @endcond */ 127 128 /** @cond DRIVER_INTERNAL_USE_ONLY */ 129 /*! 130 * @brief Channel interrupt sources 131 * @implements Gmac_Ip_ChInterruptType_structure 132 */ 133 typedef enum 134 { 135 GMAC_CH_INTERRUPT_TI = GMAC_DMA_CH0_STATUS_TI_MASK, 136 GMAC_CH_INTERRUPT_TPS = GMAC_DMA_CH0_STATUS_TPS_MASK, 137 GMAC_CH_INTERRUPT_TBU = GMAC_DMA_CH0_STATUS_TBU_MASK, 138 GMAC_CH_INTERRUPT_RI = GMAC_DMA_CH0_STATUS_RI_MASK, 139 GMAC_CH_INTERRUPT_RBU = GMAC_DMA_CH0_STATUS_RBU_MASK, 140 GMAC_CH_INTERRUPT_RPS = GMAC_DMA_CH0_STATUS_RPS_MASK, 141 GMAC_CH_INTERRUPT_RWT = GMAC_DMA_CH0_STATUS_RWT_MASK, 142 GMAC_CH_INTERRUPT_ETI = GMAC_DMA_CH0_STATUS_ETI_MASK, 143 GMAC_CH_INTERRUPT_ERI = GMAC_DMA_CH0_STATUS_ERI_MASK, 144 GMAC_CH_INTERRUPT_FBE = GMAC_DMA_CH0_STATUS_FBE_MASK, 145 GMAC_CH_INTERRUPT_CDE = GMAC_DMA_CH0_STATUS_CDE_MASK, 146 GMAC_CH_INTERRUPT_TEB = GMAC_DMA_CH0_STATUS_TEB_MASK, 147 GMAC_CH_INTERRUPT_REB = GMAC_DMA_CH0_STATUS_REB_MASK 148 } Gmac_Ip_ChInterruptType; 149 /** @endcond */ 150 151 /** @cond DRIVER_INTERNAL_USE_ONLY */ 152 /*! 153 * @brief Configurations related to the operating mode of the MAC. 154 * @implements Gmac_Ip_MacConfigType_structure 155 */ 156 typedef enum 157 { 158 GMAC_MAC_CONFIG_SA_INSERTION = GMAC_MAC_CONFIGURATION_SARC(2U), /*!< Configures MAC address inserted in SA field. */ 159 GMAC_MAC_CONFIG_SA_REPLACEMENT = GMAC_MAC_CONFIGURATION_SARC(3U), /*!< Configures MAC address replaced in SA field. */ 160 GMAC_MAC_CONFIG_CHECKSUM_OFFLOAD = GMAC_MAC_CONFIGURATION_IPC_MASK, /*!< Enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload 161 checksum checking. */ 162 GMAC_MAC_CONFIG_CRC_STRIPPING = GMAC_MAC_CONFIGURATION_CST_MASK, /*!< The last four bytes (FCS) of all packets of Ether type (type field greater than 1,536) 163 are stripped and dropped before forwarding the packet to the application. */ 164 GMAC_MAC_CONFIG_AUTO_PAD = GMAC_MAC_CONFIGURATION_ACS_MASK, /*!< The MAC strips the Pad or FCS field on the incoming packets only if the value of the 165 length field is less than 1,536 bytes. */ 166 GMAC_MAC_CONFIG_JUMBO_PKT_EN = GMAC_MAC_CONFIGURATION_JE_MASK, /*!< The MAC allows jumbo packets of 9,018 bytes (9,022 bytes for VLAN tagged packets). */ 167 GMAC_MAC_CONFIG_LOOPBACK = GMAC_MAC_CONFIGURATION_LM_MASK, /*!< MAC operates in the loopback mode at GMII or MII. */ 168 GMAC_MAC_CONFIG_ENABLE_CRS_FD = GMAC_MAC_CONFIGURATION_ECRSFD_MASK, /*!< The MAC transmitter checks the CRS signal before packet transmission in the full-duplex 169 mode. The MAC starts the transmission only when the CRS signal is low. */ 170 GMAC_MAC_CONFIG_DISABLE_RECEIVE_OWN_HD = GMAC_MAC_CONFIGURATION_DO_MASK, /*!< The MAC disables the reception of packets when the gmii_txen_o is asserted in the 171 half-duplex mode. */ 172 GMAC_MAC_CONFIG_DISABLE_CRS_HD = GMAC_MAC_CONFIGURATION_DCRS_MASK, /*!< The MAC transmitter ignores the (G)MII CRS signal during packet transmission in the 173 half-duplex mode. As a result, no errors are generated because of Loss of Carrier or 174 No Carrier during transmission. */ 175 GMAC_MAC_CONFIG_DISABLE_RETRY = GMAC_MAC_CONFIGURATION_DR_MASK, /*!< The MAC attempts only one transmission. When a collision occurs on the (G)MII interface, 176 the MAC ignores the current packet transmission and reports a Packet Abort with excessive 177 collision error in the Tx packet status. */ 178 GMAC_MAC_CONFIG_DEFERRAL_CHECK_HD = GMAC_MAC_CONFIGURATION_DC_MASK /*!< The deferral check function is enabled in the MAC. The MAC issues a Packet Abort status, 179 along with the excessive deferral error bit set in the Tx packet status, when the Tx 180 state machine is deferred for more than 24,288 bit times in 10/100 Mbps mode (155,680 bits 181 times in 1000/2500 Mbps operation). Deferral begins when the transmitter is ready to transmit, 182 but it is prevented because of an active carrier sense signal (CRS) on (G)MII. */ 183 } Gmac_Ip_MacConfigType; 184 /** @endcond */ 185 186 187 /** @cond DRIVER_INTERNAL_USE_ONLY */ 188 /*! 189 * @brief Configurations related to the MAC filters for incoming frames. 190 */ 191 typedef enum 192 { 193 GMAC_PKT_FILTER_RECV_ALL = (sint32)GMAC_MAC_PACKET_FILTER_RA_MASK, /*!< Passes all received packets to the application, irrespective of whether 194 they pass the address filter or not. */ 195 GMAC_PKT_FILTER_HASH_OR_PERFECT_FILTER = GMAC_MAC_PACKET_FILTER_HPF_MASK, /*!< The address filter passes a packet if it matches either the perfect filtering or 196 hash filtering. */ 197 GMAC_PKT_FILTER_BLOCK_CONTROL_PKTS = GMAC_MAC_PACKET_FILTER_PCF(0U), /*!< Blocks all control packets from reaching the application. */ 198 GMAC_PKT_FILTER_BLOCK_PAUSE_PKTS = GMAC_MAC_PACKET_FILTER_PCF(1U), /*!< Forwards all control packets except Pause packets to the application even 199 if they fail the Address filter. */ 200 GMAC_PKT_FILTER_PASS_ALL_CONTROL_PKTS = GMAC_MAC_PACKET_FILTER_PCF(2U), /*!< Forwards all control packets to the application even if they fail the 201 Address filter. */ 202 GMAC_PKT_FILTER_PASS_CONTROL_PKTS_ADDR_MATCH = GMAC_MAC_PACKET_FILTER_PCF(3U), /*!< Forwards the control packets that pass the Address filter. */ 203 GMAC_PKT_FILTER_DISABLE_BROADCAST = GMAC_MAC_PACKET_FILTER_DBF_MASK, /*!< Blocks all incoming broadcast packets. */ 204 GMAC_PKT_FILTER_PASS_ALL_MULTICAST = GMAC_MAC_PACKET_FILTER_PM_MASK, /*!< All received packets with a multicast destination address are passed. */ 205 GMAC_PKT_FILTER_DST_ADDR_INV_FILTER_EN = GMAC_MAC_PACKET_FILTER_DAIF_MASK, /*!< The Address checking operates in inverse filtering mode for the destination 206 address comparison for both unicast and multicast packets. */ 207 GMAC_PKT_FILTER_HASH_MULTICAST = GMAC_MAC_PACKET_FILTER_HMC_MASK, /*!< The destination address filtering of received multicast packets is done 208 according to the hash table. */ 209 GMAC_PKT_FILTER_HASH_UNICAST = GMAC_MAC_PACKET_FILTER_HUC_MASK, /*!< The destination address filtering of received unicast packets is done 210 according to the hash table. */ 211 GMAC_PKT_FILTER_PROMISCUOUS_MODE = GMAC_MAC_PACKET_FILTER_PR_MASK, /*!< Passes all incoming packets irrespective of the destination or source address. */ 212 } Gmac_Ip_PacketFilterConfigType; 213 /** @endcond */ 214 215 /*! 216 * @brief Statistics counters enumeration 217 * @implements Gmac_Ip_CounterType_structure 218 */ 219 typedef enum 220 { 221 GMAC_CTR_TX_OCTET_COUNT_GOOD_BAD, 222 GMAC_CTR_TX_PACKET_COUNT_GOOD_BAD, 223 GMAC_CTR_TX_BROADCAST_PACKETS_GOOD, 224 GMAC_CTR_TX_MULTICAST_PACKETS_GOOD, 225 GMAC_CTR_TX_64OCTETS_PACKETS_GOOD_BAD, 226 GMAC_CTR_TX_65TO127OCTETS_PACKETS_GOOD_BAD, 227 GMAC_CTR_TX_128TO255OCTETS_PACKETS_GOOD_BAD, 228 GMAC_CTR_TX_256TO511OCTETS_PACKETS_GOOD_BAD, 229 GMAC_CTR_TX_512TO1023OCTETS_PACKETS_GOOD_BAD, 230 GMAC_CTR_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD, 231 GMAC_CTR_TX_UNICAST_PACKETS_GOOD_BAD, 232 GMAC_CTR_TX_MULTICAST_PACKETS_GOOD_BAD, 233 GMAC_CTR_TX_BROADCAST_PACKETS_GOOD_BAD, 234 GMAC_CTR_TX_UNDERFLOW_ERROR_PACKETS, 235 GMAC_CTR_TX_SINGLE_COLLISION_GOOD_PACKETS, 236 GMAC_CTR_TX_MULTIPLE_COLLISION_GOOD_PACKETS, 237 GMAC_CTR_TX_DEFERRED_PACKETS, 238 GMAC_CTR_TX_LATE_COLLISION_PACKETS, 239 GMAC_CTR_TX_EXCESSIVE_COLLISION_PACKETS, 240 GMAC_CTR_TX_CARRIER_ERROR_PACKETS, 241 GMAC_CTR_TX_OCTET_COUNT_GOOD, 242 GMAC_CTR_TX_PACKET_COUNT_GOOD, 243 GMAC_CTR_TX_EXCESSIVE_DEFERRAL_ERROR, 244 GMAC_CTR_TX_PAUSE_PACKETS, 245 GMAC_CTR_TX_VLAN_PACKETS_GOOD, 246 GMAC_CTR_TX_OSIZE_PACKETS_GOOD, 247 GMAC_CTR_RESERVED, 248 GMAC_CTR_RX_PACKETS_COUNT_GOOD_BAD, 249 GMAC_CTR_RX_OCTET_COUNT_GOOD_BAD, 250 GMAC_CTR_RX_OCTET_COUNT_GOOD, 251 GMAC_CTR_RX_BROADCAST_PACKETS_GOOD, 252 GMAC_CTR_RX_MULTICAST_PACKETS_GOOD, 253 GMAC_CTR_RX_CRC_ERROR_PACKETS, 254 GMAC_CTR_RX_ALIGNMENT_ERROR_PACKETS, 255 GMAC_CTR_RX_RUNT_ERROR_PACKETS, 256 GMAC_CTR_RX_JABBER_ERROR_PACKETS, 257 GMAC_CTR_RX_UNDERSIZE_PACKETS_GOOD, 258 GMAC_CTR_RX_OVERSIZE_PACKETS_GOOD, 259 GMAC_CTR_RX_64OCTETS_PACKETS_GOOD_BAD, 260 GMAC_CTR_RX_65TO127OCTETS_PACKETS_GOOD_BAD, 261 GMAC_CTR_RX_128TO255OCTETS_PACKETS_GOOD_BAD, 262 GMAC_CTR_RX_256TO511OCTETS_PACKETS_GOOD_BAD, 263 GMAC_CTR_RX_512TO1023OCTETS_PACKETS_GOOD_BAD, 264 GMAC_CTR_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD, 265 GMAC_CTR_RX_UNICAST_PACKETS_GOOD, 266 GMAC_CTR_RX_LENGTH_ERROR_PACKETS, 267 GMAC_CTR_RX_OUT_OF_RANGE_TYPE_PACKETS, 268 GMAC_CTR_RX_PAUSE_PACKETS, 269 GMAC_CTR_RX_FIFO_OVERFLOW_PACKETS, 270 GMAC_CTR_RX_VLAN_PACKETS_GOOD_BAD, 271 GMAC_CTR_RX_WATCHDOG_ERROR_PACKETS, 272 GMAC_CTR_RX_RECEIVE_ERROR_PACKETS, 273 GMAC_CTR_RX_CONTROL_PACKETS_GOOD, 274 GMAC_CTR_NUMBER_OF_COUNTERS 275 } Gmac_Ip_CounterType; 276 277 /*! 278 * @brief Controller power state indication 279 */ 280 typedef enum 281 { 282 GMAC_PSTATE_INACTIVE = 0U, /* Controller is powered on and Transmitter/Receiver are disabled */ 283 GMAC_PSTATE_ACTIVE = 1U, /* Controller is powered on and Transmitter/Receiver are enabled */ 284 GMAC_PSTATE_SLEEP = 2U, /* Controller is sleeping (WoL or LPI) and waiting for wake-up packet */ 285 GMAC_PSTATE_RESET = 3U /* Controller is resetting its internal logic and registers */ 286 } Gmac_Ip_PowerStateType; 287 288 /*! 289 * @brief Media Independent Interface speed selection 290 * @implements Gmac_Ip_SpeedType_structure 291 */ 292 typedef enum 293 { 294 GMAC_SPEED_1G = 0U, /*!< Speed 1 Gbps. */ 295 GMAC_SPEED_10M = 2U, /*!< Speed 10 Mbps. */ 296 GMAC_SPEED_100M = 3U, /*!< Speed 100 Mbps. */ 297 #if FEATURE_OVERCLOCKED_EN 298 GMAC_SPEED_200M = GMAC_SPEED_100M, /*!< Speed 200 Mbps. */ 299 #endif 300 #if FEATURE_GMAC_SGMII_EN 301 GMAC_SPEED_2500M = 4U /*!< Speed 2500 Mbps. */ 302 #endif 303 } Gmac_Ip_SpeedType; 304 305 /** @cond DRIVER_INTERNAL_USE_ONLY */ 306 /*! 307 * @brief Media Independent Interface full-/half-duplex selection 308 * @implements Gmac_Ip_DuplexType_structure 309 */ 310 typedef enum 311 { 312 GMAC_HALF_DUPLEX = 0U, /*!< Half-duplex mode. */ 313 GMAC_FULL_DUPLEX /*!< Full-duplex mode. */ 314 } Gmac_Ip_DuplexType; 315 /** @endcond */ 316 317 /** @cond DRIVER_INTERNAL_USE_ONLY */ 318 /*! 319 * @brief Media Independent Interface mode selection 320 * @implements Gmac_Ip_MiiModeType_structure 321 */ 322 typedef enum 323 { 324 GMAC_MII_MODE = 0U, /*!< MII mode for data interface. */ 325 #if FEATURE_GMAC_RGMII_EN 326 GMAC_RGMII_MODE = 1U, /*!< RGMII mode for data interface. */ 327 #endif 328 GMAC_RMII_MODE = 4U, /*!< RMII mode for data interface. */ 329 #if FEATURE_GMAC_SGMII_EN 330 GMAC_SGMII_MODE /*!< SGMII mode for data interface. */ 331 #endif 332 } Gmac_Ip_MiiModeType; 333 /** @endcond */ 334 335 /*! 336 * @brief Source/Destination address filter selection 337 * @implements Gmac_Ip_MacAddrFilterType_structure 338 */ 339 typedef enum 340 { 341 GMAC_DST_ADRR_FILTER = 0U, /*!< Destination address filter. */ 342 GMAC_SRC_ADDR_FILTER = 1U, /*!< Source address filter. */ 343 GMAC_SRC_ADDR_INV_FILTER = 2U /*!< Source address inverse filter. */ 344 } Gmac_Ip_MacAddrFilterType; 345 346 /*! 347 * @brief CRC and Pad insertion control 348 * @implements Gmac_Ip_CrcPadControlType_structure 349 */ 350 typedef enum 351 { 352 GMAC_CRC_AND_PAD_INSERTION = 0U, /*!< Appends the CRC at the end of the transmitted packet of length greater than or equal 353 to 60 bytes. Appends padding and CRC to a packet with length less than 60 bytes.*/ 354 GMAC_CRC_INSERTION = 1U, /*!< Appends the CRC at the end of the transmitted packet but it does not append padding. 355 The application should ensure that the padding bytes are present in the packet being transferred. */ 356 GMAC_CRC_INSERTION_DISABLE = 2U, /*!< Does not append the CRC at the end of the transmitted packet. The application should 357 ensure that the padding and CRC bytes are present in the packet being transferred. */ 358 GMAC_CRC_REPLACEMENT = 3U /*!< Replaces the last four bytes of the transmitted packet with recalculated CRC bytes. 359 The application should ensure that the padding and CRC bytes are present in the packet being transferred. */ 360 } Gmac_Ip_CrcPadControlType; 361 362 /*! 363 * @brief Checksum insertion control 364 * @implements Gmac_Ip_ChecksumInsControlType_structure 365 */ 366 typedef enum 367 { 368 GMAC_CHECKSUM_INSERTION_DISABLE = 0U, /*!< Checksum insertion is disabled. */ 369 GMAC_CHECKSUM_INSERTION_IP = 1U, /*!< IP header checksum calculation and insertion are enabled. */ 370 GMAC_CHECKSUM_INSERTION_PROTO_NO_PSEUDOH = 2U, /*!< Protocol checksum calculation and insertion are enabled, 371 but pseudo-header checksum is not calculated in hardware. */ 372 GMAC_CHECKSUM_INSERTION_PROTO_PSEUDOH = 3U /*!< Protocol checksum calculation and insertion are enabled, 373 and pseudo-header checksum is calculated in hardware. */ 374 } Gmac_Ip_ChecksumInsControlType; 375 376 /*! 377 * @brief Type of payload encapsulated in the IP datagram 378 * @implements Gmac_Ip_PayloadType_structure 379 */ 380 typedef enum 381 { 382 GMAC_IP_PAYLOAD_TYPE_UNKNOWN = 0U, /*!< Unknown type or IP payload not processed. */ 383 GMAC_IP_PAYLOAD_TYPE_UDP = 1U, /*!< UDP packet. */ 384 GMAC_IP_PAYLOAD_TYPE_TCP = 2U, /*!< TCP packet. */ 385 GMAC_IP_PAYLOAD_TYPE_ICMP = 3U /*!< ICMP packet. */ 386 } Gmac_Ip_PayloadType; 387 388 /*! 389 * @brief VLAN type 390 * @implements Gmac_Ip_VlanType_structure 391 */ 392 typedef enum 393 { 394 GMAC_VLAN_TYPE_C_VLAN = 0U, /*!< C-VLAN type (0x8100). */ 395 GMAC_VLAN_TYPE_S_VLAN = 1U, /*!< S-VLAN type (0x88A8). */ 396 } Gmac_Ip_VlanType; 397 398 /*! 399 * @brief VLAN tag and type deletion, insertion, or replacement control for transmitted packets 400 * @implements Gmac_Ip_VlanInsControlType_structure 401 */ 402 typedef enum 403 { 404 GMAC_VLAN_TAG_NO_CONTROL = 0U, /*!< The VLAN tag is not altered in the packet to be transmitted. */ 405 GMAC_VLAN_TAG_DELETION = 1U, /*!< The VLAN tag is deleted from the packet to be transmitted. */ 406 GMAC_VLAN_TAG_INSERTION = 2U, /*!< The VLAN tag is inserted in the packet to be transmitted. */ 407 GMAC_VLAN_TAG_REPLACEMENT = 3U /*!< The VLAN tag is replaced in the packet to be transmitted. */ 408 } Gmac_Ip_VlanInsControlType; 409 410 /*! 411 * @brief VLAN tag stripping control for received packets. 412 * @implements Gmac_Ip_VlanStripControlType_structure 413 */ 414 typedef enum 415 { 416 GMAC_VLAN_TAG_DO_NOT_STRIP = 0U, /*!< Does not strip the inner VLAN tag in the received packet. */ 417 GMAC_VLAN_TAG_STRIP_IF_FILTER_PASS = 1U, /*!< Strips the inner VLAN tag in the received packet if the VLAN filter passes. */ 418 GMAC_VLAN_TAG_STRIP_IF_FILTER_FAIL = 2U, /*!< Strips the inner VLAN tag in the received packet if the VLAN filter fails. */ 419 GMAC_VLAN_TAG_ALWAYS_STRIP = 3U, /*!< Always strips the inner VLAN tag in the received packet. */ 420 } Gmac_Ip_VlanStripControlType; 421 422 /** @cond DRIVER_INTERNAL_USE_ONLY */ 423 /*! 424 * @brief VLAN PCP Enumeration 425 */ 426 typedef enum 427 { 428 GMAC_VLAN_PRIORITY_0 = 0x01U, 429 GMAC_VLAN_PRIORITY_1 = 0x02U, 430 GMAC_VLAN_PRIORITY_2 = 0x04U, 431 GMAC_VLAN_PRIORITY_3 = 0x08U, 432 GMAC_VLAN_PRIORITY_4 = 0x10U, 433 GMAC_VLAN_PRIORITY_5 = 0x20U, 434 GMAC_VLAN_PRIORITY_6 = 0x40U, 435 GMAC_VLAN_PRIORITY_7 = 0x80U 436 } Gmac_Ip_VlanPriorityType; 437 /** @endcond */ 438 439 /*! 440 * @brief System time correction offset. 441 * @implements Gmac_Ip_SysTimeCorrOffsetType_structure 442 */ 443 typedef enum 444 { 445 GMAC_SYS_TIME_CORR_POSITIVE = 0U, /*!< Correction value is added to the system time. */ 446 GMAC_SYS_TIME_CORR_NEGATIVE = 1U, /*!< Correction value is subtracted from the system time. */ 447 } Gmac_Ip_SysTimeCorrOffsetType; 448 449 /*! 450 * @brief Transmitter scheduling algorithm. 451 * @implements Gmac_Ip_TxSchedAlgoType_structure 452 */ 453 typedef enum { 454 GMAC_SCHED_ALGO_WRR = 0U, /*!< Weighted round robin algorithm. */ 455 GMAC_SCHED_ALGO_WFQ = 1U, /*!< Weighted fair queueing algorithm. */ 456 GMAC_SCHED_ALGO_DWRR = 2U, /*!< Deficit weighted round robin algorithm. */ 457 GMAC_SCHED_ALGO_SP = 3U /*!< Strict priority algorithm. */ 458 } Gmac_Ip_TxSchedAlgoType; 459 460 /*! 461 * @brief Available Tx threshold values. 462 * @implements Gmac_Ip_TxThresholdType_structure 463 */ 464 typedef enum { 465 GMAC_TRESHOLD_32_BYTES = 0U, 466 GMAC_TRESHOLD_64_BYTES = 1U, 467 GMAC_TRESHOLD_96_BYTES = 2U, 468 GMAC_TRESHOLD_128_BYTES = 3U, 469 GMAC_TRESHOLD_192_BYTES = 4U, 470 GMAC_TRESHOLD_256_BYTES = 5U, 471 GMAC_TRESHOLD_384_BYTES = 6U, 472 GMAC_TRESHOLD_512_BYTES = 7U 473 } Gmac_Ip_TxThresholdType; 474 475 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC) 476 /*! 477 * @brief Automotive safety errors. 478 */ 479 typedef enum { 480 GMAC_SAF_ERR_CSR_EMPTY_DATA = 0x01U, /*!< Unreachable CSR Interface Error */ 481 GMAC_SAF_ERR_ECC = 0x02U, /*!< Uncorrectable ECC Data or Address Error */ 482 GMAC_SAF_ERR_FSM_STATE_PARITY = 0x04U, /*!< Uncorrectable FSM State Parity Error */ 483 GMAC_SAF_ERR_FSM_TIMEOUT = 0x08U, /*!< Uncorrectable FSM Timeout Error */ 484 GMAC_SAF_ERR_DATA_PATH_PARITY = 0x10U, /*!< Uncorrectable Data Path Parity Error */ 485 GMAC_SAF_ERR_MASTER_INTERFACE_TIMEOUT = 0x20U /*!< Uncorrectable Master Interface Timeout Error */ 486 } Gmac_Ip_SafetyErrorType; 487 488 /*! 489 * @brief Callback function invoked when a safety event is encountered 490 */ 491 typedef void (*Gmac_Ip_SafetyCallbackType)(const uint8 Instance, const Gmac_Ip_SafetyErrorType Error); 492 #endif 493 494 /*! 495 * @brief Callback function invoked when a general event is encountered 496 */ 497 typedef void (*Gmac_Ip_CallbackType)(const uint8 Instance); 498 499 /*! 500 * @brief Callback function invoked when a channel event is encountered 501 */ 502 typedef void (*Gmac_Ip_ChCallbackType)(const uint8 Instance, const uint8 Channel); 503 504 /** @cond DRIVER_INTERNAL_USE_ONLY */ 505 /*! 506 * @brief Available queue operation mode values 507 */ 508 typedef enum 509 { 510 GMAC_OP_MODE_DISABLE = 0U, /*!< Queue not enabled */ 511 GMAC_OP_MODE_AVB = 1U, /*!< Queue enabled for Audio-Video Bridging */ 512 GMAC_OP_MODE_DCB_GEN = 2U /*!< Queue enabled for Data Center Bridging or Generic Traffic */ 513 } Gmac_Ip_OperationModeType; 514 /** @endcond */ 515 516 /** @cond DRIVER_INTERNAL_USE_ONLY */ 517 /*! 518 * @brief Send/Receive internal buffer descriptor 519 * @implements Gmac_Ip_BufferDescriptorType_structure 520 */ 521 typedef struct 522 { 523 uint32 Des0; 524 uint32 Des1; 525 uint32 Des2; 526 uint32 Des3; 527 uint32 Info0; 528 uint32 Info1; 529 uint32 Padding0; 530 uint32 Padding1; 531 } Gmac_Ip_BufferDescriptorType; 532 /** @endcond */ 533 534 typedef struct 535 { 536 uint32 TimeInterval; 537 uint8 GateControl; 538 }Gmac_Ip_TxGateControl; 539 540 typedef struct sGmac_Ip_TxTimeAwareShaper 541 { 542 uint32 BaseTimeSecond; 543 uint32 BaseTimeNanoSecond; 544 uint32 CycleTimeSecond; 545 uint32 CycleTimeNanoSecond; 546 uint32 ExtendedTime; 547 uint16 GateControlDepth; 548 uint16 ReleaseAdvanceTime; 549 uint16 HoldAdvanceTime; 550 uint8 PreemptionClassic; 551 const Gmac_Ip_TxGateControl *GateControlList; 552 }Gmac_Ip_TxTimeAwareShaper; 553 554 /*! 555 * @brief Specialization of ring configuration for Tx Rings 556 */ 557 typedef struct sGmac_Ip_TxRingConfigType 558 { 559 uint32 Weight; /*!< Scheduling weight/quantum for DCB queues */ 560 uint32 IdleSlopeCredit; /*!< Idle slope credit for AVB queues */ 561 uint32 SendSlopeCredit; /*!< Send slope credit for AVB queues */ 562 uint32 HiCredit; /*!< High credit limit for AVB queues */ 563 sint32 LoCredit; /*!< Low credit limit for AVB queues */ 564 Gmac_Ip_BufferDescriptorType *RingDesc; /*!< Buffer descriptor ring start address. */ 565 Gmac_Ip_ChCallbackType Callback; /*!< Callback function for current channel. */ 566 uint8 *Buffer; /*!< Buffer data pool start address */ 567 uint32 Interrupts; /*!< Channel interrupt sources. A logical OR of "Gmac_Ip_ChInterruptType". */ 568 uint16 BufferLen; /*!< Length of each individual buffer in a pool */ 569 uint16 RingSize; /*!< Buffer descriptors number. */ 570 uint8 PriorityMask; /*!< A logical OR of "Gmac_Ip_VlanPriorityType". */ 571 uint8 DmaBurstLength; /*!< Maximum number of beats in one DMA block data transfer. */ 572 Gmac_Ip_OperationModeType QueueOpMode; /*!< Queue operation mode */ 573 } Gmac_Ip_TxRingConfigType; 574 575 576 /*! 577 * @brief Specialization of ring configuration for Rx Rings 578 * @implements Gmac_Ip_BufferConfigType_structure 579 */ 580 typedef struct sGmac_Ip_RxRingConfigType 581 { 582 Gmac_Ip_BufferDescriptorType *RingDesc; /*!< Buffer descriptor ring start address. */ 583 Gmac_Ip_ChCallbackType Callback; /*!< Callback function for current channel. */ 584 uint8 *Buffer; /*!< Buffer data pool start address */ 585 uint32 Interrupts; /*!< Channel interrupt sources. A logical OR of "Gmac_Ip_ChInterruptType". */ 586 uint16 BufferLen; /*!< Length of each individual buffer in a pool */ 587 uint16 RingSize; /*!< Buffer descriptors number. */ 588 uint8 PriorityMask; /*!< A logical OR of "Gmac_Ip_VlanPriorityType". */ 589 uint8 DmaBurstLength; /*!< Maximum number of beats in one DMA block data transfer. */ 590 } Gmac_Ip_RxRingConfigType; 591 592 593 /*! 594 * @brief Send/Receive buffer information for the user 595 * @implements Gmac_Ip_BufferType_structure 596 */ 597 typedef struct 598 { 599 uint8 *Data; /*!< Pointer to the data buffer */ 600 uint16 Length; /*!< Length of the data buffer */ 601 } Gmac_Ip_BufferType; 602 603 /*! 604 * @brief Defines the timestamp 605 * @implements Gmac_Ip_TimestampType_structure 606 */ 607 typedef struct 608 { 609 uint32 nanoseconds; /*!< Nanoseconds part of the time. */ 610 uint32 seconds; /*!< The 32 least significant bits of the 48 bits seconds part of the time. */ 611 uint16 secondsHi; /*!< The 16 most significant bits of the 48 bit seconds part of the time. */ 612 } Gmac_Ip_TimestampType; 613 614 /*! 615 * @brief Defines a structure to configure the system time 616 * @implements Gmac_Ip_SysTimeConfigType_structure 617 */ 618 typedef struct 619 { 620 uint8 SubSecondInc; /*!< The value in nanoseconds to be accumulated every clock cycle. */ 621 uint8 SubNanoSecondsInc; /*!< The value in sub-nanoseconds to be accumulated every clock cycle, represented in nanoseconds multiplied by 2^8. 622 For example, if the required increment is 5.3ns, then subSecondInc should be 0x05 and subNanosecondsInc should 623 be 0x4C (0.3 * 2^8). */ 624 Gmac_Ip_TimestampType * InitialTimestamp; /*!< Nanoseconds part of the time. */ 625 } Gmac_Ip_SysTimeConfigType; 626 627 /*! 628 * @brief Transmit options for a particular frame. 629 * @implements Gmac_Ip_TxOptionsType_structure 630 */ 631 typedef struct 632 { 633 boolean NoInt; /*!< Does not generate interrupt on transmit completion. */ 634 Gmac_Ip_CrcPadControlType CrcPadIns; /*!< Controls the CRC and pad insertion for Tx packet. */ 635 Gmac_Ip_ChecksumInsControlType ChecksumIns; /*!< Controls the IP checksum insertion for Tx packet. */ 636 } Gmac_Ip_TxOptionsType; 637 638 /*! 639 * @brief Detailed status of a transmit buffer descriptor 640 * @implements Gmac_Ip_TxInfoType_structure 641 */ 642 typedef struct 643 { 644 uint32 ErrMask; /*!< Mask of GMAC_TX_ERR_*, representing the errors that occurred. */ 645 Gmac_Ip_TimestampType Timestamp; /*!< The timestamp of the transmitted packet. */ 646 } Gmac_Ip_TxInfoType; 647 648 /*! @brief When set, it indicates that the Checksum Offload engine detected an IP header error. */ 649 #define GMAC_TX_ERR_IP_HEADER_ERROR (0x00001U) 650 651 /*! @brief When set, it indicates that the MAC transmitter has experienced a jabber time-out. */ 652 #define GMAC_TX_ERR_JABBER_TIMEOUT (0x04000U) 653 654 /*! @brief When set, it indicates that the GMAC module flushed the packet because of a 655 * software flush command given by the CPU. */ 656 #define GMAC_TX_ERR_PACKET_FLUSHED (0x02000U) 657 658 /*! @brief When set, it indicates that the Checksum Offload engine had a failure and did not 659 * insert any checksum into the encapsulated TCP, UDP, or ICMP payload. */ 660 #define GMAC_TX_ERR_PAYLOAD_CHECKSUM_ERROR (0x01000U) 661 662 /*! @brief When set, it indicates that Loss of Carrier occurred during packet transmission. 663 * This is valid only for the packets transmitted without collision and when the MAC 664 * operates in the half-duplex mode. */ 665 #define GMAC_TX_ERR_LOSS_OF_CARRIER (0x00800U) 666 667 /*! @brief When set, it indicates that the carrier sense signal form the PHY was not asserted 668 * during transmission. */ 669 #define GMAC_TX_ERR_NO_CARRIER (0x00400U) 670 671 /*! @brief When set, it indicates that packet transmission was aborted because a collision 672 * occurred after the collision window (64 byte times including Preamble in MII mode 673 * and 512 byte times including Preamble and Carrier Extension in GMII mode). 674 * This bit is not valid if Underflow Error is set. */ 675 #define GMAC_TX_ERR_LATE_COLLISION (0x00200U) 676 677 /*! @brief When set, it indicates that the transmission was aborted after 16 successive 678 * collisions while attempting to transmit the current packet. */ 679 #define GMAC_TX_ERR_EXCESSIVE_COLLISION (0x00100U) 680 681 /*! @brief When set, it indicates that the transmission ended because of excessive deferral of 682 * over 24,288 bit times (155,680 bits times in 1000 Mbps mode or Jumbo Packet enabled mode) 683 * if deferral check was set at init. */ 684 #define GMAC_TX_ERR_EXCESSIVE_DEFERRAL (0x00008U) 685 686 /*! @brief When set, it indicates that the MAC aborted the packet because the data arrived late 687 * from the system memory. */ 688 #define GMAC_TX_ERR_UNDERFLOW_ERROR (0x00004U) 689 690 /*! 691 * @brief Detailed status of a receive buffer descriptor 692 * @implements Gmac_Ip_RxInfoType_structure 693 */ 694 typedef struct 695 { 696 uint32 ErrMask; /*!< Mask of GMAC_RX_ERR_* , representing the errors that occurred. */ 697 uint16 PktLen; /*!< Byte length of the received packet that was transferred to system memory (including CRC). */ 698 Gmac_Ip_PayloadType PayloadType; /*!< The type of payload encapsulated in the IP datagram (this field is valid only if the 699 Checksum Offloading feature is enabled when initializing the GMAC module). */ 700 boolean Ipv6; /*!< Indicates that the frame is an IPv6 frame (this field is valid only if the 701 Checksum Offloading feature is enabled when initializing the GMAC module). */ 702 boolean Ipv4; /*!< Indicates that the frame is an IPv4 frame (this field is valid only if the 703 Checksum Offloading feature is enabled when initializing the GMAC module). */ 704 boolean IpPayloadErr; /*!< Indicates that an IP payload error has occurred (this field is valid only if the 705 Checksum Offloading feature is enabled when initializing the GMAC module). */ 706 boolean IpHeaderErr; /*!< Indicates that an IP header error has occurred (this field is valid only if the 707 Checksum Offloading feature is enabled when initializing the GMAC module). */ 708 uint16 OuterVlanTag; /*!< Contains the outer VLAN tag of the received packet. */ 709 uint16 InnerVlanTag; /*!< Contains the inner VLAN tag of the received packet. This is valid only when 710 Double VLAN tag processing is enabled. */ 711 Gmac_Ip_TimestampType Timestamp; /*!< The timestamp of the received packet. */ 712 } Gmac_Ip_RxInfoType; 713 714 /*! @brief When this bit is set, it indicates that a CRC Error occurred on the received packet. */ 715 #define GMAC_RX_ERR_CRC_ERROR (0x01000000U) 716 717 /*! @brief When this bit is set, it indicates that the received packet has a non-integer multiple 718 * of bytes (odd nibbles). This bit is valid only in the MII Mode. */ 719 #define GMAC_RX_ERR_DRIBBLE_ERROR (0x00080000U) 720 721 /*! @brief When this bit is set, it indicates that the Receive error signal and Receive data valid signal 722 * are asserted during packet reception. This error also includes carrier extension error 723 * in the GMII and half-duplex mode. */ 724 #define GMAC_RX_ERR_RECEIVE_ERROR (0x00100000U) 725 726 /*! @brief When this bit is set, it indicates that the Receive Watchdog Timer has expired while 727 * receiving the current packet. The current packet is truncated after watchdog timeout. */ 728 #define GMAC_RX_ERR_WATCHDOG_TIMEOUT (0x00400000U) 729 730 /*! @brief When this bit is set, it indicates that the received packet is damaged because of 731 * buffer overflow in Rx FIFO. */ 732 #define GMAC_RX_ERR_OVERFLOW_ERROR (0x00200000U) 733 734 /*! @brief When this bit is set, it indicates that the packet length exceeds the specified maximum 735 * Ethernet size of 1518, 1522, or 2000 bytes (9018 or 9022 bytes if jumbo packet enable is set). */ 736 #define GMAC_RX_ERR_GIANT_PACKET (0x00800000U) 737 738 /*! 739 * @brief Defines the VLAN configuration structure 740 * @implements Gmac_Ip_VlanConfigType_structure 741 */ 742 typedef struct 743 { 744 boolean EnDoubleVlan; /*!< Enables processing of up to two VLAN tags on Tx and Rx (if present). */ 745 boolean EnSvlan; /*!< Enables MAC transmitter and receiver to consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets. */ 746 Gmac_Ip_VlanInsControlType OuterVlanIns; /*!< Selects if outer VLAN tag and type are deleted, inserted or replaced in transmitted packets. */ 747 Gmac_Ip_VlanInsControlType InnerVlanIns; /*!< Selects if inner VLAN tag and type are deleted, inserted or replaced in transmitted packets. Effective only if double 748 VLAN processing is enabled. */ 749 Gmac_Ip_VlanStripControlType OuterVlanStrip; /*!< Selects if outer VLAN tag is stripped in received packets. */ 750 Gmac_Ip_VlanStripControlType InnerVlanStrip; /*!< Selects if inner VLAN tag is stripped in received packets. */ 751 } Gmac_Ip_VlanConfigType; 752 #if (FEATURE_GMAC_VLAN_RX_FILTERS_NUM > 0U) 753 /*! 754 * @brief Defines the VLAN filtering and matching options for received packets 755 * @implements Gmac_Ip_VlanRxFilterType_structure 756 */ 757 typedef struct 758 { 759 boolean EnInnerVlanMatch; /*!< When true, the MAC receiver enables operation on the inner VLAN tag (if present). When false, the MAC receiver enables 760 operation on the outer VLAN tag (if present). */ 761 boolean EnSvlanMatch; /*!< When true, the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets. When false, the MAC 762 receiver enables filtering or matching for C-VLAN (Type = 0x8100) packets. */ 763 boolean DisVlanTypeMatch; /*!< When true, the MAC does not check whether the inner VLAN tag (if inner VLAN match is enabled) is of type S-VLAN or C-VLAN. 764 When false, the MAC filters or matches the inner VLAN tag (if inner VLAN match is enabled) only when VLAN tag type is 765 similar to the one specified by the Enable S-VLAN Match for received Frames.*/ 766 boolean EnInverseMatch; /*!< When true, enables VLAN tag inverse filter match. */ 767 boolean En12bitMatch; /*!< When true, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. 768 When false, the complete 16-bit VLAN tag is compared. */ 769 } Gmac_Ip_VlanRxFilterType; 770 #endif 771 /** @cond DRIVER_INTERNAL_USE_ONLY */ 772 /*! 773 * @brief Defines the GMAC module configuration structure 774 * @implements Gmac_Ip_ConfigType_structure 775 */ 776 typedef struct sGmac_Ip_ConfigType 777 { 778 uint8 RxRingCount; /*!< The number of Receive rings to be used by the driver. */ 779 uint8 TxRingCount; /*!< The number of Transmit rings to be used by the driver. */ 780 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC) 781 uint32 SafetyInterrupts; /*!< Safety interrupt sources. A logical OR of "Gmac_Ip_SafetyErrorType". */ 782 Gmac_Ip_SafetyCallbackType SafetyCallback; /*!< Safety callback function. */ 783 #endif 784 uint32 Interrupts; /*!< General interrupt sources. A logical OR of "Gmac_Ip_InterruptType". */ 785 Gmac_Ip_CallbackType Callback; /*!< Callback function */ 786 Gmac_Ip_MiiModeType MiiMode; /*!< MII mode. */ 787 Gmac_Ip_TxSchedAlgoType TxSchedAlgo; /*!< Configures the global Tx scheduling algorithm affecting all Tx Queues */ 788 /* MAC configuration */ 789 Gmac_Ip_SpeedType Speed; /*!< Speed. */ 790 Gmac_Ip_DuplexType Duplex; /*!< Duplex. */ 791 uint32 MacConfig; /*!< Configures the operating mode of the MAC. A logical OR of "Gmac_Ip_MacConfigType". */ 792 uint32 MacPktFilterConfig; /*!< Configures the MAC packet filter. A logical OR of "Gmac_Ip_PacketFilterConfigType". */ 793 boolean EnableCtrl; /*!< Configures whether the controller is enabled at initialization. */ 794 } Gmac_Ip_ConfigType; 795 /** @endcond */ 796 797 /** @cond DRIVER_INTERNAL_USE_ONLY */ 798 /*! 799 * @brief Internal driver state structure 800 * @implements Gmac_Ip_StateType_structure 801 */ 802 typedef struct sGmac_Ip_StateType 803 { 804 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC) 805 Gmac_Ip_SafetyCallbackType SafetyCallback; /*!< Callback function for safety interrupts. */ 806 #endif 807 Gmac_Ip_CallbackType Callback; /*!< Callback function for general interrupts. */ 808 Gmac_Ip_ChCallbackType RxChCallback[FEATURE_GMAC_NUM_CHANNELS]; /*!< Callback function for receive channels. */ 809 Gmac_Ip_ChCallbackType TxChCallback[FEATURE_GMAC_NUM_CHANNELS]; /*!< Callback function for transmit channels. */ 810 Gmac_Ip_BufferDescriptorType *TxCurrentDesc[FEATURE_GMAC_NUM_CHANNELS]; /*!< The current available transmit buffer descriptor pointer array. */ 811 Gmac_Ip_BufferDescriptorType *RxCurrentDesc[FEATURE_GMAC_NUM_CHANNELS]; /*!< The current available receive buffer descriptor pointer array. */ 812 Gmac_Ip_BufferDescriptorType *RxAllocDesc[FEATURE_GMAC_NUM_CHANNELS]; /*!< Pointer array used for enqueuing Rx buffers provided using Gmac_Ip_ProvideRxBuff. */ 813 uint16 RxRingCount; 814 uint16 TxRingCount; 815 } Gmac_Ip_StateType; 816 /** @endcond */ 817 818 819 #ifdef __cplusplus 820 } 821 #endif 822 823 /** @} */ 824 825 #endif /* GMAC_IP_TYPES_H */ 826
