1 /* 2 ** ################################################################### 3 ** Version: rev. 2.10, 2015-05-27 4 ** Build: b170228 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2017 NXP 11 ** Redistribution and use in source and binary forms, with or without modification, 12 ** are permitted provided that the following conditions are met: 13 ** 14 ** o Redistributions of source code must retain the above copyright notice, this list 15 ** of conditions and the following disclaimer. 16 ** 17 ** o Redistributions in binary form must reproduce the above copyright notice, this 18 ** list of conditions and the following disclaimer in the documentation and/or 19 ** other materials provided with the distribution. 20 ** 21 ** o Neither the name of the copyright holder nor the names of its 22 ** contributors may be used to endorse or promote products derived from this 23 ** software without specific prior written permission. 24 ** 25 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 26 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 29 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 32 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 ** 36 ** http: www.nxp.com 37 ** mail: support@nxp.com 38 ** 39 ** Revisions: 40 ** - rev. 1.0 (2012-06-13) 41 ** Initial version. 42 ** - rev. 1.1 (2012-06-21) 43 ** Update according to reference manual rev. 1. 44 ** - rev. 1.2 (2012-08-01) 45 ** Device type UARTLP changed to UART0. 46 ** - rev. 1.3 (2012-10-04) 47 ** Update according to reference manual rev. 3. 48 ** - rev. 1.4 (2012-11-22) 49 ** MCG module - bit LOLS in MCG_S register renamed to LOLS0. 50 ** NV registers - bit EZPORT_DIS in NV_FOPT register removed. 51 ** - rev. 2.0 (2013-10-29) 52 ** Register accessor macros added to the memory map. 53 ** Symbols for Processor Expert memory map compatibility added to the memory map. 54 ** Startup file for gcc has been updated according to CMSIS 3.2. 55 ** System initialization updated. 56 ** - rev. 2.1 (2014-01-30) 57 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 58 ** - rev. 2.2 (2014-07-16) 59 ** Module access macro module_BASES replaced by module_BASE_PTRS. 60 ** System initialization and startup updated. 61 ** - rev. 2.3 (2014-08-22) 62 ** System initialization updated - default clock config changed. 63 ** - rev. 2.4 (2014-08-28) 64 ** Update of startup files - possibility to override DefaultISR added. 65 ** - rev. 2.5 (2014-10-14) 66 ** Interrupt INT_LPTimer renamed to INT_LPTMR0. 67 ** - rev. 2.6 (2015-01-21) 68 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 69 ** - rev. 2.7 (2015-02-19) 70 ** Renamed interrupt vector LLW to LLWU. 71 ** - rev. 2.8 (2015-05-19) 72 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 73 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 74 ** Added features for PORT. 75 ** - rev. 2.9 (2015-05-25) 76 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 77 ** - rev. 2.10 (2015-05-27) 78 ** Several USB features added. 79 ** 80 ** ################################################################### 81 */ 82 83 #ifndef _MKL25Z4_FEATURES_H_ 84 #define _MKL25Z4_FEATURES_H_ 85 86 /* SOC module features */ 87 88 /* @brief ACMP availability on the SoC. */ 89 #define FSL_FEATURE_SOC_ACMP_COUNT (0) 90 /* @brief ADC16 availability on the SoC. */ 91 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 92 /* @brief ADC12 availability on the SoC. */ 93 #define FSL_FEATURE_SOC_ADC12_COUNT (0) 94 /* @brief AFE availability on the SoC. */ 95 #define FSL_FEATURE_SOC_AFE_COUNT (0) 96 /* @brief AIPS availability on the SoC. */ 97 #define FSL_FEATURE_SOC_AIPS_COUNT (0) 98 /* @brief AOI availability on the SoC. */ 99 #define FSL_FEATURE_SOC_AOI_COUNT (0) 100 /* @brief AXBS availability on the SoC. */ 101 #define FSL_FEATURE_SOC_AXBS_COUNT (0) 102 /* @brief ASMC availability on the SoC. */ 103 #define FSL_FEATURE_SOC_ASMC_COUNT (0) 104 /* @brief CADC availability on the SoC. */ 105 #define FSL_FEATURE_SOC_CADC_COUNT (0) 106 /* @brief FLEXCAN availability on the SoC. */ 107 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) 108 /* @brief MMCAU availability on the SoC. */ 109 #define FSL_FEATURE_SOC_MMCAU_COUNT (0) 110 /* @brief CMP availability on the SoC. */ 111 #define FSL_FEATURE_SOC_CMP_COUNT (1) 112 /* @brief CMT availability on the SoC. */ 113 #define FSL_FEATURE_SOC_CMT_COUNT (0) 114 /* @brief CNC availability on the SoC. */ 115 #define FSL_FEATURE_SOC_CNC_COUNT (0) 116 /* @brief CRC availability on the SoC. */ 117 #define FSL_FEATURE_SOC_CRC_COUNT (0) 118 /* @brief DAC availability on the SoC. */ 119 #define FSL_FEATURE_SOC_DAC_COUNT (1) 120 /* @brief DAC32 availability on the SoC. */ 121 #define FSL_FEATURE_SOC_DAC32_COUNT (0) 122 /* @brief DCDC availability on the SoC. */ 123 #define FSL_FEATURE_SOC_DCDC_COUNT (0) 124 /* @brief DDR availability on the SoC. */ 125 #define FSL_FEATURE_SOC_DDR_COUNT (0) 126 /* @brief DMA availability on the SoC. */ 127 #define FSL_FEATURE_SOC_DMA_COUNT (1) 128 /* @brief EDMA availability on the SoC. */ 129 #define FSL_FEATURE_SOC_EDMA_COUNT (0) 130 /* @brief DMAMUX availability on the SoC. */ 131 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 132 /* @brief DRY availability on the SoC. */ 133 #define FSL_FEATURE_SOC_DRY_COUNT (0) 134 /* @brief DSPI availability on the SoC. */ 135 #define FSL_FEATURE_SOC_DSPI_COUNT (0) 136 /* @brief EMVSIM availability on the SoC. */ 137 #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) 138 /* @brief ENC availability on the SoC. */ 139 #define FSL_FEATURE_SOC_ENC_COUNT (0) 140 /* @brief ENET availability on the SoC. */ 141 #define FSL_FEATURE_SOC_ENET_COUNT (0) 142 /* @brief EWM availability on the SoC. */ 143 #define FSL_FEATURE_SOC_EWM_COUNT (0) 144 /* @brief FB availability on the SoC. */ 145 #define FSL_FEATURE_SOC_FB_COUNT (0) 146 /* @brief FGPIO availability on the SoC. */ 147 #define FSL_FEATURE_SOC_FGPIO_COUNT (0) 148 /* @brief FLEXIO availability on the SoC. */ 149 #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) 150 /* @brief FMC availability on the SoC. */ 151 #define FSL_FEATURE_SOC_FMC_COUNT (0) 152 /* @brief FSKDT availability on the SoC. */ 153 #define FSL_FEATURE_SOC_FSKDT_COUNT (0) 154 /* @brief FTFA availability on the SoC. */ 155 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 156 /* @brief FTFE availability on the SoC. */ 157 #define FSL_FEATURE_SOC_FTFE_COUNT (0) 158 /* @brief FTFL availability on the SoC. */ 159 #define FSL_FEATURE_SOC_FTFL_COUNT (0) 160 /* @brief FTM availability on the SoC. */ 161 #define FSL_FEATURE_SOC_FTM_COUNT (0) 162 /* @brief FTMRA availability on the SoC. */ 163 #define FSL_FEATURE_SOC_FTMRA_COUNT (0) 164 /* @brief FTMRE availability on the SoC. */ 165 #define FSL_FEATURE_SOC_FTMRE_COUNT (0) 166 /* @brief FTMRH availability on the SoC. */ 167 #define FSL_FEATURE_SOC_FTMRH_COUNT (0) 168 /* @brief GPIO availability on the SoC. */ 169 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 170 /* @brief HSADC availability on the SoC. */ 171 #define FSL_FEATURE_SOC_HSADC_COUNT (0) 172 /* @brief I2C availability on the SoC. */ 173 #define FSL_FEATURE_SOC_I2C_COUNT (2) 174 /* @brief I2S availability on the SoC. */ 175 #define FSL_FEATURE_SOC_I2S_COUNT (0) 176 /* @brief ICS availability on the SoC. */ 177 #define FSL_FEATURE_SOC_ICS_COUNT (0) 178 /* @brief INTMUX availability on the SoC. */ 179 #define FSL_FEATURE_SOC_INTMUX_COUNT (0) 180 /* @brief IRQ availability on the SoC. */ 181 #define FSL_FEATURE_SOC_IRQ_COUNT (0) 182 /* @brief KBI availability on the SoC. */ 183 #define FSL_FEATURE_SOC_KBI_COUNT (0) 184 /* @brief SLCD availability on the SoC. */ 185 #define FSL_FEATURE_SOC_SLCD_COUNT (0) 186 /* @brief LCDC availability on the SoC. */ 187 #define FSL_FEATURE_SOC_LCDC_COUNT (0) 188 /* @brief LDO availability on the SoC. */ 189 #define FSL_FEATURE_SOC_LDO_COUNT (0) 190 /* @brief LLWU availability on the SoC. */ 191 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 192 /* @brief LMEM availability on the SoC. */ 193 #define FSL_FEATURE_SOC_LMEM_COUNT (0) 194 /* @brief LPI2C availability on the SoC. */ 195 #define FSL_FEATURE_SOC_LPI2C_COUNT (0) 196 /* @brief LPIT availability on the SoC. */ 197 #define FSL_FEATURE_SOC_LPIT_COUNT (0) 198 /* @brief LPSCI availability on the SoC. */ 199 #define FSL_FEATURE_SOC_LPSCI_COUNT (1) 200 /* @brief LPSPI availability on the SoC. */ 201 #define FSL_FEATURE_SOC_LPSPI_COUNT (0) 202 /* @brief LPTMR availability on the SoC. */ 203 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 204 /* @brief LPTPM availability on the SoC. */ 205 #define FSL_FEATURE_SOC_LPTPM_COUNT (0) 206 /* @brief LPUART availability on the SoC. */ 207 #define FSL_FEATURE_SOC_LPUART_COUNT (0) 208 /* @brief LTC availability on the SoC. */ 209 #define FSL_FEATURE_SOC_LTC_COUNT (0) 210 /* @brief MC availability on the SoC. */ 211 #define FSL_FEATURE_SOC_MC_COUNT (0) 212 /* @brief MCG availability on the SoC. */ 213 #define FSL_FEATURE_SOC_MCG_COUNT (1) 214 /* @brief MCGLITE availability on the SoC. */ 215 #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) 216 /* @brief MCM availability on the SoC. */ 217 #define FSL_FEATURE_SOC_MCM_COUNT (1) 218 /* @brief MMAU availability on the SoC. */ 219 #define FSL_FEATURE_SOC_MMAU_COUNT (0) 220 /* @brief MMDVSQ availability on the SoC. */ 221 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) 222 /* @brief SYSMPU availability on the SoC. */ 223 #define FSL_FEATURE_SOC_SYSMPU_COUNT (0) 224 /* @brief MSCAN availability on the SoC. */ 225 #define FSL_FEATURE_SOC_MSCAN_COUNT (0) 226 /* @brief MSCM availability on the SoC. */ 227 #define FSL_FEATURE_SOC_MSCM_COUNT (0) 228 /* @brief MTB availability on the SoC. */ 229 #define FSL_FEATURE_SOC_MTB_COUNT (1) 230 /* @brief MTBDWT availability on the SoC. */ 231 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 232 /* @brief MU availability on the SoC. */ 233 #define FSL_FEATURE_SOC_MU_COUNT (0) 234 /* @brief NFC availability on the SoC. */ 235 #define FSL_FEATURE_SOC_NFC_COUNT (0) 236 /* @brief OPAMP availability on the SoC. */ 237 #define FSL_FEATURE_SOC_OPAMP_COUNT (0) 238 /* @brief OSC availability on the SoC. */ 239 #define FSL_FEATURE_SOC_OSC_COUNT (1) 240 /* @brief OSC32 availability on the SoC. */ 241 #define FSL_FEATURE_SOC_OSC32_COUNT (0) 242 /* @brief OTFAD availability on the SoC. */ 243 #define FSL_FEATURE_SOC_OTFAD_COUNT (0) 244 /* @brief PDB availability on the SoC. */ 245 #define FSL_FEATURE_SOC_PDB_COUNT (0) 246 /* @brief PCC availability on the SoC. */ 247 #define FSL_FEATURE_SOC_PCC_COUNT (0) 248 /* @brief PGA availability on the SoC. */ 249 #define FSL_FEATURE_SOC_PGA_COUNT (0) 250 /* @brief PIT availability on the SoC. */ 251 #define FSL_FEATURE_SOC_PIT_COUNT (1) 252 /* @brief PMC availability on the SoC. */ 253 #define FSL_FEATURE_SOC_PMC_COUNT (1) 254 /* @brief PORT availability on the SoC. */ 255 #define FSL_FEATURE_SOC_PORT_COUNT (5) 256 /* @brief PWM availability on the SoC. */ 257 #define FSL_FEATURE_SOC_PWM_COUNT (0) 258 /* @brief PWT availability on the SoC. */ 259 #define FSL_FEATURE_SOC_PWT_COUNT (0) 260 /* @brief QuadSPI availability on the SoC. */ 261 #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) 262 /* @brief RCM availability on the SoC. */ 263 #define FSL_FEATURE_SOC_RCM_COUNT (1) 264 /* @brief RFSYS availability on the SoC. */ 265 #define FSL_FEATURE_SOC_RFSYS_COUNT (0) 266 /* @brief RFVBAT availability on the SoC. */ 267 #define FSL_FEATURE_SOC_RFVBAT_COUNT (0) 268 /* @brief RNG availability on the SoC. */ 269 #define FSL_FEATURE_SOC_RNG_COUNT (0) 270 /* @brief RNGB availability on the SoC. */ 271 #define FSL_FEATURE_SOC_RNGB_COUNT (0) 272 /* @brief ROM availability on the SoC. */ 273 #define FSL_FEATURE_SOC_ROM_COUNT (1) 274 /* @brief RSIM availability on the SoC. */ 275 #define FSL_FEATURE_SOC_RSIM_COUNT (0) 276 /* @brief RTC availability on the SoC. */ 277 #define FSL_FEATURE_SOC_RTC_COUNT (1) 278 /* @brief SCG availability on the SoC. */ 279 #define FSL_FEATURE_SOC_SCG_COUNT (0) 280 /* @brief SCI availability on the SoC. */ 281 #define FSL_FEATURE_SOC_SCI_COUNT (0) 282 /* @brief SDHC availability on the SoC. */ 283 #define FSL_FEATURE_SOC_SDHC_COUNT (0) 284 /* @brief SDRAM availability on the SoC. */ 285 #define FSL_FEATURE_SOC_SDRAM_COUNT (0) 286 /* @brief SEMA42 availability on the SoC. */ 287 #define FSL_FEATURE_SOC_SEMA42_COUNT (0) 288 /* @brief SIM availability on the SoC. */ 289 #define FSL_FEATURE_SOC_SIM_COUNT (1) 290 /* @brief SMC availability on the SoC. */ 291 #define FSL_FEATURE_SOC_SMC_COUNT (1) 292 /* @brief SPI availability on the SoC. */ 293 #define FSL_FEATURE_SOC_SPI_COUNT (2) 294 /* @brief TMR availability on the SoC. */ 295 #define FSL_FEATURE_SOC_TMR_COUNT (0) 296 /* @brief TPM availability on the SoC. */ 297 #define FSL_FEATURE_SOC_TPM_COUNT (3) 298 /* @brief TRGMUX availability on the SoC. */ 299 #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) 300 /* @brief TRIAMP availability on the SoC. */ 301 #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) 302 /* @brief TRNG availability on the SoC. */ 303 #define FSL_FEATURE_SOC_TRNG_COUNT (0) 304 /* @brief TSI availability on the SoC. */ 305 #define FSL_FEATURE_SOC_TSI_COUNT (1) 306 /* @brief TSTMR availability on the SoC. */ 307 #define FSL_FEATURE_SOC_TSTMR_COUNT (0) 308 /* @brief UART availability on the SoC. */ 309 #define FSL_FEATURE_SOC_UART_COUNT (2) 310 /* @brief USB availability on the SoC. */ 311 #define FSL_FEATURE_SOC_USB_COUNT (1) 312 /* @brief USBDCD availability on the SoC. */ 313 #define FSL_FEATURE_SOC_USBDCD_COUNT (0) 314 /* @brief USBHS availability on the SoC. */ 315 #define FSL_FEATURE_SOC_USBHS_COUNT (0) 316 /* @brief USBHSDCD availability on the SoC. */ 317 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) 318 /* @brief USBPHY availability on the SoC. */ 319 #define FSL_FEATURE_SOC_USBPHY_COUNT (0) 320 /* @brief VREF availability on the SoC. */ 321 #define FSL_FEATURE_SOC_VREF_COUNT (0) 322 /* @brief WDOG availability on the SoC. */ 323 #define FSL_FEATURE_SOC_WDOG_COUNT (0) 324 /* @brief XBAR availability on the SoC. */ 325 #define FSL_FEATURE_SOC_XBAR_COUNT (0) 326 /* @brief XBARA availability on the SoC. */ 327 #define FSL_FEATURE_SOC_XBARA_COUNT (0) 328 /* @brief XBARB availability on the SoC. */ 329 #define FSL_FEATURE_SOC_XBARB_COUNT (0) 330 /* @brief XCVR availability on the SoC. */ 331 #define FSL_FEATURE_SOC_XCVR_COUNT (0) 332 /* @brief XRDC availability on the SoC. */ 333 #define FSL_FEATURE_SOC_XRDC_COUNT (0) 334 /* @brief ZLL availability on the SoC. */ 335 #define FSL_FEATURE_SOC_ZLL_COUNT (0) 336 337 /* ADC16 module features */ 338 339 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 340 #define FSL_FEATURE_ADC16_HAS_PGA (0) 341 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 342 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 343 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 344 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 345 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 346 #define FSL_FEATURE_ADC16_HAS_DMA (1) 347 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 348 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 349 /* @brief Has FIFO (bit SC4[AFDEP]). */ 350 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 351 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 352 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 353 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 354 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 355 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 356 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 357 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 358 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 359 /* @brief Has HW averaging (bit SC3[AVGE]). */ 360 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 361 /* @brief Has offset correction (register OFS). */ 362 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 363 /* @brief Maximum ADC resolution. */ 364 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 365 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 366 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 367 368 /* CMP module features */ 369 370 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 371 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 372 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 373 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) 374 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 375 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) 376 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 377 #define FSL_FEATURE_CMP_HAS_DMA (1) 378 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 379 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 380 /* @brief Has DAC Test function in CMP (register DACTEST). */ 381 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 382 383 /* COP module features */ 384 385 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ 386 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (0) 387 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ 388 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (0) 389 /* @brief Has more clock sources like MCGIRC */ 390 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (0) 391 /* @brief Has the timeout long and short mode bit (COPC[COPCLKSEL] and COPC[COPCLKS]) */ 392 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (0) 393 394 /* DAC module features */ 395 396 /* @brief Define the size of hardware buffer */ 397 #define FSL_FEATURE_DAC_BUFFER_SIZE (2) 398 /* @brief Define whether the buffer supports watermark event detection or not. */ 399 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (0) 400 /* @brief Define whether the buffer supports watermark selection detection or not. */ 401 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0) 402 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 403 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0) 404 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 405 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0) 406 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 407 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0) 408 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 409 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0) 410 /* @brief Define whether FIFO buffer mode is available or not. */ 411 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) 412 /* @brief Define whether swing buffer mode is available or not.. */ 413 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) 414 415 /* DMA module features */ 416 417 /* @brief Number of DMA channels. */ 418 #define FSL_FEATURE_DMA_MODULE_CHANNEL (4) 419 /* @brief Total number of DMA channels on all modules. */ 420 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMA_COUNT * 4) 421 422 /* DMAMUX module features */ 423 424 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 425 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) 426 /* @brief Total number of DMA channels on all modules. */ 427 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4) 428 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 429 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 430 431 /* FLASH module features */ 432 433 #if defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z128VLK4) 434 /* @brief Is of type FTFA. */ 435 #define FSL_FEATURE_FLASH_IS_FTFA (1) 436 /* @brief Is of type FTFE. */ 437 #define FSL_FEATURE_FLASH_IS_FTFE (0) 438 /* @brief Is of type FTFL. */ 439 #define FSL_FEATURE_FLASH_IS_FTFL (0) 440 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 441 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 442 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 443 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 444 /* @brief Has EEPROM region protection (register FEPROT). */ 445 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 446 /* @brief Has data flash region protection (register FDPROT). */ 447 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 448 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 449 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 450 /* @brief Has flash cache control in FMC module. */ 451 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 452 /* @brief Has flash cache control in MCM module. */ 453 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 454 /* @brief Has flash cache control in MSCM module. */ 455 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 456 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 457 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 458 /* @brief P-Flash start address. */ 459 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 460 /* @brief P-Flash block count. */ 461 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 462 /* @brief P-Flash block size. */ 463 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 464 /* @brief P-Flash sector size. */ 465 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 466 /* @brief P-Flash write unit size. */ 467 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 468 /* @brief P-Flash data path width. */ 469 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 470 /* @brief P-Flash block swap feature. */ 471 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 472 /* @brief P-Flash protection region count. */ 473 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 474 /* @brief Has FlexNVM memory. */ 475 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 476 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 477 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 478 /* @brief FlexNVM block count. */ 479 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 480 /* @brief FlexNVM block size. */ 481 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 482 /* @brief FlexNVM sector size. */ 483 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 484 /* @brief FlexNVM write unit size. */ 485 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 486 /* @brief FlexNVM data path width. */ 487 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 488 /* @brief Has FlexRAM memory. */ 489 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 490 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 491 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 492 /* @brief FlexRAM size. */ 493 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 494 /* @brief Has 0x00 Read 1s Block command. */ 495 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 496 /* @brief Has 0x01 Read 1s Section command. */ 497 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 498 /* @brief Has 0x02 Program Check command. */ 499 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 500 /* @brief Has 0x03 Read Resource command. */ 501 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 502 /* @brief Has 0x06 Program Longword command. */ 503 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 504 /* @brief Has 0x07 Program Phrase command. */ 505 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 506 /* @brief Has 0x08 Erase Flash Block command. */ 507 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 508 /* @brief Has 0x09 Erase Flash Sector command. */ 509 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 510 /* @brief Has 0x0B Program Section command. */ 511 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 512 /* @brief Has 0x40 Read 1s All Blocks command. */ 513 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 514 /* @brief Has 0x41 Read Once command. */ 515 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 516 /* @brief Has 0x43 Program Once command. */ 517 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 518 /* @brief Has 0x44 Erase All Blocks command. */ 519 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 520 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 521 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 522 /* @brief Has 0x46 Swap Control command. */ 523 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 524 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 525 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 526 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 527 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 528 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 529 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 530 /* @brief Has 0x80 Program Partition command. */ 531 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 532 /* @brief Has 0x81 Set FlexRAM Function command. */ 533 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 534 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 535 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 536 /* @brief P-Flash Erase sector command address alignment. */ 537 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 538 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 539 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 540 /* @brief P-Flash Read resource command address alignment. */ 541 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 542 /* @brief P-Flash Program check command address alignment. */ 543 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 544 /* @brief P-Flash Program check command address alignment. */ 545 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 546 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 547 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 548 /* @brief FlexNVM Erase sector command address alignment. */ 549 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 550 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 551 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 552 /* @brief FlexNVM Read resource command address alignment. */ 553 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 554 /* @brief FlexNVM Program check command address alignment. */ 555 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 556 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 557 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 558 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 559 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 560 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 561 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 562 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 563 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 564 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 565 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 566 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 567 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 568 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 569 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 570 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 571 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 572 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 573 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 574 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 575 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 576 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 577 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 578 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 579 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 580 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 581 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 582 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 583 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 584 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 585 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 586 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 587 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 588 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 589 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 590 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 591 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 592 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 593 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 594 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 595 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 596 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 597 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 598 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 599 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 600 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 601 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 602 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 603 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 604 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 605 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 606 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 607 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 608 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 609 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 610 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 611 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 612 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 613 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 614 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 615 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 616 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 617 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 618 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 619 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 620 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z32VLK4) 621 /* @brief Is of type FTFA. */ 622 #define FSL_FEATURE_FLASH_IS_FTFA (1) 623 /* @brief Is of type FTFE. */ 624 #define FSL_FEATURE_FLASH_IS_FTFE (0) 625 /* @brief Is of type FTFL. */ 626 #define FSL_FEATURE_FLASH_IS_FTFL (0) 627 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 628 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 629 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 630 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 631 /* @brief Has EEPROM region protection (register FEPROT). */ 632 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 633 /* @brief Has data flash region protection (register FDPROT). */ 634 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 635 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 636 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 637 /* @brief Has flash cache control in FMC module. */ 638 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 639 /* @brief Has flash cache control in MCM module. */ 640 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 641 /* @brief Has flash cache control in MSCM module. */ 642 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 643 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 644 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 645 /* @brief P-Flash start address. */ 646 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 647 /* @brief P-Flash block count. */ 648 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 649 /* @brief P-Flash block size. */ 650 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) 651 /* @brief P-Flash sector size. */ 652 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 653 /* @brief P-Flash write unit size. */ 654 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 655 /* @brief P-Flash data path width. */ 656 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 657 /* @brief P-Flash block swap feature. */ 658 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 659 /* @brief P-Flash protection region count. */ 660 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 661 /* @brief Has FlexNVM memory. */ 662 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 663 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 664 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 665 /* @brief FlexNVM block count. */ 666 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 667 /* @brief FlexNVM block size. */ 668 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 669 /* @brief FlexNVM sector size. */ 670 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 671 /* @brief FlexNVM write unit size. */ 672 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 673 /* @brief FlexNVM data path width. */ 674 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 675 /* @brief Has FlexRAM memory. */ 676 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 677 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 678 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 679 /* @brief FlexRAM size. */ 680 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 681 /* @brief Has 0x00 Read 1s Block command. */ 682 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 683 /* @brief Has 0x01 Read 1s Section command. */ 684 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 685 /* @brief Has 0x02 Program Check command. */ 686 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 687 /* @brief Has 0x03 Read Resource command. */ 688 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 689 /* @brief Has 0x06 Program Longword command. */ 690 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 691 /* @brief Has 0x07 Program Phrase command. */ 692 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 693 /* @brief Has 0x08 Erase Flash Block command. */ 694 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 695 /* @brief Has 0x09 Erase Flash Sector command. */ 696 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 697 /* @brief Has 0x0B Program Section command. */ 698 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 699 /* @brief Has 0x40 Read 1s All Blocks command. */ 700 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 701 /* @brief Has 0x41 Read Once command. */ 702 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 703 /* @brief Has 0x43 Program Once command. */ 704 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 705 /* @brief Has 0x44 Erase All Blocks command. */ 706 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 707 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 708 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 709 /* @brief Has 0x46 Swap Control command. */ 710 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 711 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 712 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 713 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 714 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 715 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 716 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 717 /* @brief Has 0x80 Program Partition command. */ 718 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 719 /* @brief Has 0x81 Set FlexRAM Function command. */ 720 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 721 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 722 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 723 /* @brief P-Flash Erase sector command address alignment. */ 724 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 725 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 726 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 727 /* @brief P-Flash Read resource command address alignment. */ 728 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 729 /* @brief P-Flash Program check command address alignment. */ 730 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 731 /* @brief P-Flash Program check command address alignment. */ 732 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 733 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 734 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 735 /* @brief FlexNVM Erase sector command address alignment. */ 736 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 737 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 738 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 739 /* @brief FlexNVM Read resource command address alignment. */ 740 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 741 /* @brief FlexNVM Program check command address alignment. */ 742 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 743 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 744 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 745 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 746 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 747 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 748 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 749 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 750 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 751 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 752 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 753 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 754 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 755 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 756 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 757 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 758 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 759 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 760 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 761 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 762 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 763 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 764 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 765 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 766 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 767 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 768 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 769 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 770 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 771 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 772 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 773 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 774 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 775 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 776 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 777 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 778 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 779 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 780 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 781 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 782 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 783 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 784 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 785 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 786 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 787 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 788 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 789 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 790 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 791 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 792 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 793 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 794 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 795 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 796 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 797 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 798 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 799 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 800 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 801 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 802 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 803 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 804 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 805 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 806 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 807 #elif defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z64VLK4) 808 /* @brief Is of type FTFA. */ 809 #define FSL_FEATURE_FLASH_IS_FTFA (1) 810 /* @brief Is of type FTFE. */ 811 #define FSL_FEATURE_FLASH_IS_FTFE (0) 812 /* @brief Is of type FTFL. */ 813 #define FSL_FEATURE_FLASH_IS_FTFL (0) 814 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 815 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 816 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 817 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 818 /* @brief Has EEPROM region protection (register FEPROT). */ 819 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 820 /* @brief Has data flash region protection (register FDPROT). */ 821 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 822 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 823 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 824 /* @brief Has flash cache control in FMC module. */ 825 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 826 /* @brief Has flash cache control in MCM module. */ 827 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 828 /* @brief Has flash cache control in MSCM module. */ 829 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 830 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 831 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 832 /* @brief P-Flash start address. */ 833 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 834 /* @brief P-Flash block count. */ 835 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 836 /* @brief P-Flash block size. */ 837 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 838 /* @brief P-Flash sector size. */ 839 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 840 /* @brief P-Flash write unit size. */ 841 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 842 /* @brief P-Flash data path width. */ 843 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 844 /* @brief P-Flash block swap feature. */ 845 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 846 /* @brief P-Flash protection region count. */ 847 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 848 /* @brief Has FlexNVM memory. */ 849 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 850 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 851 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 852 /* @brief FlexNVM block count. */ 853 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 854 /* @brief FlexNVM block size. */ 855 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 856 /* @brief FlexNVM sector size. */ 857 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 858 /* @brief FlexNVM write unit size. */ 859 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 860 /* @brief FlexNVM data path width. */ 861 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 862 /* @brief Has FlexRAM memory. */ 863 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 864 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 865 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 866 /* @brief FlexRAM size. */ 867 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 868 /* @brief Has 0x00 Read 1s Block command. */ 869 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 870 /* @brief Has 0x01 Read 1s Section command. */ 871 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 872 /* @brief Has 0x02 Program Check command. */ 873 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 874 /* @brief Has 0x03 Read Resource command. */ 875 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 876 /* @brief Has 0x06 Program Longword command. */ 877 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 878 /* @brief Has 0x07 Program Phrase command. */ 879 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 880 /* @brief Has 0x08 Erase Flash Block command. */ 881 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 882 /* @brief Has 0x09 Erase Flash Sector command. */ 883 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 884 /* @brief Has 0x0B Program Section command. */ 885 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 886 /* @brief Has 0x40 Read 1s All Blocks command. */ 887 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 888 /* @brief Has 0x41 Read Once command. */ 889 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 890 /* @brief Has 0x43 Program Once command. */ 891 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 892 /* @brief Has 0x44 Erase All Blocks command. */ 893 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 894 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 895 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 896 /* @brief Has 0x46 Swap Control command. */ 897 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 898 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 899 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 900 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 901 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 902 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 903 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 904 /* @brief Has 0x80 Program Partition command. */ 905 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 906 /* @brief Has 0x81 Set FlexRAM Function command. */ 907 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 908 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 909 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 910 /* @brief P-Flash Erase sector command address alignment. */ 911 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 912 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 913 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 914 /* @brief P-Flash Read resource command address alignment. */ 915 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 916 /* @brief P-Flash Program check command address alignment. */ 917 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 918 /* @brief P-Flash Program check command address alignment. */ 919 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 920 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 921 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 922 /* @brief FlexNVM Erase sector command address alignment. */ 923 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 924 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 925 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 926 /* @brief FlexNVM Read resource command address alignment. */ 927 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 928 /* @brief FlexNVM Program check command address alignment. */ 929 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 930 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 931 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) 932 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 933 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) 934 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 935 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) 936 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 937 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) 938 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 939 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) 940 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 941 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) 942 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 943 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) 944 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 945 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) 946 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 947 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) 948 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 949 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) 950 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 951 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) 952 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 953 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) 954 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 955 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) 956 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 957 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) 958 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 959 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) 960 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 961 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) 962 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 963 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 964 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 965 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 966 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 967 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 968 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 969 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 970 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 971 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 972 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 973 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 974 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 975 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 976 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 977 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 978 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 979 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 980 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 981 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 982 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 983 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 984 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 985 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 986 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 987 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 988 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 989 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 990 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 991 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 992 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 993 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 994 #endif /* defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z128VLK4) */ 995 996 /* GPIO module features */ 997 998 /* @brief Has fast (single cycle) access capability via a dedicated memory region. */ 999 #define FSL_FEATURE_GPIO_HAS_FAST_GPIO (1) 1000 /* @brief Has port input disable register (PIDR). */ 1001 #define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) 1002 /* @brief Has dedicated interrupt vector. */ 1003 #define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) 1004 1005 /* I2C module features */ 1006 1007 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 1008 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 1009 /* @brief Maximum supported baud rate in kilobit per second. */ 1010 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 1011 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 1012 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1) 1013 /* @brief Has DMA support (register bit C1[DMAEN]). */ 1014 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 1015 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 1016 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (0) 1017 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 1018 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1) 1019 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 1020 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 1021 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 1022 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31) 1023 /* @brief Has control of the drive capability of the I2C pins. */ 1024 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 1025 /* @brief Has double buffering support (register S2). */ 1026 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 1027 /* @brief Has double buffer enable. */ 1028 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 1029 1030 /* LLWU module features */ 1031 1032 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 1033 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 1034 /* @brief Has pins 8-15 connected to LLWU device. */ 1035 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 1036 /* @brief Maximum number of internal modules connected to LLWU device. */ 1037 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 1038 /* @brief Number of digital filters. */ 1039 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 1040 /* @brief Has MF register. */ 1041 #define FSL_FEATURE_LLWU_HAS_MF (0) 1042 /* @brief Has PF register. */ 1043 #define FSL_FEATURE_LLWU_HAS_PF (0) 1044 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 1045 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 1046 /* @brief Has no internal module wakeup flag register. */ 1047 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 1048 /* @brief Has external pin 0 connected to LLWU device. */ 1049 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 1050 /* @brief Index of port of external pin. */ 1051 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 1052 /* @brief Number of external pin port on specified port. */ 1053 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 1054 /* @brief Has external pin 1 connected to LLWU device. */ 1055 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 1056 /* @brief Index of port of external pin. */ 1057 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 1058 /* @brief Number of external pin port on specified port. */ 1059 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 1060 /* @brief Has external pin 2 connected to LLWU device. */ 1061 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 1062 /* @brief Index of port of external pin. */ 1063 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 1064 /* @brief Number of external pin port on specified port. */ 1065 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 1066 /* @brief Has external pin 3 connected to LLWU device. */ 1067 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0) 1068 /* @brief Index of port of external pin. */ 1069 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0) 1070 /* @brief Number of external pin port on specified port. */ 1071 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0) 1072 /* @brief Has external pin 4 connected to LLWU device. */ 1073 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 1074 /* @brief Index of port of external pin. */ 1075 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 1076 /* @brief Number of external pin port on specified port. */ 1077 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 1078 /* @brief Has external pin 5 connected to LLWU device. */ 1079 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 1080 /* @brief Index of port of external pin. */ 1081 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 1082 /* @brief Number of external pin port on specified port. */ 1083 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 1084 /* @brief Has external pin 6 connected to LLWU device. */ 1085 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 1086 /* @brief Index of port of external pin. */ 1087 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 1088 /* @brief Number of external pin port on specified port. */ 1089 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 1090 /* @brief Has external pin 7 connected to LLWU device. */ 1091 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 1092 /* @brief Index of port of external pin. */ 1093 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 1094 /* @brief Number of external pin port on specified port. */ 1095 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 1096 /* @brief Has external pin 8 connected to LLWU device. */ 1097 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 1098 /* @brief Index of port of external pin. */ 1099 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 1100 /* @brief Number of external pin port on specified port. */ 1101 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 1102 /* @brief Has external pin 9 connected to LLWU device. */ 1103 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 1104 /* @brief Index of port of external pin. */ 1105 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 1106 /* @brief Number of external pin port on specified port. */ 1107 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 1108 /* @brief Has external pin 10 connected to LLWU device. */ 1109 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 1110 /* @brief Index of port of external pin. */ 1111 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 1112 /* @brief Number of external pin port on specified port. */ 1113 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 1114 /* @brief Has external pin 11 connected to LLWU device. */ 1115 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 1116 /* @brief Index of port of external pin. */ 1117 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 1118 /* @brief Number of external pin port on specified port. */ 1119 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 1120 /* @brief Has external pin 12 connected to LLWU device. */ 1121 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) 1122 /* @brief Index of port of external pin. */ 1123 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) 1124 /* @brief Number of external pin port on specified port. */ 1125 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1126 /* @brief Has external pin 13 connected to LLWU device. */ 1127 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) 1128 /* @brief Index of port of external pin. */ 1129 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) 1130 /* @brief Number of external pin port on specified port. */ 1131 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) 1132 /* @brief Has external pin 14 connected to LLWU device. */ 1133 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1134 /* @brief Index of port of external pin. */ 1135 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1136 /* @brief Number of external pin port on specified port. */ 1137 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1138 /* @brief Has external pin 15 connected to LLWU device. */ 1139 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1140 /* @brief Index of port of external pin. */ 1141 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1142 /* @brief Number of external pin port on specified port. */ 1143 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1144 /* @brief Has external pin 16 connected to LLWU device. */ 1145 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 1146 /* @brief Index of port of external pin. */ 1147 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 1148 /* @brief Number of external pin port on specified port. */ 1149 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 1150 /* @brief Has external pin 17 connected to LLWU device. */ 1151 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 1152 /* @brief Index of port of external pin. */ 1153 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 1154 /* @brief Number of external pin port on specified port. */ 1155 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 1156 /* @brief Has external pin 18 connected to LLWU device. */ 1157 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 1158 /* @brief Index of port of external pin. */ 1159 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 1160 /* @brief Number of external pin port on specified port. */ 1161 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 1162 /* @brief Has external pin 19 connected to LLWU device. */ 1163 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 1164 /* @brief Index of port of external pin. */ 1165 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 1166 /* @brief Number of external pin port on specified port. */ 1167 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 1168 /* @brief Has external pin 20 connected to LLWU device. */ 1169 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 1170 /* @brief Index of port of external pin. */ 1171 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 1172 /* @brief Number of external pin port on specified port. */ 1173 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 1174 /* @brief Has external pin 21 connected to LLWU device. */ 1175 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 1176 /* @brief Index of port of external pin. */ 1177 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 1178 /* @brief Number of external pin port on specified port. */ 1179 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 1180 /* @brief Has external pin 22 connected to LLWU device. */ 1181 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1182 /* @brief Index of port of external pin. */ 1183 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1184 /* @brief Number of external pin port on specified port. */ 1185 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1186 /* @brief Has external pin 23 connected to LLWU device. */ 1187 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1188 /* @brief Index of port of external pin. */ 1189 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1190 /* @brief Number of external pin port on specified port. */ 1191 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1192 /* @brief Has external pin 24 connected to LLWU device. */ 1193 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1194 /* @brief Index of port of external pin. */ 1195 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1196 /* @brief Number of external pin port on specified port. */ 1197 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1198 /* @brief Has external pin 25 connected to LLWU device. */ 1199 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1200 /* @brief Index of port of external pin. */ 1201 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1202 /* @brief Number of external pin port on specified port. */ 1203 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1204 /* @brief Has external pin 26 connected to LLWU device. */ 1205 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1206 /* @brief Index of port of external pin. */ 1207 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1208 /* @brief Number of external pin port on specified port. */ 1209 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1210 /* @brief Has external pin 27 connected to LLWU device. */ 1211 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1212 /* @brief Index of port of external pin. */ 1213 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1214 /* @brief Number of external pin port on specified port. */ 1215 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1216 /* @brief Has external pin 28 connected to LLWU device. */ 1217 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1218 /* @brief Index of port of external pin. */ 1219 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1220 /* @brief Number of external pin port on specified port. */ 1221 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1222 /* @brief Has external pin 29 connected to LLWU device. */ 1223 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1224 /* @brief Index of port of external pin. */ 1225 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1226 /* @brief Number of external pin port on specified port. */ 1227 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1228 /* @brief Has external pin 30 connected to LLWU device. */ 1229 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1230 /* @brief Index of port of external pin. */ 1231 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1232 /* @brief Number of external pin port on specified port. */ 1233 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1234 /* @brief Has external pin 31 connected to LLWU device. */ 1235 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1236 /* @brief Index of port of external pin. */ 1237 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1238 /* @brief Number of external pin port on specified port. */ 1239 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1240 /* @brief Has internal module 0 connected to LLWU device. */ 1241 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1242 /* @brief Has internal module 1 connected to LLWU device. */ 1243 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1244 /* @brief Has internal module 2 connected to LLWU device. */ 1245 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0) 1246 /* @brief Has internal module 3 connected to LLWU device. */ 1247 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 1248 /* @brief Has internal module 4 connected to LLWU device. */ 1249 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 1250 /* @brief Has internal module 5 connected to LLWU device. */ 1251 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 1252 /* @brief Has internal module 6 connected to LLWU device. */ 1253 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1254 /* @brief Has internal module 7 connected to LLWU device. */ 1255 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 1256 /* @brief Has Version ID Register (LLWU_VERID). */ 1257 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1258 /* @brief Has Parameter Register (LLWU_PARAM). */ 1259 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1260 /* @brief Width of registers of the LLWU. */ 1261 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1262 /* @brief Has DMA Enable register (LLWU_DE). */ 1263 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1264 1265 /* LPTMR module features */ 1266 1267 /* @brief Has shared interrupt handler with another LPTMR module. */ 1268 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1269 /* @brief Whether LPTMR counter is 32 bits width. */ 1270 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1271 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1272 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1273 1274 /* MCG module features */ 1275 1276 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1277 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 1278 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1279 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) 1280 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1281 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) 1282 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1283 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) 1284 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1285 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) 1286 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1287 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1288 /* @brief FRDIV supports 1280. */ 1289 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1290 /* @brief FRDIV supports 1536. */ 1291 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1292 /* @brief MCGFFCLK divider. */ 1293 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1294 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1295 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) 1296 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1297 #define FSL_FEATURE_MCG_HAS_RTC_32K (0) 1298 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1299 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1300 /* @brief Has 48MHz internal oscillator. */ 1301 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 1302 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1303 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1304 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1305 #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) 1306 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1307 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1308 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1309 #define FSL_FEATURE_MCG_USE_OSCSEL (0) 1310 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1311 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1312 /* @brief TBD */ 1313 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1314 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1315 #define FSL_FEATURE_MCG_HAS_PLL (1) 1316 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1317 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 1318 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1319 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 1320 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1321 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) 1322 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1323 #define FSL_FEATURE_MCG_HAS_FLL (1) 1324 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1325 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1326 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1327 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1328 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1329 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1330 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1331 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1332 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1333 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1334 /* @brief Has external clock monitor (register bit C6[CME]). */ 1335 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1336 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1337 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1338 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1339 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1340 /* @brief Has PEI mode or PBI mode. */ 1341 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1342 /* @brief Reset clock mode is BLPI. */ 1343 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1344 1345 /* interrupt module features */ 1346 1347 /* @brief Lowest interrupt request number. */ 1348 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1349 /* @brief Highest interrupt request number. */ 1350 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 1351 1352 /* OSC module features */ 1353 1354 /* @brief Has OSC1 external oscillator. */ 1355 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1356 /* @brief Has OSC0 external oscillator. */ 1357 #define FSL_FEATURE_OSC_HAS_OSC0 (1) 1358 /* @brief Has OSC external oscillator (without index). */ 1359 #define FSL_FEATURE_OSC_HAS_OSC (0) 1360 /* @brief Number of OSC external oscillators. */ 1361 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1362 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1363 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 1364 1365 /* PIT module features */ 1366 1367 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1368 #define FSL_FEATURE_PIT_TIMER_COUNT (2) 1369 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1370 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 1371 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1372 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1373 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1374 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 1375 1376 /* PMC module features */ 1377 1378 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1379 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1380 /* @brief Has Bandgap Buffer Enable. */ 1381 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1382 /* @brief Has Bandgap Buffer Drive Select. */ 1383 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1384 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1385 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1386 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1387 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1388 /* @brief Has LPO. */ 1389 #define FSL_FEATURE_PMC_HAS_LPO (0) 1390 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1391 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1392 /* @brief Has acknowledge isolation support. */ 1393 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1394 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1395 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1396 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1397 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1398 /* @brief Has PMC_HVDSC1. */ 1399 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1400 /* @brief Has PMC_PARAM. */ 1401 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1402 /* @brief Has PMC_VERID. */ 1403 #define FSL_FEATURE_PMC_HAS_VERID (0) 1404 1405 /* PORT module features */ 1406 1407 /* @brief Has control lock (register bit PCR[LK]). */ 1408 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) 1409 /* @brief Has open drain control (register bit PCR[ODE]). */ 1410 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 1411 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1412 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 1413 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1414 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1415 /* @brief Has pull resistor selection available. */ 1416 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (0) 1417 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1418 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1419 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1420 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1421 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1422 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1423 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1424 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1425 /* @brief Has separate drive strength register (HDRVE). */ 1426 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1427 /* @brief Has glitch filter (register IOFLT). */ 1428 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1429 /* @brief Defines width of PCR[MUX] field. */ 1430 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1431 /* @brief Has dedicated interrupt vector. */ 1432 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1433 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1434 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1435 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1436 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1437 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1438 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1439 1440 /* RCM module features */ 1441 1442 /* @brief Has Loss-of-Lock Reset support. */ 1443 #define FSL_FEATURE_RCM_HAS_LOL (1) 1444 /* @brief Has Loss-of-Clock Reset support. */ 1445 #define FSL_FEATURE_RCM_HAS_LOC (1) 1446 /* @brief Has JTAG generated Reset support. */ 1447 #define FSL_FEATURE_RCM_HAS_JTAG (0) 1448 /* @brief Has EzPort generated Reset support. */ 1449 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1450 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1451 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1452 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1453 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1454 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1455 #define FSL_FEATURE_RCM_HAS_SSRS (0) 1456 /* @brief Has Version ID Register (RCM_VERID). */ 1457 #define FSL_FEATURE_RCM_HAS_VERID (0) 1458 /* @brief Has Parameter Register (RCM_PARAM). */ 1459 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1460 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1461 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1462 /* @brief Width of registers of the RCM. */ 1463 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1464 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1465 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1466 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1467 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1468 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1469 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1470 1471 /* RTC module features */ 1472 1473 /* @brief Has wakeup pin. */ 1474 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1475 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1476 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (0) 1477 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1478 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1479 /* @brief Has read/write access control (registers WAR and RAR). */ 1480 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) 1481 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1482 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 1483 /* @brief Has RTC_CLKIN available. */ 1484 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) 1485 /* @brief Has prescaler adjust for LPO. */ 1486 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1487 /* @brief Has Clock Pin Enable field. */ 1488 #define FSL_FEATURE_RTC_HAS_CPE (0) 1489 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1490 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1491 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1492 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1493 1494 /* SIM module features */ 1495 1496 /* @brief Has USB FS divider. */ 1497 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1498 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1499 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) 1500 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1501 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 1502 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1503 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1504 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1505 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1506 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1507 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1508 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1509 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 1510 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1511 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1512 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1513 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1514 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1515 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1516 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1517 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1518 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1519 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1520 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1521 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1522 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1523 #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) 1524 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1525 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1526 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1527 #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) 1528 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1529 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (1) 1530 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1531 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (1) 1532 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1533 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1) 1534 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1535 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1536 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1537 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1538 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1539 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1540 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1541 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1542 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1543 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1544 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1545 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1546 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1547 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1548 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1549 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1550 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1551 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1552 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1553 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1554 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1555 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) 1556 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1557 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1558 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1559 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1560 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1561 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) 1562 /* @brief Has FTM module(s) configuration. */ 1563 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 1564 /* @brief Number of FTM modules. */ 1565 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 1566 /* @brief Number of FTM triggers with selectable source. */ 1567 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 1568 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1569 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 1570 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1571 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1572 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1573 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1574 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1575 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1576 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1577 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1578 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1579 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1580 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1581 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 1582 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1583 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 1584 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1585 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 1586 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1587 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1588 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1589 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1590 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1591 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1592 /* @brief Has TPM module(s) configuration. */ 1593 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) 1594 /* @brief The highest TPM module index. */ 1595 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) 1596 /* @brief Has TPM module with index 0. */ 1597 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) 1598 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1599 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) 1600 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1601 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) 1602 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1603 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) 1604 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1605 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) 1606 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1607 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) 1608 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1609 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) 1610 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1611 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) 1612 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1613 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1614 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1615 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1616 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1617 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1618 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1619 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1620 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1621 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1622 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1623 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1624 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1625 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1626 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1627 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1628 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1629 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 1630 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1631 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1632 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1633 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1634 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1635 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1636 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1637 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1638 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1639 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1640 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1641 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1642 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1643 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) 1644 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1645 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) 1646 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1647 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1648 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1649 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) 1650 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1651 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1652 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1653 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1654 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1655 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1656 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1657 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) 1658 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1659 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1660 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1661 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1662 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1663 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1664 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1665 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1666 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1667 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1668 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1669 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1670 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1671 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1672 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1673 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1674 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1675 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1676 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1677 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1678 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1679 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1680 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1681 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1682 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1683 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1684 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1685 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1686 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1687 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1688 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1689 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1690 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1691 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1692 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1693 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1694 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1695 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1696 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1697 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1698 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1699 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1700 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1701 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1702 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1703 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1704 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1705 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1706 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1707 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1708 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1709 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1710 /* @brief Has miscellanious control register (register MCR). */ 1711 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1712 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1713 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) 1714 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1715 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1716 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1717 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1718 1719 /* SMC module features */ 1720 1721 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1722 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1723 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1724 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1725 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1726 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1727 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1728 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1729 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1730 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1731 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1732 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1733 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1734 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1735 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1736 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1737 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1738 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1739 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1740 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1741 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1742 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1743 /* @brief Has stop submode. */ 1744 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1745 /* @brief Has stop submode 0(VLLS0). */ 1746 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1747 /* @brief Has stop submode 2(VLLS2). */ 1748 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 1749 /* @brief Has SMC_PARAM. */ 1750 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1751 /* @brief Has SMC_VERID. */ 1752 #define FSL_FEATURE_SMC_HAS_VERID (0) 1753 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1754 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1755 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1756 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1757 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1758 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1759 1760 /* SPI module features */ 1761 1762 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1763 #define FSL_FEATURE_SPI_HAS_FIFO (0) 1764 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ 1765 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) 1766 /* @brief Has separate DMA RX and TX requests. */ 1767 #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1768 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ 1769 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) (0) 1770 /* @brief Maximum transfer data width in bits. */ 1771 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8) 1772 /* @brief The data register name has postfix (L as low and H as high). */ 1773 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0) 1774 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1775 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1776 /* @brief Has 16-bit data transfer support. */ 1777 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (0) 1778 1779 /* SysTick module features */ 1780 1781 /* @brief Systick has external reference clock. */ 1782 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 1783 /* @brief Systick external reference clock is core clock divided by this value. */ 1784 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 1785 1786 /* TPM module features */ 1787 1788 /* @brief Bus clock is the source clock for the module. */ 1789 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 1790 /* @brief Number of channels. */ 1791 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 1792 ((x) == TPM0 ? (6) : \ 1793 ((x) == TPM1 ? (2) : \ 1794 ((x) == TPM2 ? (2) : (-1)))) 1795 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1796 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1797 /* @brief Has TPM_PARAM. */ 1798 #define FSL_FEATURE_TPM_HAS_PARAM (0) 1799 /* @brief Has TPM_VERID. */ 1800 #define FSL_FEATURE_TPM_HAS_VERID (0) 1801 /* @brief Has TPM_GLOBAL. */ 1802 #define FSL_FEATURE_TPM_HAS_GLOBAL (0) 1803 /* @brief Has TPM_TRIG. */ 1804 #define FSL_FEATURE_TPM_HAS_TRIG (0) 1805 /* @brief Has counter pause on trigger. */ 1806 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (0) 1807 /* @brief Has external trigger selection. */ 1808 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (0) 1809 /* @brief Has TPM_COMBINE register. */ 1810 #define FSL_FEATURE_TPM_HAS_COMBINE (0) 1811 /* @brief Whether COMBINE register has effect. */ 1812 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (0) 1813 /* @brief Has TPM_POL. */ 1814 #define FSL_FEATURE_TPM_HAS_POL (0) 1815 /* @brief Has TPM_FILTER register. */ 1816 #define FSL_FEATURE_TPM_HAS_FILTER (0) 1817 /* @brief Whether FILTER register has effect. */ 1818 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (0) 1819 /* @brief Has TPM_QDCTRL register. */ 1820 #define FSL_FEATURE_TPM_HAS_QDCTRL (0) 1821 /* @brief Whether QDCTRL register has effect. */ 1822 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (0) 1823 1824 /* TSI module features */ 1825 1826 /* @brief TSI module version. */ 1827 #define FSL_FEATURE_TSI_VERSION (4) 1828 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ 1829 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) 1830 /* @brief Number of TSI channels. */ 1831 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16) 1832 1833 /* LPSCI module features */ 1834 1835 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1836 #define FSL_FEATURE_LPSCI_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1837 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1838 #define FSL_FEATURE_LPSCI_HAS_LOW_POWER_UART_SUPPORT (1) 1839 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1840 #define FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) 1841 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1842 #define FSL_FEATURE_LPSCI_HAS_FIFO (0) 1843 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1844 #define FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT (0) 1845 /* @brief Infrared (modulation) is supported. */ 1846 #define FSL_FEATURE_LPSCI_HAS_IR_SUPPORT (0) 1847 /* @brief 2 bits long stop bit is available. */ 1848 #define FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1849 /* @brief If 10-bit mode is supported. */ 1850 #define FSL_FEATURE_LPSCI_HAS_10BIT_DATA_SUPPORT (1) 1851 /* @brief Baud rate fine adjustment is available. */ 1852 #define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 1853 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1854 #define FSL_FEATURE_LPSCI_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 1855 /* @brief Baud rate oversampling is available. */ 1856 #define FSL_FEATURE_LPSCI_HAS_RX_RESYNC_SUPPORT (1) 1857 /* @brief Baud rate oversampling is available. */ 1858 #define FSL_FEATURE_LPSCI_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 1859 /* @brief Peripheral type. */ 1860 #define FSL_FEATURE_LPSCI_IS_SCI (1) 1861 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1862 #define FSL_FEATURE_LPSCI_FIFO_SIZE (0) 1863 /* @brief Maximal data width without parity bit. */ 1864 #define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_NO_PARITY (10) 1865 /* @brief Maximal data width with parity bit. */ 1866 #define FSL_FEATURE_LPSCI_MAX_DATA_WIDTH_WITH_PARITY (9) 1867 /* @brief Supports two match addresses to filter incoming frames. */ 1868 #define FSL_FEATURE_LPSCI_HAS_ADDRESS_MATCHING (1) 1869 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1870 #define FSL_FEATURE_LPSCI_HAS_DMA_ENABLE (1) 1871 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1872 #define FSL_FEATURE_LPSCI_HAS_DMA_SELECT (0) 1873 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1874 #define FSL_FEATURE_LPSCI_HAS_BIT_ORDER_SELECT (1) 1875 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1876 #define FSL_FEATURE_LPSCI_HAS_SMART_CARD_SUPPORT (0) 1877 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1878 #define FSL_FEATURE_LPSCI_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1879 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1880 #define FSL_FEATURE_LPSCI_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1881 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1882 #define FSL_FEATURE_LPSCI_HAS_32BIT_REGISTERS (0) 1883 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1884 #define FSL_FEATURE_LPSCI_HAS_LIN_BREAK_DETECT (1) 1885 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1886 #define FSL_FEATURE_LPSCI_HAS_WAIT_MODE_OPERATION (0) 1887 /* @brief Has separate DMA RX and TX requests. */ 1888 #define FSL_FEATURE_LPSCI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1889 1890 /* UART module features */ 1891 1892 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1893 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1894 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1895 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1896 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1897 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) 1898 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1899 #define FSL_FEATURE_UART_HAS_FIFO (0) 1900 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1901 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) 1902 /* @brief Infrared (modulation) is supported. */ 1903 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 1904 /* @brief 2 bits long stop bit is available. */ 1905 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1906 /* @brief If 10-bit mode is supported. */ 1907 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) 1908 /* @brief Baud rate fine adjustment is available. */ 1909 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 1910 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1911 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1912 /* @brief Baud rate oversampling is available. */ 1913 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) 1914 /* @brief Baud rate oversampling is available. */ 1915 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 1916 /* @brief Peripheral type. */ 1917 #define FSL_FEATURE_UART_IS_SCI (1) 1918 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1919 #define FSL_FEATURE_UART_FIFO_SIZE (0) 1920 /* @brief Maximal data width without parity bit. */ 1921 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) 1922 /* @brief Maximal data width with parity bit. */ 1923 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (8) 1924 /* @brief Supports two match addresses to filter incoming frames. */ 1925 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (0) 1926 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1927 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1928 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1929 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1930 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1931 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (0) 1932 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1933 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) 1934 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1935 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1936 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1937 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1938 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1939 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1940 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1941 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1942 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1943 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1944 /* @brief Has separate DMA RX and TX requests. */ 1945 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1946 1947 /* USB module features */ 1948 1949 /* @brief KHCI module instance count */ 1950 #define FSL_FEATURE_USB_KHCI_COUNT (1) 1951 /* @brief HOST mode enabled */ 1952 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 1953 /* @brief OTG mode enabled */ 1954 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 1955 /* @brief Size of the USB dedicated RAM */ 1956 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 1957 /* @brief Has KEEP_ALIVE_CTRL register */ 1958 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 1959 /* @brief Has the Dynamic SOF threshold compare support */ 1960 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) 1961 /* @brief Has the VBUS detect support */ 1962 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) 1963 /* @brief Has the IRC48M module clock support */ 1964 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (0) 1965 /* @brief Number of endpoints supported */ 1966 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 1967 1968 #endif /* _MKL25Z4_FEATURES_H_ */ 1969 1970
