1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_NETC_F2_COMMON.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_NETC_F2_COMMON 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_NETC_F2_COMMON_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_NETC_F2_COMMON_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- NETC_F2_COMMON Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup NETC_F2_COMMON_Peripheral_Access_Layer NETC_F2_COMMON Peripheral Access Layer 68 * @{ 69 */ 70 71 /** NETC_F2_COMMON - Size of Registers Arrays */ 72 #define NETC_F2_COMMON_NUM_PROFILE_COUNT 2u 73 74 /** NETC_F2_COMMON - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[4096]; 77 __I uint32_t IPCAPR; /**< Ingress port capability register, offset: 0x1000 */ 78 __I uint32_t EPCAPR; /**< Egress port capability register, offset: 0x1004 */ 79 uint8_t RESERVED_1[8]; 80 __I uint32_t OSR; /**< Operational state register, offset: 0x1010 */ 81 uint8_t RESERVED_2[44]; 82 __IO uint32_t CMECR; /**< Correctable memory error configuration register, offset: 0x1040 */ 83 __IO uint32_t CMESR; /**< Correctable memory error status register, offset: 0x1044 */ 84 uint8_t RESERVED_3[4]; 85 __I uint32_t CMECTR; /**< Correctable memory error count register, offset: 0x104C */ 86 uint8_t RESERVED_4[16]; 87 __IO uint32_t UNMACECR; /**< Uncorrectable non-fatal MAC error configuration register, offset: 0x1060 */ 88 __I uint32_t UNMACESR; /**< Uncorrectable non-fatal MAC error status register, offset: 0x1064 */ 89 uint8_t RESERVED_5[8]; 90 __IO uint32_t UNSBECR; /**< Uncorrectable non-fatal system bus error configuration register, offset: 0x1070 */ 91 __IO uint32_t UNSBESR; /**< Uncorrectable non-fatal system bus error status register, offset: 0x1074 */ 92 uint8_t RESERVED_6[4]; 93 __I uint32_t UNSBECTR; /**< Uncorrectable non-fatal system bus error count register, offset: 0x107C */ 94 __IO uint32_t UFSBECR; /**< Uncorrectable fatal system bus error configuration register, offset: 0x1080 */ 95 __IO uint32_t UFSBESR; /**< Uncorrectable fatal system bus error status register, offset: 0x1084 */ 96 uint8_t RESERVED_7[8]; 97 __IO uint32_t UNMECR; /**< Uncorrectable non-fatal memory error configuration register, offset: 0x1090 */ 98 __IO uint32_t UNMESR0; /**< Uncorrectable non-fatal memory error status register 0, offset: 0x1094 */ 99 __I uint32_t UNMESR1; /**< Uncorrectable non-fatal memory error status register 1, offset: 0x1098 */ 100 __I uint32_t UNMECTR; /**< Uncorrectable non-fatal memory error count register, offset: 0x109C */ 101 __IO uint32_t UFMECR; /**< Uncorrectable fatal memory error configuration register, offset: 0x10A0 */ 102 __IO uint32_t UFMESR0; /**< Uncorrectable fatal memory error status register 0, offset: 0x10A4 */ 103 __I uint32_t UFMESR1; /**< Uncorrectable fatal memory error status register 1, offset: 0x10A8 */ 104 uint8_t RESERVED_8[4]; 105 __IO uint32_t UNIECR; /**< Uncorrectable non-fatal integrity error configuration register, offset: 0x10B0 */ 106 __IO uint32_t UNIESR; /**< Uncorrectable non-fatal integrity error status register, offset: 0x10B4 */ 107 uint8_t RESERVED_9[4]; 108 __I uint32_t UNIECTR; /**< Uncorrectable non-fatal integrity error count register, offset: 0x10BC */ 109 __IO uint32_t UFIECR; /**< Uncorrectable fatal integrity error configuration register, offset: 0x10C0 */ 110 __IO uint32_t UFIESR; /**< Uncorrectable fatal integrity error status register, offset: 0x10C4 */ 111 uint8_t RESERVED_10[32]; 112 __I uint32_t EMDIOIRR; /**< External MDIO interrupt reason register, offset: 0x10E8 */ 113 __IO uint32_t EMDIOMSIVR; /**< External MDIO MSI-X vector register, offset: 0x10EC */ 114 uint8_t RESERVED_11[16]; 115 __IO uint32_t TCCR; /**< Time capture configuration register, offset: 0x1100 */ 116 __IO uint32_t TCIER; /**< Time capture interrupt enable register, offset: 0x1104 */ 117 __IO uint32_t TCRPIDR; /**< Time capture receive port interrupt detect register, offset: 0x1108 */ 118 __I uint32_t TCRPSR; /**< Time capture receive port status register, offset: 0x110C */ 119 uint8_t RESERVED_12[4]; 120 __I uint32_t TCRPTSR; /**< Time capture receive port timestamp register, offset: 0x1114 */ 121 __IO uint32_t TCMSIVR; /**< Time capture MSI-X vector register, offset: 0x1118 */ 122 uint8_t RESERVED_13[228]; 123 __IO uint32_t CVLANR1; /**< Custom VLAN Ethertype register 1, offset: 0x1200 */ 124 __IO uint32_t CVLANR2; /**< Custom VLAN Ethertype register 2, offset: 0x1204 */ 125 __IO uint32_t PSRTAGETR; /**< Pre-Standard RTAG Ethertype register, offset: 0x1208 */ 126 uint8_t RESERVED_14[20]; 127 __IO uint32_t DOSL2CR; /**< DoS L2 configuration register, offset: 0x1220 */ 128 uint8_t RESERVED_15[220]; 129 struct { /* offset: 0x1300, array step: 0x10 */ 130 __IO uint32_t VLANIPVMPR0; /**< VLAN to IPV mapping profile 0 register 0..VLAN to IPV mapping profile 1 register 0, array offset: 0x1300, array step: 0x10 */ 131 __IO uint32_t VLANIPVMPR1; /**< VLAN to IPV mapping profile 0 register 1..VLAN to IPV mapping profile 1 register 1, array offset: 0x1304, array step: 0x10 */ 132 __IO uint32_t VLANDRMPR; /**< VLAN to DR mapping profile 0 register..VLAN to DR mapping profile 1 register, array offset: 0x1308, array step: 0x10 */ 133 uint8_t RESERVED_0[4]; 134 } NUM_PROFILE[NETC_F2_COMMON_NUM_PROFILE_COUNT]; 135 uint8_t RESERVED_16[800]; 136 __I uint32_t IPFCAPR; /**< Ingress port filter capability register, offset: 0x1640 */ 137 __I uint32_t IPFTCAPR; /**< Ingress port filter table capability register, offset: 0x1644 */ 138 __I uint32_t IPFTMOR; /**< Ingress port filter table memory operational register, offset: 0x1648 */ 139 uint8_t RESERVED_17[436]; 140 __I uint32_t ITMCAPR; /**< Index table memory capability register, offset: 0x1800 */ 141 uint8_t RESERVED_18[12]; 142 __I uint32_t RPCAPR; /**< Rate policer capability register, offset: 0x1810 */ 143 __I uint32_t RPITCAPR; /**< Rate policer index table capability register, offset: 0x1814 */ 144 __IO uint32_t RPITMAR; /**< Rate policer index table memory allocation register, offset: 0x1818 */ 145 __I uint32_t RPITOR; /**< Rate policer index table operational register, offset: 0x181C */ 146 uint8_t RESERVED_19[4]; 147 __I uint32_t ISCITCAPR; /**< Ingress stream counter index table capability register, offset: 0x1824 */ 148 __IO uint32_t ISCITMAR; /**< Ingress stream counter index table memory allocation register, offset: 0x1828 */ 149 __I uint32_t ISCITOR; /**< Ingress stream counter index table operational register, offset: 0x182C */ 150 __I uint32_t ISCAPR; /**< Ingress stream capability register, offset: 0x1830 */ 151 __I uint32_t ISITCAPR; /**< Ingress stream index table capability register, offset: 0x1834 */ 152 __IO uint32_t ISITMAR; /**< Ingress stream index table memory allocation register, offset: 0x1838 */ 153 __I uint32_t ISITOR; /**< Ingress stream index table operational register, offset: 0x183C */ 154 uint8_t RESERVED_20[4]; 155 __I uint32_t ISQGITCAPR; /**< Ingress sequence generation index table capability register, offset: 0x1844 */ 156 __IO uint32_t ISQGITMAR; /**< Ingress sequence generation index table memory allocation register, offset: 0x1848 */ 157 __I uint32_t ISQGITOR; /**< Ingress sequence generation index table operational register, offset: 0x184C */ 158 uint8_t RESERVED_21[16]; 159 __I uint32_t SGCAPR; /**< Stream gate capability register, offset: 0x1860 */ 160 __I uint32_t SGIITCAPR; /**< Stream gate instance index table capability register, offset: 0x1864 */ 161 __IO uint32_t SGIITMAR; /**< Stream gate instance index table memory allocation register, offset: 0x1868 */ 162 __I uint32_t SGIITOR; /**< Stream gate instance index table operational register, offset: 0x186C */ 163 uint8_t RESERVED_22[4]; 164 __I uint32_t SGCLITCAPR; /**< Stream gate control list index table capability register, offset: 0x1874 */ 165 __IO uint32_t SGCLITMAR; /**< Stream gate control list index table memory allocation register, offset: 0x1878 */ 166 __I uint32_t SGCLTMOR; /**< Stream gate control list table memory operational register, offset: 0x187C */ 167 __I uint32_t FMICAPR; /**< Frame modification ingress capability register, offset: 0x1880 */ 168 __I uint32_t FMECAPR; /**< Frame modification egress capability register, offset: 0x1884 */ 169 __I uint32_t FMITCAPR; /**< Frame modification index table capability register, offset: 0x1888 */ 170 __IO uint32_t FMITMAR; /**< Frame modification index table memory allocation register, offset: 0x188C */ 171 __I uint32_t FMITOR; /**< Frame modification index table operational register, offset: 0x1890 */ 172 __I uint32_t FMDITCAPR; /**< Frame modification data index table capability register, offset: 0x1894 */ 173 __IO uint32_t FMDITMAR; /**< Frame modification data index table memory allocation register, offset: 0x1898 */ 174 uint8_t RESERVED_23[36]; 175 __I uint32_t ETCAPR; /**< Egress treatment capability register, offset: 0x18C0 */ 176 __I uint32_t ETTCAPR; /**< Egress treatment table capability register, offset: 0x18C4 */ 177 uint8_t RESERVED_24[4]; 178 __I uint32_t ETTOR; /**< Egress treatment table operational register, offset: 0x18CC */ 179 uint8_t RESERVED_25[4]; 180 __I uint32_t TGSTCAPR; /**< Time gate scheduling table capability register, offset: 0x18D4 */ 181 uint8_t RESERVED_26[4]; 182 __I uint32_t TGSTMOR; /**< Time gate scheduling table memory operation register, offset: 0x18DC */ 183 __I uint32_t ESQRCAPR; /**< Egress sequence recovery capability register, offset: 0x18E0 */ 184 __I uint32_t ESQRTCAPR; /**< Egress sequence recovery table capability register, offset: 0x18E4 */ 185 uint8_t RESERVED_27[4]; 186 __I uint32_t ECTCAPR; /**< Egress counter table capability register, offset: 0x18EC */ 187 uint8_t RESERVED_28[16]; 188 __I uint32_t HTMCAPR; /**< Hash table memory capability register, offset: 0x1900 */ 189 __I uint32_t HTMOR; /**< Hash table memory operational register, offset: 0x1904 */ 190 uint8_t RESERVED_29[8]; 191 __I uint32_t ISIDCAPR; /**< Ingress stream identification capability register, offset: 0x1910 */ 192 __I uint32_t ISIDHTCAPR; /**< Ingress stream identification hash table capability register, offset: 0x1914 */ 193 uint8_t RESERVED_30[8]; 194 __I uint32_t ISIDKC0OR; /**< Ingress stream identification key construction 0 operational register, offset: 0x1920 */ 195 __IO uint32_t ISIDKC0CR0; /**< Ingress stream identification key construction 0 configuration register 0, offset: 0x1924 */ 196 uint8_t RESERVED_31[8]; 197 __IO uint32_t ISIDKC0PF0CR; /**< Ingress stream identification key construction 0 payload field 0 configuration register, offset: 0x1930 */ 198 __IO uint32_t ISIDKC0PF1CR; /**< Ingress stream identification key construction 0 payload field 1 configuration register, offset: 0x1934 */ 199 __IO uint32_t ISIDKC0PF2CR; /**< Ingress stream identification key construction 0 payload field 2 configuration register, offset: 0x1938 */ 200 __IO uint32_t ISIDKC0PF3CR; /**< Ingress stream identification key construction 0 payload field 3 configuration register, offset: 0x193C */ 201 __I uint32_t ISIDKC1OR; /**< Ingress stream identification key construction 1 operational register, offset: 0x1940 */ 202 __IO uint32_t ISIDKC1CR0; /**< Ingress stream identification key construction 1 configuration register 0, offset: 0x1944 */ 203 uint8_t RESERVED_32[8]; 204 __IO uint32_t ISIDKC1PF0CR; /**< Ingress stream identification key construction 1 payload field 0 configuration register, offset: 0x1950 */ 205 __IO uint32_t ISIDKC1PF1CR; /**< Ingress stream identification key construction 1 payload field 1 configuration register, offset: 0x1954 */ 206 __IO uint32_t ISIDKC1PF2CR; /**< Ingress stream identification key construction 1 payload field 2 configuration register, offset: 0x1958 */ 207 __IO uint32_t ISIDKC1PF3CR; /**< Ingress stream identification key construction 1 payload field 3 configuration register, offset: 0x195C */ 208 __I uint32_t ISIDKC2OR; /**< Ingress stream identification key construction 2 operational register, offset: 0x1960 */ 209 __IO uint32_t ISIDKC2CR0; /**< Ingress stream identification key construction 2 configuration register 0, offset: 0x1964 */ 210 uint8_t RESERVED_33[8]; 211 __IO uint32_t ISIDKC2PF0CR; /**< Ingress stream identification key construction 2 payload field 0 configuration register, offset: 0x1970 */ 212 __IO uint32_t ISIDKC2PF1CR; /**< Ingress stream identification key construction 2 payload field 1 configuration register, offset: 0x1974 */ 213 __IO uint32_t ISIDKC2PF2CR; /**< Ingress stream identification key construction 2 payload field 2 configuration register, offset: 0x1978 */ 214 __IO uint32_t ISIDKC2PF3CR; /**< Ingress stream identification key construction 2 payload field 3 configuration register, offset: 0x197C */ 215 __I uint32_t ISIDKC3OR; /**< Ingress stream identification key construction 3 operational register, offset: 0x1980 */ 216 __IO uint32_t ISIDKC3CR0; /**< Ingress stream identification key construction 3 configuration register 0, offset: 0x1984 */ 217 uint8_t RESERVED_34[8]; 218 __IO uint32_t ISIDKC3PF0CR; /**< Ingress stream identification key construction 3 payload field 0 configuration register, offset: 0x1990 */ 219 __IO uint32_t ISIDKC3PF1CR; /**< Ingress stream identification key construction 3 payload field 1 configuration register, offset: 0x1994 */ 220 __IO uint32_t ISIDKC3PF2CR; /**< Ingress stream identification key construction 3 payload field 2 configuration register, offset: 0x1998 */ 221 __IO uint32_t ISIDKC3PF3CR; /**< Ingress stream identification key construction 3 payload field 3 configuration register, offset: 0x199C */ 222 uint8_t RESERVED_35[96]; 223 __I uint32_t ISFHTCAPR; /**< Ingress stream filter hash table capability register, offset: 0x1A00 */ 224 __I uint32_t ISFHTOR; /**< Ingress stream filter hash table operational register, offset: 0x1A04 */ 225 } NETC_F2_COMMON_Type, *NETC_F2_COMMON_MemMapPtr; 226 227 /** Number of instances of the NETC_F2_COMMON module. */ 228 #define NETC_F2_COMMON_INSTANCE_COUNT (1u) 229 230 /* NETC_F2_COMMON - Peripheral instance base addresses */ 231 /** Peripheral NETC__SW0_COMMON base address */ 232 #define IP_NETC__SW0_COMMON_BASE (0x74A00000u) 233 /** Peripheral NETC__SW0_COMMON base pointer */ 234 #define IP_NETC__SW0_COMMON ((NETC_F2_COMMON_Type *)IP_NETC__SW0_COMMON_BASE) 235 /** Array initializer of NETC_F2_COMMON peripheral base addresses */ 236 #define IP_NETC_F2_COMMON_BASE_ADDRS { IP_NETC__SW0_COMMON_BASE } 237 /** Array initializer of NETC_F2_COMMON peripheral base pointers */ 238 #define IP_NETC_F2_COMMON_BASE_PTRS { IP_NETC__SW0_COMMON } 239 240 /* ---------------------------------------------------------------------------- 241 -- NETC_F2_COMMON Register Masks 242 ---------------------------------------------------------------------------- */ 243 244 /*! 245 * @addtogroup NETC_F2_COMMON_Register_Masks NETC_F2_COMMON Register Masks 246 * @{ 247 */ 248 249 /*! @name IPCAPR - Ingress port capability register */ 250 /*! @{ */ 251 252 #define NETC_F2_COMMON_IPCAPR_RP_MASK (0x1U) 253 #define NETC_F2_COMMON_IPCAPR_RP_SHIFT (0U) 254 #define NETC_F2_COMMON_IPCAPR_RP_WIDTH (1U) 255 #define NETC_F2_COMMON_IPCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPCAPR_RP_SHIFT)) & NETC_F2_COMMON_IPCAPR_RP_MASK) 256 257 #define NETC_F2_COMMON_IPCAPR_IPFLT_MASK (0x2U) 258 #define NETC_F2_COMMON_IPCAPR_IPFLT_SHIFT (1U) 259 #define NETC_F2_COMMON_IPCAPR_IPFLT_WIDTH (1U) 260 #define NETC_F2_COMMON_IPCAPR_IPFLT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPCAPR_IPFLT_SHIFT)) & NETC_F2_COMMON_IPCAPR_IPFLT_MASK) 261 262 #define NETC_F2_COMMON_IPCAPR_ISID_MASK (0x4U) 263 #define NETC_F2_COMMON_IPCAPR_ISID_SHIFT (2U) 264 #define NETC_F2_COMMON_IPCAPR_ISID_WIDTH (1U) 265 #define NETC_F2_COMMON_IPCAPR_ISID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPCAPR_ISID_SHIFT)) & NETC_F2_COMMON_IPCAPR_ISID_MASK) 266 267 #define NETC_F2_COMMON_IPCAPR_SDU_MASK (0x1F00U) 268 #define NETC_F2_COMMON_IPCAPR_SDU_SHIFT (8U) 269 #define NETC_F2_COMMON_IPCAPR_SDU_WIDTH (5U) 270 #define NETC_F2_COMMON_IPCAPR_SDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPCAPR_SDU_SHIFT)) & NETC_F2_COMMON_IPCAPR_SDU_MASK) 271 272 #define NETC_F2_COMMON_IPCAPR_NUM_VQMP_MASK (0xF0000U) 273 #define NETC_F2_COMMON_IPCAPR_NUM_VQMP_SHIFT (16U) 274 #define NETC_F2_COMMON_IPCAPR_NUM_VQMP_WIDTH (4U) 275 #define NETC_F2_COMMON_IPCAPR_NUM_VQMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPCAPR_NUM_VQMP_SHIFT)) & NETC_F2_COMMON_IPCAPR_NUM_VQMP_MASK) 276 /*! @} */ 277 278 /*! @name EPCAPR - Egress port capability register */ 279 /*! @{ */ 280 281 #define NETC_F2_COMMON_EPCAPR_ET_MASK (0x1U) 282 #define NETC_F2_COMMON_EPCAPR_ET_SHIFT (0U) 283 #define NETC_F2_COMMON_EPCAPR_ET_WIDTH (1U) 284 #define NETC_F2_COMMON_EPCAPR_ET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_EPCAPR_ET_SHIFT)) & NETC_F2_COMMON_EPCAPR_ET_MASK) 285 286 #define NETC_F2_COMMON_EPCAPR_SDU_MASK (0x1F00U) 287 #define NETC_F2_COMMON_EPCAPR_SDU_SHIFT (8U) 288 #define NETC_F2_COMMON_EPCAPR_SDU_WIDTH (5U) 289 #define NETC_F2_COMMON_EPCAPR_SDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_EPCAPR_SDU_SHIFT)) & NETC_F2_COMMON_EPCAPR_SDU_MASK) 290 291 #define NETC_F2_COMMON_EPCAPR_NUM_QVMP_MASK (0xF0000U) 292 #define NETC_F2_COMMON_EPCAPR_NUM_QVMP_SHIFT (16U) 293 #define NETC_F2_COMMON_EPCAPR_NUM_QVMP_WIDTH (4U) 294 #define NETC_F2_COMMON_EPCAPR_NUM_QVMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_EPCAPR_NUM_QVMP_SHIFT)) & NETC_F2_COMMON_EPCAPR_NUM_QVMP_MASK) 295 /*! @} */ 296 297 /*! @name OSR - Operational state register */ 298 /*! @{ */ 299 300 #define NETC_F2_COMMON_OSR_STATE_MASK (0x1U) 301 #define NETC_F2_COMMON_OSR_STATE_SHIFT (0U) 302 #define NETC_F2_COMMON_OSR_STATE_WIDTH (1U) 303 #define NETC_F2_COMMON_OSR_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_OSR_STATE_SHIFT)) & NETC_F2_COMMON_OSR_STATE_MASK) 304 305 #define NETC_F2_COMMON_OSR_ITM_STATE_MASK (0x2U) 306 #define NETC_F2_COMMON_OSR_ITM_STATE_SHIFT (1U) 307 #define NETC_F2_COMMON_OSR_ITM_STATE_WIDTH (1U) 308 #define NETC_F2_COMMON_OSR_ITM_STATE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_OSR_ITM_STATE_SHIFT)) & NETC_F2_COMMON_OSR_ITM_STATE_MASK) 309 /*! @} */ 310 311 /*! @name CMECR - Correctable memory error configuration register */ 312 /*! @{ */ 313 314 #define NETC_F2_COMMON_CMECR_THRESHOLD_MASK (0xFFU) 315 #define NETC_F2_COMMON_CMECR_THRESHOLD_SHIFT (0U) 316 #define NETC_F2_COMMON_CMECR_THRESHOLD_WIDTH (8U) 317 #define NETC_F2_COMMON_CMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_CMECR_THRESHOLD_SHIFT)) & NETC_F2_COMMON_CMECR_THRESHOLD_MASK) 318 /*! @} */ 319 320 /*! @name CMESR - Correctable memory error status register */ 321 /*! @{ */ 322 323 #define NETC_F2_COMMON_CMESR_MEM_ID_MASK (0x1F0000U) 324 #define NETC_F2_COMMON_CMESR_MEM_ID_SHIFT (16U) 325 #define NETC_F2_COMMON_CMESR_MEM_ID_WIDTH (5U) 326 #define NETC_F2_COMMON_CMESR_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_CMESR_MEM_ID_SHIFT)) & NETC_F2_COMMON_CMESR_MEM_ID_MASK) 327 328 #define NETC_F2_COMMON_CMESR_SBEE_MASK (0x80000000U) 329 #define NETC_F2_COMMON_CMESR_SBEE_SHIFT (31U) 330 #define NETC_F2_COMMON_CMESR_SBEE_WIDTH (1U) 331 #define NETC_F2_COMMON_CMESR_SBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_CMESR_SBEE_SHIFT)) & NETC_F2_COMMON_CMESR_SBEE_MASK) 332 /*! @} */ 333 334 /*! @name CMECTR - Correctable memory error count register */ 335 /*! @{ */ 336 337 #define NETC_F2_COMMON_CMECTR_COUNT_MASK (0xFFU) 338 #define NETC_F2_COMMON_CMECTR_COUNT_SHIFT (0U) 339 #define NETC_F2_COMMON_CMECTR_COUNT_WIDTH (8U) 340 #define NETC_F2_COMMON_CMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_CMECTR_COUNT_SHIFT)) & NETC_F2_COMMON_CMECTR_COUNT_MASK) 341 /*! @} */ 342 343 /*! @name UNMACECR - Uncorrectable non-fatal MAC error configuration register */ 344 /*! @{ */ 345 346 #define NETC_F2_COMMON_UNMACECR_PORT0_MASK (0x1U) 347 #define NETC_F2_COMMON_UNMACECR_PORT0_SHIFT (0U) 348 #define NETC_F2_COMMON_UNMACECR_PORT0_WIDTH (1U) 349 #define NETC_F2_COMMON_UNMACECR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMACECR_PORT0_SHIFT)) & NETC_F2_COMMON_UNMACECR_PORT0_MASK) 350 351 #define NETC_F2_COMMON_UNMACECR_PORT1_MASK (0x2U) 352 #define NETC_F2_COMMON_UNMACECR_PORT1_SHIFT (1U) 353 #define NETC_F2_COMMON_UNMACECR_PORT1_WIDTH (1U) 354 #define NETC_F2_COMMON_UNMACECR_PORT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMACECR_PORT1_SHIFT)) & NETC_F2_COMMON_UNMACECR_PORT1_MASK) 355 356 #define NETC_F2_COMMON_UNMACECR_PORT2_MASK (0x4U) 357 #define NETC_F2_COMMON_UNMACECR_PORT2_SHIFT (2U) 358 #define NETC_F2_COMMON_UNMACECR_PORT2_WIDTH (1U) 359 #define NETC_F2_COMMON_UNMACECR_PORT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMACECR_PORT2_SHIFT)) & NETC_F2_COMMON_UNMACECR_PORT2_MASK) 360 /*! @} */ 361 362 /*! @name UNMACESR - Uncorrectable non-fatal MAC error status register */ 363 /*! @{ */ 364 365 #define NETC_F2_COMMON_UNMACESR_PORT0_MASK (0x1U) 366 #define NETC_F2_COMMON_UNMACESR_PORT0_SHIFT (0U) 367 #define NETC_F2_COMMON_UNMACESR_PORT0_WIDTH (1U) 368 #define NETC_F2_COMMON_UNMACESR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMACESR_PORT0_SHIFT)) & NETC_F2_COMMON_UNMACESR_PORT0_MASK) 369 370 #define NETC_F2_COMMON_UNMACESR_PORT1_MASK (0x2U) 371 #define NETC_F2_COMMON_UNMACESR_PORT1_SHIFT (1U) 372 #define NETC_F2_COMMON_UNMACESR_PORT1_WIDTH (1U) 373 #define NETC_F2_COMMON_UNMACESR_PORT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMACESR_PORT1_SHIFT)) & NETC_F2_COMMON_UNMACESR_PORT1_MASK) 374 375 #define NETC_F2_COMMON_UNMACESR_PORT2_MASK (0x4U) 376 #define NETC_F2_COMMON_UNMACESR_PORT2_SHIFT (2U) 377 #define NETC_F2_COMMON_UNMACESR_PORT2_WIDTH (1U) 378 #define NETC_F2_COMMON_UNMACESR_PORT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMACESR_PORT2_SHIFT)) & NETC_F2_COMMON_UNMACESR_PORT2_MASK) 379 /*! @} */ 380 381 /*! @name UNSBECR - Uncorrectable non-fatal system bus error configuration register */ 382 /*! @{ */ 383 384 #define NETC_F2_COMMON_UNSBECR_THRESHOLD_MASK (0xFFU) 385 #define NETC_F2_COMMON_UNSBECR_THRESHOLD_SHIFT (0U) 386 #define NETC_F2_COMMON_UNSBECR_THRESHOLD_WIDTH (8U) 387 #define NETC_F2_COMMON_UNSBECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNSBECR_THRESHOLD_SHIFT)) & NETC_F2_COMMON_UNSBECR_THRESHOLD_MASK) 388 /*! @} */ 389 390 /*! @name UNSBESR - Uncorrectable non-fatal system bus error status register */ 391 /*! @{ */ 392 393 #define NETC_F2_COMMON_UNSBESR_SB_ID_MASK (0xFU) 394 #define NETC_F2_COMMON_UNSBESR_SB_ID_SHIFT (0U) 395 #define NETC_F2_COMMON_UNSBESR_SB_ID_WIDTH (4U) 396 #define NETC_F2_COMMON_UNSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNSBESR_SB_ID_SHIFT)) & NETC_F2_COMMON_UNSBESR_SB_ID_MASK) 397 398 #define NETC_F2_COMMON_UNSBESR_SBE_MASK (0x80000000U) 399 #define NETC_F2_COMMON_UNSBESR_SBE_SHIFT (31U) 400 #define NETC_F2_COMMON_UNSBESR_SBE_WIDTH (1U) 401 #define NETC_F2_COMMON_UNSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNSBESR_SBE_SHIFT)) & NETC_F2_COMMON_UNSBESR_SBE_MASK) 402 /*! @} */ 403 404 /*! @name UNSBECTR - Uncorrectable non-fatal system bus error count register */ 405 /*! @{ */ 406 407 #define NETC_F2_COMMON_UNSBECTR_COUNT_MASK (0xFFU) 408 #define NETC_F2_COMMON_UNSBECTR_COUNT_SHIFT (0U) 409 #define NETC_F2_COMMON_UNSBECTR_COUNT_WIDTH (8U) 410 #define NETC_F2_COMMON_UNSBECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNSBECTR_COUNT_SHIFT)) & NETC_F2_COMMON_UNSBECTR_COUNT_MASK) 411 /*! @} */ 412 413 /*! @name UFSBECR - Uncorrectable fatal system bus error configuration register */ 414 /*! @{ */ 415 416 #define NETC_F2_COMMON_UFSBECR_RD_MASK (0x80000000U) 417 #define NETC_F2_COMMON_UFSBECR_RD_SHIFT (31U) 418 #define NETC_F2_COMMON_UFSBECR_RD_WIDTH (1U) 419 #define NETC_F2_COMMON_UFSBECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFSBECR_RD_SHIFT)) & NETC_F2_COMMON_UFSBECR_RD_MASK) 420 /*! @} */ 421 422 /*! @name UFSBESR - Uncorrectable fatal system bus error status register */ 423 /*! @{ */ 424 425 #define NETC_F2_COMMON_UFSBESR_SB_ID_MASK (0xFU) 426 #define NETC_F2_COMMON_UFSBESR_SB_ID_SHIFT (0U) 427 #define NETC_F2_COMMON_UFSBESR_SB_ID_WIDTH (4U) 428 #define NETC_F2_COMMON_UFSBESR_SB_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFSBESR_SB_ID_SHIFT)) & NETC_F2_COMMON_UFSBESR_SB_ID_MASK) 429 430 #define NETC_F2_COMMON_UFSBESR_M_MASK (0x40000000U) 431 #define NETC_F2_COMMON_UFSBESR_M_SHIFT (30U) 432 #define NETC_F2_COMMON_UFSBESR_M_WIDTH (1U) 433 #define NETC_F2_COMMON_UFSBESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFSBESR_M_SHIFT)) & NETC_F2_COMMON_UFSBESR_M_MASK) 434 435 #define NETC_F2_COMMON_UFSBESR_SBE_MASK (0x80000000U) 436 #define NETC_F2_COMMON_UFSBESR_SBE_SHIFT (31U) 437 #define NETC_F2_COMMON_UFSBESR_SBE_WIDTH (1U) 438 #define NETC_F2_COMMON_UFSBESR_SBE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFSBESR_SBE_SHIFT)) & NETC_F2_COMMON_UFSBESR_SBE_MASK) 439 /*! @} */ 440 441 /*! @name UNMECR - Uncorrectable non-fatal memory error configuration register */ 442 /*! @{ */ 443 444 #define NETC_F2_COMMON_UNMECR_THRESHOLD_MASK (0xFFU) 445 #define NETC_F2_COMMON_UNMECR_THRESHOLD_SHIFT (0U) 446 #define NETC_F2_COMMON_UNMECR_THRESHOLD_WIDTH (8U) 447 #define NETC_F2_COMMON_UNMECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMECR_THRESHOLD_SHIFT)) & NETC_F2_COMMON_UNMECR_THRESHOLD_MASK) 448 449 #define NETC_F2_COMMON_UNMECR_RD_MASK (0x80000000U) 450 #define NETC_F2_COMMON_UNMECR_RD_SHIFT (31U) 451 #define NETC_F2_COMMON_UNMECR_RD_WIDTH (1U) 452 #define NETC_F2_COMMON_UNMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMECR_RD_SHIFT)) & NETC_F2_COMMON_UNMECR_RD_MASK) 453 /*! @} */ 454 455 /*! @name UNMESR0 - Uncorrectable non-fatal memory error status register 0 */ 456 /*! @{ */ 457 458 #define NETC_F2_COMMON_UNMESR0_SYNDROME_MASK (0x7FFU) 459 #define NETC_F2_COMMON_UNMESR0_SYNDROME_SHIFT (0U) 460 #define NETC_F2_COMMON_UNMESR0_SYNDROME_WIDTH (11U) 461 #define NETC_F2_COMMON_UNMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMESR0_SYNDROME_SHIFT)) & NETC_F2_COMMON_UNMESR0_SYNDROME_MASK) 462 463 #define NETC_F2_COMMON_UNMESR0_MEM_ID_MASK (0x1F0000U) 464 #define NETC_F2_COMMON_UNMESR0_MEM_ID_SHIFT (16U) 465 #define NETC_F2_COMMON_UNMESR0_MEM_ID_WIDTH (5U) 466 #define NETC_F2_COMMON_UNMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMESR0_MEM_ID_SHIFT)) & NETC_F2_COMMON_UNMESR0_MEM_ID_MASK) 467 468 #define NETC_F2_COMMON_UNMESR0_MBEE_MASK (0x80000000U) 469 #define NETC_F2_COMMON_UNMESR0_MBEE_SHIFT (31U) 470 #define NETC_F2_COMMON_UNMESR0_MBEE_WIDTH (1U) 471 #define NETC_F2_COMMON_UNMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMESR0_MBEE_SHIFT)) & NETC_F2_COMMON_UNMESR0_MBEE_MASK) 472 /*! @} */ 473 474 /*! @name UNMESR1 - Uncorrectable non-fatal memory error status register 1 */ 475 /*! @{ */ 476 477 #define NETC_F2_COMMON_UNMESR1_ADDR_MASK (0xFFFFFFFFU) 478 #define NETC_F2_COMMON_UNMESR1_ADDR_SHIFT (0U) 479 #define NETC_F2_COMMON_UNMESR1_ADDR_WIDTH (32U) 480 #define NETC_F2_COMMON_UNMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMESR1_ADDR_SHIFT)) & NETC_F2_COMMON_UNMESR1_ADDR_MASK) 481 /*! @} */ 482 483 /*! @name UNMECTR - Uncorrectable non-fatal memory error count register */ 484 /*! @{ */ 485 486 #define NETC_F2_COMMON_UNMECTR_COUNT_MASK (0xFFU) 487 #define NETC_F2_COMMON_UNMECTR_COUNT_SHIFT (0U) 488 #define NETC_F2_COMMON_UNMECTR_COUNT_WIDTH (8U) 489 #define NETC_F2_COMMON_UNMECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNMECTR_COUNT_SHIFT)) & NETC_F2_COMMON_UNMECTR_COUNT_MASK) 490 /*! @} */ 491 492 /*! @name UFMECR - Uncorrectable fatal memory error configuration register */ 493 /*! @{ */ 494 495 #define NETC_F2_COMMON_UFMECR_RD_MASK (0x80000000U) 496 #define NETC_F2_COMMON_UFMECR_RD_SHIFT (31U) 497 #define NETC_F2_COMMON_UFMECR_RD_WIDTH (1U) 498 #define NETC_F2_COMMON_UFMECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFMECR_RD_SHIFT)) & NETC_F2_COMMON_UFMECR_RD_MASK) 499 /*! @} */ 500 501 /*! @name UFMESR0 - Uncorrectable fatal memory error status register 0 */ 502 /*! @{ */ 503 504 #define NETC_F2_COMMON_UFMESR0_SYNDROME_MASK (0x7FFU) 505 #define NETC_F2_COMMON_UFMESR0_SYNDROME_SHIFT (0U) 506 #define NETC_F2_COMMON_UFMESR0_SYNDROME_WIDTH (11U) 507 #define NETC_F2_COMMON_UFMESR0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFMESR0_SYNDROME_SHIFT)) & NETC_F2_COMMON_UFMESR0_SYNDROME_MASK) 508 509 #define NETC_F2_COMMON_UFMESR0_MEM_ID_MASK (0x1F0000U) 510 #define NETC_F2_COMMON_UFMESR0_MEM_ID_SHIFT (16U) 511 #define NETC_F2_COMMON_UFMESR0_MEM_ID_WIDTH (5U) 512 #define NETC_F2_COMMON_UFMESR0_MEM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFMESR0_MEM_ID_SHIFT)) & NETC_F2_COMMON_UFMESR0_MEM_ID_MASK) 513 514 #define NETC_F2_COMMON_UFMESR0_M_MASK (0x40000000U) 515 #define NETC_F2_COMMON_UFMESR0_M_SHIFT (30U) 516 #define NETC_F2_COMMON_UFMESR0_M_WIDTH (1U) 517 #define NETC_F2_COMMON_UFMESR0_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFMESR0_M_SHIFT)) & NETC_F2_COMMON_UFMESR0_M_MASK) 518 519 #define NETC_F2_COMMON_UFMESR0_MBEE_MASK (0x80000000U) 520 #define NETC_F2_COMMON_UFMESR0_MBEE_SHIFT (31U) 521 #define NETC_F2_COMMON_UFMESR0_MBEE_WIDTH (1U) 522 #define NETC_F2_COMMON_UFMESR0_MBEE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFMESR0_MBEE_SHIFT)) & NETC_F2_COMMON_UFMESR0_MBEE_MASK) 523 /*! @} */ 524 525 /*! @name UFMESR1 - Uncorrectable fatal memory error status register 1 */ 526 /*! @{ */ 527 528 #define NETC_F2_COMMON_UFMESR1_ADDR_MASK (0xFFFFFFFFU) 529 #define NETC_F2_COMMON_UFMESR1_ADDR_SHIFT (0U) 530 #define NETC_F2_COMMON_UFMESR1_ADDR_WIDTH (32U) 531 #define NETC_F2_COMMON_UFMESR1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFMESR1_ADDR_SHIFT)) & NETC_F2_COMMON_UFMESR1_ADDR_MASK) 532 /*! @} */ 533 534 /*! @name UNIECR - Uncorrectable non-fatal integrity error configuration register */ 535 /*! @{ */ 536 537 #define NETC_F2_COMMON_UNIECR_THRESHOLD_MASK (0xFFU) 538 #define NETC_F2_COMMON_UNIECR_THRESHOLD_SHIFT (0U) 539 #define NETC_F2_COMMON_UNIECR_THRESHOLD_WIDTH (8U) 540 #define NETC_F2_COMMON_UNIECR_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNIECR_THRESHOLD_SHIFT)) & NETC_F2_COMMON_UNIECR_THRESHOLD_MASK) 541 542 #define NETC_F2_COMMON_UNIECR_RD_MASK (0x80000000U) 543 #define NETC_F2_COMMON_UNIECR_RD_SHIFT (31U) 544 #define NETC_F2_COMMON_UNIECR_RD_WIDTH (1U) 545 #define NETC_F2_COMMON_UNIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNIECR_RD_SHIFT)) & NETC_F2_COMMON_UNIECR_RD_MASK) 546 /*! @} */ 547 548 /*! @name UNIESR - Uncorrectable non-fatal integrity error status register */ 549 /*! @{ */ 550 551 #define NETC_F2_COMMON_UNIESR_LINK_SLICE_ID_MASK (0xFU) 552 #define NETC_F2_COMMON_UNIESR_LINK_SLICE_ID_SHIFT (0U) 553 #define NETC_F2_COMMON_UNIESR_LINK_SLICE_ID_WIDTH (4U) 554 #define NETC_F2_COMMON_UNIESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNIESR_LINK_SLICE_ID_SHIFT)) & NETC_F2_COMMON_UNIESR_LINK_SLICE_ID_MASK) 555 556 #define NETC_F2_COMMON_UNIESR_BLOCK_ID_MASK (0xF0U) 557 #define NETC_F2_COMMON_UNIESR_BLOCK_ID_SHIFT (4U) 558 #define NETC_F2_COMMON_UNIESR_BLOCK_ID_WIDTH (4U) 559 #define NETC_F2_COMMON_UNIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNIESR_BLOCK_ID_SHIFT)) & NETC_F2_COMMON_UNIESR_BLOCK_ID_MASK) 560 561 #define NETC_F2_COMMON_UNIESR_SM_ID_MASK (0x3F00U) 562 #define NETC_F2_COMMON_UNIESR_SM_ID_SHIFT (8U) 563 #define NETC_F2_COMMON_UNIESR_SM_ID_WIDTH (6U) 564 #define NETC_F2_COMMON_UNIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNIESR_SM_ID_SHIFT)) & NETC_F2_COMMON_UNIESR_SM_ID_MASK) 565 566 #define NETC_F2_COMMON_UNIESR_ENGINE_ID_MASK (0x10000U) 567 #define NETC_F2_COMMON_UNIESR_ENGINE_ID_SHIFT (16U) 568 #define NETC_F2_COMMON_UNIESR_ENGINE_ID_WIDTH (1U) 569 #define NETC_F2_COMMON_UNIESR_ENGINE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNIESR_ENGINE_ID_SHIFT)) & NETC_F2_COMMON_UNIESR_ENGINE_ID_MASK) 570 571 #define NETC_F2_COMMON_UNIESR_INTERR_MASK (0x80000000U) 572 #define NETC_F2_COMMON_UNIESR_INTERR_SHIFT (31U) 573 #define NETC_F2_COMMON_UNIESR_INTERR_WIDTH (1U) 574 #define NETC_F2_COMMON_UNIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNIESR_INTERR_SHIFT)) & NETC_F2_COMMON_UNIESR_INTERR_MASK) 575 /*! @} */ 576 577 /*! @name UNIECTR - Uncorrectable non-fatal integrity error count register */ 578 /*! @{ */ 579 580 #define NETC_F2_COMMON_UNIECTR_COUNT_MASK (0xFFU) 581 #define NETC_F2_COMMON_UNIECTR_COUNT_SHIFT (0U) 582 #define NETC_F2_COMMON_UNIECTR_COUNT_WIDTH (8U) 583 #define NETC_F2_COMMON_UNIECTR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UNIECTR_COUNT_SHIFT)) & NETC_F2_COMMON_UNIECTR_COUNT_MASK) 584 /*! @} */ 585 586 /*! @name UFIECR - Uncorrectable fatal integrity error configuration register */ 587 /*! @{ */ 588 589 #define NETC_F2_COMMON_UFIECR_RD_MASK (0x80000000U) 590 #define NETC_F2_COMMON_UFIECR_RD_SHIFT (31U) 591 #define NETC_F2_COMMON_UFIECR_RD_WIDTH (1U) 592 #define NETC_F2_COMMON_UFIECR_RD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFIECR_RD_SHIFT)) & NETC_F2_COMMON_UFIECR_RD_MASK) 593 /*! @} */ 594 595 /*! @name UFIESR - Uncorrectable fatal integrity error status register */ 596 /*! @{ */ 597 598 #define NETC_F2_COMMON_UFIESR_LINK_SLICE_ID_MASK (0xFU) 599 #define NETC_F2_COMMON_UFIESR_LINK_SLICE_ID_SHIFT (0U) 600 #define NETC_F2_COMMON_UFIESR_LINK_SLICE_ID_WIDTH (4U) 601 #define NETC_F2_COMMON_UFIESR_LINK_SLICE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFIESR_LINK_SLICE_ID_SHIFT)) & NETC_F2_COMMON_UFIESR_LINK_SLICE_ID_MASK) 602 603 #define NETC_F2_COMMON_UFIESR_BLOCK_ID_MASK (0xF0U) 604 #define NETC_F2_COMMON_UFIESR_BLOCK_ID_SHIFT (4U) 605 #define NETC_F2_COMMON_UFIESR_BLOCK_ID_WIDTH (4U) 606 #define NETC_F2_COMMON_UFIESR_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFIESR_BLOCK_ID_SHIFT)) & NETC_F2_COMMON_UFIESR_BLOCK_ID_MASK) 607 608 #define NETC_F2_COMMON_UFIESR_SM_ID_MASK (0x3F00U) 609 #define NETC_F2_COMMON_UFIESR_SM_ID_SHIFT (8U) 610 #define NETC_F2_COMMON_UFIESR_SM_ID_WIDTH (6U) 611 #define NETC_F2_COMMON_UFIESR_SM_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFIESR_SM_ID_SHIFT)) & NETC_F2_COMMON_UFIESR_SM_ID_MASK) 612 613 #define NETC_F2_COMMON_UFIESR_ENGINE_ID_MASK (0x10000U) 614 #define NETC_F2_COMMON_UFIESR_ENGINE_ID_SHIFT (16U) 615 #define NETC_F2_COMMON_UFIESR_ENGINE_ID_WIDTH (1U) 616 #define NETC_F2_COMMON_UFIESR_ENGINE_ID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFIESR_ENGINE_ID_SHIFT)) & NETC_F2_COMMON_UFIESR_ENGINE_ID_MASK) 617 618 #define NETC_F2_COMMON_UFIESR_M_MASK (0x40000000U) 619 #define NETC_F2_COMMON_UFIESR_M_SHIFT (30U) 620 #define NETC_F2_COMMON_UFIESR_M_WIDTH (1U) 621 #define NETC_F2_COMMON_UFIESR_M(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFIESR_M_SHIFT)) & NETC_F2_COMMON_UFIESR_M_MASK) 622 623 #define NETC_F2_COMMON_UFIESR_INTERR_MASK (0x80000000U) 624 #define NETC_F2_COMMON_UFIESR_INTERR_SHIFT (31U) 625 #define NETC_F2_COMMON_UFIESR_INTERR_WIDTH (1U) 626 #define NETC_F2_COMMON_UFIESR_INTERR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_UFIESR_INTERR_SHIFT)) & NETC_F2_COMMON_UFIESR_INTERR_MASK) 627 /*! @} */ 628 629 /*! @name EMDIOIRR - External MDIO interrupt reason register */ 630 /*! @{ */ 631 632 #define NETC_F2_COMMON_EMDIOIRR_PORT0_MASK (0x1U) 633 #define NETC_F2_COMMON_EMDIOIRR_PORT0_SHIFT (0U) 634 #define NETC_F2_COMMON_EMDIOIRR_PORT0_WIDTH (1U) 635 #define NETC_F2_COMMON_EMDIOIRR_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_EMDIOIRR_PORT0_SHIFT)) & NETC_F2_COMMON_EMDIOIRR_PORT0_MASK) 636 637 #define NETC_F2_COMMON_EMDIOIRR_PORT1_MASK (0x2U) 638 #define NETC_F2_COMMON_EMDIOIRR_PORT1_SHIFT (1U) 639 #define NETC_F2_COMMON_EMDIOIRR_PORT1_WIDTH (1U) 640 #define NETC_F2_COMMON_EMDIOIRR_PORT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_EMDIOIRR_PORT1_SHIFT)) & NETC_F2_COMMON_EMDIOIRR_PORT1_MASK) 641 642 #define NETC_F2_COMMON_EMDIOIRR_PORT2_MASK (0x4U) 643 #define NETC_F2_COMMON_EMDIOIRR_PORT2_SHIFT (2U) 644 #define NETC_F2_COMMON_EMDIOIRR_PORT2_WIDTH (1U) 645 #define NETC_F2_COMMON_EMDIOIRR_PORT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_EMDIOIRR_PORT2_SHIFT)) & NETC_F2_COMMON_EMDIOIRR_PORT2_MASK) 646 /*! @} */ 647 648 /*! @name EMDIOMSIVR - External MDIO MSI-X vector register */ 649 /*! @{ */ 650 651 #define NETC_F2_COMMON_EMDIOMSIVR_VECTOR_MASK (0xFU) 652 #define NETC_F2_COMMON_EMDIOMSIVR_VECTOR_SHIFT (0U) 653 #define NETC_F2_COMMON_EMDIOMSIVR_VECTOR_WIDTH (4U) 654 #define NETC_F2_COMMON_EMDIOMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_EMDIOMSIVR_VECTOR_SHIFT)) & NETC_F2_COMMON_EMDIOMSIVR_VECTOR_MASK) 655 /*! @} */ 656 657 /*! @name TCCR - Time capture configuration register */ 658 /*! @{ */ 659 660 #define NETC_F2_COMMON_TCCR_TIMEOUT_MASK (0xFFFFFFU) 661 #define NETC_F2_COMMON_TCCR_TIMEOUT_SHIFT (0U) 662 #define NETC_F2_COMMON_TCCR_TIMEOUT_WIDTH (24U) 663 #define NETC_F2_COMMON_TCCR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCCR_TIMEOUT_SHIFT)) & NETC_F2_COMMON_TCCR_TIMEOUT_MASK) 664 665 #define NETC_F2_COMMON_TCCR_ARM_MASK (0xC0000000U) 666 #define NETC_F2_COMMON_TCCR_ARM_SHIFT (30U) 667 #define NETC_F2_COMMON_TCCR_ARM_WIDTH (2U) 668 #define NETC_F2_COMMON_TCCR_ARM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCCR_ARM_SHIFT)) & NETC_F2_COMMON_TCCR_ARM_MASK) 669 /*! @} */ 670 671 /*! @name TCIER - Time capture interrupt enable register */ 672 /*! @{ */ 673 674 #define NETC_F2_COMMON_TCIER_TRANSMIT_MASK (0x40000000U) 675 #define NETC_F2_COMMON_TCIER_TRANSMIT_SHIFT (30U) 676 #define NETC_F2_COMMON_TCIER_TRANSMIT_WIDTH (1U) 677 #define NETC_F2_COMMON_TCIER_TRANSMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCIER_TRANSMIT_SHIFT)) & NETC_F2_COMMON_TCIER_TRANSMIT_MASK) 678 679 #define NETC_F2_COMMON_TCIER_TIMEOUT_MASK (0x80000000U) 680 #define NETC_F2_COMMON_TCIER_TIMEOUT_SHIFT (31U) 681 #define NETC_F2_COMMON_TCIER_TIMEOUT_WIDTH (1U) 682 #define NETC_F2_COMMON_TCIER_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCIER_TIMEOUT_SHIFT)) & NETC_F2_COMMON_TCIER_TIMEOUT_MASK) 683 /*! @} */ 684 685 /*! @name TCRPIDR - Time capture receive port interrupt detect register */ 686 /*! @{ */ 687 688 #define NETC_F2_COMMON_TCRPIDR_TX_PORT0_MASK (0x1U) 689 #define NETC_F2_COMMON_TCRPIDR_TX_PORT0_SHIFT (0U) 690 #define NETC_F2_COMMON_TCRPIDR_TX_PORT0_WIDTH (1U) 691 #define NETC_F2_COMMON_TCRPIDR_TX_PORT0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCRPIDR_TX_PORT0_SHIFT)) & NETC_F2_COMMON_TCRPIDR_TX_PORT0_MASK) 692 693 #define NETC_F2_COMMON_TCRPIDR_TX_PORT1_MASK (0x2U) 694 #define NETC_F2_COMMON_TCRPIDR_TX_PORT1_SHIFT (1U) 695 #define NETC_F2_COMMON_TCRPIDR_TX_PORT1_WIDTH (1U) 696 #define NETC_F2_COMMON_TCRPIDR_TX_PORT1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCRPIDR_TX_PORT1_SHIFT)) & NETC_F2_COMMON_TCRPIDR_TX_PORT1_MASK) 697 698 #define NETC_F2_COMMON_TCRPIDR_TX_PORT2_MASK (0x4U) 699 #define NETC_F2_COMMON_TCRPIDR_TX_PORT2_SHIFT (2U) 700 #define NETC_F2_COMMON_TCRPIDR_TX_PORT2_WIDTH (1U) 701 #define NETC_F2_COMMON_TCRPIDR_TX_PORT2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCRPIDR_TX_PORT2_SHIFT)) & NETC_F2_COMMON_TCRPIDR_TX_PORT2_MASK) 702 703 #define NETC_F2_COMMON_TCRPIDR_TRANSMIT_MASK (0x40000000U) 704 #define NETC_F2_COMMON_TCRPIDR_TRANSMIT_SHIFT (30U) 705 #define NETC_F2_COMMON_TCRPIDR_TRANSMIT_WIDTH (1U) 706 #define NETC_F2_COMMON_TCRPIDR_TRANSMIT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCRPIDR_TRANSMIT_SHIFT)) & NETC_F2_COMMON_TCRPIDR_TRANSMIT_MASK) 707 708 #define NETC_F2_COMMON_TCRPIDR_TIMEOUT_MASK (0x80000000U) 709 #define NETC_F2_COMMON_TCRPIDR_TIMEOUT_SHIFT (31U) 710 #define NETC_F2_COMMON_TCRPIDR_TIMEOUT_WIDTH (1U) 711 #define NETC_F2_COMMON_TCRPIDR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCRPIDR_TIMEOUT_SHIFT)) & NETC_F2_COMMON_TCRPIDR_TIMEOUT_MASK) 712 /*! @} */ 713 714 /*! @name TCRPSR - Time capture receive port status register */ 715 /*! @{ */ 716 717 #define NETC_F2_COMMON_TCRPSR_RX_PORT_MASK (0x1FU) 718 #define NETC_F2_COMMON_TCRPSR_RX_PORT_SHIFT (0U) 719 #define NETC_F2_COMMON_TCRPSR_RX_PORT_WIDTH (5U) 720 #define NETC_F2_COMMON_TCRPSR_RX_PORT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCRPSR_RX_PORT_SHIFT)) & NETC_F2_COMMON_TCRPSR_RX_PORT_MASK) 721 722 #define NETC_F2_COMMON_TCRPSR_RX_CNT_MASK (0x300U) 723 #define NETC_F2_COMMON_TCRPSR_RX_CNT_SHIFT (8U) 724 #define NETC_F2_COMMON_TCRPSR_RX_CNT_WIDTH (2U) 725 #define NETC_F2_COMMON_TCRPSR_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCRPSR_RX_CNT_SHIFT)) & NETC_F2_COMMON_TCRPSR_RX_CNT_MASK) 726 /*! @} */ 727 728 /*! @name TCRPTSR - Time capture receive port timestamp register */ 729 /*! @{ */ 730 731 #define NETC_F2_COMMON_TCRPTSR_TIMESTAMP_MASK (0xFFFFFFFFU) 732 #define NETC_F2_COMMON_TCRPTSR_TIMESTAMP_SHIFT (0U) 733 #define NETC_F2_COMMON_TCRPTSR_TIMESTAMP_WIDTH (32U) 734 #define NETC_F2_COMMON_TCRPTSR_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCRPTSR_TIMESTAMP_SHIFT)) & NETC_F2_COMMON_TCRPTSR_TIMESTAMP_MASK) 735 /*! @} */ 736 737 /*! @name TCMSIVR - Time capture MSI-X vector register */ 738 /*! @{ */ 739 740 #define NETC_F2_COMMON_TCMSIVR_VECTOR_MASK (0xFU) 741 #define NETC_F2_COMMON_TCMSIVR_VECTOR_SHIFT (0U) 742 #define NETC_F2_COMMON_TCMSIVR_VECTOR_WIDTH (4U) 743 #define NETC_F2_COMMON_TCMSIVR_VECTOR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TCMSIVR_VECTOR_SHIFT)) & NETC_F2_COMMON_TCMSIVR_VECTOR_MASK) 744 /*! @} */ 745 746 /*! @name CVLANR1 - Custom VLAN Ethertype register 1 */ 747 /*! @{ */ 748 749 #define NETC_F2_COMMON_CVLANR1_ETYPE_MASK (0xFFFFU) 750 #define NETC_F2_COMMON_CVLANR1_ETYPE_SHIFT (0U) 751 #define NETC_F2_COMMON_CVLANR1_ETYPE_WIDTH (16U) 752 #define NETC_F2_COMMON_CVLANR1_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_CVLANR1_ETYPE_SHIFT)) & NETC_F2_COMMON_CVLANR1_ETYPE_MASK) 753 754 #define NETC_F2_COMMON_CVLANR1_V_MASK (0x80000000U) 755 #define NETC_F2_COMMON_CVLANR1_V_SHIFT (31U) 756 #define NETC_F2_COMMON_CVLANR1_V_WIDTH (1U) 757 #define NETC_F2_COMMON_CVLANR1_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_CVLANR1_V_SHIFT)) & NETC_F2_COMMON_CVLANR1_V_MASK) 758 /*! @} */ 759 760 /*! @name CVLANR2 - Custom VLAN Ethertype register 2 */ 761 /*! @{ */ 762 763 #define NETC_F2_COMMON_CVLANR2_ETYPE_MASK (0xFFFFU) 764 #define NETC_F2_COMMON_CVLANR2_ETYPE_SHIFT (0U) 765 #define NETC_F2_COMMON_CVLANR2_ETYPE_WIDTH (16U) 766 #define NETC_F2_COMMON_CVLANR2_ETYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_CVLANR2_ETYPE_SHIFT)) & NETC_F2_COMMON_CVLANR2_ETYPE_MASK) 767 768 #define NETC_F2_COMMON_CVLANR2_V_MASK (0x80000000U) 769 #define NETC_F2_COMMON_CVLANR2_V_SHIFT (31U) 770 #define NETC_F2_COMMON_CVLANR2_V_WIDTH (1U) 771 #define NETC_F2_COMMON_CVLANR2_V(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_CVLANR2_V_SHIFT)) & NETC_F2_COMMON_CVLANR2_V_MASK) 772 /*! @} */ 773 774 /*! @name PSRTAGETR - Pre-Standard RTAG Ethertype register */ 775 /*! @{ */ 776 777 #define NETC_F2_COMMON_PSRTAGETR_ETHERTYPE_MASK (0xFFFFU) 778 #define NETC_F2_COMMON_PSRTAGETR_ETHERTYPE_SHIFT (0U) 779 #define NETC_F2_COMMON_PSRTAGETR_ETHERTYPE_WIDTH (16U) 780 #define NETC_F2_COMMON_PSRTAGETR_ETHERTYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_PSRTAGETR_ETHERTYPE_SHIFT)) & NETC_F2_COMMON_PSRTAGETR_ETHERTYPE_MASK) 781 /*! @} */ 782 783 /*! @name DOSL2CR - DoS L2 configuration register */ 784 /*! @{ */ 785 786 #define NETC_F2_COMMON_DOSL2CR_SAMEADDR_MASK (0x1U) 787 #define NETC_F2_COMMON_DOSL2CR_SAMEADDR_SHIFT (0U) 788 #define NETC_F2_COMMON_DOSL2CR_SAMEADDR_WIDTH (1U) 789 #define NETC_F2_COMMON_DOSL2CR_SAMEADDR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_DOSL2CR_SAMEADDR_SHIFT)) & NETC_F2_COMMON_DOSL2CR_SAMEADDR_MASK) 790 791 #define NETC_F2_COMMON_DOSL2CR_MSAMCC_MASK (0x2U) 792 #define NETC_F2_COMMON_DOSL2CR_MSAMCC_SHIFT (1U) 793 #define NETC_F2_COMMON_DOSL2CR_MSAMCC_WIDTH (1U) 794 #define NETC_F2_COMMON_DOSL2CR_MSAMCC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_DOSL2CR_MSAMCC_SHIFT)) & NETC_F2_COMMON_DOSL2CR_MSAMCC_MASK) 795 /*! @} */ 796 797 /*! @name VLANIPVMPR0 - VLAN to IPV mapping profile 0 register 0..VLAN to IPV mapping profile 1 register 0 */ 798 /*! @{ */ 799 800 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_0_MASK (0x7U) 801 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_0_SHIFT (0U) 802 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_0_WIDTH (3U) 803 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_0_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_0_MASK) 804 805 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_1_MASK (0x70U) 806 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_1_SHIFT (4U) 807 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_1_WIDTH (3U) 808 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_1_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_1_MASK) 809 810 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_2_MASK (0x700U) 811 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_2_SHIFT (8U) 812 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_2_WIDTH (3U) 813 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_2_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_2_MASK) 814 815 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_3_MASK (0x7000U) 816 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_3_SHIFT (12U) 817 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_3_WIDTH (3U) 818 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_3_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_3_MASK) 819 820 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_4_MASK (0x70000U) 821 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_4_SHIFT (16U) 822 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_4_WIDTH (3U) 823 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_4_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_4_MASK) 824 825 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_5_MASK (0x700000U) 826 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_5_SHIFT (20U) 827 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_5_WIDTH (3U) 828 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_5_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_5_MASK) 829 830 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_6_MASK (0x7000000U) 831 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_6_SHIFT (24U) 832 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_6_WIDTH (3U) 833 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_6_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_6_MASK) 834 835 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_7_MASK (0x70000000U) 836 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_7_SHIFT (28U) 837 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_7_WIDTH (3U) 838 #define NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_7_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR0_PCP_DEI_7_MASK) 839 /*! @} */ 840 841 /*! @name VLANIPVMPR1 - VLAN to IPV mapping profile 0 register 1..VLAN to IPV mapping profile 1 register 1 */ 842 /*! @{ */ 843 844 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_8_MASK (0x7U) 845 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_8_SHIFT (0U) 846 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_8_WIDTH (3U) 847 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_8_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_8_MASK) 848 849 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_9_MASK (0x70U) 850 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_9_SHIFT (4U) 851 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_9_WIDTH (3U) 852 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_9_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_9_MASK) 853 854 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_10_MASK (0x700U) 855 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_10_SHIFT (8U) 856 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_10_WIDTH (3U) 857 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_10_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_10_MASK) 858 859 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_11_MASK (0x7000U) 860 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_11_SHIFT (12U) 861 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_11_WIDTH (3U) 862 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_11_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_11_MASK) 863 864 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_12_MASK (0x70000U) 865 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_12_SHIFT (16U) 866 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_12_WIDTH (3U) 867 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_12_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_12_MASK) 868 869 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_13_MASK (0x700000U) 870 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_13_SHIFT (20U) 871 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_13_WIDTH (3U) 872 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_13_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_13_MASK) 873 874 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_14_MASK (0x7000000U) 875 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_14_SHIFT (24U) 876 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_14_WIDTH (3U) 877 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_14_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_14_MASK) 878 879 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_15_MASK (0x70000000U) 880 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_15_SHIFT (28U) 881 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_15_WIDTH (3U) 882 #define NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_15_SHIFT)) & NETC_F2_COMMON_VLANIPVMPR1_PCP_DEI_15_MASK) 883 /*! @} */ 884 885 /*! @name VLANDRMPR - VLAN to DR mapping profile 0 register..VLAN to DR mapping profile 1 register */ 886 /*! @{ */ 887 888 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_0_MASK (0x3U) 889 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_0_SHIFT (0U) 890 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_0_WIDTH (2U) 891 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_0(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_0_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_0_MASK) 892 893 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_1_MASK (0xCU) 894 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_1_SHIFT (2U) 895 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_1_WIDTH (2U) 896 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_1(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_1_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_1_MASK) 897 898 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_2_MASK (0x30U) 899 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_2_SHIFT (4U) 900 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_2_WIDTH (2U) 901 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_2(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_2_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_2_MASK) 902 903 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_3_MASK (0xC0U) 904 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_3_SHIFT (6U) 905 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_3_WIDTH (2U) 906 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_3(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_3_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_3_MASK) 907 908 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_4_MASK (0x300U) 909 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_4_SHIFT (8U) 910 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_4_WIDTH (2U) 911 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_4(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_4_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_4_MASK) 912 913 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_5_MASK (0xC00U) 914 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_5_SHIFT (10U) 915 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_5_WIDTH (2U) 916 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_5(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_5_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_5_MASK) 917 918 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_6_MASK (0x3000U) 919 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_6_SHIFT (12U) 920 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_6_WIDTH (2U) 921 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_6(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_6_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_6_MASK) 922 923 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_7_MASK (0xC000U) 924 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_7_SHIFT (14U) 925 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_7_WIDTH (2U) 926 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_7(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_7_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_7_MASK) 927 928 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_8_MASK (0x30000U) 929 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_8_SHIFT (16U) 930 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_8_WIDTH (2U) 931 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_8(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_8_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_8_MASK) 932 933 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_9_MASK (0xC0000U) 934 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_9_SHIFT (18U) 935 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_9_WIDTH (2U) 936 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_9(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_9_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_9_MASK) 937 938 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_10_MASK (0x300000U) 939 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_10_SHIFT (20U) 940 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_10_WIDTH (2U) 941 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_10(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_10_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_10_MASK) 942 943 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_11_MASK (0xC00000U) 944 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_11_SHIFT (22U) 945 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_11_WIDTH (2U) 946 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_11(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_11_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_11_MASK) 947 948 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_12_MASK (0x3000000U) 949 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_12_SHIFT (24U) 950 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_12_WIDTH (2U) 951 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_12(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_12_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_12_MASK) 952 953 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_13_MASK (0xC000000U) 954 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_13_SHIFT (26U) 955 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_13_WIDTH (2U) 956 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_13(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_13_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_13_MASK) 957 958 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_14_MASK (0x30000000U) 959 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_14_SHIFT (28U) 960 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_14_WIDTH (2U) 961 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_14(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_14_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_14_MASK) 962 963 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_15_MASK (0xC0000000U) 964 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_15_SHIFT (30U) 965 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_15_WIDTH (2U) 966 #define NETC_F2_COMMON_VLANDRMPR_PCP_DEI_15(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_VLANDRMPR_PCP_DEI_15_SHIFT)) & NETC_F2_COMMON_VLANDRMPR_PCP_DEI_15_MASK) 967 /*! @} */ 968 969 /*! @name IPFCAPR - Ingress port filter capability register */ 970 /*! @{ */ 971 972 #define NETC_F2_COMMON_IPFCAPR_RP_MASK (0x1U) 973 #define NETC_F2_COMMON_IPFCAPR_RP_SHIFT (0U) 974 #define NETC_F2_COMMON_IPFCAPR_RP_WIDTH (1U) 975 #define NETC_F2_COMMON_IPFCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPFCAPR_RP_SHIFT)) & NETC_F2_COMMON_IPFCAPR_RP_MASK) 976 977 #define NETC_F2_COMMON_IPFCAPR_ISID_MASK (0x2U) 978 #define NETC_F2_COMMON_IPFCAPR_ISID_SHIFT (1U) 979 #define NETC_F2_COMMON_IPFCAPR_ISID_WIDTH (1U) 980 #define NETC_F2_COMMON_IPFCAPR_ISID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPFCAPR_ISID_SHIFT)) & NETC_F2_COMMON_IPFCAPR_ISID_MASK) 981 /*! @} */ 982 983 /*! @name IPFTCAPR - Ingress port filter table capability register */ 984 /*! @{ */ 985 986 #define NETC_F2_COMMON_IPFTCAPR_NUM_WORDS_MASK (0xFFFFU) 987 #define NETC_F2_COMMON_IPFTCAPR_NUM_WORDS_SHIFT (0U) 988 #define NETC_F2_COMMON_IPFTCAPR_NUM_WORDS_WIDTH (16U) 989 #define NETC_F2_COMMON_IPFTCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPFTCAPR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_IPFTCAPR_NUM_WORDS_MASK) 990 991 #define NETC_F2_COMMON_IPFTCAPR_MGMT_MASK (0x10000U) 992 #define NETC_F2_COMMON_IPFTCAPR_MGMT_SHIFT (16U) 993 #define NETC_F2_COMMON_IPFTCAPR_MGMT_WIDTH (1U) 994 #define NETC_F2_COMMON_IPFTCAPR_MGMT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPFTCAPR_MGMT_SHIFT)) & NETC_F2_COMMON_IPFTCAPR_MGMT_MASK) 995 996 #define NETC_F2_COMMON_IPFTCAPR_ACCESS_METH_MASK (0xF00000U) 997 #define NETC_F2_COMMON_IPFTCAPR_ACCESS_METH_SHIFT (20U) 998 #define NETC_F2_COMMON_IPFTCAPR_ACCESS_METH_WIDTH (4U) 999 #define NETC_F2_COMMON_IPFTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPFTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_IPFTCAPR_ACCESS_METH_MASK) 1000 1001 #define NETC_F2_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_MASK (0xF000000U) 1002 #define NETC_F2_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_SHIFT (24U) 1003 #define NETC_F2_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_WIDTH (4U) 1004 #define NETC_F2_COMMON_IPFTCAPR_ENTRY_MAX_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_SHIFT)) & NETC_F2_COMMON_IPFTCAPR_ENTRY_MAX_WORDS_MASK) 1005 1006 #define NETC_F2_COMMON_IPFTCAPR_WORD_SIZE_MASK (0x30000000U) 1007 #define NETC_F2_COMMON_IPFTCAPR_WORD_SIZE_SHIFT (28U) 1008 #define NETC_F2_COMMON_IPFTCAPR_WORD_SIZE_WIDTH (2U) 1009 #define NETC_F2_COMMON_IPFTCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPFTCAPR_WORD_SIZE_SHIFT)) & NETC_F2_COMMON_IPFTCAPR_WORD_SIZE_MASK) 1010 /*! @} */ 1011 1012 /*! @name IPFTMOR - Ingress port filter table memory operational register */ 1013 /*! @{ */ 1014 1015 #define NETC_F2_COMMON_IPFTMOR_NUM_WORDS_MASK (0xFFFFU) 1016 #define NETC_F2_COMMON_IPFTMOR_NUM_WORDS_SHIFT (0U) 1017 #define NETC_F2_COMMON_IPFTMOR_NUM_WORDS_WIDTH (16U) 1018 #define NETC_F2_COMMON_IPFTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_IPFTMOR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_IPFTMOR_NUM_WORDS_MASK) 1019 /*! @} */ 1020 1021 /*! @name ITMCAPR - Index table memory capability register */ 1022 /*! @{ */ 1023 1024 #define NETC_F2_COMMON_ITMCAPR_NUM_WORDS_MASK (0xFFFFU) 1025 #define NETC_F2_COMMON_ITMCAPR_NUM_WORDS_SHIFT (0U) 1026 #define NETC_F2_COMMON_ITMCAPR_NUM_WORDS_WIDTH (16U) 1027 #define NETC_F2_COMMON_ITMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ITMCAPR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_ITMCAPR_NUM_WORDS_MASK) 1028 1029 #define NETC_F2_COMMON_ITMCAPR_WORD_SIZE_MASK (0x30000000U) 1030 #define NETC_F2_COMMON_ITMCAPR_WORD_SIZE_SHIFT (28U) 1031 #define NETC_F2_COMMON_ITMCAPR_WORD_SIZE_WIDTH (2U) 1032 #define NETC_F2_COMMON_ITMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ITMCAPR_WORD_SIZE_SHIFT)) & NETC_F2_COMMON_ITMCAPR_WORD_SIZE_MASK) 1033 1034 #define NETC_F2_COMMON_ITMCAPR_MLOC_MASK (0xC0000000U) 1035 #define NETC_F2_COMMON_ITMCAPR_MLOC_SHIFT (30U) 1036 #define NETC_F2_COMMON_ITMCAPR_MLOC_WIDTH (2U) 1037 #define NETC_F2_COMMON_ITMCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ITMCAPR_MLOC_SHIFT)) & NETC_F2_COMMON_ITMCAPR_MLOC_MASK) 1038 /*! @} */ 1039 1040 /*! @name RPCAPR - Rate policer capability register */ 1041 /*! @{ */ 1042 1043 #define NETC_F2_COMMON_RPCAPR_TRTCM_MASK (0x1U) 1044 #define NETC_F2_COMMON_RPCAPR_TRTCM_SHIFT (0U) 1045 #define NETC_F2_COMMON_RPCAPR_TRTCM_WIDTH (1U) 1046 #define NETC_F2_COMMON_RPCAPR_TRTCM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_RPCAPR_TRTCM_SHIFT)) & NETC_F2_COMMON_RPCAPR_TRTCM_MASK) 1047 1048 #define NETC_F2_COMMON_RPCAPR_CM_MASK (0x2U) 1049 #define NETC_F2_COMMON_RPCAPR_CM_SHIFT (1U) 1050 #define NETC_F2_COMMON_RPCAPR_CM_WIDTH (1U) 1051 #define NETC_F2_COMMON_RPCAPR_CM(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_RPCAPR_CM_SHIFT)) & NETC_F2_COMMON_RPCAPR_CM_MASK) 1052 /*! @} */ 1053 1054 /*! @name RPITCAPR - Rate policer index table capability register */ 1055 /*! @{ */ 1056 1057 #define NETC_F2_COMMON_RPITCAPR_NUM_ENTRIES_MASK (0x3FFFU) 1058 #define NETC_F2_COMMON_RPITCAPR_NUM_ENTRIES_SHIFT (0U) 1059 #define NETC_F2_COMMON_RPITCAPR_NUM_ENTRIES_WIDTH (14U) 1060 #define NETC_F2_COMMON_RPITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_RPITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_RPITCAPR_NUM_ENTRIES_MASK) 1061 1062 #define NETC_F2_COMMON_RPITCAPR_ACCESS_METH_MASK (0xF00000U) 1063 #define NETC_F2_COMMON_RPITCAPR_ACCESS_METH_SHIFT (20U) 1064 #define NETC_F2_COMMON_RPITCAPR_ACCESS_METH_WIDTH (4U) 1065 #define NETC_F2_COMMON_RPITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_RPITCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_RPITCAPR_ACCESS_METH_MASK) 1066 /*! @} */ 1067 1068 /*! @name RPITMAR - Rate policer index table memory allocation register */ 1069 /*! @{ */ 1070 1071 #define NETC_F2_COMMON_RPITMAR_NUM_WORDS_MASK (0xFFFFU) 1072 #define NETC_F2_COMMON_RPITMAR_NUM_WORDS_SHIFT (0U) 1073 #define NETC_F2_COMMON_RPITMAR_NUM_WORDS_WIDTH (16U) 1074 #define NETC_F2_COMMON_RPITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_RPITMAR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_RPITMAR_NUM_WORDS_MASK) 1075 /*! @} */ 1076 1077 /*! @name RPITOR - Rate policer index table operational register */ 1078 /*! @{ */ 1079 1080 #define NETC_F2_COMMON_RPITOR_NUM_ENTRIES_MASK (0x3FFFU) 1081 #define NETC_F2_COMMON_RPITOR_NUM_ENTRIES_SHIFT (0U) 1082 #define NETC_F2_COMMON_RPITOR_NUM_ENTRIES_WIDTH (14U) 1083 #define NETC_F2_COMMON_RPITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_RPITOR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_RPITOR_NUM_ENTRIES_MASK) 1084 /*! @} */ 1085 1086 /*! @name ISCITCAPR - Ingress stream counter index table capability register */ 1087 /*! @{ */ 1088 1089 #define NETC_F2_COMMON_ISCITCAPR_NUM_ENTRIES_MASK (0xFFFFU) 1090 #define NETC_F2_COMMON_ISCITCAPR_NUM_ENTRIES_SHIFT (0U) 1091 #define NETC_F2_COMMON_ISCITCAPR_NUM_ENTRIES_WIDTH (16U) 1092 #define NETC_F2_COMMON_ISCITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISCITCAPR_NUM_ENTRIES_MASK) 1093 1094 #define NETC_F2_COMMON_ISCITCAPR_ACCESS_METH_MASK (0xF00000U) 1095 #define NETC_F2_COMMON_ISCITCAPR_ACCESS_METH_SHIFT (20U) 1096 #define NETC_F2_COMMON_ISCITCAPR_ACCESS_METH_WIDTH (4U) 1097 #define NETC_F2_COMMON_ISCITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCITCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_ISCITCAPR_ACCESS_METH_MASK) 1098 /*! @} */ 1099 1100 /*! @name ISCITMAR - Ingress stream counter index table memory allocation register */ 1101 /*! @{ */ 1102 1103 #define NETC_F2_COMMON_ISCITMAR_NUM_WORDS_MASK (0xFFFFU) 1104 #define NETC_F2_COMMON_ISCITMAR_NUM_WORDS_SHIFT (0U) 1105 #define NETC_F2_COMMON_ISCITMAR_NUM_WORDS_WIDTH (16U) 1106 #define NETC_F2_COMMON_ISCITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCITMAR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_ISCITMAR_NUM_WORDS_MASK) 1107 /*! @} */ 1108 1109 /*! @name ISCITOR - Ingress stream counter index table operational register */ 1110 /*! @{ */ 1111 1112 #define NETC_F2_COMMON_ISCITOR_NUM_ENTRIES_MASK (0xFFFFU) 1113 #define NETC_F2_COMMON_ISCITOR_NUM_ENTRIES_SHIFT (0U) 1114 #define NETC_F2_COMMON_ISCITOR_NUM_ENTRIES_WIDTH (16U) 1115 #define NETC_F2_COMMON_ISCITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCITOR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISCITOR_NUM_ENTRIES_MASK) 1116 /*! @} */ 1117 1118 /*! @name ISCAPR - Ingress stream capability register */ 1119 /*! @{ */ 1120 1121 #define NETC_F2_COMMON_ISCAPR_ISQG_MASK (0x2U) 1122 #define NETC_F2_COMMON_ISCAPR_ISQG_SHIFT (1U) 1123 #define NETC_F2_COMMON_ISCAPR_ISQG_WIDTH (1U) 1124 #define NETC_F2_COMMON_ISCAPR_ISQG(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCAPR_ISQG_SHIFT)) & NETC_F2_COMMON_ISCAPR_ISQG_MASK) 1125 1126 #define NETC_F2_COMMON_ISCAPR_SG_MASK (0x8U) 1127 #define NETC_F2_COMMON_ISCAPR_SG_SHIFT (3U) 1128 #define NETC_F2_COMMON_ISCAPR_SG_WIDTH (1U) 1129 #define NETC_F2_COMMON_ISCAPR_SG(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCAPR_SG_SHIFT)) & NETC_F2_COMMON_ISCAPR_SG_MASK) 1130 1131 #define NETC_F2_COMMON_ISCAPR_RP_MASK (0x10U) 1132 #define NETC_F2_COMMON_ISCAPR_RP_SHIFT (4U) 1133 #define NETC_F2_COMMON_ISCAPR_RP_WIDTH (1U) 1134 #define NETC_F2_COMMON_ISCAPR_RP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCAPR_RP_SHIFT)) & NETC_F2_COMMON_ISCAPR_RP_MASK) 1135 1136 #define NETC_F2_COMMON_ISCAPR_MAXSDU_MASK (0x20U) 1137 #define NETC_F2_COMMON_ISCAPR_MAXSDU_SHIFT (5U) 1138 #define NETC_F2_COMMON_ISCAPR_MAXSDU_WIDTH (1U) 1139 #define NETC_F2_COMMON_ISCAPR_MAXSDU(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCAPR_MAXSDU_SHIFT)) & NETC_F2_COMMON_ISCAPR_MAXSDU_MASK) 1140 1141 #define NETC_F2_COMMON_ISCAPR_FWD_MASK (0x200U) 1142 #define NETC_F2_COMMON_ISCAPR_FWD_SHIFT (9U) 1143 #define NETC_F2_COMMON_ISCAPR_FWD_WIDTH (1U) 1144 #define NETC_F2_COMMON_ISCAPR_FWD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCAPR_FWD_SHIFT)) & NETC_F2_COMMON_ISCAPR_FWD_MASK) 1145 1146 #define NETC_F2_COMMON_ISCAPR_ET_MASK (0x400U) 1147 #define NETC_F2_COMMON_ISCAPR_ET_SHIFT (10U) 1148 #define NETC_F2_COMMON_ISCAPR_ET_WIDTH (1U) 1149 #define NETC_F2_COMMON_ISCAPR_ET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISCAPR_ET_SHIFT)) & NETC_F2_COMMON_ISCAPR_ET_MASK) 1150 /*! @} */ 1151 1152 /*! @name ISITCAPR - Ingress stream index table capability register */ 1153 /*! @{ */ 1154 1155 #define NETC_F2_COMMON_ISITCAPR_NUM_ENTRIES_MASK (0xFFFFU) 1156 #define NETC_F2_COMMON_ISITCAPR_NUM_ENTRIES_SHIFT (0U) 1157 #define NETC_F2_COMMON_ISITCAPR_NUM_ENTRIES_WIDTH (16U) 1158 #define NETC_F2_COMMON_ISITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISITCAPR_NUM_ENTRIES_MASK) 1159 1160 #define NETC_F2_COMMON_ISITCAPR_ACCESS_METH_MASK (0xF00000U) 1161 #define NETC_F2_COMMON_ISITCAPR_ACCESS_METH_SHIFT (20U) 1162 #define NETC_F2_COMMON_ISITCAPR_ACCESS_METH_WIDTH (4U) 1163 #define NETC_F2_COMMON_ISITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISITCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_ISITCAPR_ACCESS_METH_MASK) 1164 /*! @} */ 1165 1166 /*! @name ISITMAR - Ingress stream index table memory allocation register */ 1167 /*! @{ */ 1168 1169 #define NETC_F2_COMMON_ISITMAR_NUM_WORDS_MASK (0xFFFFU) 1170 #define NETC_F2_COMMON_ISITMAR_NUM_WORDS_SHIFT (0U) 1171 #define NETC_F2_COMMON_ISITMAR_NUM_WORDS_WIDTH (16U) 1172 #define NETC_F2_COMMON_ISITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISITMAR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_ISITMAR_NUM_WORDS_MASK) 1173 /*! @} */ 1174 1175 /*! @name ISITOR - Ingress stream index table operational register */ 1176 /*! @{ */ 1177 1178 #define NETC_F2_COMMON_ISITOR_NUM_ENTRIES_MASK (0xFFFFU) 1179 #define NETC_F2_COMMON_ISITOR_NUM_ENTRIES_SHIFT (0U) 1180 #define NETC_F2_COMMON_ISITOR_NUM_ENTRIES_WIDTH (16U) 1181 #define NETC_F2_COMMON_ISITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISITOR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISITOR_NUM_ENTRIES_MASK) 1182 /*! @} */ 1183 1184 /*! @name ISQGITCAPR - Ingress sequence generation index table capability register */ 1185 /*! @{ */ 1186 1187 #define NETC_F2_COMMON_ISQGITCAPR_NUM_ENTRIES_MASK (0xFFFFU) 1188 #define NETC_F2_COMMON_ISQGITCAPR_NUM_ENTRIES_SHIFT (0U) 1189 #define NETC_F2_COMMON_ISQGITCAPR_NUM_ENTRIES_WIDTH (16U) 1190 #define NETC_F2_COMMON_ISQGITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISQGITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISQGITCAPR_NUM_ENTRIES_MASK) 1191 1192 #define NETC_F2_COMMON_ISQGITCAPR_ACCESS_METH_MASK (0xF00000U) 1193 #define NETC_F2_COMMON_ISQGITCAPR_ACCESS_METH_SHIFT (20U) 1194 #define NETC_F2_COMMON_ISQGITCAPR_ACCESS_METH_WIDTH (4U) 1195 #define NETC_F2_COMMON_ISQGITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISQGITCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_ISQGITCAPR_ACCESS_METH_MASK) 1196 /*! @} */ 1197 1198 /*! @name ISQGITMAR - Ingress sequence generation index table memory allocation register */ 1199 /*! @{ */ 1200 1201 #define NETC_F2_COMMON_ISQGITMAR_NUM_WORDS_MASK (0x1FFFU) 1202 #define NETC_F2_COMMON_ISQGITMAR_NUM_WORDS_SHIFT (0U) 1203 #define NETC_F2_COMMON_ISQGITMAR_NUM_WORDS_WIDTH (13U) 1204 #define NETC_F2_COMMON_ISQGITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISQGITMAR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_ISQGITMAR_NUM_WORDS_MASK) 1205 /*! @} */ 1206 1207 /*! @name ISQGITOR - Ingress sequence generation index table operational register */ 1208 /*! @{ */ 1209 1210 #define NETC_F2_COMMON_ISQGITOR_NUM_ENTRIES_MASK (0xFFFFU) 1211 #define NETC_F2_COMMON_ISQGITOR_NUM_ENTRIES_SHIFT (0U) 1212 #define NETC_F2_COMMON_ISQGITOR_NUM_ENTRIES_WIDTH (16U) 1213 #define NETC_F2_COMMON_ISQGITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISQGITOR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISQGITOR_NUM_ENTRIES_MASK) 1214 /*! @} */ 1215 1216 /*! @name SGCAPR - Stream gate capability register */ 1217 /*! @{ */ 1218 1219 #define NETC_F2_COMMON_SGCAPR_GLC_AO_MASK (0x1U) 1220 #define NETC_F2_COMMON_SGCAPR_GLC_AO_SHIFT (0U) 1221 #define NETC_F2_COMMON_SGCAPR_GLC_AO_WIDTH (1U) 1222 #define NETC_F2_COMMON_SGCAPR_GLC_AO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCAPR_GLC_AO_SHIFT)) & NETC_F2_COMMON_SGCAPR_GLC_AO_MASK) 1223 1224 #define NETC_F2_COMMON_SGCAPR_GLC_GC_MASK (0x2U) 1225 #define NETC_F2_COMMON_SGCAPR_GLC_GC_SHIFT (1U) 1226 #define NETC_F2_COMMON_SGCAPR_GLC_GC_WIDTH (1U) 1227 #define NETC_F2_COMMON_SGCAPR_GLC_GC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCAPR_GLC_GC_SHIFT)) & NETC_F2_COMMON_SGCAPR_GLC_GC_MASK) 1228 1229 #define NETC_F2_COMMON_SGCAPR_GLC_IO_MASK (0x4U) 1230 #define NETC_F2_COMMON_SGCAPR_GLC_IO_SHIFT (2U) 1231 #define NETC_F2_COMMON_SGCAPR_GLC_IO_WIDTH (1U) 1232 #define NETC_F2_COMMON_SGCAPR_GLC_IO(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCAPR_GLC_IO_SHIFT)) & NETC_F2_COMMON_SGCAPR_GLC_IO_MASK) 1233 1234 #define NETC_F2_COMMON_SGCAPR_GLC_IPV_MASK (0x8U) 1235 #define NETC_F2_COMMON_SGCAPR_GLC_IPV_SHIFT (3U) 1236 #define NETC_F2_COMMON_SGCAPR_GLC_IPV_WIDTH (1U) 1237 #define NETC_F2_COMMON_SGCAPR_GLC_IPV(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCAPR_GLC_IPV_SHIFT)) & NETC_F2_COMMON_SGCAPR_GLC_IPV_MASK) 1238 1239 #define NETC_F2_COMMON_SGCAPR_GLC_CTD_MASK (0x10U) 1240 #define NETC_F2_COMMON_SGCAPR_GLC_CTD_SHIFT (4U) 1241 #define NETC_F2_COMMON_SGCAPR_GLC_CTD_WIDTH (1U) 1242 #define NETC_F2_COMMON_SGCAPR_GLC_CTD(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCAPR_GLC_CTD_SHIFT)) & NETC_F2_COMMON_SGCAPR_GLC_CTD_MASK) 1243 /*! @} */ 1244 1245 /*! @name SGIITCAPR - Stream gate instance index table capability register */ 1246 /*! @{ */ 1247 1248 #define NETC_F2_COMMON_SGIITCAPR_NUM_ENTRIES_MASK (0xFFFFU) 1249 #define NETC_F2_COMMON_SGIITCAPR_NUM_ENTRIES_SHIFT (0U) 1250 #define NETC_F2_COMMON_SGIITCAPR_NUM_ENTRIES_WIDTH (16U) 1251 #define NETC_F2_COMMON_SGIITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGIITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_SGIITCAPR_NUM_ENTRIES_MASK) 1252 1253 #define NETC_F2_COMMON_SGIITCAPR_ACCESS_METH_MASK (0xF00000U) 1254 #define NETC_F2_COMMON_SGIITCAPR_ACCESS_METH_SHIFT (20U) 1255 #define NETC_F2_COMMON_SGIITCAPR_ACCESS_METH_WIDTH (4U) 1256 #define NETC_F2_COMMON_SGIITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGIITCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_SGIITCAPR_ACCESS_METH_MASK) 1257 /*! @} */ 1258 1259 /*! @name SGIITMAR - Stream gate instance index table memory allocation register */ 1260 /*! @{ */ 1261 1262 #define NETC_F2_COMMON_SGIITMAR_NUM_WORDS_MASK (0xFFFFU) 1263 #define NETC_F2_COMMON_SGIITMAR_NUM_WORDS_SHIFT (0U) 1264 #define NETC_F2_COMMON_SGIITMAR_NUM_WORDS_WIDTH (16U) 1265 #define NETC_F2_COMMON_SGIITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGIITMAR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_SGIITMAR_NUM_WORDS_MASK) 1266 /*! @} */ 1267 1268 /*! @name SGIITOR - Stream gate instance index table operational register */ 1269 /*! @{ */ 1270 1271 #define NETC_F2_COMMON_SGIITOR_NUM_ENTRIES_MASK (0xFFFFU) 1272 #define NETC_F2_COMMON_SGIITOR_NUM_ENTRIES_SHIFT (0U) 1273 #define NETC_F2_COMMON_SGIITOR_NUM_ENTRIES_WIDTH (16U) 1274 #define NETC_F2_COMMON_SGIITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGIITOR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_SGIITOR_NUM_ENTRIES_MASK) 1275 /*! @} */ 1276 1277 /*! @name SGCLITCAPR - Stream gate control list index table capability register */ 1278 /*! @{ */ 1279 1280 #define NETC_F2_COMMON_SGCLITCAPR_NUM_WORDS_MASK (0xFFFFU) 1281 #define NETC_F2_COMMON_SGCLITCAPR_NUM_WORDS_SHIFT (0U) 1282 #define NETC_F2_COMMON_SGCLITCAPR_NUM_WORDS_WIDTH (16U) 1283 #define NETC_F2_COMMON_SGCLITCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCLITCAPR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_SGCLITCAPR_NUM_WORDS_MASK) 1284 1285 #define NETC_F2_COMMON_SGCLITCAPR_ACCESS_METH_MASK (0xF00000U) 1286 #define NETC_F2_COMMON_SGCLITCAPR_ACCESS_METH_SHIFT (20U) 1287 #define NETC_F2_COMMON_SGCLITCAPR_ACCESS_METH_WIDTH (4U) 1288 #define NETC_F2_COMMON_SGCLITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCLITCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_SGCLITCAPR_ACCESS_METH_MASK) 1289 /*! @} */ 1290 1291 /*! @name SGCLITMAR - Stream gate control list index table memory allocation register */ 1292 /*! @{ */ 1293 1294 #define NETC_F2_COMMON_SGCLITMAR_NUM_WORDS_MASK (0xFFFFU) 1295 #define NETC_F2_COMMON_SGCLITMAR_NUM_WORDS_SHIFT (0U) 1296 #define NETC_F2_COMMON_SGCLITMAR_NUM_WORDS_WIDTH (16U) 1297 #define NETC_F2_COMMON_SGCLITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCLITMAR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_SGCLITMAR_NUM_WORDS_MASK) 1298 /*! @} */ 1299 1300 /*! @name SGCLTMOR - Stream gate control list table memory operational register */ 1301 /*! @{ */ 1302 1303 #define NETC_F2_COMMON_SGCLTMOR_NUM_WORDS_MASK (0xFFFFU) 1304 #define NETC_F2_COMMON_SGCLTMOR_NUM_WORDS_SHIFT (0U) 1305 #define NETC_F2_COMMON_SGCLTMOR_NUM_WORDS_WIDTH (16U) 1306 #define NETC_F2_COMMON_SGCLTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_SGCLTMOR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_SGCLTMOR_NUM_WORDS_MASK) 1307 /*! @} */ 1308 1309 /*! @name FMICAPR - Frame modification ingress capability register */ 1310 /*! @{ */ 1311 1312 #define NETC_F2_COMMON_FMICAPR_L2_ACT_MASK (0xFFU) 1313 #define NETC_F2_COMMON_FMICAPR_L2_ACT_SHIFT (0U) 1314 #define NETC_F2_COMMON_FMICAPR_L2_ACT_WIDTH (8U) 1315 #define NETC_F2_COMMON_FMICAPR_L2_ACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMICAPR_L2_ACT_SHIFT)) & NETC_F2_COMMON_FMICAPR_L2_ACT_MASK) 1316 /*! @} */ 1317 1318 /*! @name FMECAPR - Frame modification egress capability register */ 1319 /*! @{ */ 1320 1321 #define NETC_F2_COMMON_FMECAPR_L2_ACT_MASK (0xFFU) 1322 #define NETC_F2_COMMON_FMECAPR_L2_ACT_SHIFT (0U) 1323 #define NETC_F2_COMMON_FMECAPR_L2_ACT_WIDTH (8U) 1324 #define NETC_F2_COMMON_FMECAPR_L2_ACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMECAPR_L2_ACT_SHIFT)) & NETC_F2_COMMON_FMECAPR_L2_ACT_MASK) 1325 1326 #define NETC_F2_COMMON_FMECAPR_L3_ACT_MASK (0xFF0000U) 1327 #define NETC_F2_COMMON_FMECAPR_L3_ACT_SHIFT (16U) 1328 #define NETC_F2_COMMON_FMECAPR_L3_ACT_WIDTH (8U) 1329 #define NETC_F2_COMMON_FMECAPR_L3_ACT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMECAPR_L3_ACT_SHIFT)) & NETC_F2_COMMON_FMECAPR_L3_ACT_MASK) 1330 /*! @} */ 1331 1332 /*! @name FMITCAPR - Frame modification index table capability register */ 1333 /*! @{ */ 1334 1335 #define NETC_F2_COMMON_FMITCAPR_NUM_ENTRIES_MASK (0x1FFFU) 1336 #define NETC_F2_COMMON_FMITCAPR_NUM_ENTRIES_SHIFT (0U) 1337 #define NETC_F2_COMMON_FMITCAPR_NUM_ENTRIES_WIDTH (13U) 1338 #define NETC_F2_COMMON_FMITCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMITCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_FMITCAPR_NUM_ENTRIES_MASK) 1339 1340 #define NETC_F2_COMMON_FMITCAPR_ACCESS_METH_MASK (0xF00000U) 1341 #define NETC_F2_COMMON_FMITCAPR_ACCESS_METH_SHIFT (20U) 1342 #define NETC_F2_COMMON_FMITCAPR_ACCESS_METH_WIDTH (4U) 1343 #define NETC_F2_COMMON_FMITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMITCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_FMITCAPR_ACCESS_METH_MASK) 1344 /*! @} */ 1345 1346 /*! @name FMITMAR - Frame modification index table memory allocation register */ 1347 /*! @{ */ 1348 1349 #define NETC_F2_COMMON_FMITMAR_NUM_WORDS_MASK (0x1FFFU) 1350 #define NETC_F2_COMMON_FMITMAR_NUM_WORDS_SHIFT (0U) 1351 #define NETC_F2_COMMON_FMITMAR_NUM_WORDS_WIDTH (13U) 1352 #define NETC_F2_COMMON_FMITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMITMAR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_FMITMAR_NUM_WORDS_MASK) 1353 /*! @} */ 1354 1355 /*! @name FMITOR - Frame modification index table operational register */ 1356 /*! @{ */ 1357 1358 #define NETC_F2_COMMON_FMITOR_NUM_ENTRIES_MASK (0x1FFFU) 1359 #define NETC_F2_COMMON_FMITOR_NUM_ENTRIES_SHIFT (0U) 1360 #define NETC_F2_COMMON_FMITOR_NUM_ENTRIES_WIDTH (13U) 1361 #define NETC_F2_COMMON_FMITOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMITOR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_FMITOR_NUM_ENTRIES_MASK) 1362 /*! @} */ 1363 1364 /*! @name FMDITCAPR - Frame modification data index table capability register */ 1365 /*! @{ */ 1366 1367 #define NETC_F2_COMMON_FMDITCAPR_NUM_WORDS_MASK (0xFFFFU) 1368 #define NETC_F2_COMMON_FMDITCAPR_NUM_WORDS_SHIFT (0U) 1369 #define NETC_F2_COMMON_FMDITCAPR_NUM_WORDS_WIDTH (16U) 1370 #define NETC_F2_COMMON_FMDITCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMDITCAPR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_FMDITCAPR_NUM_WORDS_MASK) 1371 1372 #define NETC_F2_COMMON_FMDITCAPR_ACCESS_METH_MASK (0xF00000U) 1373 #define NETC_F2_COMMON_FMDITCAPR_ACCESS_METH_SHIFT (20U) 1374 #define NETC_F2_COMMON_FMDITCAPR_ACCESS_METH_WIDTH (4U) 1375 #define NETC_F2_COMMON_FMDITCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMDITCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_FMDITCAPR_ACCESS_METH_MASK) 1376 /*! @} */ 1377 1378 /*! @name FMDITMAR - Frame modification data index table memory allocation register */ 1379 /*! @{ */ 1380 1381 #define NETC_F2_COMMON_FMDITMAR_NUM_WORDS_MASK (0xFFFFU) 1382 #define NETC_F2_COMMON_FMDITMAR_NUM_WORDS_SHIFT (0U) 1383 #define NETC_F2_COMMON_FMDITMAR_NUM_WORDS_WIDTH (16U) 1384 #define NETC_F2_COMMON_FMDITMAR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_FMDITMAR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_FMDITMAR_NUM_WORDS_MASK) 1385 /*! @} */ 1386 1387 /*! @name ETCAPR - Egress treatment capability register */ 1388 /*! @{ */ 1389 1390 #define NETC_F2_COMMON_ETCAPR_ESQR_MASK (0x1U) 1391 #define NETC_F2_COMMON_ETCAPR_ESQR_SHIFT (0U) 1392 #define NETC_F2_COMMON_ETCAPR_ESQR_WIDTH (1U) 1393 #define NETC_F2_COMMON_ETCAPR_ESQR(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ETCAPR_ESQR_SHIFT)) & NETC_F2_COMMON_ETCAPR_ESQR_MASK) 1394 /*! @} */ 1395 1396 /*! @name ETTCAPR - Egress treatment table capability register */ 1397 /*! @{ */ 1398 1399 #define NETC_F2_COMMON_ETTCAPR_NUM_ENTRIES_MASK (0xFFFFU) 1400 #define NETC_F2_COMMON_ETTCAPR_NUM_ENTRIES_SHIFT (0U) 1401 #define NETC_F2_COMMON_ETTCAPR_NUM_ENTRIES_WIDTH (16U) 1402 #define NETC_F2_COMMON_ETTCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ETTCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ETTCAPR_NUM_ENTRIES_MASK) 1403 1404 #define NETC_F2_COMMON_ETTCAPR_ACCESS_METH_MASK (0xF00000U) 1405 #define NETC_F2_COMMON_ETTCAPR_ACCESS_METH_SHIFT (20U) 1406 #define NETC_F2_COMMON_ETTCAPR_ACCESS_METH_WIDTH (4U) 1407 #define NETC_F2_COMMON_ETTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ETTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_ETTCAPR_ACCESS_METH_MASK) 1408 /*! @} */ 1409 1410 /*! @name ETTOR - Egress treatment table operational register */ 1411 /*! @{ */ 1412 1413 #define NETC_F2_COMMON_ETTOR_NUM_ENTRIES_MASK (0xFFFFU) 1414 #define NETC_F2_COMMON_ETTOR_NUM_ENTRIES_SHIFT (0U) 1415 #define NETC_F2_COMMON_ETTOR_NUM_ENTRIES_WIDTH (16U) 1416 #define NETC_F2_COMMON_ETTOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ETTOR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ETTOR_NUM_ENTRIES_MASK) 1417 /*! @} */ 1418 1419 /*! @name TGSTCAPR - Time gate scheduling table capability register */ 1420 /*! @{ */ 1421 1422 #define NETC_F2_COMMON_TGSTCAPR_NUM_WORDS_MASK (0xFFFFU) 1423 #define NETC_F2_COMMON_TGSTCAPR_NUM_WORDS_SHIFT (0U) 1424 #define NETC_F2_COMMON_TGSTCAPR_NUM_WORDS_WIDTH (16U) 1425 #define NETC_F2_COMMON_TGSTCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TGSTCAPR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_TGSTCAPR_NUM_WORDS_MASK) 1426 1427 #define NETC_F2_COMMON_TGSTCAPR_ACCESS_METH_MASK (0xF00000U) 1428 #define NETC_F2_COMMON_TGSTCAPR_ACCESS_METH_SHIFT (20U) 1429 #define NETC_F2_COMMON_TGSTCAPR_ACCESS_METH_WIDTH (4U) 1430 #define NETC_F2_COMMON_TGSTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TGSTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_TGSTCAPR_ACCESS_METH_MASK) 1431 1432 #define NETC_F2_COMMON_TGSTCAPR_MAX_GCL_LEN_MASK (0x3000000U) 1433 #define NETC_F2_COMMON_TGSTCAPR_MAX_GCL_LEN_SHIFT (24U) 1434 #define NETC_F2_COMMON_TGSTCAPR_MAX_GCL_LEN_WIDTH (2U) 1435 #define NETC_F2_COMMON_TGSTCAPR_MAX_GCL_LEN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TGSTCAPR_MAX_GCL_LEN_SHIFT)) & NETC_F2_COMMON_TGSTCAPR_MAX_GCL_LEN_MASK) 1436 /*! @} */ 1437 1438 /*! @name TGSTMOR - Time gate scheduling table memory operation register */ 1439 /*! @{ */ 1440 1441 #define NETC_F2_COMMON_TGSTMOR_NUM_WORDS_MASK (0xFFFFU) 1442 #define NETC_F2_COMMON_TGSTMOR_NUM_WORDS_SHIFT (0U) 1443 #define NETC_F2_COMMON_TGSTMOR_NUM_WORDS_WIDTH (16U) 1444 #define NETC_F2_COMMON_TGSTMOR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_TGSTMOR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_TGSTMOR_NUM_WORDS_MASK) 1445 /*! @} */ 1446 1447 /*! @name ESQRCAPR - Egress sequence recovery capability register */ 1448 /*! @{ */ 1449 1450 #define NETC_F2_COMMON_ESQRCAPR_SQR_TYPE_MASK (0x3U) 1451 #define NETC_F2_COMMON_ESQRCAPR_SQR_TYPE_SHIFT (0U) 1452 #define NETC_F2_COMMON_ESQRCAPR_SQR_TYPE_WIDTH (2U) 1453 #define NETC_F2_COMMON_ESQRCAPR_SQR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ESQRCAPR_SQR_TYPE_SHIFT)) & NETC_F2_COMMON_ESQRCAPR_SQR_TYPE_MASK) 1454 1455 #define NETC_F2_COMMON_ESQRCAPR_SQR_ALG_MASK (0xCU) 1456 #define NETC_F2_COMMON_ESQRCAPR_SQR_ALG_SHIFT (2U) 1457 #define NETC_F2_COMMON_ESQRCAPR_SQR_ALG_WIDTH (2U) 1458 #define NETC_F2_COMMON_ESQRCAPR_SQR_ALG(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ESQRCAPR_SQR_ALG_SHIFT)) & NETC_F2_COMMON_ESQRCAPR_SQR_ALG_MASK) 1459 1460 #define NETC_F2_COMMON_ESQRCAPR_SQR_MAX_HL_MASK (0x700U) 1461 #define NETC_F2_COMMON_ESQRCAPR_SQR_MAX_HL_SHIFT (8U) 1462 #define NETC_F2_COMMON_ESQRCAPR_SQR_MAX_HL_WIDTH (3U) 1463 #define NETC_F2_COMMON_ESQRCAPR_SQR_MAX_HL(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ESQRCAPR_SQR_MAX_HL_SHIFT)) & NETC_F2_COMMON_ESQRCAPR_SQR_MAX_HL_MASK) 1464 /*! @} */ 1465 1466 /*! @name ESQRTCAPR - Egress sequence recovery table capability register */ 1467 /*! @{ */ 1468 1469 #define NETC_F2_COMMON_ESQRTCAPR_NUM_ENTRIES_MASK (0xFFFFU) 1470 #define NETC_F2_COMMON_ESQRTCAPR_NUM_ENTRIES_SHIFT (0U) 1471 #define NETC_F2_COMMON_ESQRTCAPR_NUM_ENTRIES_WIDTH (16U) 1472 #define NETC_F2_COMMON_ESQRTCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ESQRTCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ESQRTCAPR_NUM_ENTRIES_MASK) 1473 1474 #define NETC_F2_COMMON_ESQRTCAPR_ACCESS_METH_MASK (0xF00000U) 1475 #define NETC_F2_COMMON_ESQRTCAPR_ACCESS_METH_SHIFT (20U) 1476 #define NETC_F2_COMMON_ESQRTCAPR_ACCESS_METH_WIDTH (4U) 1477 #define NETC_F2_COMMON_ESQRTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ESQRTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_ESQRTCAPR_ACCESS_METH_MASK) 1478 /*! @} */ 1479 1480 /*! @name ECTCAPR - Egress counter table capability register */ 1481 /*! @{ */ 1482 1483 #define NETC_F2_COMMON_ECTCAPR_NUM_ENTRIES_MASK (0xFFFFU) 1484 #define NETC_F2_COMMON_ECTCAPR_NUM_ENTRIES_SHIFT (0U) 1485 #define NETC_F2_COMMON_ECTCAPR_NUM_ENTRIES_WIDTH (16U) 1486 #define NETC_F2_COMMON_ECTCAPR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ECTCAPR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ECTCAPR_NUM_ENTRIES_MASK) 1487 1488 #define NETC_F2_COMMON_ECTCAPR_ACCESS_METH_MASK (0xF00000U) 1489 #define NETC_F2_COMMON_ECTCAPR_ACCESS_METH_SHIFT (20U) 1490 #define NETC_F2_COMMON_ECTCAPR_ACCESS_METH_WIDTH (4U) 1491 #define NETC_F2_COMMON_ECTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ECTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_ECTCAPR_ACCESS_METH_MASK) 1492 /*! @} */ 1493 1494 /*! @name HTMCAPR - Hash table memory capability register */ 1495 /*! @{ */ 1496 1497 #define NETC_F2_COMMON_HTMCAPR_NUM_WORDS_MASK (0xFFFFU) 1498 #define NETC_F2_COMMON_HTMCAPR_NUM_WORDS_SHIFT (0U) 1499 #define NETC_F2_COMMON_HTMCAPR_NUM_WORDS_WIDTH (16U) 1500 #define NETC_F2_COMMON_HTMCAPR_NUM_WORDS(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_HTMCAPR_NUM_WORDS_SHIFT)) & NETC_F2_COMMON_HTMCAPR_NUM_WORDS_MASK) 1501 1502 #define NETC_F2_COMMON_HTMCAPR_WORD_SIZE_MASK (0x30000000U) 1503 #define NETC_F2_COMMON_HTMCAPR_WORD_SIZE_SHIFT (28U) 1504 #define NETC_F2_COMMON_HTMCAPR_WORD_SIZE_WIDTH (2U) 1505 #define NETC_F2_COMMON_HTMCAPR_WORD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_HTMCAPR_WORD_SIZE_SHIFT)) & NETC_F2_COMMON_HTMCAPR_WORD_SIZE_MASK) 1506 1507 #define NETC_F2_COMMON_HTMCAPR_MLOC_MASK (0xC0000000U) 1508 #define NETC_F2_COMMON_HTMCAPR_MLOC_SHIFT (30U) 1509 #define NETC_F2_COMMON_HTMCAPR_MLOC_WIDTH (2U) 1510 #define NETC_F2_COMMON_HTMCAPR_MLOC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_HTMCAPR_MLOC_SHIFT)) & NETC_F2_COMMON_HTMCAPR_MLOC_MASK) 1511 /*! @} */ 1512 1513 /*! @name HTMOR - Hash table memory operational register */ 1514 /*! @{ */ 1515 1516 #define NETC_F2_COMMON_HTMOR_AMOUNT_MASK (0xFFFFU) 1517 #define NETC_F2_COMMON_HTMOR_AMOUNT_SHIFT (0U) 1518 #define NETC_F2_COMMON_HTMOR_AMOUNT_WIDTH (16U) 1519 #define NETC_F2_COMMON_HTMOR_AMOUNT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_HTMOR_AMOUNT_SHIFT)) & NETC_F2_COMMON_HTMOR_AMOUNT_MASK) 1520 1521 #define NETC_F2_COMMON_HTMOR_WATERMARK_MASK (0xFFFF0000U) 1522 #define NETC_F2_COMMON_HTMOR_WATERMARK_SHIFT (16U) 1523 #define NETC_F2_COMMON_HTMOR_WATERMARK_WIDTH (16U) 1524 #define NETC_F2_COMMON_HTMOR_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_HTMOR_WATERMARK_SHIFT)) & NETC_F2_COMMON_HTMOR_WATERMARK_MASK) 1525 /*! @} */ 1526 1527 /*! @name ISIDCAPR - Ingress stream identification capability register */ 1528 /*! @{ */ 1529 1530 #define NETC_F2_COMMON_ISIDCAPR_NUM_KC_MASK (0x3U) 1531 #define NETC_F2_COMMON_ISIDCAPR_NUM_KC_SHIFT (0U) 1532 #define NETC_F2_COMMON_ISIDCAPR_NUM_KC_WIDTH (2U) 1533 #define NETC_F2_COMMON_ISIDCAPR_NUM_KC(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDCAPR_NUM_KC_SHIFT)) & NETC_F2_COMMON_ISIDCAPR_NUM_KC_MASK) 1534 1535 #define NETC_F2_COMMON_ISIDCAPR_NUM_PF_MASK (0x1CU) 1536 #define NETC_F2_COMMON_ISIDCAPR_NUM_PF_SHIFT (2U) 1537 #define NETC_F2_COMMON_ISIDCAPR_NUM_PF_WIDTH (3U) 1538 #define NETC_F2_COMMON_ISIDCAPR_NUM_PF(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDCAPR_NUM_PF_SHIFT)) & NETC_F2_COMMON_ISIDCAPR_NUM_PF_MASK) 1539 1540 #define NETC_F2_COMMON_ISIDCAPR_MAX_KSIZE_MASK (0x1F00U) 1541 #define NETC_F2_COMMON_ISIDCAPR_MAX_KSIZE_SHIFT (8U) 1542 #define NETC_F2_COMMON_ISIDCAPR_MAX_KSIZE_WIDTH (5U) 1543 #define NETC_F2_COMMON_ISIDCAPR_MAX_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDCAPR_MAX_KSIZE_SHIFT)) & NETC_F2_COMMON_ISIDCAPR_MAX_KSIZE_MASK) 1544 1545 #define NETC_F2_COMMON_ISIDCAPR_UFT_MASK (0x10000U) 1546 #define NETC_F2_COMMON_ISIDCAPR_UFT_SHIFT (16U) 1547 #define NETC_F2_COMMON_ISIDCAPR_UFT_WIDTH (1U) 1548 #define NETC_F2_COMMON_ISIDCAPR_UFT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDCAPR_UFT_SHIFT)) & NETC_F2_COMMON_ISIDCAPR_UFT_MASK) 1549 1550 #define NETC_F2_COMMON_ISIDCAPR_ETHFT_MASK (0x20000U) 1551 #define NETC_F2_COMMON_ISIDCAPR_ETHFT_SHIFT (17U) 1552 #define NETC_F2_COMMON_ISIDCAPR_ETHFT_WIDTH (1U) 1553 #define NETC_F2_COMMON_ISIDCAPR_ETHFT(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDCAPR_ETHFT_SHIFT)) & NETC_F2_COMMON_ISIDCAPR_ETHFT_MASK) 1554 /*! @} */ 1555 1556 /*! @name ISIDHTCAPR - Ingress stream identification hash table capability register */ 1557 /*! @{ */ 1558 1559 #define NETC_F2_COMMON_ISIDHTCAPR_ACCESS_METH_MASK (0xF00000U) 1560 #define NETC_F2_COMMON_ISIDHTCAPR_ACCESS_METH_SHIFT (20U) 1561 #define NETC_F2_COMMON_ISIDHTCAPR_ACCESS_METH_WIDTH (4U) 1562 #define NETC_F2_COMMON_ISIDHTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDHTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_ISIDHTCAPR_ACCESS_METH_MASK) 1563 /*! @} */ 1564 1565 /*! @name ISIDKC0OR - Ingress stream identification key construction 0 operational register */ 1566 /*! @{ */ 1567 1568 #define NETC_F2_COMMON_ISIDKC0OR_NUM_ENTRIES_MASK (0xFFFFU) 1569 #define NETC_F2_COMMON_ISIDKC0OR_NUM_ENTRIES_SHIFT (0U) 1570 #define NETC_F2_COMMON_ISIDKC0OR_NUM_ENTRIES_WIDTH (16U) 1571 #define NETC_F2_COMMON_ISIDKC0OR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0OR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISIDKC0OR_NUM_ENTRIES_MASK) 1572 1573 #define NETC_F2_COMMON_ISIDKC0OR_EN_MASK (0x80000000U) 1574 #define NETC_F2_COMMON_ISIDKC0OR_EN_SHIFT (31U) 1575 #define NETC_F2_COMMON_ISIDKC0OR_EN_WIDTH (1U) 1576 #define NETC_F2_COMMON_ISIDKC0OR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0OR_EN_SHIFT)) & NETC_F2_COMMON_ISIDKC0OR_EN_MASK) 1577 /*! @} */ 1578 1579 /*! @name ISIDKC0CR0 - Ingress stream identification key construction 0 configuration register 0 */ 1580 /*! @{ */ 1581 1582 #define NETC_F2_COMMON_ISIDKC0CR0_VALID_MASK (0x1U) 1583 #define NETC_F2_COMMON_ISIDKC0CR0_VALID_SHIFT (0U) 1584 #define NETC_F2_COMMON_ISIDKC0CR0_VALID_WIDTH (1U) 1585 #define NETC_F2_COMMON_ISIDKC0CR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_VALID_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_VALID_MASK) 1586 1587 #define NETC_F2_COMMON_ISIDKC0CR0_PORTP_MASK (0x2U) 1588 #define NETC_F2_COMMON_ISIDKC0CR0_PORTP_SHIFT (1U) 1589 #define NETC_F2_COMMON_ISIDKC0CR0_PORTP_WIDTH (1U) 1590 #define NETC_F2_COMMON_ISIDKC0CR0_PORTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_PORTP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_PORTP_MASK) 1591 1592 #define NETC_F2_COMMON_ISIDKC0CR0_SPMP_MASK (0x4U) 1593 #define NETC_F2_COMMON_ISIDKC0CR0_SPMP_SHIFT (2U) 1594 #define NETC_F2_COMMON_ISIDKC0CR0_SPMP_WIDTH (1U) 1595 #define NETC_F2_COMMON_ISIDKC0CR0_SPMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_SPMP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_SPMP_MASK) 1596 1597 #define NETC_F2_COMMON_ISIDKC0CR0_DMACP_MASK (0x8U) 1598 #define NETC_F2_COMMON_ISIDKC0CR0_DMACP_SHIFT (3U) 1599 #define NETC_F2_COMMON_ISIDKC0CR0_DMACP_WIDTH (1U) 1600 #define NETC_F2_COMMON_ISIDKC0CR0_DMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_DMACP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_DMACP_MASK) 1601 1602 #define NETC_F2_COMMON_ISIDKC0CR0_SMACP_MASK (0x10U) 1603 #define NETC_F2_COMMON_ISIDKC0CR0_SMACP_SHIFT (4U) 1604 #define NETC_F2_COMMON_ISIDKC0CR0_SMACP_WIDTH (1U) 1605 #define NETC_F2_COMMON_ISIDKC0CR0_SMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_SMACP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_SMACP_MASK) 1606 1607 #define NETC_F2_COMMON_ISIDKC0CR0_OVIDP_MASK (0x20U) 1608 #define NETC_F2_COMMON_ISIDKC0CR0_OVIDP_SHIFT (5U) 1609 #define NETC_F2_COMMON_ISIDKC0CR0_OVIDP_WIDTH (1U) 1610 #define NETC_F2_COMMON_ISIDKC0CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_OVIDP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_OVIDP_MASK) 1611 1612 #define NETC_F2_COMMON_ISIDKC0CR0_OPCPP_MASK (0x40U) 1613 #define NETC_F2_COMMON_ISIDKC0CR0_OPCPP_SHIFT (6U) 1614 #define NETC_F2_COMMON_ISIDKC0CR0_OPCPP_WIDTH (1U) 1615 #define NETC_F2_COMMON_ISIDKC0CR0_OPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_OPCPP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_OPCPP_MASK) 1616 1617 #define NETC_F2_COMMON_ISIDKC0CR0_IVIDP_MASK (0x80U) 1618 #define NETC_F2_COMMON_ISIDKC0CR0_IVIDP_SHIFT (7U) 1619 #define NETC_F2_COMMON_ISIDKC0CR0_IVIDP_WIDTH (1U) 1620 #define NETC_F2_COMMON_ISIDKC0CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_IVIDP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_IVIDP_MASK) 1621 1622 #define NETC_F2_COMMON_ISIDKC0CR0_IPCPP_MASK (0x100U) 1623 #define NETC_F2_COMMON_ISIDKC0CR0_IPCPP_SHIFT (8U) 1624 #define NETC_F2_COMMON_ISIDKC0CR0_IPCPP_WIDTH (1U) 1625 #define NETC_F2_COMMON_ISIDKC0CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_IPCPP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_IPCPP_MASK) 1626 1627 #define NETC_F2_COMMON_ISIDKC0CR0_SQTP_MASK (0x200U) 1628 #define NETC_F2_COMMON_ISIDKC0CR0_SQTP_SHIFT (9U) 1629 #define NETC_F2_COMMON_ISIDKC0CR0_SQTP_WIDTH (1U) 1630 #define NETC_F2_COMMON_ISIDKC0CR0_SQTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_SQTP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_SQTP_MASK) 1631 1632 #define NETC_F2_COMMON_ISIDKC0CR0_ETP_MASK (0x400U) 1633 #define NETC_F2_COMMON_ISIDKC0CR0_ETP_SHIFT (10U) 1634 #define NETC_F2_COMMON_ISIDKC0CR0_ETP_WIDTH (1U) 1635 #define NETC_F2_COMMON_ISIDKC0CR0_ETP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0CR0_ETP_SHIFT)) & NETC_F2_COMMON_ISIDKC0CR0_ETP_MASK) 1636 /*! @} */ 1637 1638 /*! @name ISIDKC0PF0CR - Ingress stream identification key construction 0 payload field 0 configuration register */ 1639 /*! @{ */ 1640 1641 #define NETC_F2_COMMON_ISIDKC0PF0CR_PFP_MASK (0x1U) 1642 #define NETC_F2_COMMON_ISIDKC0PF0CR_PFP_SHIFT (0U) 1643 #define NETC_F2_COMMON_ISIDKC0PF0CR_PFP_WIDTH (1U) 1644 #define NETC_F2_COMMON_ISIDKC0PF0CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF0CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF0CR_PFP_MASK) 1645 1646 #define NETC_F2_COMMON_ISIDKC0PF0CR_NUM_BYTES_MASK (0x1EU) 1647 #define NETC_F2_COMMON_ISIDKC0PF0CR_NUM_BYTES_SHIFT (1U) 1648 #define NETC_F2_COMMON_ISIDKC0PF0CR_NUM_BYTES_WIDTH (4U) 1649 #define NETC_F2_COMMON_ISIDKC0PF0CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF0CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF0CR_NUM_BYTES_MASK) 1650 1651 #define NETC_F2_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_MASK (0x7F00U) 1652 #define NETC_F2_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_SHIFT (8U) 1653 #define NETC_F2_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_WIDTH (7U) 1654 #define NETC_F2_COMMON_ISIDKC0PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF0CR_BYTE_OFFSET_MASK) 1655 1656 #define NETC_F2_COMMON_ISIDKC0PF0CR_FBMASK_MASK (0x70000U) 1657 #define NETC_F2_COMMON_ISIDKC0PF0CR_FBMASK_SHIFT (16U) 1658 #define NETC_F2_COMMON_ISIDKC0PF0CR_FBMASK_WIDTH (3U) 1659 #define NETC_F2_COMMON_ISIDKC0PF0CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF0CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF0CR_FBMASK_MASK) 1660 1661 #define NETC_F2_COMMON_ISIDKC0PF0CR_LBMASK_MASK (0x700000U) 1662 #define NETC_F2_COMMON_ISIDKC0PF0CR_LBMASK_SHIFT (20U) 1663 #define NETC_F2_COMMON_ISIDKC0PF0CR_LBMASK_WIDTH (3U) 1664 #define NETC_F2_COMMON_ISIDKC0PF0CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF0CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF0CR_LBMASK_MASK) 1665 /*! @} */ 1666 1667 /*! @name ISIDKC0PF1CR - Ingress stream identification key construction 0 payload field 1 configuration register */ 1668 /*! @{ */ 1669 1670 #define NETC_F2_COMMON_ISIDKC0PF1CR_PFP_MASK (0x1U) 1671 #define NETC_F2_COMMON_ISIDKC0PF1CR_PFP_SHIFT (0U) 1672 #define NETC_F2_COMMON_ISIDKC0PF1CR_PFP_WIDTH (1U) 1673 #define NETC_F2_COMMON_ISIDKC0PF1CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF1CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF1CR_PFP_MASK) 1674 1675 #define NETC_F2_COMMON_ISIDKC0PF1CR_NUM_BYTES_MASK (0x1EU) 1676 #define NETC_F2_COMMON_ISIDKC0PF1CR_NUM_BYTES_SHIFT (1U) 1677 #define NETC_F2_COMMON_ISIDKC0PF1CR_NUM_BYTES_WIDTH (4U) 1678 #define NETC_F2_COMMON_ISIDKC0PF1CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF1CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF1CR_NUM_BYTES_MASK) 1679 1680 #define NETC_F2_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_MASK (0x7F00U) 1681 #define NETC_F2_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_SHIFT (8U) 1682 #define NETC_F2_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_WIDTH (7U) 1683 #define NETC_F2_COMMON_ISIDKC0PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF1CR_BYTE_OFFSET_MASK) 1684 1685 #define NETC_F2_COMMON_ISIDKC0PF1CR_FBMASK_MASK (0x70000U) 1686 #define NETC_F2_COMMON_ISIDKC0PF1CR_FBMASK_SHIFT (16U) 1687 #define NETC_F2_COMMON_ISIDKC0PF1CR_FBMASK_WIDTH (3U) 1688 #define NETC_F2_COMMON_ISIDKC0PF1CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF1CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF1CR_FBMASK_MASK) 1689 1690 #define NETC_F2_COMMON_ISIDKC0PF1CR_LBMASK_MASK (0x700000U) 1691 #define NETC_F2_COMMON_ISIDKC0PF1CR_LBMASK_SHIFT (20U) 1692 #define NETC_F2_COMMON_ISIDKC0PF1CR_LBMASK_WIDTH (3U) 1693 #define NETC_F2_COMMON_ISIDKC0PF1CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF1CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF1CR_LBMASK_MASK) 1694 /*! @} */ 1695 1696 /*! @name ISIDKC0PF2CR - Ingress stream identification key construction 0 payload field 2 configuration register */ 1697 /*! @{ */ 1698 1699 #define NETC_F2_COMMON_ISIDKC0PF2CR_PFP_MASK (0x1U) 1700 #define NETC_F2_COMMON_ISIDKC0PF2CR_PFP_SHIFT (0U) 1701 #define NETC_F2_COMMON_ISIDKC0PF2CR_PFP_WIDTH (1U) 1702 #define NETC_F2_COMMON_ISIDKC0PF2CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF2CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF2CR_PFP_MASK) 1703 1704 #define NETC_F2_COMMON_ISIDKC0PF2CR_NUM_BYTES_MASK (0x1EU) 1705 #define NETC_F2_COMMON_ISIDKC0PF2CR_NUM_BYTES_SHIFT (1U) 1706 #define NETC_F2_COMMON_ISIDKC0PF2CR_NUM_BYTES_WIDTH (4U) 1707 #define NETC_F2_COMMON_ISIDKC0PF2CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF2CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF2CR_NUM_BYTES_MASK) 1708 1709 #define NETC_F2_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_MASK (0x7F00U) 1710 #define NETC_F2_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_SHIFT (8U) 1711 #define NETC_F2_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_WIDTH (7U) 1712 #define NETC_F2_COMMON_ISIDKC0PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF2CR_BYTE_OFFSET_MASK) 1713 1714 #define NETC_F2_COMMON_ISIDKC0PF2CR_FBMASK_MASK (0x70000U) 1715 #define NETC_F2_COMMON_ISIDKC0PF2CR_FBMASK_SHIFT (16U) 1716 #define NETC_F2_COMMON_ISIDKC0PF2CR_FBMASK_WIDTH (3U) 1717 #define NETC_F2_COMMON_ISIDKC0PF2CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF2CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF2CR_FBMASK_MASK) 1718 1719 #define NETC_F2_COMMON_ISIDKC0PF2CR_LBMASK_MASK (0x700000U) 1720 #define NETC_F2_COMMON_ISIDKC0PF2CR_LBMASK_SHIFT (20U) 1721 #define NETC_F2_COMMON_ISIDKC0PF2CR_LBMASK_WIDTH (3U) 1722 #define NETC_F2_COMMON_ISIDKC0PF2CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF2CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF2CR_LBMASK_MASK) 1723 /*! @} */ 1724 1725 /*! @name ISIDKC0PF3CR - Ingress stream identification key construction 0 payload field 3 configuration register */ 1726 /*! @{ */ 1727 1728 #define NETC_F2_COMMON_ISIDKC0PF3CR_PFP_MASK (0x1U) 1729 #define NETC_F2_COMMON_ISIDKC0PF3CR_PFP_SHIFT (0U) 1730 #define NETC_F2_COMMON_ISIDKC0PF3CR_PFP_WIDTH (1U) 1731 #define NETC_F2_COMMON_ISIDKC0PF3CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF3CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF3CR_PFP_MASK) 1732 1733 #define NETC_F2_COMMON_ISIDKC0PF3CR_NUM_BYTES_MASK (0x1EU) 1734 #define NETC_F2_COMMON_ISIDKC0PF3CR_NUM_BYTES_SHIFT (1U) 1735 #define NETC_F2_COMMON_ISIDKC0PF3CR_NUM_BYTES_WIDTH (4U) 1736 #define NETC_F2_COMMON_ISIDKC0PF3CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF3CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF3CR_NUM_BYTES_MASK) 1737 1738 #define NETC_F2_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_MASK (0x7F00U) 1739 #define NETC_F2_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_SHIFT (8U) 1740 #define NETC_F2_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_WIDTH (7U) 1741 #define NETC_F2_COMMON_ISIDKC0PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF3CR_BYTE_OFFSET_MASK) 1742 1743 #define NETC_F2_COMMON_ISIDKC0PF3CR_FBMASK_MASK (0x70000U) 1744 #define NETC_F2_COMMON_ISIDKC0PF3CR_FBMASK_SHIFT (16U) 1745 #define NETC_F2_COMMON_ISIDKC0PF3CR_FBMASK_WIDTH (3U) 1746 #define NETC_F2_COMMON_ISIDKC0PF3CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF3CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF3CR_FBMASK_MASK) 1747 1748 #define NETC_F2_COMMON_ISIDKC0PF3CR_LBMASK_MASK (0x700000U) 1749 #define NETC_F2_COMMON_ISIDKC0PF3CR_LBMASK_SHIFT (20U) 1750 #define NETC_F2_COMMON_ISIDKC0PF3CR_LBMASK_WIDTH (3U) 1751 #define NETC_F2_COMMON_ISIDKC0PF3CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC0PF3CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC0PF3CR_LBMASK_MASK) 1752 /*! @} */ 1753 1754 /*! @name ISIDKC1OR - Ingress stream identification key construction 1 operational register */ 1755 /*! @{ */ 1756 1757 #define NETC_F2_COMMON_ISIDKC1OR_NUM_ENTRIES_MASK (0xFFFFU) 1758 #define NETC_F2_COMMON_ISIDKC1OR_NUM_ENTRIES_SHIFT (0U) 1759 #define NETC_F2_COMMON_ISIDKC1OR_NUM_ENTRIES_WIDTH (16U) 1760 #define NETC_F2_COMMON_ISIDKC1OR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1OR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISIDKC1OR_NUM_ENTRIES_MASK) 1761 1762 #define NETC_F2_COMMON_ISIDKC1OR_EN_MASK (0x80000000U) 1763 #define NETC_F2_COMMON_ISIDKC1OR_EN_SHIFT (31U) 1764 #define NETC_F2_COMMON_ISIDKC1OR_EN_WIDTH (1U) 1765 #define NETC_F2_COMMON_ISIDKC1OR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1OR_EN_SHIFT)) & NETC_F2_COMMON_ISIDKC1OR_EN_MASK) 1766 /*! @} */ 1767 1768 /*! @name ISIDKC1CR0 - Ingress stream identification key construction 1 configuration register 0 */ 1769 /*! @{ */ 1770 1771 #define NETC_F2_COMMON_ISIDKC1CR0_VALID_MASK (0x1U) 1772 #define NETC_F2_COMMON_ISIDKC1CR0_VALID_SHIFT (0U) 1773 #define NETC_F2_COMMON_ISIDKC1CR0_VALID_WIDTH (1U) 1774 #define NETC_F2_COMMON_ISIDKC1CR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_VALID_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_VALID_MASK) 1775 1776 #define NETC_F2_COMMON_ISIDKC1CR0_PORTP_MASK (0x2U) 1777 #define NETC_F2_COMMON_ISIDKC1CR0_PORTP_SHIFT (1U) 1778 #define NETC_F2_COMMON_ISIDKC1CR0_PORTP_WIDTH (1U) 1779 #define NETC_F2_COMMON_ISIDKC1CR0_PORTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_PORTP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_PORTP_MASK) 1780 1781 #define NETC_F2_COMMON_ISIDKC1CR0_SPMP_MASK (0x4U) 1782 #define NETC_F2_COMMON_ISIDKC1CR0_SPMP_SHIFT (2U) 1783 #define NETC_F2_COMMON_ISIDKC1CR0_SPMP_WIDTH (1U) 1784 #define NETC_F2_COMMON_ISIDKC1CR0_SPMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_SPMP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_SPMP_MASK) 1785 1786 #define NETC_F2_COMMON_ISIDKC1CR0_DMACP_MASK (0x8U) 1787 #define NETC_F2_COMMON_ISIDKC1CR0_DMACP_SHIFT (3U) 1788 #define NETC_F2_COMMON_ISIDKC1CR0_DMACP_WIDTH (1U) 1789 #define NETC_F2_COMMON_ISIDKC1CR0_DMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_DMACP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_DMACP_MASK) 1790 1791 #define NETC_F2_COMMON_ISIDKC1CR0_SMACP_MASK (0x10U) 1792 #define NETC_F2_COMMON_ISIDKC1CR0_SMACP_SHIFT (4U) 1793 #define NETC_F2_COMMON_ISIDKC1CR0_SMACP_WIDTH (1U) 1794 #define NETC_F2_COMMON_ISIDKC1CR0_SMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_SMACP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_SMACP_MASK) 1795 1796 #define NETC_F2_COMMON_ISIDKC1CR0_OVIDP_MASK (0x20U) 1797 #define NETC_F2_COMMON_ISIDKC1CR0_OVIDP_SHIFT (5U) 1798 #define NETC_F2_COMMON_ISIDKC1CR0_OVIDP_WIDTH (1U) 1799 #define NETC_F2_COMMON_ISIDKC1CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_OVIDP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_OVIDP_MASK) 1800 1801 #define NETC_F2_COMMON_ISIDKC1CR0_OPCPP_MASK (0x40U) 1802 #define NETC_F2_COMMON_ISIDKC1CR0_OPCPP_SHIFT (6U) 1803 #define NETC_F2_COMMON_ISIDKC1CR0_OPCPP_WIDTH (1U) 1804 #define NETC_F2_COMMON_ISIDKC1CR0_OPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_OPCPP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_OPCPP_MASK) 1805 1806 #define NETC_F2_COMMON_ISIDKC1CR0_IVIDP_MASK (0x80U) 1807 #define NETC_F2_COMMON_ISIDKC1CR0_IVIDP_SHIFT (7U) 1808 #define NETC_F2_COMMON_ISIDKC1CR0_IVIDP_WIDTH (1U) 1809 #define NETC_F2_COMMON_ISIDKC1CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_IVIDP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_IVIDP_MASK) 1810 1811 #define NETC_F2_COMMON_ISIDKC1CR0_IPCPP_MASK (0x100U) 1812 #define NETC_F2_COMMON_ISIDKC1CR0_IPCPP_SHIFT (8U) 1813 #define NETC_F2_COMMON_ISIDKC1CR0_IPCPP_WIDTH (1U) 1814 #define NETC_F2_COMMON_ISIDKC1CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_IPCPP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_IPCPP_MASK) 1815 1816 #define NETC_F2_COMMON_ISIDKC1CR0_SQTP_MASK (0x200U) 1817 #define NETC_F2_COMMON_ISIDKC1CR0_SQTP_SHIFT (9U) 1818 #define NETC_F2_COMMON_ISIDKC1CR0_SQTP_WIDTH (1U) 1819 #define NETC_F2_COMMON_ISIDKC1CR0_SQTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_SQTP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_SQTP_MASK) 1820 1821 #define NETC_F2_COMMON_ISIDKC1CR0_ETP_MASK (0x400U) 1822 #define NETC_F2_COMMON_ISIDKC1CR0_ETP_SHIFT (10U) 1823 #define NETC_F2_COMMON_ISIDKC1CR0_ETP_WIDTH (1U) 1824 #define NETC_F2_COMMON_ISIDKC1CR0_ETP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1CR0_ETP_SHIFT)) & NETC_F2_COMMON_ISIDKC1CR0_ETP_MASK) 1825 /*! @} */ 1826 1827 /*! @name ISIDKC1PF0CR - Ingress stream identification key construction 1 payload field 0 configuration register */ 1828 /*! @{ */ 1829 1830 #define NETC_F2_COMMON_ISIDKC1PF0CR_PFP_MASK (0x1U) 1831 #define NETC_F2_COMMON_ISIDKC1PF0CR_PFP_SHIFT (0U) 1832 #define NETC_F2_COMMON_ISIDKC1PF0CR_PFP_WIDTH (1U) 1833 #define NETC_F2_COMMON_ISIDKC1PF0CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF0CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF0CR_PFP_MASK) 1834 1835 #define NETC_F2_COMMON_ISIDKC1PF0CR_NUM_BYTES_MASK (0x1EU) 1836 #define NETC_F2_COMMON_ISIDKC1PF0CR_NUM_BYTES_SHIFT (1U) 1837 #define NETC_F2_COMMON_ISIDKC1PF0CR_NUM_BYTES_WIDTH (4U) 1838 #define NETC_F2_COMMON_ISIDKC1PF0CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF0CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF0CR_NUM_BYTES_MASK) 1839 1840 #define NETC_F2_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_MASK (0x7F00U) 1841 #define NETC_F2_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_SHIFT (8U) 1842 #define NETC_F2_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_WIDTH (7U) 1843 #define NETC_F2_COMMON_ISIDKC1PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF0CR_BYTE_OFFSET_MASK) 1844 1845 #define NETC_F2_COMMON_ISIDKC1PF0CR_FBMASK_MASK (0x70000U) 1846 #define NETC_F2_COMMON_ISIDKC1PF0CR_FBMASK_SHIFT (16U) 1847 #define NETC_F2_COMMON_ISIDKC1PF0CR_FBMASK_WIDTH (3U) 1848 #define NETC_F2_COMMON_ISIDKC1PF0CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF0CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF0CR_FBMASK_MASK) 1849 1850 #define NETC_F2_COMMON_ISIDKC1PF0CR_LBMASK_MASK (0x700000U) 1851 #define NETC_F2_COMMON_ISIDKC1PF0CR_LBMASK_SHIFT (20U) 1852 #define NETC_F2_COMMON_ISIDKC1PF0CR_LBMASK_WIDTH (3U) 1853 #define NETC_F2_COMMON_ISIDKC1PF0CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF0CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF0CR_LBMASK_MASK) 1854 /*! @} */ 1855 1856 /*! @name ISIDKC1PF1CR - Ingress stream identification key construction 1 payload field 1 configuration register */ 1857 /*! @{ */ 1858 1859 #define NETC_F2_COMMON_ISIDKC1PF1CR_PFP_MASK (0x1U) 1860 #define NETC_F2_COMMON_ISIDKC1PF1CR_PFP_SHIFT (0U) 1861 #define NETC_F2_COMMON_ISIDKC1PF1CR_PFP_WIDTH (1U) 1862 #define NETC_F2_COMMON_ISIDKC1PF1CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF1CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF1CR_PFP_MASK) 1863 1864 #define NETC_F2_COMMON_ISIDKC1PF1CR_NUM_BYTES_MASK (0x1EU) 1865 #define NETC_F2_COMMON_ISIDKC1PF1CR_NUM_BYTES_SHIFT (1U) 1866 #define NETC_F2_COMMON_ISIDKC1PF1CR_NUM_BYTES_WIDTH (4U) 1867 #define NETC_F2_COMMON_ISIDKC1PF1CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF1CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF1CR_NUM_BYTES_MASK) 1868 1869 #define NETC_F2_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_MASK (0x7F00U) 1870 #define NETC_F2_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_SHIFT (8U) 1871 #define NETC_F2_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_WIDTH (7U) 1872 #define NETC_F2_COMMON_ISIDKC1PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF1CR_BYTE_OFFSET_MASK) 1873 1874 #define NETC_F2_COMMON_ISIDKC1PF1CR_FBMASK_MASK (0x70000U) 1875 #define NETC_F2_COMMON_ISIDKC1PF1CR_FBMASK_SHIFT (16U) 1876 #define NETC_F2_COMMON_ISIDKC1PF1CR_FBMASK_WIDTH (3U) 1877 #define NETC_F2_COMMON_ISIDKC1PF1CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF1CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF1CR_FBMASK_MASK) 1878 1879 #define NETC_F2_COMMON_ISIDKC1PF1CR_LBMASK_MASK (0x700000U) 1880 #define NETC_F2_COMMON_ISIDKC1PF1CR_LBMASK_SHIFT (20U) 1881 #define NETC_F2_COMMON_ISIDKC1PF1CR_LBMASK_WIDTH (3U) 1882 #define NETC_F2_COMMON_ISIDKC1PF1CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF1CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF1CR_LBMASK_MASK) 1883 /*! @} */ 1884 1885 /*! @name ISIDKC1PF2CR - Ingress stream identification key construction 1 payload field 2 configuration register */ 1886 /*! @{ */ 1887 1888 #define NETC_F2_COMMON_ISIDKC1PF2CR_PFP_MASK (0x1U) 1889 #define NETC_F2_COMMON_ISIDKC1PF2CR_PFP_SHIFT (0U) 1890 #define NETC_F2_COMMON_ISIDKC1PF2CR_PFP_WIDTH (1U) 1891 #define NETC_F2_COMMON_ISIDKC1PF2CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF2CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF2CR_PFP_MASK) 1892 1893 #define NETC_F2_COMMON_ISIDKC1PF2CR_NUM_BYTES_MASK (0x1EU) 1894 #define NETC_F2_COMMON_ISIDKC1PF2CR_NUM_BYTES_SHIFT (1U) 1895 #define NETC_F2_COMMON_ISIDKC1PF2CR_NUM_BYTES_WIDTH (4U) 1896 #define NETC_F2_COMMON_ISIDKC1PF2CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF2CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF2CR_NUM_BYTES_MASK) 1897 1898 #define NETC_F2_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_MASK (0x7F00U) 1899 #define NETC_F2_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_SHIFT (8U) 1900 #define NETC_F2_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_WIDTH (7U) 1901 #define NETC_F2_COMMON_ISIDKC1PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF2CR_BYTE_OFFSET_MASK) 1902 1903 #define NETC_F2_COMMON_ISIDKC1PF2CR_FBMASK_MASK (0x70000U) 1904 #define NETC_F2_COMMON_ISIDKC1PF2CR_FBMASK_SHIFT (16U) 1905 #define NETC_F2_COMMON_ISIDKC1PF2CR_FBMASK_WIDTH (3U) 1906 #define NETC_F2_COMMON_ISIDKC1PF2CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF2CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF2CR_FBMASK_MASK) 1907 1908 #define NETC_F2_COMMON_ISIDKC1PF2CR_LBMASK_MASK (0x700000U) 1909 #define NETC_F2_COMMON_ISIDKC1PF2CR_LBMASK_SHIFT (20U) 1910 #define NETC_F2_COMMON_ISIDKC1PF2CR_LBMASK_WIDTH (3U) 1911 #define NETC_F2_COMMON_ISIDKC1PF2CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF2CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF2CR_LBMASK_MASK) 1912 /*! @} */ 1913 1914 /*! @name ISIDKC1PF3CR - Ingress stream identification key construction 1 payload field 3 configuration register */ 1915 /*! @{ */ 1916 1917 #define NETC_F2_COMMON_ISIDKC1PF3CR_PFP_MASK (0x1U) 1918 #define NETC_F2_COMMON_ISIDKC1PF3CR_PFP_SHIFT (0U) 1919 #define NETC_F2_COMMON_ISIDKC1PF3CR_PFP_WIDTH (1U) 1920 #define NETC_F2_COMMON_ISIDKC1PF3CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF3CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF3CR_PFP_MASK) 1921 1922 #define NETC_F2_COMMON_ISIDKC1PF3CR_NUM_BYTES_MASK (0x1EU) 1923 #define NETC_F2_COMMON_ISIDKC1PF3CR_NUM_BYTES_SHIFT (1U) 1924 #define NETC_F2_COMMON_ISIDKC1PF3CR_NUM_BYTES_WIDTH (4U) 1925 #define NETC_F2_COMMON_ISIDKC1PF3CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF3CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF3CR_NUM_BYTES_MASK) 1926 1927 #define NETC_F2_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_MASK (0x7F00U) 1928 #define NETC_F2_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_SHIFT (8U) 1929 #define NETC_F2_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_WIDTH (7U) 1930 #define NETC_F2_COMMON_ISIDKC1PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF3CR_BYTE_OFFSET_MASK) 1931 1932 #define NETC_F2_COMMON_ISIDKC1PF3CR_FBMASK_MASK (0x70000U) 1933 #define NETC_F2_COMMON_ISIDKC1PF3CR_FBMASK_SHIFT (16U) 1934 #define NETC_F2_COMMON_ISIDKC1PF3CR_FBMASK_WIDTH (3U) 1935 #define NETC_F2_COMMON_ISIDKC1PF3CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF3CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF3CR_FBMASK_MASK) 1936 1937 #define NETC_F2_COMMON_ISIDKC1PF3CR_LBMASK_MASK (0x700000U) 1938 #define NETC_F2_COMMON_ISIDKC1PF3CR_LBMASK_SHIFT (20U) 1939 #define NETC_F2_COMMON_ISIDKC1PF3CR_LBMASK_WIDTH (3U) 1940 #define NETC_F2_COMMON_ISIDKC1PF3CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC1PF3CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC1PF3CR_LBMASK_MASK) 1941 /*! @} */ 1942 1943 /*! @name ISIDKC2OR - Ingress stream identification key construction 2 operational register */ 1944 /*! @{ */ 1945 1946 #define NETC_F2_COMMON_ISIDKC2OR_NUM_ENTRIES_MASK (0xFFFFU) 1947 #define NETC_F2_COMMON_ISIDKC2OR_NUM_ENTRIES_SHIFT (0U) 1948 #define NETC_F2_COMMON_ISIDKC2OR_NUM_ENTRIES_WIDTH (16U) 1949 #define NETC_F2_COMMON_ISIDKC2OR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2OR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISIDKC2OR_NUM_ENTRIES_MASK) 1950 1951 #define NETC_F2_COMMON_ISIDKC2OR_EN_MASK (0x80000000U) 1952 #define NETC_F2_COMMON_ISIDKC2OR_EN_SHIFT (31U) 1953 #define NETC_F2_COMMON_ISIDKC2OR_EN_WIDTH (1U) 1954 #define NETC_F2_COMMON_ISIDKC2OR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2OR_EN_SHIFT)) & NETC_F2_COMMON_ISIDKC2OR_EN_MASK) 1955 /*! @} */ 1956 1957 /*! @name ISIDKC2CR0 - Ingress stream identification key construction 2 configuration register 0 */ 1958 /*! @{ */ 1959 1960 #define NETC_F2_COMMON_ISIDKC2CR0_VALID_MASK (0x1U) 1961 #define NETC_F2_COMMON_ISIDKC2CR0_VALID_SHIFT (0U) 1962 #define NETC_F2_COMMON_ISIDKC2CR0_VALID_WIDTH (1U) 1963 #define NETC_F2_COMMON_ISIDKC2CR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_VALID_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_VALID_MASK) 1964 1965 #define NETC_F2_COMMON_ISIDKC2CR0_PORTP_MASK (0x2U) 1966 #define NETC_F2_COMMON_ISIDKC2CR0_PORTP_SHIFT (1U) 1967 #define NETC_F2_COMMON_ISIDKC2CR0_PORTP_WIDTH (1U) 1968 #define NETC_F2_COMMON_ISIDKC2CR0_PORTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_PORTP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_PORTP_MASK) 1969 1970 #define NETC_F2_COMMON_ISIDKC2CR0_SPMP_MASK (0x4U) 1971 #define NETC_F2_COMMON_ISIDKC2CR0_SPMP_SHIFT (2U) 1972 #define NETC_F2_COMMON_ISIDKC2CR0_SPMP_WIDTH (1U) 1973 #define NETC_F2_COMMON_ISIDKC2CR0_SPMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_SPMP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_SPMP_MASK) 1974 1975 #define NETC_F2_COMMON_ISIDKC2CR0_DMACP_MASK (0x8U) 1976 #define NETC_F2_COMMON_ISIDKC2CR0_DMACP_SHIFT (3U) 1977 #define NETC_F2_COMMON_ISIDKC2CR0_DMACP_WIDTH (1U) 1978 #define NETC_F2_COMMON_ISIDKC2CR0_DMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_DMACP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_DMACP_MASK) 1979 1980 #define NETC_F2_COMMON_ISIDKC2CR0_SMACP_MASK (0x10U) 1981 #define NETC_F2_COMMON_ISIDKC2CR0_SMACP_SHIFT (4U) 1982 #define NETC_F2_COMMON_ISIDKC2CR0_SMACP_WIDTH (1U) 1983 #define NETC_F2_COMMON_ISIDKC2CR0_SMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_SMACP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_SMACP_MASK) 1984 1985 #define NETC_F2_COMMON_ISIDKC2CR0_OVIDP_MASK (0x20U) 1986 #define NETC_F2_COMMON_ISIDKC2CR0_OVIDP_SHIFT (5U) 1987 #define NETC_F2_COMMON_ISIDKC2CR0_OVIDP_WIDTH (1U) 1988 #define NETC_F2_COMMON_ISIDKC2CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_OVIDP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_OVIDP_MASK) 1989 1990 #define NETC_F2_COMMON_ISIDKC2CR0_OPCPP_MASK (0x40U) 1991 #define NETC_F2_COMMON_ISIDKC2CR0_OPCPP_SHIFT (6U) 1992 #define NETC_F2_COMMON_ISIDKC2CR0_OPCPP_WIDTH (1U) 1993 #define NETC_F2_COMMON_ISIDKC2CR0_OPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_OPCPP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_OPCPP_MASK) 1994 1995 #define NETC_F2_COMMON_ISIDKC2CR0_IVIDP_MASK (0x80U) 1996 #define NETC_F2_COMMON_ISIDKC2CR0_IVIDP_SHIFT (7U) 1997 #define NETC_F2_COMMON_ISIDKC2CR0_IVIDP_WIDTH (1U) 1998 #define NETC_F2_COMMON_ISIDKC2CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_IVIDP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_IVIDP_MASK) 1999 2000 #define NETC_F2_COMMON_ISIDKC2CR0_IPCPP_MASK (0x100U) 2001 #define NETC_F2_COMMON_ISIDKC2CR0_IPCPP_SHIFT (8U) 2002 #define NETC_F2_COMMON_ISIDKC2CR0_IPCPP_WIDTH (1U) 2003 #define NETC_F2_COMMON_ISIDKC2CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_IPCPP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_IPCPP_MASK) 2004 2005 #define NETC_F2_COMMON_ISIDKC2CR0_SQTP_MASK (0x200U) 2006 #define NETC_F2_COMMON_ISIDKC2CR0_SQTP_SHIFT (9U) 2007 #define NETC_F2_COMMON_ISIDKC2CR0_SQTP_WIDTH (1U) 2008 #define NETC_F2_COMMON_ISIDKC2CR0_SQTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_SQTP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_SQTP_MASK) 2009 2010 #define NETC_F2_COMMON_ISIDKC2CR0_ETP_MASK (0x400U) 2011 #define NETC_F2_COMMON_ISIDKC2CR0_ETP_SHIFT (10U) 2012 #define NETC_F2_COMMON_ISIDKC2CR0_ETP_WIDTH (1U) 2013 #define NETC_F2_COMMON_ISIDKC2CR0_ETP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2CR0_ETP_SHIFT)) & NETC_F2_COMMON_ISIDKC2CR0_ETP_MASK) 2014 /*! @} */ 2015 2016 /*! @name ISIDKC2PF0CR - Ingress stream identification key construction 2 payload field 0 configuration register */ 2017 /*! @{ */ 2018 2019 #define NETC_F2_COMMON_ISIDKC2PF0CR_PFP_MASK (0x1U) 2020 #define NETC_F2_COMMON_ISIDKC2PF0CR_PFP_SHIFT (0U) 2021 #define NETC_F2_COMMON_ISIDKC2PF0CR_PFP_WIDTH (1U) 2022 #define NETC_F2_COMMON_ISIDKC2PF0CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF0CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF0CR_PFP_MASK) 2023 2024 #define NETC_F2_COMMON_ISIDKC2PF0CR_NUM_BYTES_MASK (0x1EU) 2025 #define NETC_F2_COMMON_ISIDKC2PF0CR_NUM_BYTES_SHIFT (1U) 2026 #define NETC_F2_COMMON_ISIDKC2PF0CR_NUM_BYTES_WIDTH (4U) 2027 #define NETC_F2_COMMON_ISIDKC2PF0CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF0CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF0CR_NUM_BYTES_MASK) 2028 2029 #define NETC_F2_COMMON_ISIDKC2PF0CR_BYTE_OFFSET_MASK (0x7F00U) 2030 #define NETC_F2_COMMON_ISIDKC2PF0CR_BYTE_OFFSET_SHIFT (8U) 2031 #define NETC_F2_COMMON_ISIDKC2PF0CR_BYTE_OFFSET_WIDTH (7U) 2032 #define NETC_F2_COMMON_ISIDKC2PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF0CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF0CR_BYTE_OFFSET_MASK) 2033 2034 #define NETC_F2_COMMON_ISIDKC2PF0CR_FBMASK_MASK (0x70000U) 2035 #define NETC_F2_COMMON_ISIDKC2PF0CR_FBMASK_SHIFT (16U) 2036 #define NETC_F2_COMMON_ISIDKC2PF0CR_FBMASK_WIDTH (3U) 2037 #define NETC_F2_COMMON_ISIDKC2PF0CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF0CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF0CR_FBMASK_MASK) 2038 2039 #define NETC_F2_COMMON_ISIDKC2PF0CR_LBMASK_MASK (0x700000U) 2040 #define NETC_F2_COMMON_ISIDKC2PF0CR_LBMASK_SHIFT (20U) 2041 #define NETC_F2_COMMON_ISIDKC2PF0CR_LBMASK_WIDTH (3U) 2042 #define NETC_F2_COMMON_ISIDKC2PF0CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF0CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF0CR_LBMASK_MASK) 2043 /*! @} */ 2044 2045 /*! @name ISIDKC2PF1CR - Ingress stream identification key construction 2 payload field 1 configuration register */ 2046 /*! @{ */ 2047 2048 #define NETC_F2_COMMON_ISIDKC2PF1CR_PFP_MASK (0x1U) 2049 #define NETC_F2_COMMON_ISIDKC2PF1CR_PFP_SHIFT (0U) 2050 #define NETC_F2_COMMON_ISIDKC2PF1CR_PFP_WIDTH (1U) 2051 #define NETC_F2_COMMON_ISIDKC2PF1CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF1CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF1CR_PFP_MASK) 2052 2053 #define NETC_F2_COMMON_ISIDKC2PF1CR_NUM_BYTES_MASK (0x1EU) 2054 #define NETC_F2_COMMON_ISIDKC2PF1CR_NUM_BYTES_SHIFT (1U) 2055 #define NETC_F2_COMMON_ISIDKC2PF1CR_NUM_BYTES_WIDTH (4U) 2056 #define NETC_F2_COMMON_ISIDKC2PF1CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF1CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF1CR_NUM_BYTES_MASK) 2057 2058 #define NETC_F2_COMMON_ISIDKC2PF1CR_BYTE_OFFSET_MASK (0x7F00U) 2059 #define NETC_F2_COMMON_ISIDKC2PF1CR_BYTE_OFFSET_SHIFT (8U) 2060 #define NETC_F2_COMMON_ISIDKC2PF1CR_BYTE_OFFSET_WIDTH (7U) 2061 #define NETC_F2_COMMON_ISIDKC2PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF1CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF1CR_BYTE_OFFSET_MASK) 2062 2063 #define NETC_F2_COMMON_ISIDKC2PF1CR_FBMASK_MASK (0x70000U) 2064 #define NETC_F2_COMMON_ISIDKC2PF1CR_FBMASK_SHIFT (16U) 2065 #define NETC_F2_COMMON_ISIDKC2PF1CR_FBMASK_WIDTH (3U) 2066 #define NETC_F2_COMMON_ISIDKC2PF1CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF1CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF1CR_FBMASK_MASK) 2067 2068 #define NETC_F2_COMMON_ISIDKC2PF1CR_LBMASK_MASK (0x700000U) 2069 #define NETC_F2_COMMON_ISIDKC2PF1CR_LBMASK_SHIFT (20U) 2070 #define NETC_F2_COMMON_ISIDKC2PF1CR_LBMASK_WIDTH (3U) 2071 #define NETC_F2_COMMON_ISIDKC2PF1CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF1CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF1CR_LBMASK_MASK) 2072 /*! @} */ 2073 2074 /*! @name ISIDKC2PF2CR - Ingress stream identification key construction 2 payload field 2 configuration register */ 2075 /*! @{ */ 2076 2077 #define NETC_F2_COMMON_ISIDKC2PF2CR_PFP_MASK (0x1U) 2078 #define NETC_F2_COMMON_ISIDKC2PF2CR_PFP_SHIFT (0U) 2079 #define NETC_F2_COMMON_ISIDKC2PF2CR_PFP_WIDTH (1U) 2080 #define NETC_F2_COMMON_ISIDKC2PF2CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF2CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF2CR_PFP_MASK) 2081 2082 #define NETC_F2_COMMON_ISIDKC2PF2CR_NUM_BYTES_MASK (0x1EU) 2083 #define NETC_F2_COMMON_ISIDKC2PF2CR_NUM_BYTES_SHIFT (1U) 2084 #define NETC_F2_COMMON_ISIDKC2PF2CR_NUM_BYTES_WIDTH (4U) 2085 #define NETC_F2_COMMON_ISIDKC2PF2CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF2CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF2CR_NUM_BYTES_MASK) 2086 2087 #define NETC_F2_COMMON_ISIDKC2PF2CR_BYTE_OFFSET_MASK (0x7F00U) 2088 #define NETC_F2_COMMON_ISIDKC2PF2CR_BYTE_OFFSET_SHIFT (8U) 2089 #define NETC_F2_COMMON_ISIDKC2PF2CR_BYTE_OFFSET_WIDTH (7U) 2090 #define NETC_F2_COMMON_ISIDKC2PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF2CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF2CR_BYTE_OFFSET_MASK) 2091 2092 #define NETC_F2_COMMON_ISIDKC2PF2CR_FBMASK_MASK (0x70000U) 2093 #define NETC_F2_COMMON_ISIDKC2PF2CR_FBMASK_SHIFT (16U) 2094 #define NETC_F2_COMMON_ISIDKC2PF2CR_FBMASK_WIDTH (3U) 2095 #define NETC_F2_COMMON_ISIDKC2PF2CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF2CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF2CR_FBMASK_MASK) 2096 2097 #define NETC_F2_COMMON_ISIDKC2PF2CR_LBMASK_MASK (0x700000U) 2098 #define NETC_F2_COMMON_ISIDKC2PF2CR_LBMASK_SHIFT (20U) 2099 #define NETC_F2_COMMON_ISIDKC2PF2CR_LBMASK_WIDTH (3U) 2100 #define NETC_F2_COMMON_ISIDKC2PF2CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF2CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF2CR_LBMASK_MASK) 2101 /*! @} */ 2102 2103 /*! @name ISIDKC2PF3CR - Ingress stream identification key construction 2 payload field 3 configuration register */ 2104 /*! @{ */ 2105 2106 #define NETC_F2_COMMON_ISIDKC2PF3CR_PFP_MASK (0x1U) 2107 #define NETC_F2_COMMON_ISIDKC2PF3CR_PFP_SHIFT (0U) 2108 #define NETC_F2_COMMON_ISIDKC2PF3CR_PFP_WIDTH (1U) 2109 #define NETC_F2_COMMON_ISIDKC2PF3CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF3CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF3CR_PFP_MASK) 2110 2111 #define NETC_F2_COMMON_ISIDKC2PF3CR_NUM_BYTES_MASK (0x1EU) 2112 #define NETC_F2_COMMON_ISIDKC2PF3CR_NUM_BYTES_SHIFT (1U) 2113 #define NETC_F2_COMMON_ISIDKC2PF3CR_NUM_BYTES_WIDTH (4U) 2114 #define NETC_F2_COMMON_ISIDKC2PF3CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF3CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF3CR_NUM_BYTES_MASK) 2115 2116 #define NETC_F2_COMMON_ISIDKC2PF3CR_BYTE_OFFSET_MASK (0x7F00U) 2117 #define NETC_F2_COMMON_ISIDKC2PF3CR_BYTE_OFFSET_SHIFT (8U) 2118 #define NETC_F2_COMMON_ISIDKC2PF3CR_BYTE_OFFSET_WIDTH (7U) 2119 #define NETC_F2_COMMON_ISIDKC2PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF3CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF3CR_BYTE_OFFSET_MASK) 2120 2121 #define NETC_F2_COMMON_ISIDKC2PF3CR_FBMASK_MASK (0x70000U) 2122 #define NETC_F2_COMMON_ISIDKC2PF3CR_FBMASK_SHIFT (16U) 2123 #define NETC_F2_COMMON_ISIDKC2PF3CR_FBMASK_WIDTH (3U) 2124 #define NETC_F2_COMMON_ISIDKC2PF3CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF3CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF3CR_FBMASK_MASK) 2125 2126 #define NETC_F2_COMMON_ISIDKC2PF3CR_LBMASK_MASK (0x700000U) 2127 #define NETC_F2_COMMON_ISIDKC2PF3CR_LBMASK_SHIFT (20U) 2128 #define NETC_F2_COMMON_ISIDKC2PF3CR_LBMASK_WIDTH (3U) 2129 #define NETC_F2_COMMON_ISIDKC2PF3CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC2PF3CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC2PF3CR_LBMASK_MASK) 2130 /*! @} */ 2131 2132 /*! @name ISIDKC3OR - Ingress stream identification key construction 3 operational register */ 2133 /*! @{ */ 2134 2135 #define NETC_F2_COMMON_ISIDKC3OR_NUM_ENTRIES_MASK (0xFFFFU) 2136 #define NETC_F2_COMMON_ISIDKC3OR_NUM_ENTRIES_SHIFT (0U) 2137 #define NETC_F2_COMMON_ISIDKC3OR_NUM_ENTRIES_WIDTH (16U) 2138 #define NETC_F2_COMMON_ISIDKC3OR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3OR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISIDKC3OR_NUM_ENTRIES_MASK) 2139 2140 #define NETC_F2_COMMON_ISIDKC3OR_EN_MASK (0x80000000U) 2141 #define NETC_F2_COMMON_ISIDKC3OR_EN_SHIFT (31U) 2142 #define NETC_F2_COMMON_ISIDKC3OR_EN_WIDTH (1U) 2143 #define NETC_F2_COMMON_ISIDKC3OR_EN(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3OR_EN_SHIFT)) & NETC_F2_COMMON_ISIDKC3OR_EN_MASK) 2144 /*! @} */ 2145 2146 /*! @name ISIDKC3CR0 - Ingress stream identification key construction 3 configuration register 0 */ 2147 /*! @{ */ 2148 2149 #define NETC_F2_COMMON_ISIDKC3CR0_VALID_MASK (0x1U) 2150 #define NETC_F2_COMMON_ISIDKC3CR0_VALID_SHIFT (0U) 2151 #define NETC_F2_COMMON_ISIDKC3CR0_VALID_WIDTH (1U) 2152 #define NETC_F2_COMMON_ISIDKC3CR0_VALID(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_VALID_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_VALID_MASK) 2153 2154 #define NETC_F2_COMMON_ISIDKC3CR0_PORTP_MASK (0x2U) 2155 #define NETC_F2_COMMON_ISIDKC3CR0_PORTP_SHIFT (1U) 2156 #define NETC_F2_COMMON_ISIDKC3CR0_PORTP_WIDTH (1U) 2157 #define NETC_F2_COMMON_ISIDKC3CR0_PORTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_PORTP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_PORTP_MASK) 2158 2159 #define NETC_F2_COMMON_ISIDKC3CR0_SPMP_MASK (0x4U) 2160 #define NETC_F2_COMMON_ISIDKC3CR0_SPMP_SHIFT (2U) 2161 #define NETC_F2_COMMON_ISIDKC3CR0_SPMP_WIDTH (1U) 2162 #define NETC_F2_COMMON_ISIDKC3CR0_SPMP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_SPMP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_SPMP_MASK) 2163 2164 #define NETC_F2_COMMON_ISIDKC3CR0_DMACP_MASK (0x8U) 2165 #define NETC_F2_COMMON_ISIDKC3CR0_DMACP_SHIFT (3U) 2166 #define NETC_F2_COMMON_ISIDKC3CR0_DMACP_WIDTH (1U) 2167 #define NETC_F2_COMMON_ISIDKC3CR0_DMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_DMACP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_DMACP_MASK) 2168 2169 #define NETC_F2_COMMON_ISIDKC3CR0_SMACP_MASK (0x10U) 2170 #define NETC_F2_COMMON_ISIDKC3CR0_SMACP_SHIFT (4U) 2171 #define NETC_F2_COMMON_ISIDKC3CR0_SMACP_WIDTH (1U) 2172 #define NETC_F2_COMMON_ISIDKC3CR0_SMACP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_SMACP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_SMACP_MASK) 2173 2174 #define NETC_F2_COMMON_ISIDKC3CR0_OVIDP_MASK (0x20U) 2175 #define NETC_F2_COMMON_ISIDKC3CR0_OVIDP_SHIFT (5U) 2176 #define NETC_F2_COMMON_ISIDKC3CR0_OVIDP_WIDTH (1U) 2177 #define NETC_F2_COMMON_ISIDKC3CR0_OVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_OVIDP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_OVIDP_MASK) 2178 2179 #define NETC_F2_COMMON_ISIDKC3CR0_OPCPP_MASK (0x40U) 2180 #define NETC_F2_COMMON_ISIDKC3CR0_OPCPP_SHIFT (6U) 2181 #define NETC_F2_COMMON_ISIDKC3CR0_OPCPP_WIDTH (1U) 2182 #define NETC_F2_COMMON_ISIDKC3CR0_OPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_OPCPP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_OPCPP_MASK) 2183 2184 #define NETC_F2_COMMON_ISIDKC3CR0_IVIDP_MASK (0x80U) 2185 #define NETC_F2_COMMON_ISIDKC3CR0_IVIDP_SHIFT (7U) 2186 #define NETC_F2_COMMON_ISIDKC3CR0_IVIDP_WIDTH (1U) 2187 #define NETC_F2_COMMON_ISIDKC3CR0_IVIDP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_IVIDP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_IVIDP_MASK) 2188 2189 #define NETC_F2_COMMON_ISIDKC3CR0_IPCPP_MASK (0x100U) 2190 #define NETC_F2_COMMON_ISIDKC3CR0_IPCPP_SHIFT (8U) 2191 #define NETC_F2_COMMON_ISIDKC3CR0_IPCPP_WIDTH (1U) 2192 #define NETC_F2_COMMON_ISIDKC3CR0_IPCPP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_IPCPP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_IPCPP_MASK) 2193 2194 #define NETC_F2_COMMON_ISIDKC3CR0_SQTP_MASK (0x200U) 2195 #define NETC_F2_COMMON_ISIDKC3CR0_SQTP_SHIFT (9U) 2196 #define NETC_F2_COMMON_ISIDKC3CR0_SQTP_WIDTH (1U) 2197 #define NETC_F2_COMMON_ISIDKC3CR0_SQTP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_SQTP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_SQTP_MASK) 2198 2199 #define NETC_F2_COMMON_ISIDKC3CR0_ETP_MASK (0x400U) 2200 #define NETC_F2_COMMON_ISIDKC3CR0_ETP_SHIFT (10U) 2201 #define NETC_F2_COMMON_ISIDKC3CR0_ETP_WIDTH (1U) 2202 #define NETC_F2_COMMON_ISIDKC3CR0_ETP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3CR0_ETP_SHIFT)) & NETC_F2_COMMON_ISIDKC3CR0_ETP_MASK) 2203 /*! @} */ 2204 2205 /*! @name ISIDKC3PF0CR - Ingress stream identification key construction 3 payload field 0 configuration register */ 2206 /*! @{ */ 2207 2208 #define NETC_F2_COMMON_ISIDKC3PF0CR_PFP_MASK (0x1U) 2209 #define NETC_F2_COMMON_ISIDKC3PF0CR_PFP_SHIFT (0U) 2210 #define NETC_F2_COMMON_ISIDKC3PF0CR_PFP_WIDTH (1U) 2211 #define NETC_F2_COMMON_ISIDKC3PF0CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF0CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF0CR_PFP_MASK) 2212 2213 #define NETC_F2_COMMON_ISIDKC3PF0CR_NUM_BYTES_MASK (0x1EU) 2214 #define NETC_F2_COMMON_ISIDKC3PF0CR_NUM_BYTES_SHIFT (1U) 2215 #define NETC_F2_COMMON_ISIDKC3PF0CR_NUM_BYTES_WIDTH (4U) 2216 #define NETC_F2_COMMON_ISIDKC3PF0CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF0CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF0CR_NUM_BYTES_MASK) 2217 2218 #define NETC_F2_COMMON_ISIDKC3PF0CR_BYTE_OFFSET_MASK (0x7F00U) 2219 #define NETC_F2_COMMON_ISIDKC3PF0CR_BYTE_OFFSET_SHIFT (8U) 2220 #define NETC_F2_COMMON_ISIDKC3PF0CR_BYTE_OFFSET_WIDTH (7U) 2221 #define NETC_F2_COMMON_ISIDKC3PF0CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF0CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF0CR_BYTE_OFFSET_MASK) 2222 2223 #define NETC_F2_COMMON_ISIDKC3PF0CR_FBMASK_MASK (0x70000U) 2224 #define NETC_F2_COMMON_ISIDKC3PF0CR_FBMASK_SHIFT (16U) 2225 #define NETC_F2_COMMON_ISIDKC3PF0CR_FBMASK_WIDTH (3U) 2226 #define NETC_F2_COMMON_ISIDKC3PF0CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF0CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF0CR_FBMASK_MASK) 2227 2228 #define NETC_F2_COMMON_ISIDKC3PF0CR_LBMASK_MASK (0x700000U) 2229 #define NETC_F2_COMMON_ISIDKC3PF0CR_LBMASK_SHIFT (20U) 2230 #define NETC_F2_COMMON_ISIDKC3PF0CR_LBMASK_WIDTH (3U) 2231 #define NETC_F2_COMMON_ISIDKC3PF0CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF0CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF0CR_LBMASK_MASK) 2232 /*! @} */ 2233 2234 /*! @name ISIDKC3PF1CR - Ingress stream identification key construction 3 payload field 1 configuration register */ 2235 /*! @{ */ 2236 2237 #define NETC_F2_COMMON_ISIDKC3PF1CR_PFP_MASK (0x1U) 2238 #define NETC_F2_COMMON_ISIDKC3PF1CR_PFP_SHIFT (0U) 2239 #define NETC_F2_COMMON_ISIDKC3PF1CR_PFP_WIDTH (1U) 2240 #define NETC_F2_COMMON_ISIDKC3PF1CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF1CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF1CR_PFP_MASK) 2241 2242 #define NETC_F2_COMMON_ISIDKC3PF1CR_NUM_BYTES_MASK (0x1EU) 2243 #define NETC_F2_COMMON_ISIDKC3PF1CR_NUM_BYTES_SHIFT (1U) 2244 #define NETC_F2_COMMON_ISIDKC3PF1CR_NUM_BYTES_WIDTH (4U) 2245 #define NETC_F2_COMMON_ISIDKC3PF1CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF1CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF1CR_NUM_BYTES_MASK) 2246 2247 #define NETC_F2_COMMON_ISIDKC3PF1CR_BYTE_OFFSET_MASK (0x7F00U) 2248 #define NETC_F2_COMMON_ISIDKC3PF1CR_BYTE_OFFSET_SHIFT (8U) 2249 #define NETC_F2_COMMON_ISIDKC3PF1CR_BYTE_OFFSET_WIDTH (7U) 2250 #define NETC_F2_COMMON_ISIDKC3PF1CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF1CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF1CR_BYTE_OFFSET_MASK) 2251 2252 #define NETC_F2_COMMON_ISIDKC3PF1CR_FBMASK_MASK (0x70000U) 2253 #define NETC_F2_COMMON_ISIDKC3PF1CR_FBMASK_SHIFT (16U) 2254 #define NETC_F2_COMMON_ISIDKC3PF1CR_FBMASK_WIDTH (3U) 2255 #define NETC_F2_COMMON_ISIDKC3PF1CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF1CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF1CR_FBMASK_MASK) 2256 2257 #define NETC_F2_COMMON_ISIDKC3PF1CR_LBMASK_MASK (0x700000U) 2258 #define NETC_F2_COMMON_ISIDKC3PF1CR_LBMASK_SHIFT (20U) 2259 #define NETC_F2_COMMON_ISIDKC3PF1CR_LBMASK_WIDTH (3U) 2260 #define NETC_F2_COMMON_ISIDKC3PF1CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF1CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF1CR_LBMASK_MASK) 2261 /*! @} */ 2262 2263 /*! @name ISIDKC3PF2CR - Ingress stream identification key construction 3 payload field 2 configuration register */ 2264 /*! @{ */ 2265 2266 #define NETC_F2_COMMON_ISIDKC3PF2CR_PFP_MASK (0x1U) 2267 #define NETC_F2_COMMON_ISIDKC3PF2CR_PFP_SHIFT (0U) 2268 #define NETC_F2_COMMON_ISIDKC3PF2CR_PFP_WIDTH (1U) 2269 #define NETC_F2_COMMON_ISIDKC3PF2CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF2CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF2CR_PFP_MASK) 2270 2271 #define NETC_F2_COMMON_ISIDKC3PF2CR_NUM_BYTES_MASK (0x1EU) 2272 #define NETC_F2_COMMON_ISIDKC3PF2CR_NUM_BYTES_SHIFT (1U) 2273 #define NETC_F2_COMMON_ISIDKC3PF2CR_NUM_BYTES_WIDTH (4U) 2274 #define NETC_F2_COMMON_ISIDKC3PF2CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF2CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF2CR_NUM_BYTES_MASK) 2275 2276 #define NETC_F2_COMMON_ISIDKC3PF2CR_BYTE_OFFSET_MASK (0x7F00U) 2277 #define NETC_F2_COMMON_ISIDKC3PF2CR_BYTE_OFFSET_SHIFT (8U) 2278 #define NETC_F2_COMMON_ISIDKC3PF2CR_BYTE_OFFSET_WIDTH (7U) 2279 #define NETC_F2_COMMON_ISIDKC3PF2CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF2CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF2CR_BYTE_OFFSET_MASK) 2280 2281 #define NETC_F2_COMMON_ISIDKC3PF2CR_FBMASK_MASK (0x70000U) 2282 #define NETC_F2_COMMON_ISIDKC3PF2CR_FBMASK_SHIFT (16U) 2283 #define NETC_F2_COMMON_ISIDKC3PF2CR_FBMASK_WIDTH (3U) 2284 #define NETC_F2_COMMON_ISIDKC3PF2CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF2CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF2CR_FBMASK_MASK) 2285 2286 #define NETC_F2_COMMON_ISIDKC3PF2CR_LBMASK_MASK (0x700000U) 2287 #define NETC_F2_COMMON_ISIDKC3PF2CR_LBMASK_SHIFT (20U) 2288 #define NETC_F2_COMMON_ISIDKC3PF2CR_LBMASK_WIDTH (3U) 2289 #define NETC_F2_COMMON_ISIDKC3PF2CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF2CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF2CR_LBMASK_MASK) 2290 /*! @} */ 2291 2292 /*! @name ISIDKC3PF3CR - Ingress stream identification key construction 3 payload field 3 configuration register */ 2293 /*! @{ */ 2294 2295 #define NETC_F2_COMMON_ISIDKC3PF3CR_PFP_MASK (0x1U) 2296 #define NETC_F2_COMMON_ISIDKC3PF3CR_PFP_SHIFT (0U) 2297 #define NETC_F2_COMMON_ISIDKC3PF3CR_PFP_WIDTH (1U) 2298 #define NETC_F2_COMMON_ISIDKC3PF3CR_PFP(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF3CR_PFP_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF3CR_PFP_MASK) 2299 2300 #define NETC_F2_COMMON_ISIDKC3PF3CR_NUM_BYTES_MASK (0x1EU) 2301 #define NETC_F2_COMMON_ISIDKC3PF3CR_NUM_BYTES_SHIFT (1U) 2302 #define NETC_F2_COMMON_ISIDKC3PF3CR_NUM_BYTES_WIDTH (4U) 2303 #define NETC_F2_COMMON_ISIDKC3PF3CR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF3CR_NUM_BYTES_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF3CR_NUM_BYTES_MASK) 2304 2305 #define NETC_F2_COMMON_ISIDKC3PF3CR_BYTE_OFFSET_MASK (0x7F00U) 2306 #define NETC_F2_COMMON_ISIDKC3PF3CR_BYTE_OFFSET_SHIFT (8U) 2307 #define NETC_F2_COMMON_ISIDKC3PF3CR_BYTE_OFFSET_WIDTH (7U) 2308 #define NETC_F2_COMMON_ISIDKC3PF3CR_BYTE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF3CR_BYTE_OFFSET_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF3CR_BYTE_OFFSET_MASK) 2309 2310 #define NETC_F2_COMMON_ISIDKC3PF3CR_FBMASK_MASK (0x70000U) 2311 #define NETC_F2_COMMON_ISIDKC3PF3CR_FBMASK_SHIFT (16U) 2312 #define NETC_F2_COMMON_ISIDKC3PF3CR_FBMASK_WIDTH (3U) 2313 #define NETC_F2_COMMON_ISIDKC3PF3CR_FBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF3CR_FBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF3CR_FBMASK_MASK) 2314 2315 #define NETC_F2_COMMON_ISIDKC3PF3CR_LBMASK_MASK (0x700000U) 2316 #define NETC_F2_COMMON_ISIDKC3PF3CR_LBMASK_SHIFT (20U) 2317 #define NETC_F2_COMMON_ISIDKC3PF3CR_LBMASK_WIDTH (3U) 2318 #define NETC_F2_COMMON_ISIDKC3PF3CR_LBMASK(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISIDKC3PF3CR_LBMASK_SHIFT)) & NETC_F2_COMMON_ISIDKC3PF3CR_LBMASK_MASK) 2319 /*! @} */ 2320 2321 /*! @name ISFHTCAPR - Ingress stream filter hash table capability register */ 2322 /*! @{ */ 2323 2324 #define NETC_F2_COMMON_ISFHTCAPR_ACCESS_METH_MASK (0xF00000U) 2325 #define NETC_F2_COMMON_ISFHTCAPR_ACCESS_METH_SHIFT (20U) 2326 #define NETC_F2_COMMON_ISFHTCAPR_ACCESS_METH_WIDTH (4U) 2327 #define NETC_F2_COMMON_ISFHTCAPR_ACCESS_METH(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISFHTCAPR_ACCESS_METH_SHIFT)) & NETC_F2_COMMON_ISFHTCAPR_ACCESS_METH_MASK) 2328 /*! @} */ 2329 2330 /*! @name ISFHTOR - Ingress stream filter hash table operational register */ 2331 /*! @{ */ 2332 2333 #define NETC_F2_COMMON_ISFHTOR_NUM_ENTRIES_MASK (0xFFFFU) 2334 #define NETC_F2_COMMON_ISFHTOR_NUM_ENTRIES_SHIFT (0U) 2335 #define NETC_F2_COMMON_ISFHTOR_NUM_ENTRIES_WIDTH (16U) 2336 #define NETC_F2_COMMON_ISFHTOR_NUM_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << NETC_F2_COMMON_ISFHTOR_NUM_ENTRIES_SHIFT)) & NETC_F2_COMMON_ISFHTOR_NUM_ENTRIES_MASK) 2337 /*! @} */ 2338 2339 /*! 2340 * @} 2341 */ /* end of group NETC_F2_COMMON_Register_Masks */ 2342 2343 /*! 2344 * @} 2345 */ /* end of group NETC_F2_COMMON_Peripheral_Access_Layer */ 2346 2347 #endif /* #if !defined(S32Z2_NETC_F2_COMMON_H_) */ 2348
