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/hal_nxp-3.6.0/s32/soc/s32z27/include/
DLinflexd_Uart_Ip_Defines.h92 …FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boole…
100 …FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boolean) FALSE, (boole…
DPlatformTypes.h157 #ifndef FALSE
163 #define FALSE false macro
169 #define FALSE 0
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Selector.c183 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXCscCssClkswSwip()
205 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
207 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
221 …p_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_CLK_SW_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
223 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
231 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
233 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
315 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
337 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
339 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswRampupRampdownSwip()
[all …]
DClock_Ip_Specific.c203 boolean TimeoutOccurred = FALSE; in Clock_Ip_PllPowerClockIp()
219 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK)) && (FALSE == Time… in Clock_Ip_PllPowerClockIp()
243 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK57_MASK)) && (FALSE == Time… in Clock_Ip_PllPowerClockIp()
261 boolean TimeoutOccurred = FALSE; in Clock_Ip_PowerClockIpModules()
279 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK53_MASK)) && (FALSE == Time… in Clock_Ip_PowerClockIpModules()
303 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK51_MASK)) && (FALSE == Time… in Clock_Ip_PowerClockIpModules()
327 …while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK47_MASK)) && (FALSE == Time… in Clock_Ip_PowerClockIpModules()
350 …while((0U == (IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK24_MASK)) && (FALSE == Time… in Clock_Ip_PowerClockIpModules()
529 if (FALSE == Clock_Ip_bObjectsAreInitialized) in Clock_Ip_ClockInitializeObjects()
/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/src/
DClock_Ip_IntOsc.c185 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetFircDivSelHSEb()
224 while ((CLOCK_IP_WFI_EXECUTED != WfiStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_SetFircDivSelHSEb()
226 if (FALSE == TimeoutOccurred) in Clock_Ip_SetFircDivSelHSEb()
381 boolean TimeoutOccurred = FALSE; in SetInputSouceSytemClock()
398 while ((0U == ScsStatus) && (FALSE == TimeoutOccurred)); in SetInputSouceSytemClock()
400 if (FALSE != TimeoutOccurred) in SetInputSouceSytemClock()
452 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetSirc_TrustedCall()
502 while ((0U == IrcoscStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_SetSirc_TrustedCall()
504 if (FALSE != TimeoutOccurred) in Clock_Ip_SetSirc_TrustedCall()
513 boolean TimeoutOccurred = FALSE; in Clock_Ip_EnableSirc_TrustedCall()
[all …]
DClock_Ip_ExtOsc.c181 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompleteSOSC()
199 while ((0U == SoscStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteSOSC()
201 if (FALSE != TimeoutOccurred) in Clock_Ip_CompleteSOSC()
294 CLOCK_IP_DEV_ASSERT(FALSE); in Clock_Ip_SetSOSC_TrustedCall()
356 CLOCK_IP_DEV_ASSERT(FALSE); in Clock_Ip_SetSOSC_TrustedCall()
DClock_Ip_Specific.c337 boolean FircConfigFound = FALSE; in DisableSafeClock()
346 if (Clock_Ip_apConfig->Ircoscs[Index].Enable == FALSE) in DisableSafeClock()
356 if ((FircConfigFound == FALSE) && (Clock_Ip_bFircWasEnabledBeforeMcuInit == FALSE)) in DisableSafeClock()
465 boolean TimeoutOccurred = FALSE; in Clock_Ip_SpecificPlatformInitClock()
482 Clock_Ip_bFircWasEnabledBeforeMcuInit = FALSE; in Clock_Ip_SpecificPlatformInitClock()
499 while ((IrcoscStatus == 0U) && (FALSE == TimeoutOccurred)); in Clock_Ip_SpecificPlatformInitClock()
501 if (FALSE != TimeoutOccurred) in Clock_Ip_SpecificPlatformInitClock()
939 if (FALSE == Clock_Ip_bObjsAreInitialized) in Clock_Ip_ClockInitializeObjects()
1028 Clock_Ip_bAcceptedCopyClockConfiguration = FALSE; in Clock_Ip_ClockPowerModeChangeNotification()
DClock_Ip_Pll.c186 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompleteSpll()
203 while ((0U == SpllStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteSpll()
205 if (FALSE == TimeoutOccurred) in Clock_Ip_CompleteSpll()
327 CLOCK_IP_DEV_ASSERT(FALSE); in Clock_Ip_SetSpll_TrustedCall()
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Selector.c185 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXCscCssClkswSwip()
207 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
209 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
223 …p_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_CLK_SW_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
225 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
233 …_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_SWIP_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_SetCgmXCscCssClkswSwip()
235 if (FALSE == TimeoutOccurred) in Clock_Ip_SetCgmXCscCssClkswSwip()
289 boolean TimeoutOccurred = FALSE; in Clock_Ip_ResetCgmXCscCssCsGrip()
310 …ck_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_MUX_CSS_CS_MASK)) && (FALSE == TimeoutOccurred… in Clock_Ip_ResetCgmXCscCssCsGrip()
312 if (FALSE == TimeoutOccurred) in Clock_Ip_ResetCgmXCscCssCsGrip()
[all …]
DClock_Ip_Pll.c250 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
266 while ((0U == PllLockStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
386 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompletePlldigRdivMfiMfnSdmen()
402 while ((0U == PllLockStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompletePlldigRdivMfiMfnSdmen()
519 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetLfastPLL()
553 while (FALSE == TimeoutOccurred); in Clock_Ip_SetLfastPLL()
567 while (FALSE == TimeoutOccurred); in Clock_Ip_SetLfastPLL()
583 boolean TimeoutOccurred = FALSE; in Clock_Ip_CompleteLfastPLL()
599 while ((0U != PllEnableStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteLfastPLL()
616 while ((1U != PllLockStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_CompleteLfastPLL()
DClock_Ip_Divider.c147 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
200 … while ((MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING == DividerStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
236 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
278 … while ((MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING == DividerStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
354 boolean TimeoutOccurred = FALSE; in Clock_Ip_SetCgmXDeDivFmtStatWithoutPhase()
395 … while ((MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING == DividerStatus) && (FALSE == TimeoutOccurred)); in Clock_Ip_SetCgmXDeDivFmtStatWithoutPhase()
/hal_nxp-3.6.0/s32/drivers/s32ze/Uart/src/
DLinflexd_Uart_Ip.c263 boolean ResetIdle = FALSE; in Linflexd_Uart_Ip_SetBaudrate()
264 boolean IsReturn = FALSE; in Linflexd_Uart_Ip_SetBaudrate()
404 UartStatePtr->IsDriverInitialized = FALSE; in Linflexd_Uart_Ip_Init()
423 Linflexd_Uart_Ip_SetTransmitterState(Base, FALSE); in Linflexd_Uart_Ip_Init()
424 Linflexd_Uart_Ip_SetReceiverState(Base, FALSE); in Linflexd_Uart_Ip_Init()
469 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_DATA_TRANSMITTED_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
471 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_DATA_RECEPTION_COMPLETE_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
475 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_FRAME_ERROR_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
476 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_BUFFER_OVERRUN_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
481 Linflexd_Uart_Ip_SetInterruptMode(Base, LINFLEXD_TIMEOUT_INT, FALSE); in Linflexd_Uart_Ip_Deinit()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip_HwAccess.h141 return (((Base->MCR & eMIOS_MCR_FRZ_MASK) >> eMIOS_MCR_FRZ_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDebugMode()
166 …DIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE; in Emios_Pwm_Ip_GetOutputUpdate()
201 … & (uint32)((uint32)eMIOS_UCDIS_UCDIS0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE; in Emios_Pwm_Ip_GetChannelEnable()
282 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetFreezeEnable()
296 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetOutDisable()
325 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetPrescalerEnable()
343 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetDMARequest()
358 return (((Base->CH.UC[Channel].C & eMIOS_C_DMA_MASK) >> eMIOS_C_DMA_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetDMARequest()
373 uint8 ValueConvert = (Value == FALSE)? 0U : 1U; in Emios_Pwm_Ip_SetInterruptRequest()
388 return (((Base->CH.UC[Channel].C & eMIOS_C_FEN_MASK) >> eMIOS_C_FEN_SHIFT) == 0U)? FALSE : TRUE; in Emios_Pwm_Ip_GetInterruptRequest()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/Spi/src/
DSpi_Ip.c288 boolean ErrorFlag = (boolean)FALSE; in Spi_Ip_TransferProcess()
312 if((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_TransferProcess()
346 if(((boolean)TRUE == ErrorFlag) || ((boolean)FALSE == State->KeepCs)) in Spi_Ip_TransferProcess()
637 boolean ClearCS = (boolean)FALSE; in Spi_Ip_DmaConfig()
638 boolean EnScatterGather = (boolean)FALSE; in Spi_Ip_DmaConfig()
650 if((boolean)FALSE == State->KeepCs) in Spi_Ip_DmaConfig()
675 if((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_DmaConfig()
689 EnScatterGather = (boolean)FALSE; in Spi_Ip_DmaConfig()
699 EnScatterGather = (boolean)FALSE; in Spi_Ip_DmaConfig()
832 if((boolean)FALSE == State->PhyUnitConfig->SlaveMode) in Spi_Ip_DmaConfig()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/src/
DOsIf_Timer_System.c289 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_Init()
331 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
343 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
385 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
397 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
440 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
452 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
489 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
501 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/src/
DOsIf_Timer_System.c307 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_Init()
354 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
366 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
415 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
427 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
469 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
481 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
519 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
531 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/src/
DOsIf_Timer_System.c307 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_Init()
354 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
366 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetCounter()
415 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
427 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_GetElapsed()
469 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
481 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_SetTimerFrequency()
519 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
531 OSIF_DEV_ASSERT(FALSE); in OsIf_Timer_System_MicrosToTicks()
/hal_nxp-3.6.0/s32/drivers/s32k3/Pwm/src/
DEmios_Pwm_Ip.c239 boolean Ret = FALSE; in Emios_Pwm_Ip_ValidateMode()
242 … (((Emios_Pwm_Ip_aChannelModes[Instance][(uint8)Mode] >> Channel) & 0x01UL) == 1UL) ? TRUE : FALSE; in Emios_Pwm_Ip_ValidateMode()
487 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
498 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
505 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
512 …ios_Pwm_Ip_aCheckEnableNotif[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] == 0U)? FALSE : TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwfmb()
553 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
570 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
583 Emios_Pwm_Ip_SetInterruptRequest(Base, Channel, FALSE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
596 …ios_Pwm_Ip_aCheckEnableNotif[eMios_Pwm_Ip_IndexInChState[Instance][Channel]] == 0U)? FALSE : TRUE); in Emios_Pwm_Ip_SetDutyCycleOpwfm()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h94 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrTxStatus()
116 return (0U == RegValue)? TRUE : FALSE; in Qspi_Ip_GetClrAhbStatus()
448 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetSlaveLockStatusA()
451 return FALSE; in Qspi_Ip_DLLGetSlaveLockStatusA()
465 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetLockStatusA()
468 return FALSE; in Qspi_Ip_DLLGetLockStatusA()
481 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_DLLGetErrorStatusA()
484 return FALSE; in Qspi_Ip_DLLGetErrorStatusA()
715 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_GetBusyStatus()
739 return (RegValue != 0U)? TRUE : FALSE; in Qspi_Ip_GetRxDataEvent()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/EthSwt_NETC/src/
DNetc_EthSwt_Ip.c153 static boolean MirrorConfigurationDone = FALSE;
632 return ((*ElapsedTimeInOut >= TimeoutTicks) ? TRUE : FALSE); in Netc_EthSwt_Ip_TimeoutExpired()
717 *FoundEntry = FALSE;
720 SearchCriteriaData.SearchActeData.ActivityFlag=FALSE;
723 SearchCriteriaData.SearchKeyeData.SearchMulticastMacAddr=FALSE;
1041 *PortEnable = FALSE;
1052 *PortEnable = FALSE;
1064 *PortEnable = FALSE;
1425 boolean MatchedEntryFound = FALSE;
1604 …MECAPE_MASK) >> NETC_ETHSWT_IP_FDBTABLE_CFGE_CONFIG_FIELD_TIMECAPE_SHIFT) != 0x0UL) ? TRUE : FALSE;
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Icu/src/
DWkpu_Ip.c495 FALSE); in Wkpu_Ip_DisableInterrupt()
502 FALSE); in Wkpu_Ip_DisableInterrupt()
733 FALSE); in Wkpu_Ip_SetActivationCondition()
741 FALSE); in Wkpu_Ip_SetActivationCondition()
755 FALSE); in Wkpu_Ip_SetActivationCondition()
761 FALSE); in Wkpu_Ip_SetActivationCondition()
802 boolean bstate = FALSE; in Wkpu_Ip_GetInputState()
867 Wkpu_Ip_u32ChState[Wkpu_Ip_IndexInChState[hwChannel]].notificationEnable = FALSE; in Wkpu_Ip_DisableNotification()
989 if (Wkpu_Ip_IsNMIConfigLock(base, coreShift) == FALSE) in Wkpu_Ip_DeinitNMI()
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcl/src/
DLcu_Ip_Irq.c131 boolean RetStatus = FALSE; in HwAcc_Lcu_GetLutIntEnable()
142 boolean RetStatus = FALSE; in HwAcc_Lcu_GetLutStatus()
162 boolean RetStatus = FALSE; in HwAcc_Lcu_GetForceIntEnable()
173 boolean RetStatus = FALSE; in HwAcc_Lcu_GetForceStatus()
DEmios_Mcl_Ip.c91 {(boolean)FALSE, (uint8)255}
328 if (Emios_Ip_axIpIsInitialized[Instance].instanceInitState == FALSE) in Emios_Mcl_Ip_Deinit()
354 Emios_Ip_axChState[Instance][CurrentChannel].channelInitState = FALSE; in Emios_Mcl_Ip_Deinit()
357 Emios_Ip_axIpIsInitialized[Instance].instanceInitState = FALSE; in Emios_Mcl_Ip_Deinit()
391 boolean Valid = FALSE; in Emios_Mcl_Ip_ValidateChannel()
460 boolean Valid = FALSE; in Emios_Mcl_Ip_ValidateMultiCoreInit()
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/include/
DPlatformTypes.h152 #ifndef FALSE
158 #define FALSE false macro
164 #define FALSE 0
/hal_nxp-3.6.0/s32/drivers/s32k1/BaseNXP/include/
DPlatformTypes.h152 #ifndef FALSE
158 #define FALSE false macro
164 #define FALSE 0

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