Searched refs:ExpectedFifoWrites (Results 1 – 2 of 2) sorted by relevance
331 if (State->CurrentTxFifoSlot > (State->ExpectedFifoWrites - State->TxIndex)) in Spi_Ip_TransferProcess()333 State->CurrentTxFifoSlot = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_TransferProcess()451 State->TxIndex = State->ExpectedFifoWrites; in Spi_Ip_TxDmaTcdSGConfig()478 DmaTcdList[5u].Value = State->ExpectedFifoWrites; /* iteration count */ in Spi_Ip_TxDmaTcdSGConfig()634 uint16 NumberDmaIterWrite = State->ExpectedFifoWrites; in Spi_Ip_DmaConfig()852 uint16 NumberDmaIterWrite = State->ExpectedFifoWrites - State->TxIndex; in Spi_Ip_DmaContinueTransfer()1180 State->ExpectedFifoWrites = Length; in Spi_Ip_UpdateTxRxCounter()1184 State->ExpectedFifoWrites = Length/2u; in Spi_Ip_UpdateTxRxCounter()1186 State->ExpectedFifoReads = State->ExpectedFifoWrites; in Spi_Ip_UpdateTxRxCounter()1189 State->ExpectedFifoReads = State->ExpectedFifoWrites/2u; in Spi_Ip_UpdateTxRxCounter()[all …]
231 …uint16 ExpectedFifoWrites; /**< Store number of frames needs to be transmit for current transfer… member
