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Searched refs:Enable (Results 1 – 25 of 48) sorted by relevance

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/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/src/
DClock_Ip_Gate.c207 Config.Enable = 0U; in Clock_Ip_ClockUpdateSimLPO1KEnable()
211 Config.Enable = 1U; in Clock_Ip_ClockUpdateSimLPO1KEnable()
239 Config.Enable = 0U; in Clock_Ip_ClockUpdateSimLPO32KEnable()
243 Config.Enable = 1U; in Clock_Ip_ClockUpdateSimLPO32KEnable()
271 Config.Enable = 0U; in Clock_Ip_ClockUpdateSimClkoutEnable()
275 Config.Enable = 1U; in Clock_Ip_ClockUpdateSimClkoutEnable()
303 Config.Enable = 0U; in Clock_Ip_ClockUpdatePccCgcEnable()
307 Config.Enable = 1U; in Clock_Ip_ClockUpdatePccCgcEnable()
337 Config.Enable = 0U; in Clock_Ip_ClockUpdateSimGate()
341 Config.Enable = 1U; in Clock_Ip_ClockUpdateSimGate()
[all …]
DClock_Ip_Specific.c346 if (Clock_Ip_apConfig->Ircoscs[Index].Enable == FALSE) in DisableSafeClock()
399 … SimLpoValue |= ((uint32)(Config->Gates[Index].Enable) << SIM_LPOCLKS_LPO32KCLKEN_SHIFT); in SetSimLpoclksRegister_TrustedCall()
405 SimLpoValue |= ((uint32)(Config->Gates[Index].Enable) << SIM_LPOCLKS_LPO1KCLKEN_SHIFT); in SetSimLpoclksRegister_TrustedCall()
552 …FircConfiguration.Enable = (uint16)(IP_SCG->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) >> SCG_FIRCCSR_FIRC… in getFircConfig()
586 …SoscConfiguration.Enable = (uint16)(IP_SCG->SOSCCSR & SCG_SOSCCSR_SOSCEN_MASK) >> SCG_SOSCCSR_SOSC… in getSoscConfig()
619 …SpllConfiguration.Enable = (uint16)(IP_SCG->SPLLCSR & SCG_SPLLCSR_SPLLEN_MASK) >> SCG_SPLLCSR_SPLL… in getSpllConfig()
657 …CmuConfiguration.Enable = (Clock_Ip_apxCmu[0U]->GCR & CMU_FC_GCR_FCE_MASK) >> CMU_FC_GCR_FCE_SHIFT; in getCmuFircConfig()
664 …CmuConfiguration.Enable = (Clock_Ip_apxCmu[1U]->GCR & CMU_FC_GCR_FCE_MASK) >> CMU_FC_GCR_FCE_SHIFT; in getCmuFircConfig()
1068 Clock_Ip_pxFircClock->Enable(Clock_Ip_pxFircConfig); in Clock_Ip_ClockPowerModeChangeNotification()
1070 Clock_Ip_pxSoscClock->Enable(Clock_Ip_pxSoscConfig); /* Enable */ in Clock_Ip_ClockPowerModeChangeNotification()
[all …]
DClock_Ip_IntOsc.c463 SircConfig.Enable = 1U; /* enabled */ in Clock_Ip_SetSirc_TrustedCall()
470 SircConfig.Enable = Config->Enable; in Clock_Ip_SetSirc_TrustedCall()
484 if (1U == SircConfig.Enable) in Clock_Ip_SetSirc_TrustedCall()
565 if (1U == Config->Enable) in Clock_Ip_EnableSircVlp_TrustedCall()
595 if (1U == Config->Enable) in Clock_Ip_EnableSircStop_TrustedCall()
647 if (1U == Config->Enable) in Clock_Ip_SetFirc_TrustedCall()
687 if (1U == Config->Enable) in Clock_Ip_SetFirc_TrustedCall()
720 if (1U == Config->Enable) in Clock_Ip_EnableFirc_TrustedCall()
DClock_Ip_Monitor.c306 …if (HashCmu[Index] != ((((uint32)Config->Enable) ^ ((uint32)Config->Interrupt) ^ ((uint32)Config->… in Clock_Ip_SetCmuFcFceRefCntLfrefHfref()
308 …HashCmu[Index] = ((((uint32)Config->Enable) ^ ((uint32)Config->Interrupt) ^ ((uint32)Config->Monit… in Clock_Ip_SetCmuFcFceRefCntLfrefHfref()
391 if (Config->Enable != 0U) in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
/hal_nxp-3.6.0/s32/drivers/s32ze/Uart/include/
DLinflexd_Uart_Ip_HwAccess.h303 static inline void Linflexd_Uart_Ip_EnableMonitorIdleState(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_EnableMonitorIdleState() argument
305 Base->UARTCR |= LINFLEXD_UARTCR_MIS(Enable); in Linflexd_Uart_Ip_EnableMonitorIdleState()
319 static inline void Linflexd_Uart_Ip_EnableTimerReset(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_EnableTimerReset() argument
321 Base->UARTCR |= LINFLEXD_UARTCR_DTU_PCETX(Enable); in Linflexd_Uart_Ip_EnableTimerReset()
382 static inline void Linflexd_Uart_Ip_SetParityControl(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_SetParityControl() argument
388 RegValTemp |= LINFLEXD_UARTCR_PCE(Enable ? 1UL : 0UL); in Linflexd_Uart_Ip_SetParityControl()
710 static inline void Linflexd_Uart_Ip_SetDmaTxEnable(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_SetDmaTxEnable() argument
712 Base->DMATXE = LINFLEXD_DMATXE_DTE0(Enable ? 1UL : 0UL); in Linflexd_Uart_Ip_SetDmaTxEnable()
723 static inline void Linflexd_Uart_Ip_SetDmaRxEnable(LINFLEXD_Type *Base, boolean Enable) in Linflexd_Uart_Ip_SetDmaRxEnable() argument
725 Base->DMARXE = LINFLEXD_DMARXE_DRE0(Enable ? 1UL : 0UL); in Linflexd_Uart_Ip_SetDmaRxEnable()
/hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/include/
DGmac_Ip.h530 boolean Enable);
541 boolean Enable);
558 boolean Enable);
575 boolean Enable);
594 boolean Enable);
651 boolean Enable);
666 boolean Enable);
733 boolean Enable,
/hal_nxp-3.6.0/s32/drivers/s32k3/Fls/include/
DQspi_Ip_HwAccess.h275 boolean Enable in Qspi_Ip_DLLSlaveEnA() argument
281 RegValue |= QuadSPI_DLLCRA_SLV_EN(Enable? 1U : 0U); in Qspi_Ip_DLLSlaveEnA()
289 boolean Enable in Qspi_Ip_DLLSlaveUpdateA() argument
295 RegValue |= QuadSPI_DLLCRA_SLV_UPD(Enable? 1U : 0U); in Qspi_Ip_DLLSlaveUpdateA()
304 boolean Enable in Qspi_Ip_DLLEnableA() argument
310 RegValue |= QuadSPI_DLLCRA_DLLEN(Enable? 1U : 0U); in Qspi_Ip_DLLEnableA()
319 boolean Enable in Qspi_Ip_DLLSlaveBypassA() argument
325 RegValue |= QuadSPI_DLLCRA_SLV_DLL_BYPASS(Enable? 1U : 0U); in Qspi_Ip_DLLSlaveBypassA()
335 boolean Enable in Qspi_Ip_DLLSlaveAutoUpdateA() argument
341 RegValue |= QuadSPI_DLLCRA_SLAVE_AUTO_UPDT(Enable? 1U : 0U); in Qspi_Ip_DLLSlaveAutoUpdateA()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_ExtOsc.c181 if (Config->Enable != 0U) in Clock_Ip_SetFxoscOsconBypEocvGmSel()
225 if (Config->Enable != 0U) in Clock_Ip_CompleteFxoscOsconBypEocvGmSel()
284 if (1U == Config->Enable) in Clock_Ip_EnableFxoscOsconBypEocvGmSel()
324 if (Config->Enable != 0U) in Clock_Ip_SetSxoscOsconEocv()
355 if (Config->Enable != 0U) in Clock_Ip_CompleteSxoscOsconEocv()
DClock_Ip_Gate.c155 if (Config->Enable != 0U) in Clock_Ip_ClockSetGateMcMePartitionCollectionClockRequest()
236 Config.Enable = 0U; in Clock_Ip_ClockUpdateGateMcMePartitionCollectionClockRequest()
240 Config.Enable = 1U; in Clock_Ip_ClockUpdateGateMcMePartitionCollectionClockRequest()
DClock_Ip_Pll.c193 if (Config->Enable != 0U) in Clock_Ip_SetPllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
275 if (1U == Config->Enable) in Clock_Ip_EnablePllRdivMfiMfnOdiv2SdmenSsscgbypSpreadctlStepnoStepsize()
332 if (Config->Enable != 0U) in Clock_Ip_SetPllRdivMfiMfnOdiv2Sdmen()
394 if (1U == Config->Enable) in Clock_Ip_EnablePllRdivMfiMfnOdiv2Sdmen()
DClock_Ip_Specific.c508 FircConfig.Enable = TRUE; in EnableFircInStandbyMode()
509 Clock_Ip_pxFircStdbyClock->Enable(&FircConfig); in EnableFircInStandbyMode()
522 SircConfig.Enable = TRUE; in EnableSircInStandbyMode()
523 Clock_Ip_pxSircStdbyClock->Enable(&SircConfig); in EnableSircInStandbyMode()
DClock_Ip_Monitor.c338 …if (HashCmu[Index] != ((((uint32)Config->Enable) ^ ((uint32)Config->Interrupt) ^ ((uint32)Config->… in Clock_Ip_SetCmuFcFceRefCntLfrefHfref()
340 …HashCmu[Index] = ((((uint32)Config->Enable) ^ ((uint32)Config->Interrupt) ^ ((uint32)Config->Monit… in Clock_Ip_SetCmuFcFceRefCntLfrefHfref()
423 if (Config->Enable != 0U) in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
DClock_Ip_IntOsc.c147 if (Config->Enable != 0U) in Clock_Ip_SetFircStdby()
177 if (Config->Enable != 0U) in Clock_Ip_SetSircStdby()
/hal_nxp-3.6.0/s32/drivers/s32ze/Eth_NETC/include/
DNetc_Eth_Ip.h141 …_Ip_EnableCreditBasedShaper(const uint8 ctrlIndex, const uint8 TrafficClass, const boolean Enable);
563 …StatusType Netc_Eth_Ip_ConfigPortTimeGateScheduling( const uint8 CtrlIndex, const boolean Enable );
647 …mentFrame(const uint8 CtrlIdx, uint16 BuffIdx, uint8 SwitchIndex, uint8 PortIndex, boolean Enable);
655 …Type Netc_Eth_Ip_TimestampTxFrame(const uint8 CtrlIdx, const uint16 BuffIdx, const boolean Enable);
752 Std_ReturnType Netc_Eth_Ip_EnableIngressPortFiltering(const uint8 CtrlIndex, boolean Enable );
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Gate.c151 if (Config->Enable != 0U) in Clock_Ip_ClockSetGateClockControlEnableGprPctl()
175 Config.Enable = 0U; in Clock_Ip_ClockUpdateGateClockControlEnableGprPctl()
179 Config.Enable = 1U; in Clock_Ip_ClockUpdateGateClockControlEnableGprPctl()
DClock_Ip_Pll.c201 if (Config->Enable != 0U) in Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
291 if (1U == Config->Enable) in Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
345 if (Config->Enable != 0U) in Clock_Ip_SetPlldigRdivMfiMfnSdmen()
426 if (1U == Config->Enable) in Clock_Ip_EnablePlldigRdivMfiMfnSdmen()
530 if (1U == Config->Enable) in Clock_Ip_SetLfastPLL()
642 if (1U == Config->Enable) in Clock_Ip_EnableLfastPLL()
DClock_Ip_ExtOsc.c174 if (Config->Enable != 0U) in Clock_Ip_SetFxoscOsconBypEocvGmSel()
218 if (Config->Enable != 0U) in Clock_Ip_CompleteFxoscOsconBypEocvGmSel()
277 if (1U == Config->Enable) in Clock_Ip_EnableFxoscOsconBypEocvGmSel()
DClock_Ip_Monitor.c306 …if (HashCmu[Index] != ((((uint32)Config->Enable) ^ ((uint32)Config->Interrupt) ^ ((uint32)Config->… in Clock_Ip_SetCmuFcFceRefCntLfrefHfref()
308 …HashCmu[Index] = ((((uint32)Config->Enable) ^ ((uint32)Config->Interrupt) ^ ((uint32)Config->Monit… in Clock_Ip_SetCmuFcFceRefCntLfrefHfref()
411 if (Config->Enable != 0U) in Clock_Ip_EnableCmuFcFceRefCntLfrefHfref()
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/include/
DClock_Ip_Private.h293 intOscEnableCallback Enable; member
309 extOscEnableCallback Enable; member
352 pllEnableCallback Enable; member
384 clockMonitorEnableCallback Enable; member
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Private.h293 intOscEnableCallback Enable; member
309 extOscEnableCallback Enable; member
352 pllEnableCallback Enable; member
384 clockMonitorEnableCallback Enable; member
/hal_nxp-3.6.0/s32/drivers/s32k1/Mcu/include/
DClock_Ip_Private.h293 intOscEnableCallback Enable; member
309 extOscEnableCallback Enable; member
352 pllEnableCallback Enable; member
384 clockMonitorEnableCallback Enable; member
/hal_nxp-3.6.0/s32/drivers/s32ze/EthSwt_NETC/include/
DNetc_EthSwt_Ip.h407 …e Netc_EthSwt_Ip_EnableVlan( uint8 SwitchIdx, uint8 SwitchPortIdx, uint16 VlanId, boolean Enable );
883 … Netc_EthSwt_Ip_EnableIngressPortFiltering( uint8 SwitchIdx, uint8 SwitchPortIdx, boolean Enable );
979 …Shaper(uint8 SwitchIdx, const uint8 SwitchPortIdx, const uint8 TrafficClass, const boolean Enable);
1010 boolean Enable
/hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip.c2354 boolean Enable) in Gmac_Ip_SetBroadcastForwardAll() argument
2362 if (Enable) in Gmac_Ip_SetBroadcastForwardAll()
2384 boolean Enable) in Gmac_Ip_SetMulticastForwardAll() argument
2392 if (Enable) in Gmac_Ip_SetMulticastForwardAll()
2416 boolean Enable) in Gmac_Ip_SetUnicastHashFilter() argument
2424 if (Enable) in Gmac_Ip_SetUnicastHashFilter()
2445 boolean Enable) in Gmac_Ip_SetMulticastHashFilter() argument
2453 if (Enable) in Gmac_Ip_SetMulticastHashFilter()
2474 boolean Enable) in Gmac_Ip_SetHashOrPerfectFilter() argument
2482 if (Enable) in Gmac_Ip_SetHashOrPerfectFilter()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/Can_CANEXCEL/include/
DCanEXCEL_Ip_HwAccess.h653 static inline void CanXL_SetXLErrorResponse(CANXL_SIC_Type * Base, boolean Enable) in CanXL_SetXLErrorResponse() argument
655 …Base->BCFG2 = (Base->BCFG2 & ~CANXL_SIC_BCFG2_XLER_MASK) | CANXL_SIC_BCFG2_XLER(Enable ? 1UL : 0UL… in CanXL_SetXLErrorResponse()
663 static inline void CanXL_SetPwmModeEnable(CANXL_SIC_Type * Base, boolean Enable) in CanXL_SetPwmModeEnable() argument
665 …Base->BCFG2 = (Base->BCFG2 & ~CANXL_SIC_BCFG2_TMSE_MASK) | CANXL_SIC_BCFG2_TMSE(Enable ? 1UL : 0UL… in CanXL_SetPwmModeEnable()
/hal_nxp-3.6.0/s32/drivers/s32k3/Pwm/include/
DEmios_Pwm_Ip.h150 boolean Enable);
163 boolean Enable);

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