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/hal_nxp-3.6.0/mcux/mcux-sdk/middleware/issdk/tools/Serial_To_MQTT/
DCloudBridgeNXPDemo.py20 from Tkconstants import END, NORMAL, DISABLED, E, W, N, S
355 …eground='black', bg='orange').grid(row=0, column=0, rowspan=2, columnspan=17, sticky=W + E + N + S)
356 …t, image=nxpLogo, bg='white').grid(row=0, column=17, rowspan=2, columnspan=1, sticky=W + E + N + S)
359 textBox.grid(row=2, column=0, rowspan=4, columnspan=18, sticky=W + E + N + S)
361 …ow', state=DISABLED, anchor=W).grid(row=6, column=0, rowspan=2, columnspan=1, sticky=W + E + N + S)
363 userNameEntry.grid(row=6, column=1, rowspan=2, columnspan=8, sticky=W + E + N + S)
365 …ow', state=DISABLED, anchor=W).grid(row=6, column=9, rowspan=2, columnspan=1, sticky=W + E + N + S)
367 passwordEntry.grid(row=6, column=10, rowspan=2, columnspan=8, sticky=W + E + N + S)
370 …ow', state=DISABLED, anchor=W).grid(row=8, column=9, rowspan=2, columnspan=1, sticky=W + E + N + S)
372 clientIdEntry.grid(row=8, column=10, rowspan=2, columnspan=8, sticky=W + E + N + S)
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/cau3/
Dfsl_cau3.h895 const uint8_t *E,
1145 const uint8_t *E,
1180 const uint8_t *E,
1213 const uint8_t *E,
Dfsl_cau3.c804 static status_t cau3_pkha_clear_regabne(CAU3_Type *base, bool A, bool B, bool N, bool E);
2357 static status_t cau3_pkha_clear_regabne(CAU3_Type *base, bool A, bool B, bool N, bool E) in cau3_pkha_clear_regabne() argument
2377 if (E) in cau3_pkha_clear_regabne()
2515 const uint8_t *E, in cau3_pkha_init_data() argument
2540 …lear_regabne(base, (bool)(uintptr_t)A, (bool)(uintptr_t)B, (bool)(uintptr_t)N, (bool)(uintptr_t)E); in cau3_pkha_init_data()
2574 if (E != NULL) in cau3_pkha_init_data()
2576 (void)cau3_pkha_write_reg(base, kCAU3_PKHA_RegE, 0, E, sizeE); in cau3_pkha_init_data()
3307 const uint8_t *E, in CAU3_PKHA_ModExp() argument
3341 cau3_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, E, sizeE); in CAU3_PKHA_ModExp()
3971 const uint8_t *E, in CAU3_PKHA_ECC_PointMul() argument
[all …]
/hal_nxp-3.6.0/s32/
DREADME54 Patch List for S32Z/E:
64 for S32Z/E.
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/ltc/
Dfsl_ltc.c178 static status_t ltc_pkha_clear_regabne(LTC_Type *base, bool A, bool B, bool N, bool E);
3823 static status_t ltc_pkha_clear_regabne(LTC_Type *base, bool A, bool B, bool N, bool E) in ltc_pkha_clear_regabne() argument
3843 if (E) in ltc_pkha_clear_regabne()
3978 const uint8_t *E, in ltc_pkha_init_data() argument
4003 …lear_regabne(base, (bool)(uintptr_t)A, (bool)(uintptr_t)B, (bool)(uintptr_t)N, (bool)(uintptr_t)E); in ltc_pkha_init_data()
4037 if (NULL != E) in ltc_pkha_init_data()
4039 (void)ltc_pkha_write_reg(base, kLTC_PKHA_RegE, 0, E, sizeE); in ltc_pkha_init_data()
4689 const uint8_t *E, in LTC_PKHA_ModExp() argument
4714 ltc_pkha_init_data(base, A, sizeA, NULL, 0, N, sizeN, E, sizeE); in LTC_PKHA_ModExp()
5136 const uint8_t *E, in LTC_PKHA_ECC_PointMul() argument
[all …]
Dfsl_ltc.h1375 const uint8_t *E,
1580 const uint8_t *E,
/hal_nxp-3.6.0/mcux/mcux-sdk/drivers/caam/
Dfsl_caam.c7294 const uint8_t *E, in caam_pkha_algorithm_operation_command() argument
7347 if ((E != NULL) && (sizeE != 0U)) in caam_pkha_algorithm_operation_command()
7351 DESC_SET_ADDR(descriptor[10], E); in caam_pkha_algorithm_operation_command()
7423 const uint8_t *E, in caam_pkha_ecc_algorithm_operation_command() argument
7501 if ((E != NULL) && (sizeE != 0U)) in caam_pkha_ecc_algorithm_operation_command()
7504 DESC_SET_ADDR(descriptor[20], E); in caam_pkha_ecc_algorithm_operation_command()
8095 const uint8_t *E,
8110 const uint8_t *E, in CAAM_PKHA_ModExpNonBlocking() argument
8135 …m_pkha_algorithm_operation_command(base, handle, descriptor, A, sizeA, NULL, 0, N, sizeN, E, sizeE, in CAAM_PKHA_ModExpNonBlocking()
8166 const uint8_t *E, in CAAM_PKHA_ModExp() argument
[all …]
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX6/gcc/
DMIMX8DX6xxxxx_cm4_ram.ld7 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX2/gcc/
DMIMX8DX2xxxxx_cm4_ram.ld7 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC55S36/gcc/
DLPC55S36_flash.ld36 POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x00000000; /* SRAM E(16K) reserved for…
DLPC55S36_ram.ld36 POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x0; /* SRAM E(16K) reserved …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX1/gcc/
DMIMX8DX1xxxxx_cm4_ram.ld7 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QM6/gcc/
DMIMX8QM6xxxFF_cm4_core0_ram.ld5 ** Reference manual: IMX8QMRM, Rev. E, Jun. 2018
DMIMX8QM6xxxFF_cm4_core1_ram.ld5 ** Reference manual: IMX8QMRM, Rev. E, Jun. 2018
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX4/gcc/
DMIMX8QX4xxxxx_cm4_ram.ld5 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX3/gcc/
DMIMX8QX3xxxxx_cm4_ram.ld5 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX3/gcc/
DMIMX8DX3xxxxx_cm4_ram.ld5 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/LPC5536/gcc/
DLPC5536_ram.ld37 POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x0; /* SRAM E(16K) reserved …
DLPC5536_flash.ld37 POWERQUAD_RAMSIZE = DEFINED(__powerquad__) ? 0x00004000 : 0x00000000; /* SRAM E(16K) reserved for…
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX2/gcc/
DMIMX8QX2xxxxx_cm4_ram.ld7 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX1/gcc/
DMIMX8QX1xxxxx_cm4_ram.ld7 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX5/gcc/
DMIMX8DX5xxxxx_cm4_ram.ld7 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8DX4/gcc/
DMIMX8DX4xxxxx_cm4_ram.ld5 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8UX6/gcc/
DMIMX8UX6xxxxx_cm4_ram.ld8 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMX8QX5/gcc/
DMIMX8QX5xxxxx_cm4_ram.ld7 ** Reference manual: IMX8DQXPRM, Rev. E, 6/2019

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