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Searched refs:DMA_DCHPRI31_CHPRI_MASK (Results 1 – 25 of 33) sorted by relevance

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/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV56F24/
DMKV56F24.h10771 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
10775 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h8189 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
8191 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV58F24/
DMKV58F24.h10775 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
10779 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h8183 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
8185 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK26F18/
DMK26F18.h10617 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
10621 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h8251 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
8253 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h8253 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
8255 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h10668 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
10672 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK66F18/
DMK66F18.h10668 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
10672 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h5508 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
5512 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h5509 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
5513 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h13932 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
13936 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h15496 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
15500 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h15512 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
15516 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h16544 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
16548 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h17780 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
17784 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h17782 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
17786 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h17329 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
17333 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h18149 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
18153 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h18935 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
18939 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h19009 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
19013 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h30125 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
30129 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
DMIMXRT1165_cm4.h30122 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
30126 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm7.h30443 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
30447 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h32129 #define DMA_DCHPRI31_CHPRI_MASK (0xFU) macro
32133 … (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)

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