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Searched refs:DMA_CH1_STATUS (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k3/Eth_GMAC/src/
DGmac_Ip_Irq.c183 if ((IP_GMAC_0->DMA_CH1_STATUS & GMAC_DMA_CH1_STATUS_TI_MASK) != 0U) in ISR()
218 if ((IP_GMAC_0->DMA_CH1_STATUS & GMAC_DMA_CH1_STATUS_RI_MASK) != 0U) in ISR()
325 if ((IP_GMAC_1->DMA_CH1_STATUS & GMAC_DMA_CH1_STATUS_TI_MASK) != 0U) in ISR()
359 if ((IP_GMAC_1->DMA_CH1_STATUS & GMAC_DMA_CH1_STATUS_RI_MASK) != 0U) in ISR()
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_EMAC.h426 __IO uint32_t DMA_CH1_STATUS; /**< DMA Channel 1 Status, offset: 0x11E0 */ member