1 /*
2  * NOTE: File generated by lpc_cfg_utils.py
3  * from LPC55S36JBD100/signal_configuration.xml
4  *
5  * Copyright 2022 NXP
6  * SPDX-License-Identifier: Apache-2.0
7  */
8 
9 #ifndef _ZEPHYR_DTS_BINDING_LPC55S36JBD100_
10 #define _ZEPHYR_DTS_BINDING_LPC55S36JBD100_
11 
12 #define IOCON_MUX(offset, type, mux)		\
13 	(((offset & 0xFFF) << 20) |		\
14 	(((type) & 0x3) << 18) |		\
15 	(((mux) & 0xF) << 0))
16 
17 #define IOCON_TYPE_D 0x0
18 #define IOCON_TYPE_I 0x1
19 #define IOCON_TYPE_A 0x2
20 
21 #define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
22 #define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
23 #define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
24 #define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
25 #define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
26 #define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
27 #define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
28 #define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
29 #define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */
30 #define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
31 #define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
32 #define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
33 #define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
34 #define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
35 #define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
36 #define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
37 #define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
38 #define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
39 #define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
40 #define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
41 #define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
42 #define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
43 #define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
44 #define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
45 #define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
46 #define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
47 #define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
48 #define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
49 #define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
50 #define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
51 #define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
52 #define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
53 #define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
54 #define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
55 #define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
56 #define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
57 #define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
58 #define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
59 #define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
60 #define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
61 #define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
62 #define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
63 #define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
64 #define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
65 #define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
66 #define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
67 #define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
68 #define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
69 #define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
70 #define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
71 #define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
72 #define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
73 #define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
74 #define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
75 #define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
76 #define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
77 #define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
78 #define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
79 #define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
80 #define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
81 #define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
82 #define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
83 #define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
84 #define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
85 #define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
86 #define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
87 #define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
88 #define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
89 #define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
90 #define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
91 #define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
92 #define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */
93 #define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
94 #define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
95 #define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
96 #define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
97 #define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
98 #define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */
99 #define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
100 #define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
101 #define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
102 #define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
103 #define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
104 #define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
105 #define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
106 #define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
107 #define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
108 #define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
109 #define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */
110 #define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
111 #define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
112 #define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
113 #define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
114 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
115 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
116 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
117 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
118 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
119 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
120 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
121 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
122 #define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */
123 #define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
124 #define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
125 #define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
126 #define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
127 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
128 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
129 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
130 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
131 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
132 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
133 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
134 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */
135 #define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
136 #define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
137 #define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
138 #define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
139 #define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
140 #define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
141 #define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */
142 #define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */
143 #define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */
144 #define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */
145 #define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */
146 #define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
147 #define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
148 #define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
149 #define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
150 #define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
151 #define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
152 #define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
153 #define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
154 #define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
155 #define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */
156 #define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */
157 #define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
158 #define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
159 #define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
160 #define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
161 #define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
162 #define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
163 #define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
164 #define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
165 #define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
166 #define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
167 #define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
168 #define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
169 #define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
170 #define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
171 #define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
172 #define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
173 #define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
174 #define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
175 #define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
176 #define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
177 #define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */
178 #define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
179 #define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
180 #define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
181 #define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
182 #define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
183 #define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
184 #define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
185 #define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
186 #define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
187 #define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
188 #define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
189 #define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
190 #define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
191 #define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
192 #define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
193 #define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
194 #define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
195 #define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
196 #define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
197 #define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
198 #define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
199 #define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
200 #define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
201 #define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
202 #define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
203 #define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
204 #define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
205 #define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
206 #define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
207 #define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
208 #define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
209 #define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
210 #define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
211 #define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
212 #define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
213 #define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
214 #define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
215 #define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
216 #define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
217 #define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
218 #define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
219 #define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
220 #define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
221 #define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
222 #define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
223 #define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
224 #define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
225 #define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
226 #define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
227 #define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
228 #define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
229 #define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
230 #define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
231 #define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
232 #define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
233 #define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
234 #define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
235 #define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
236 #define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
237 #define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
238 #define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
239 #define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
240 #define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */
241 #define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */
242 #define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
243 #define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
244 #define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
245 #define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
246 #define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
247 #define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
248 #define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
249 #define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
250 #define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
251 #define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */
252 #define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
253 #define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
254 #define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
255 #define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
256 #define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
257 #define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
258 #define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */
259 #define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */
260 #define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */
261 #define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */
262 #define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
263 #define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
264 #define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
265 #define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
266 #define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
267 #define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
268 #define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
269 #define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
270 #define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */
271 #define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */
272 #define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
273 #define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
274 #define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
275 #define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
276 #define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
277 #define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
278 #define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
279 #define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
280 #define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
281 #define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
282 #define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
283 #define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
284 #define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
285 #define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
286 #define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
287 #define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
288 #define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
289 #define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
290 #define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
291 #define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
292 #define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */
293 #define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
294 #define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
295 #define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
296 #define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
297 #define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
298 #define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
299 #define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
300 #define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
301 #define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
302 #define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
303 #define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
304 #define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
305 #define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
306 #define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
307 #define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
308 #define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
309 #define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
310 #define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
311 #define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
312 #define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
313 #define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
314 #define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
315 #define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
316 #define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
317 #define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
318 #define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
319 #define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
320 #define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
321 #define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
322 #define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
323 #define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
324 #define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
325 #define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
326 #define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
327 #define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
328 #define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
329 #define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
330 #define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
331 #define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
332 #define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
333 #define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
334 #define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
335 #define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
336 #define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
337 #define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
338 #define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
339 #define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
340 #define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
341 #define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
342 #define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
343 #define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
344 #define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
345 #define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
346 #define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
347 #define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
348 #define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
349 #define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
350 #define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
351 #define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
352 #define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
353 #define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
354 #define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
355 #define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
356 #define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
357 #define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
358 #define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
359 #define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
360 #define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */
361 #define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */
362 #define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
363 #define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
364 #define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
365 #define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
366 #define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
367 #define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
368 #define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
369 #define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
370 #define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
371 #define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */
372 #define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */
373 #define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
374 #define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
375 #define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
376 #define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
377 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
378 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
379 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
380 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
381 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
382 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
383 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
384 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
385 #define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
386 #define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
387 #define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
388 #define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
389 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
390 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
391 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
392 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
393 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
394 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
395 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
396 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */
397 #define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
398 #define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
399 #define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
400 #define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
401 #define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
402 #define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
403 #define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */
404 #define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */
405 #define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */
406 #define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */
407 #define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */
408 #define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
409 #define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
410 #define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
411 #define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
412 #define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
413 #define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
414 #define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
415 #define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
416 #define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */
417 #define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
418 #define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
419 #define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
420 #define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
421 #define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
422 #define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
423 #define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
424 #define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
425 #define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
426 #define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
427 #define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
428 #define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
429 #define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
430 #define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
431 #define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
432 #define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
433 #define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
434 #define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
435 #define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
436 #define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
437 #define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
438 #define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
439 #define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
440 #define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
441 #define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
442 #define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
443 #define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
444 #define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
445 #define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
446 #define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
447 #define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
448 #define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
449 #define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
450 #define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
451 #define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
452 #define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
453 #define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
454 #define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
455 #define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
456 #define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
457 #define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
458 #define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
459 #define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
460 #define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
461 #define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
462 #define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
463 #define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
464 #define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
465 #define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
466 #define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
467 #define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
468 #define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
469 #define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
470 #define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
471 #define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
472 #define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
473 #define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
474 #define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
475 #define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
476 #define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
477 #define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
478 #define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
479 #define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */
480 #define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */
481 #define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
482 #define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
483 #define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
484 #define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
485 #define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
486 #define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
487 #define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
488 #define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
489 #define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
490 #define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */
491 #define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */
492 #define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
493 #define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
494 #define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
495 #define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
496 #define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
497 #define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
498 #define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */
499 #define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */
500 #define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */
501 #define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */
502 #define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */
503 #define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
504 #define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
505 #define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
506 #define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
507 #define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
508 #define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
509 #define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
510 #define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
511 #define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
512 #define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
513 #define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
514 #define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
515 #define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
516 #define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
517 #define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
518 #define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
519 #define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
520 #define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
521 #define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
522 #define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
523 #define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
524 #define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
525 #define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
526 #define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
527 #define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
528 #define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
529 #define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
530 #define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
531 #define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
532 #define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
533 #define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
534 #define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
535 #define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
536 #define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
537 #define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
538 #define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
539 #define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
540 #define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
541 #define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
542 #define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
543 #define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */
544 #define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
545 #define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
546 #define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
547 #define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
548 #define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
549 #define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
550 #define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
551 #define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
552 #define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
553 #define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
554 #define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
555 #define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
556 #define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
557 #define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
558 #define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
559 #define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
560 #define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
561 #define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
562 #define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
563 #define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
564 #define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */
565 #define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
566 #define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
567 #define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
568 #define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
569 #define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
570 #define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
571 #define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
572 #define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
573 #define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
574 #define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
575 #define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
576 #define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
577 #define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
578 #define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
579 #define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
580 #define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
581 #define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
582 #define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
583 #define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
584 #define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
585 #define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
586 #define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
587 #define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
588 #define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
589 #define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
590 #define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
591 #define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
592 #define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
593 #define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
594 #define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
595 #define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
596 #define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
597 #define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
598 #define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
599 #define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
600 #define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
601 #define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
602 #define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
603 #define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
604 #define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
605 #define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
606 #define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
607 #define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
608 #define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
609 #define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
610 #define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
611 #define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
612 #define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
613 #define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
614 #define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
615 #define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
616 #define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
617 #define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
618 #define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
619 #define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
620 #define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
621 #define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
622 #define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
623 #define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
624 #define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
625 #define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
626 #define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
627 #define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
628 #define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
629 #define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
630 #define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
631 #define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
632 #define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */
633 #define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */
634 #define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */
635 #define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */
636 #define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
637 #define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
638 #define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
639 #define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
640 #define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
641 #define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
642 #define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
643 #define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
644 #define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
645 #define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */
646 #define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */
647 #define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
648 #define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
649 #define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
650 #define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
651 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
652 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
653 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
654 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
655 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
656 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
657 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
658 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
659 #define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
660 #define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
661 #define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
662 #define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
663 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
664 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
665 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
666 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
667 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
668 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
669 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
670 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */
671 #define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
672 #define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
673 #define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
674 #define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
675 #define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
676 #define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
677 #define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */
678 #define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */
679 #define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */
680 #define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */
681 #define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
682 #define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
683 #define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
684 #define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
685 #define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
686 #define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
687 #define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
688 #define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
689 #define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */
690 #define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */
691 #define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
692 #define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
693 #define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
694 #define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
695 #define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
696 #define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
697 #define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
698 #define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
699 #define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
700 #define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
701 #define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
702 #define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
703 #define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
704 #define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
705 #define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
706 #define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
707 #define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
708 #define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
709 #define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
710 #define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
711 #define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
712 #define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
713 #define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
714 #define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
715 #define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
716 #define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
717 #define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
718 #define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
719 #define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
720 #define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
721 #define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
722 #define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
723 #define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
724 #define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
725 #define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
726 #define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
727 #define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
728 #define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
729 #define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
730 #define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
731 #define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
732 #define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
733 #define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
734 #define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
735 #define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
736 #define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
737 #define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
738 #define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
739 #define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
740 #define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
741 #define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
742 #define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
743 #define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
744 #define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
745 #define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
746 #define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
747 #define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
748 #define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
749 #define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
750 #define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
751 #define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
752 #define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
753 #define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
754 #define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
755 #define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
756 #define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
757 #define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
758 #define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */
759 #define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */
760 #define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
761 #define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */
762 #define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
763 #define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
764 #define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
765 #define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
766 #define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
767 #define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
768 #define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
769 #define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
770 #define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */
771 #define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */
772 #define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
773 #define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
774 #define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
775 #define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
776 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
777 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
778 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
779 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
780 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
781 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
782 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
783 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
784 #define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
785 #define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
786 #define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
787 #define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
788 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
789 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
790 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
791 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
792 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
793 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
794 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
795 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */
796 #define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
797 #define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
798 #define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
799 #define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
800 #define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
801 #define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
802 #define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */
803 #define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */
804 #define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */
805 #define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */
806 #define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
807 #define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
808 #define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
809 #define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
810 #define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
811 #define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
812 #define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
813 #define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
814 #define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
815 #define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
816 #define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
817 #define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
818 #define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
819 #define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
820 #define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
821 #define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
822 #define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
823 #define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
824 #define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
825 #define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
826 #define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
827 #define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
828 #define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
829 #define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
830 #define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
831 #define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
832 #define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
833 #define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
834 #define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
835 #define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
836 #define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
837 #define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
838 #define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
839 #define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
840 #define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
841 #define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
842 #define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
843 #define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
844 #define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
845 #define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
846 #define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
847 #define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
848 #define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
849 #define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
850 #define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
851 #define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
852 #define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
853 #define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
854 #define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
855 #define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
856 #define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
857 #define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
858 #define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
859 #define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
860 #define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
861 #define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
862 #define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
863 #define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
864 #define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
865 #define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
866 #define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */
867 #define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */
868 #define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
869 #define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
870 #define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
871 #define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
872 #define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
873 #define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
874 #define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
875 #define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
876 #define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
877 #define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
878 #define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
879 #define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
880 #define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
881 #define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
882 #define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
883 #define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
884 #define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
885 #define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
886 #define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
887 #define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
888 #define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
889 #define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
890 #define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
891 #define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
892 #define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
893 #define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
894 #define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
895 #define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
896 #define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
897 #define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
898 #define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
899 #define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
900 #define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
901 #define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
902 #define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
903 #define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
904 #define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
905 #define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
906 #define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
907 #define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
908 #define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
909 #define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
910 #define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
911 #define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
912 #define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
913 #define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
914 #define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
915 #define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
916 #define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
917 #define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
918 #define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
919 #define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
920 #define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
921 #define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
922 #define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
923 #define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
924 #define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
925 #define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
926 #define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
927 #define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
928 #define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
929 #define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
930 #define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
931 #define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
932 #define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
933 #define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
934 #define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
935 #define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */
936 #define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */
937 #define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */
938 #define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
939 #define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
940 #define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
941 #define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
942 #define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
943 #define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
944 #define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
945 #define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
946 #define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
947 #define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */
948 #define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */
949 #define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
950 #define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
951 #define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
952 #define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
953 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
954 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
955 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
956 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
957 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
958 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
959 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
960 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
961 #define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
962 #define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
963 #define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
964 #define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
965 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
966 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
967 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
968 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
969 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
970 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
971 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
972 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */
973 #define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
974 #define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
975 #define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
976 #define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
977 #define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
978 #define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
979 #define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */
980 #define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */
981 #define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */
982 #define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */
983 #define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */
984 #define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
985 #define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
986 #define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
987 #define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
988 #define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
989 #define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
990 #define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
991 #define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
992 #define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */
993 #define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */
994 #define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
995 #define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
996 #define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
997 #define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
998 #define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
999 #define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1000 #define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1001 #define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1002 #define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1003 #define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1004 #define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1005 #define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1006 #define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1007 #define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1008 #define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1009 #define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1010 #define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1011 #define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1012 #define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1013 #define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1014 #define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1015 #define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1016 #define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1017 #define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1018 #define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1019 #define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1020 #define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1021 #define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1022 #define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1023 #define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1024 #define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1025 #define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1026 #define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1027 #define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1028 #define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1029 #define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1030 #define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1031 #define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1032 #define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1033 #define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1034 #define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1035 #define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1036 #define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1037 #define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1038 #define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1039 #define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1040 #define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1041 #define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1042 #define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1043 #define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1044 #define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1045 #define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1046 #define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1047 #define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1048 #define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1049 #define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1050 #define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1051 #define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1052 #define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1053 #define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1054 #define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1055 #define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1056 #define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */
1057 #define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */
1058 #define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */
1059 #define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */
1060 #define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1061 #define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1062 #define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */
1063 #define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */
1064 #define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1065 #define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1066 #define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1067 #define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1068 #define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1069 #define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1070 #define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1071 #define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1072 #define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */
1073 #define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */
1074 #define QSPI_CS0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 9) /* PIO0_7 */
1075 #define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */
1076 #define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */
1077 #define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */
1078 #define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1079 #define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1080 #define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1081 #define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1082 #define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1083 #define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1084 #define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1085 #define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1086 #define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1087 #define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1088 #define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1089 #define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1090 #define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1091 #define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1092 #define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1093 #define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1094 #define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1095 #define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1096 #define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1097 #define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1098 #define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1099 #define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1100 #define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1101 #define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1102 #define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1103 #define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1104 #define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1105 #define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1106 #define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1107 #define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1108 #define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1109 #define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1110 #define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1111 #define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1112 #define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1113 #define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1114 #define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1115 #define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1116 #define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1117 #define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1118 #define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1119 #define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1120 #define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1121 #define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1122 #define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1123 #define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1124 #define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1125 #define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1126 #define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1127 #define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1128 #define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1129 #define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1130 #define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1131 #define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1132 #define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1133 #define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1134 #define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1135 #define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1136 #define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1137 #define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1138 #define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1139 #define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1140 #define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1141 #define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1142 #define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1143 #define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1144 #define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1145 #define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1146 #define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1147 #define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1148 #define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */
1149 #define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */
1150 #define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */
1151 #define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1152 #define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1153 #define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1154 #define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1155 #define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1156 #define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1157 #define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1158 #define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1159 #define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1160 #define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1161 #define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */
1162 #define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */
1163 #define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */
1164 #define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */
1165 #define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */
1166 #define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1167 #define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1168 #define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1169 #define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1170 #define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1171 #define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1172 #define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1173 #define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1174 #define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */
1175 #define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */
1176 #define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1177 #define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1178 #define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1179 #define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1180 #define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1181 #define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1182 #define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1183 #define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1184 #define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1185 #define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1186 #define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1187 #define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1188 #define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1189 #define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1190 #define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1191 #define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1192 #define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1193 #define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1194 #define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1195 #define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1196 #define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1197 #define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1198 #define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1199 #define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1200 #define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1201 #define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1202 #define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1203 #define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1204 #define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1205 #define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1206 #define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1207 #define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1208 #define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1209 #define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1210 #define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1211 #define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1212 #define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1213 #define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1214 #define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1215 #define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1216 #define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1217 #define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1218 #define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1219 #define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1220 #define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1221 #define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1222 #define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1223 #define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1224 #define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1225 #define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1226 #define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1227 #define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1228 #define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1229 #define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1230 #define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1231 #define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1232 #define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1233 #define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1234 #define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1235 #define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1236 #define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1237 #define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1238 #define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */
1239 #define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */
1240 #define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1241 #define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */
1242 #define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1243 #define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1244 #define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1245 #define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1246 #define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1247 #define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1248 #define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1249 #define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1250 #define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1251 #define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */
1252 #define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */
1253 #define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */
1254 #define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */
1255 #define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */
1256 #define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */
1257 #define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1258 #define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1259 #define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1260 #define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1261 #define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1262 #define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1263 #define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1264 #define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1265 #define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1266 #define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1267 #define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1268 #define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1269 #define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1270 #define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1271 #define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1272 #define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1273 #define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1274 #define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1275 #define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1276 #define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1277 #define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1278 #define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */
1279 #define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1280 #define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1281 #define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1282 #define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1283 #define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1284 #define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1285 #define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1286 #define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1287 #define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */
1288 #define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1289 #define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1290 #define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1291 #define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1292 #define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1293 #define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1294 #define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1295 #define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1296 #define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1297 #define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1298 #define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1299 #define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1300 #define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1301 #define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1302 #define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1303 #define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1304 #define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1305 #define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1306 #define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1307 #define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1308 #define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1309 #define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1310 #define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1311 #define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1312 #define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1313 #define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1314 #define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1315 #define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1316 #define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1317 #define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1318 #define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1319 #define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1320 #define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1321 #define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1322 #define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1323 #define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1324 #define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1325 #define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1326 #define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1327 #define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1328 #define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1329 #define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1330 #define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1331 #define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1332 #define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1333 #define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1334 #define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1335 #define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1336 #define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1337 #define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1338 #define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1339 #define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1340 #define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1341 #define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1342 #define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1343 #define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1344 #define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1345 #define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1346 #define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1347 #define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1348 #define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1349 #define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1350 #define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */
1351 #define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */
1352 #define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1353 #define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1354 #define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1355 #define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1356 #define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1357 #define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1358 #define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1359 #define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1360 #define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1361 #define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */
1362 #define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */
1363 #define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */
1364 #define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */
1365 #define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */
1366 #define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1367 #define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1368 #define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1369 #define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1370 #define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1371 #define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1372 #define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1373 #define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1374 #define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1375 #define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */
1376 #define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */
1377 #define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1378 #define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1379 #define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1380 #define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1381 #define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1382 #define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1383 #define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1384 #define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1385 #define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1386 #define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1387 #define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1388 #define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1389 #define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1390 #define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1391 #define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1392 #define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1393 #define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1394 #define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1395 #define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1396 #define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1397 #define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1398 #define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1399 #define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1400 #define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1401 #define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1402 #define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1403 #define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1404 #define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1405 #define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1406 #define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1407 #define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1408 #define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1409 #define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1410 #define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1411 #define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1412 #define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1413 #define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1414 #define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1415 #define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1416 #define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1417 #define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1418 #define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1419 #define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1420 #define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1421 #define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1422 #define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1423 #define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1424 #define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1425 #define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1426 #define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1427 #define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1428 #define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1429 #define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1430 #define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1431 #define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1432 #define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1433 #define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1434 #define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1435 #define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1436 #define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1437 #define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1438 #define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1439 #define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */
1440 #define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1441 #define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1442 #define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1443 #define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1444 #define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1445 #define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1446 #define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1447 #define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1448 #define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1449 #define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */
1450 #define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */
1451 #define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */
1452 #define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */
1453 #define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */
1454 #define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1455 #define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1456 #define ADC0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1457 #define ADC0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1458 #define ADC1_CH3A_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1459 #define ADC1_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1460 #define ADC1_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1461 #define ADC1_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1462 #define ADC1_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1463 #define AOI1_OUT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 12) /* PIO0_12 */
1464 #define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1465 #define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1466 #define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1467 #define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1468 #define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1469 #define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1470 #define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1471 #define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1472 #define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1473 #define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1474 #define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1475 #define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1476 #define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1477 #define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1478 #define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1479 #define DMA0_TRIG023_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1480 #define DMA0_TRIG024_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1481 #define DMA0_TRIG025_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1482 #define DMA0_TRIG026_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1483 #define DMA0_TRIG027_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1484 #define DMA0_TRIG028_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1485 #define DMA0_TRIG029_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1486 #define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1487 #define DMA0_TRIG030_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1488 #define DMA0_TRIG031_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1489 #define DMA0_TRIG032_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1490 #define DMA0_TRIG033_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1491 #define DMA0_TRIG034_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1492 #define DMA0_TRIG035_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1493 #define DMA0_TRIG036_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1494 #define DMA0_TRIG037_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1495 #define DMA0_TRIG038_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1496 #define DMA0_TRIG039_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1497 #define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1498 #define DMA0_TRIG040_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1499 #define DMA0_TRIG041_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1500 #define DMA0_TRIG042_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1501 #define DMA0_TRIG043_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1502 #define DMA0_TRIG044_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1503 #define DMA0_TRIG045_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1504 #define DMA0_TRIG046_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1505 #define DMA0_TRIG047_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1506 #define DMA0_TRIG048_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1507 #define DMA0_TRIG049_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1508 #define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1509 #define DMA0_TRIG050_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1510 #define DMA0_TRIG051_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1511 #define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1512 #define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1513 #define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1514 #define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1515 #define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1516 #define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1517 #define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1518 #define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1519 #define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1520 #define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1521 #define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1522 #define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1523 #define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1524 #define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1525 #define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1526 #define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */
1527 #define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 7) /* PIO0_12 */
1528 #define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1529 #define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1530 #define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1531 #define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1532 #define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1533 #define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1534 #define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1535 #define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1536 #define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1537 #define PIO0_12_PIO0_12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */
1538 #define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
1539 #define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
1540 #define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
1541 #define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
1542 #define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
1543 #define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
1544 #define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 4) /* PIO0_12 */
1545 #define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */
1546 #define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */
1547 #define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 10) /* PIO0_12 */
1548 #define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 3) /* PIO0_12 */
1549 #define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1550 #define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1551 #define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1552 #define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1553 #define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1554 #define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1555 #define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1556 #define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1557 #define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1558 #define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1559 #define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1560 #define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1561 #define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1562 #define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1563 #define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1564 #define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1565 #define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1566 #define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1567 #define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1568 #define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1569 #define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1570 #define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1571 #define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1572 #define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1573 #define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1574 #define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1575 #define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1576 #define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1577 #define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1578 #define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1579 #define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1580 #define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1581 #define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1582 #define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1583 #define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1584 #define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1585 #define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1586 #define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1587 #define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1588 #define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1589 #define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1590 #define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1591 #define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1592 #define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1593 #define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1594 #define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1595 #define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1596 #define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1597 #define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1598 #define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1599 #define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1600 #define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1601 #define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1602 #define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1603 #define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1604 #define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1605 #define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1606 #define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1607 #define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1608 #define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1609 #define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */
1610 #define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1611 #define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1612 #define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1613 #define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1614 #define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1615 #define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1616 #define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1617 #define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1618 #define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1619 #define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1620 #define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1621 #define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1622 #define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1623 #define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1624 #define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1625 #define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1626 #define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1627 #define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1628 #define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1629 #define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1630 #define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1631 #define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1632 #define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1633 #define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1634 #define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1635 #define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1636 #define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1637 #define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1638 #define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1639 #define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1640 #define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1641 #define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1642 #define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1643 #define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1644 #define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1645 #define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1646 #define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1647 #define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1648 #define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1649 #define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1650 #define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1651 #define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1652 #define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1653 #define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1654 #define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1655 #define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1656 #define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1657 #define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1658 #define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1659 #define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1660 #define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1661 #define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1662 #define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1663 #define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1664 #define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1665 #define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1666 #define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1667 #define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1668 #define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1669 #define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1670 #define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1671 #define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1672 #define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1673 #define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1674 #define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1675 #define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1676 #define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1677 #define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */
1678 #define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */
1679 #define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1680 #define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1681 #define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1682 #define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1683 #define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1684 #define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1685 #define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1686 #define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1687 #define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1688 #define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */
1689 #define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1690 #define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1691 #define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1692 #define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1693 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1694 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1695 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1696 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1697 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1698 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1699 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1700 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1701 #define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1702 #define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1703 #define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1704 #define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1705 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1706 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1707 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1708 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1709 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1710 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1711 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1712 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */
1713 #define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
1714 #define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
1715 #define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
1716 #define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
1717 #define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
1718 #define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
1719 #define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */
1720 #define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */
1721 #define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */
1722 #define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */
1723 #define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */
1724 #define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1725 #define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1726 #define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1727 #define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1728 #define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1729 #define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1730 #define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1731 #define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1732 #define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1733 #define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1734 #define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1735 #define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1736 #define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1737 #define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1738 #define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1739 #define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1740 #define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1741 #define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1742 #define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1743 #define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1744 #define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1745 #define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1746 #define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1747 #define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1748 #define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1749 #define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1750 #define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1751 #define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1752 #define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1753 #define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1754 #define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1755 #define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1756 #define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1757 #define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1758 #define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1759 #define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1760 #define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1761 #define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1762 #define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1763 #define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1764 #define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1765 #define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1766 #define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1767 #define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1768 #define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1769 #define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1770 #define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1771 #define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1772 #define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1773 #define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1774 #define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1775 #define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1776 #define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1777 #define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1778 #define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1779 #define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1780 #define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1781 #define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1782 #define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1783 #define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1784 #define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */
1785 #define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1786 #define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1787 #define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1788 #define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1789 #define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1790 #define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1791 #define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1792 #define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1793 #define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1794 #define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1795 #define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1796 #define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1797 #define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1798 #define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1799 #define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1800 #define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1801 #define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1802 #define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1803 #define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1804 #define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1805 #define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1806 #define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1807 #define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1808 #define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1809 #define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1810 #define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1811 #define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1812 #define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1813 #define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1814 #define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1815 #define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1816 #define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1817 #define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1818 #define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1819 #define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1820 #define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1821 #define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1822 #define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1823 #define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1824 #define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1825 #define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1826 #define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1827 #define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1828 #define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1829 #define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1830 #define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1831 #define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1832 #define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1833 #define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1834 #define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1835 #define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1836 #define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1837 #define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1838 #define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1839 #define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1840 #define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1841 #define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1842 #define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1843 #define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1844 #define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1845 #define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1846 #define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1847 #define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1848 #define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1849 #define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1850 #define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1851 #define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1852 #define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */
1853 #define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */
1854 #define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1855 #define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1856 #define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1857 #define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1858 #define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1859 #define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1860 #define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1861 #define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1862 #define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1863 #define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */
1864 #define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1865 #define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1866 #define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1867 #define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1868 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1869 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1870 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1871 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1872 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1873 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1874 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1875 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1876 #define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1877 #define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1878 #define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1879 #define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1880 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1881 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1882 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1883 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1884 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1885 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1886 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1887 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */
1888 #define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
1889 #define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
1890 #define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
1891 #define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
1892 #define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
1893 #define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
1894 #define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */
1895 #define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */
1896 #define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */
1897 #define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */
1898 #define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */
1899 #define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1900 #define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1901 #define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1902 #define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1903 #define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1904 #define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1905 #define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1906 #define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1907 #define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1908 #define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1909 #define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1910 #define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1911 #define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1912 #define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1913 #define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1914 #define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1915 #define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1916 #define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1917 #define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1918 #define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1919 #define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1920 #define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1921 #define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1922 #define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1923 #define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1924 #define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1925 #define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1926 #define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1927 #define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1928 #define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */
1929 #define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1930 #define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1931 #define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1932 #define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1933 #define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1934 #define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1935 #define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1936 #define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1937 #define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1938 #define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1939 #define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1940 #define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1941 #define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1942 #define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1943 #define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1944 #define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1945 #define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1946 #define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1947 #define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1948 #define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1949 #define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1950 #define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1951 #define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1952 #define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1953 #define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1954 #define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1955 #define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1956 #define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1957 #define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1958 #define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1959 #define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1960 #define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1961 #define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1962 #define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1963 #define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1964 #define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1965 #define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1966 #define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1967 #define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1968 #define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1969 #define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1970 #define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1971 #define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1972 #define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1973 #define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1974 #define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1975 #define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1976 #define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1977 #define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1978 #define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1979 #define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1980 #define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1981 #define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1982 #define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1983 #define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1984 #define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1985 #define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1986 #define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1987 #define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1988 #define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1989 #define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1990 #define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1991 #define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */
1992 #define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1993 #define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1994 #define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1995 #define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1996 #define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1997 #define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1998 #define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
1999 #define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
2000 #define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
2001 #define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */
2002 #define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */
2003 #define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */
2004 #define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */
2005 #define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */
2006 #define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */
2007 #define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2008 #define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2009 #define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2010 #define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2011 #define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2012 #define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2013 #define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2014 #define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2015 #define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2016 #define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */
2017 #define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */
2018 #define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2019 #define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2020 #define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2021 #define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2022 #define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2023 #define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2024 #define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2025 #define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2026 #define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2027 #define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2028 #define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2029 #define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2030 #define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2031 #define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2032 #define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2033 #define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2034 #define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2035 #define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2036 #define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2037 #define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2038 #define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */
2039 #define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2040 #define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2041 #define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2042 #define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2043 #define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2044 #define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2045 #define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2046 #define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2047 #define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2048 #define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2049 #define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2050 #define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2051 #define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2052 #define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2053 #define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2054 #define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2055 #define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2056 #define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2057 #define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2058 #define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2059 #define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2060 #define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2061 #define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2062 #define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2063 #define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2064 #define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2065 #define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2066 #define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2067 #define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2068 #define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2069 #define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2070 #define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2071 #define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2072 #define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2073 #define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2074 #define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2075 #define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2076 #define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2077 #define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2078 #define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2079 #define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2080 #define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2081 #define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2082 #define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2083 #define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2084 #define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2085 #define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2086 #define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2087 #define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2088 #define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2089 #define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2090 #define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2091 #define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2092 #define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2093 #define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2094 #define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2095 #define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2096 #define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2097 #define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2098 #define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2099 #define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2100 #define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2101 #define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */
2102 #define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2103 #define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2104 #define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2105 #define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2106 #define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2107 #define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2108 #define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2109 #define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2110 #define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2111 #define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */
2112 #define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */
2113 #define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */
2114 #define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */
2115 #define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2116 #define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2117 #define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2118 #define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2119 #define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2120 #define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2121 #define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2122 #define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2123 #define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */
2124 #define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */
2125 #define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2126 #define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2127 #define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2128 #define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2129 #define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2130 #define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2131 #define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2132 #define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2133 #define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2134 #define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2135 #define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2136 #define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2137 #define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2138 #define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2139 #define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2140 #define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2141 #define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2142 #define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2143 #define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2144 #define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2145 #define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2146 #define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2147 #define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2148 #define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2149 #define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2150 #define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2151 #define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2152 #define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2153 #define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2154 #define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2155 #define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2156 #define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2157 #define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2158 #define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2159 #define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2160 #define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2161 #define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2162 #define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2163 #define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2164 #define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2165 #define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2166 #define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2167 #define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2168 #define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2169 #define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2170 #define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2171 #define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2172 #define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2173 #define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2174 #define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2175 #define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2176 #define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2177 #define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2178 #define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2179 #define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2180 #define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2181 #define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2182 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2183 #define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2184 #define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2185 #define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2186 #define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2187 #define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */
2188 #define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */
2189 #define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2190 #define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */
2191 #define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2192 #define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2193 #define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2194 #define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2195 #define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2196 #define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2197 #define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2198 #define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2199 #define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2200 #define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */
2201 #define QSPI_SCLK_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 9) /* PIO0_17 */
2202 #define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
2203 #define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
2204 #define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
2205 #define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
2206 #define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
2207 #define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
2208 #define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */
2209 #define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */
2210 #define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */
2211 #define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */
2212 #define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */
2213 #define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2214 #define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2215 #define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2216 #define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2217 #define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2218 #define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2219 #define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2220 #define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2221 #define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */
2222 #define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */
2223 #define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */
2224 #define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2225 #define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2226 #define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2227 #define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2228 #define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2229 #define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2230 #define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2231 #define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2232 #define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2233 #define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2234 #define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2235 #define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2236 #define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2237 #define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2238 #define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2239 #define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2240 #define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2241 #define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2242 #define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2243 #define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2244 #define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2245 #define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2246 #define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2247 #define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2248 #define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2249 #define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2250 #define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2251 #define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2252 #define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2253 #define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2254 #define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2255 #define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2256 #define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2257 #define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2258 #define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2259 #define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2260 #define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2261 #define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2262 #define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2263 #define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2264 #define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2265 #define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2266 #define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2267 #define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2268 #define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2269 #define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2270 #define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2271 #define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2272 #define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2273 #define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2274 #define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2275 #define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2276 #define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2277 #define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2278 #define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2279 #define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2280 #define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2281 #define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2282 #define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2283 #define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2284 #define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2285 #define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2286 #define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */
2287 #define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */
2288 #define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2289 #define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2290 #define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2291 #define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2292 #define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2293 #define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2294 #define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2295 #define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2296 #define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2297 #define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2298 #define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */
2299 #define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */
2300 #define QSPI_DIN1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 12) /* PIO0_18 */
2301 #define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */
2302 #define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */
2303 #define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */
2304 #define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */
2305 #define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */
2306 #define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2307 #define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2308 #define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2309 #define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2310 #define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2311 #define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2312 #define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2313 #define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2314 #define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2315 #define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2316 #define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2317 #define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2318 #define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2319 #define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2320 #define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2321 #define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2322 #define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2323 #define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2324 #define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2325 #define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2326 #define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2327 #define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2328 #define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2329 #define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2330 #define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */
2331 #define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2332 #define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2333 #define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2334 #define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2335 #define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2336 #define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2337 #define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2338 #define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2339 #define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2340 #define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2341 #define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2342 #define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2343 #define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2344 #define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2345 #define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2346 #define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2347 #define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */
2348 #define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */
2349 #define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2350 #define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2351 #define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2352 #define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2353 #define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2354 #define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2355 #define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2356 #define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2357 #define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2358 #define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2359 #define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2360 #define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2361 #define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2362 #define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2363 #define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2364 #define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2365 #define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2366 #define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2367 #define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2368 #define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2369 #define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2370 #define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2371 #define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2372 #define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2373 #define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2374 #define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2375 #define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2376 #define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2377 #define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2378 #define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2379 #define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2380 #define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2381 #define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2382 #define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2383 #define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2384 #define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2385 #define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2386 #define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2387 #define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2388 #define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2389 #define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2390 #define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2391 #define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2392 #define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2393 #define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2394 #define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2395 #define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2396 #define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2397 #define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2398 #define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2399 #define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2400 #define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2401 #define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2402 #define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2403 #define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2404 #define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2405 #define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2406 #define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2407 #define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2408 #define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2409 #define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2410 #define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2411 #define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2412 #define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2413 #define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2414 #define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2415 #define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2416 #define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */
2417 #define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */
2418 #define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */
2419 #define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */
2420 #define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2421 #define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2422 #define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2423 #define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2424 #define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2425 #define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2426 #define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2427 #define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2428 #define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2429 #define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */
2430 #define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */
2431 #define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2432 #define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2433 #define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2434 #define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2435 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2436 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2437 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2438 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2439 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2440 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2441 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2442 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2443 #define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2444 #define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2445 #define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2446 #define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2447 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2448 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2449 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2450 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2451 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2452 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2453 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2454 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */
2455 #define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */
2456 #define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */
2457 #define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */
2458 #define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */
2459 #define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */
2460 #define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2461 #define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2462 #define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2463 #define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2464 #define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2465 #define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2466 #define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2467 #define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2468 #define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2469 #define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2470 #define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2471 #define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2472 #define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2473 #define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2474 #define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2475 #define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2476 #define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */
2477 #define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2478 #define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2479 #define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2480 #define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2481 #define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2482 #define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2483 #define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2484 #define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2485 #define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2486 #define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2487 #define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2488 #define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2489 #define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */
2490 #define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2491 #define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2492 #define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2493 #define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2494 #define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2495 #define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2496 #define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2497 #define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2498 #define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2499 #define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2500 #define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2501 #define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2502 #define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2503 #define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2504 #define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2505 #define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2506 #define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2507 #define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2508 #define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2509 #define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2510 #define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2511 #define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2512 #define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2513 #define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2514 #define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2515 #define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2516 #define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2517 #define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2518 #define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2519 #define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2520 #define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2521 #define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2522 #define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2523 #define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2524 #define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2525 #define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2526 #define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2527 #define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2528 #define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2529 #define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2530 #define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2531 #define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2532 #define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2533 #define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2534 #define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2535 #define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2536 #define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2537 #define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2538 #define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2539 #define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2540 #define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2541 #define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2542 #define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2543 #define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2544 #define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2545 #define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2546 #define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2547 #define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2548 #define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2549 #define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2550 #define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2551 #define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2552 #define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */
2553 #define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */
2554 #define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */
2555 #define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2556 #define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */
2557 #define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2558 #define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2559 #define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2560 #define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2561 #define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2562 #define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2563 #define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2564 #define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2565 #define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */
2566 #define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */
2567 #define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
2568 #define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
2569 #define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
2570 #define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
2571 #define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
2572 #define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
2573 #define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */
2574 #define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */
2575 #define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */
2576 #define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */
2577 #define SPI_CS0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 12) /* PIO0_20 */
2578 #define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2579 #define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2580 #define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2581 #define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2582 #define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2583 #define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2584 #define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2585 #define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2586 #define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */
2587 #define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */
2588 #define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */
2589 #define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2590 #define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2591 #define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2592 #define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2593 #define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2594 #define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2595 #define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2596 #define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2597 #define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2598 #define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2599 #define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2600 #define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2601 #define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2602 #define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2603 #define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2604 #define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2605 #define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2606 #define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2607 #define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2608 #define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2609 #define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2610 #define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2611 #define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2612 #define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2613 #define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2614 #define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2615 #define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2616 #define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2617 #define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2618 #define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2619 #define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2620 #define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2621 #define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2622 #define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2623 #define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2624 #define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2625 #define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2626 #define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2627 #define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2628 #define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2629 #define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2630 #define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2631 #define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2632 #define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2633 #define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2634 #define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2635 #define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2636 #define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2637 #define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2638 #define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2639 #define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2640 #define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2641 #define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2642 #define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2643 #define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2644 #define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2645 #define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2646 #define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2647 #define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2648 #define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2649 #define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2650 #define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2651 #define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2652 #define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2653 #define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2654 #define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2655 #define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2656 #define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */
2657 #define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */
2658 #define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */
2659 #define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */
2660 #define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2661 #define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */
2662 #define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2663 #define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2664 #define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2665 #define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2666 #define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2667 #define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2668 #define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2669 #define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2670 #define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */
2671 #define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2672 #define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2673 #define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2674 #define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2675 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2676 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2677 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2678 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2679 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2680 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2681 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2682 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2683 #define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */
2684 #define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2685 #define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2686 #define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2687 #define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2688 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2689 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2690 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2691 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2692 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2693 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2694 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2695 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */
2696 #define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
2697 #define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
2698 #define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
2699 #define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
2700 #define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
2701 #define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
2702 #define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */
2703 #define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */
2704 #define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */
2705 #define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */
2706 #define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */
2707 #define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */
2708 #define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2709 #define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2710 #define ADC0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2711 #define ADC0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2712 #define ADC1_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2713 #define ADC1_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2714 #define ADC1_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2715 #define ADC1_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2716 #define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2717 #define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2718 #define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2719 #define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2720 #define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2721 #define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2722 #define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2723 #define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2724 #define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2725 #define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2726 #define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2727 #define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2728 #define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2729 #define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2730 #define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2731 #define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2732 #define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2733 #define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2734 #define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2735 #define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2736 #define CT_INP15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */
2737 #define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2738 #define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2739 #define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2740 #define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2741 #define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2742 #define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2743 #define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2744 #define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2745 #define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2746 #define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2747 #define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2748 #define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2749 #define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2750 #define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2751 #define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2752 #define DMA0_TRIG023_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2753 #define DMA0_TRIG024_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2754 #define DMA0_TRIG025_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2755 #define DMA0_TRIG026_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2756 #define DMA0_TRIG027_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2757 #define DMA0_TRIG028_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2758 #define DMA0_TRIG029_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2759 #define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2760 #define DMA0_TRIG030_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2761 #define DMA0_TRIG031_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2762 #define DMA0_TRIG032_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2763 #define DMA0_TRIG033_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2764 #define DMA0_TRIG034_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2765 #define DMA0_TRIG035_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2766 #define DMA0_TRIG036_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2767 #define DMA0_TRIG037_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2768 #define DMA0_TRIG038_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2769 #define DMA0_TRIG039_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2770 #define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2771 #define DMA0_TRIG040_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2772 #define DMA0_TRIG041_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2773 #define DMA0_TRIG042_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2774 #define DMA0_TRIG043_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2775 #define DMA0_TRIG044_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2776 #define DMA0_TRIG045_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2777 #define DMA0_TRIG046_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2778 #define DMA0_TRIG047_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2779 #define DMA0_TRIG048_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2780 #define DMA0_TRIG049_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2781 #define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2782 #define DMA0_TRIG050_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2783 #define DMA0_TRIG051_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2784 #define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2785 #define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2786 #define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2787 #define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2788 #define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2789 #define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2790 #define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2791 #define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2792 #define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2793 #define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2794 #define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2795 #define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2796 #define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2797 #define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2798 #define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2799 #define ENC0_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2800 #define ENC0_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2801 #define ENC1_PHASEA_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2802 #define ENC1_PHASEB_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2803 #define EXTTRIG_IN5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2804 #define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */
2805 #define FC7_RTS_SCL_SSEL1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */
2806 #define FLEXSPI0_SCLK_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 5) /* PIO0_22 */
2807 #define FLEXSPI0_SS1_N_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 6) /* PIO0_22 */
2808 #define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2809 #define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2810 #define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2811 #define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2812 #define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2813 #define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2814 #define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2815 #define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2816 #define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2817 #define PIO0_22_PIO0_22_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */
2818 #define PWM0_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2819 #define PWM0_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2820 #define PWM0_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2821 #define PWM0_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2822 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2823 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2824 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2825 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2826 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2827 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2828 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2829 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2830 #define PWM1_EXTA0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2831 #define PWM1_EXTA1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2832 #define PWM1_EXTA2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2833 #define PWM1_EXTA3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2834 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2835 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2836 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2837 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2838 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2839 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2840 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2841 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 13) /* PIO0_22 */
2842 #define PWM1_X0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 11) /* PIO0_22 */
2843 #define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */
2844 #define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */
2845 #define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */
2846 #define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */
2847 #define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */
2848 #define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */
2849 #define ADC0_CH8B_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2850 #define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2851 #define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2852 #define ADC0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2853 #define ADC0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2854 #define ADC1_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2855 #define ADC1_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2856 #define ADC1_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2857 #define ADC1_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2858 #define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */
2859 #define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */
2860 #define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2861 #define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2862 #define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2863 #define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2864 #define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2865 #define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2866 #define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2867 #define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2868 #define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2869 #define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2870 #define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2871 #define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2872 #define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2873 #define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2874 #define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2875 #define DMA0_TRIG023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2876 #define DMA0_TRIG024_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2877 #define DMA0_TRIG025_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2878 #define DMA0_TRIG026_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2879 #define DMA0_TRIG027_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2880 #define DMA0_TRIG028_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2881 #define DMA0_TRIG029_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2882 #define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2883 #define DMA0_TRIG030_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2884 #define DMA0_TRIG031_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2885 #define DMA0_TRIG032_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2886 #define DMA0_TRIG033_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2887 #define DMA0_TRIG034_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2888 #define DMA0_TRIG035_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2889 #define DMA0_TRIG036_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2890 #define DMA0_TRIG037_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2891 #define DMA0_TRIG038_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2892 #define DMA0_TRIG039_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2893 #define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2894 #define DMA0_TRIG040_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2895 #define DMA0_TRIG041_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2896 #define DMA0_TRIG042_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2897 #define DMA0_TRIG043_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2898 #define DMA0_TRIG044_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2899 #define DMA0_TRIG045_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2900 #define DMA0_TRIG046_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2901 #define DMA0_TRIG047_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2902 #define DMA0_TRIG048_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2903 #define DMA0_TRIG049_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2904 #define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2905 #define DMA0_TRIG050_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2906 #define DMA0_TRIG051_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2907 #define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2908 #define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2909 #define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2910 #define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2911 #define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2912 #define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2913 #define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2914 #define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2915 #define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2916 #define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2917 #define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2918 #define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2919 #define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2920 #define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2921 #define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2922 #define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */
2923 #define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2924 #define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */
2925 #define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2926 #define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2927 #define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2928 #define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2929 #define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2930 #define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2931 #define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2932 #define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2933 #define PIO0_23_PIO0_23_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */
2934 #define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */
2935 #define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */
2936 #define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */
2937 #define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */
2938 #define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2939 #define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2940 #define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2941 #define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2942 #define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2943 #define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2944 #define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2945 #define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2946 #define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2947 #define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2948 #define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2949 #define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2950 #define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2951 #define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2952 #define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2953 #define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2954 #define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2955 #define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2956 #define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2957 #define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2958 #define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2959 #define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2960 #define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2961 #define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2962 #define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2963 #define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2964 #define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2965 #define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2966 #define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */
2967 #define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2968 #define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2969 #define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2970 #define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2971 #define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2972 #define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2973 #define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2974 #define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2975 #define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2976 #define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2977 #define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2978 #define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2979 #define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2980 #define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2981 #define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2982 #define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2983 #define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2984 #define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2985 #define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2986 #define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2987 #define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2988 #define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2989 #define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2990 #define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2991 #define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2992 #define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2993 #define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2994 #define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2995 #define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2996 #define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2997 #define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2998 #define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
2999 #define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3000 #define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3001 #define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3002 #define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3003 #define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3004 #define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3005 #define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3006 #define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3007 #define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3008 #define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3009 #define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3010 #define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3011 #define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3012 #define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3013 #define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3014 #define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3015 #define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3016 #define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3017 #define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3018 #define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3019 #define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3020 #define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3021 #define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3022 #define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3023 #define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3024 #define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3025 #define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3026 #define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3027 #define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3028 #define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3029 #define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */
3030 #define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3031 #define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3032 #define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */
3033 #define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3034 #define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3035 #define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3036 #define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3037 #define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3038 #define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3039 #define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3040 #define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3041 #define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */
3042 #define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */
3043 #define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */
3044 #define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
3045 #define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
3046 #define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
3047 #define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
3048 #define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
3049 #define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
3050 #define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */
3051 #define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */
3052 #define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */
3053 #define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */
3054 #define SPI_CS0_DIS_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 12) /* PIO0_24 */
3055 #define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */
3056 #define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3057 #define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3058 #define ADC0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3059 #define ADC0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3060 #define ADC1_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3061 #define ADC1_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3062 #define ADC1_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3063 #define ADC1_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3064 #define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3065 #define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3066 #define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3067 #define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3068 #define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3069 #define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3070 #define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3071 #define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3072 #define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3073 #define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3074 #define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3075 #define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3076 #define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3077 #define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3078 #define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3079 #define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3080 #define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3081 #define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3082 #define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3083 #define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3084 #define CT_INP9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */
3085 #define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3086 #define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3087 #define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3088 #define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3089 #define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3090 #define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3091 #define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3092 #define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3093 #define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3094 #define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3095 #define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3096 #define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3097 #define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3098 #define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3099 #define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3100 #define DMA0_TRIG023_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3101 #define DMA0_TRIG024_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3102 #define DMA0_TRIG025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3103 #define DMA0_TRIG026_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3104 #define DMA0_TRIG027_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3105 #define DMA0_TRIG028_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3106 #define DMA0_TRIG029_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3107 #define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3108 #define DMA0_TRIG030_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3109 #define DMA0_TRIG031_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3110 #define DMA0_TRIG032_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3111 #define DMA0_TRIG033_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3112 #define DMA0_TRIG034_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3113 #define DMA0_TRIG035_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3114 #define DMA0_TRIG036_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3115 #define DMA0_TRIG037_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3116 #define DMA0_TRIG038_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3117 #define DMA0_TRIG039_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3118 #define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3119 #define DMA0_TRIG040_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3120 #define DMA0_TRIG041_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3121 #define DMA0_TRIG042_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3122 #define DMA0_TRIG043_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3123 #define DMA0_TRIG044_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3124 #define DMA0_TRIG045_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3125 #define DMA0_TRIG046_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3126 #define DMA0_TRIG047_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3127 #define DMA0_TRIG048_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3128 #define DMA0_TRIG049_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3129 #define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3130 #define DMA0_TRIG050_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3131 #define DMA0_TRIG051_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3132 #define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3133 #define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3134 #define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3135 #define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3136 #define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3137 #define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3138 #define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3139 #define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3140 #define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3141 #define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3142 #define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3143 #define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3144 #define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3145 #define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3146 #define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3147 #define ENC0_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3148 #define ENC0_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3149 #define ENC1_PHASEA_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3150 #define ENC1_PHASEB_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3151 #define EXTTRIG_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3152 #define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */
3153 #define FLEXSPI0_DQS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 6) /* PIO0_25 */
3154 #define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3155 #define HSCMP0_OUT_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 7) /* PIO0_25 */
3156 #define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3157 #define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3158 #define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3159 #define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3160 #define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3161 #define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3162 #define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3163 #define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3164 #define PIO0_25_PIO0_25_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */
3165 #define PWM0_A0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 11) /* PIO0_25 */
3166 #define PWM0_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3167 #define PWM0_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3168 #define PWM0_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3169 #define PWM0_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3170 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3171 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3172 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3173 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3174 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3175 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3176 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3177 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3178 #define PWM1_EXTA0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3179 #define PWM1_EXTA1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3180 #define PWM1_EXTA2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3181 #define PWM1_EXTA3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3182 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3183 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3184 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3185 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3186 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3187 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3188 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3189 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 13) /* PIO0_25 */
3190 #define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
3191 #define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
3192 #define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
3193 #define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
3194 #define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
3195 #define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
3196 #define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */
3197 #define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */
3198 #define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */
3199 #define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */
3200 #define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3201 #define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3202 #define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3203 #define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3204 #define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3205 #define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3206 #define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3207 #define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3208 #define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */
3209 #define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3210 #define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3211 #define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3212 #define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3213 #define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3214 #define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3215 #define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3216 #define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3217 #define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3218 #define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3219 #define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3220 #define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3221 #define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3222 #define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3223 #define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3224 #define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3225 #define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3226 #define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3227 #define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3228 #define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3229 #define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */
3230 #define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3231 #define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3232 #define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3233 #define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3234 #define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3235 #define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3236 #define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3237 #define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3238 #define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3239 #define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3240 #define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3241 #define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3242 #define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3243 #define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3244 #define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3245 #define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3246 #define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3247 #define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3248 #define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3249 #define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3250 #define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3251 #define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3252 #define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3253 #define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3254 #define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3255 #define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3256 #define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3257 #define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3258 #define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3259 #define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3260 #define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3261 #define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3262 #define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3263 #define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3264 #define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3265 #define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3266 #define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3267 #define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3268 #define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3269 #define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3270 #define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3271 #define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3272 #define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3273 #define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3274 #define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3275 #define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3276 #define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3277 #define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3278 #define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3279 #define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3280 #define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3281 #define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3282 #define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3283 #define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3284 #define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3285 #define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3286 #define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3287 #define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3288 #define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3289 #define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3290 #define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3291 #define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3292 #define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */
3293 #define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */
3294 #define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */
3295 #define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3296 #define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */
3297 #define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3298 #define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3299 #define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3300 #define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3301 #define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3302 #define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3303 #define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3304 #define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3305 #define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3306 #define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */
3307 #define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */
3308 #define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */
3309 #define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */
3310 #define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */
3311 #define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */
3312 #define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */
3313 #define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3314 #define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3315 #define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3316 #define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3317 #define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3318 #define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3319 #define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3320 #define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3321 #define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */
3322 #define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3323 #define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3324 #define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3325 #define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3326 #define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3327 #define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3328 #define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3329 #define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3330 #define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3331 #define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3332 #define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3333 #define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3334 #define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3335 #define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3336 #define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3337 #define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3338 #define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3339 #define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3340 #define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3341 #define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3342 #define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3343 #define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3344 #define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3345 #define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3346 #define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3347 #define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3348 #define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3349 #define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3350 #define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3351 #define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3352 #define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3353 #define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3354 #define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3355 #define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3356 #define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3357 #define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3358 #define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3359 #define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3360 #define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3361 #define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3362 #define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3363 #define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3364 #define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3365 #define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3366 #define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3367 #define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3368 #define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3369 #define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3370 #define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3371 #define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3372 #define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3373 #define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3374 #define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3375 #define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3376 #define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3377 #define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3378 #define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3379 #define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3380 #define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3381 #define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3382 #define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3383 #define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3384 #define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */
3385 #define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */
3386 #define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */
3387 #define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3388 #define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3389 #define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3390 #define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3391 #define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3392 #define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3393 #define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3394 #define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3395 #define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3396 #define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3397 #define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */
3398 #define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */
3399 #define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */
3400 #define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */
3401 #define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */
3402 #define SPI_CS1_DIS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 12) /* PIO0_27 */
3403 #define ADC0_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3404 #define ADC0_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3405 #define ADC0_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3406 #define ADC0_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3407 #define ADC1_TRIG0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3408 #define ADC1_TRIG1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3409 #define ADC1_TRIG2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3410 #define ADC1_TRIG3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3411 #define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3412 #define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3413 #define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3414 #define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3415 #define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3416 #define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3417 #define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3418 #define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3419 #define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3420 #define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3421 #define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3422 #define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3423 #define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3424 #define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3425 #define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3426 #define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3427 #define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3428 #define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3429 #define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3430 #define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3431 #define CT_INP11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */
3432 #define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3433 #define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3434 #define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3435 #define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3436 #define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3437 #define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3438 #define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3439 #define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3440 #define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3441 #define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3442 #define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3443 #define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3444 #define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3445 #define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3446 #define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3447 #define DMA0_TRIG023_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3448 #define DMA0_TRIG024_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3449 #define DMA0_TRIG025_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3450 #define DMA0_TRIG026_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3451 #define DMA0_TRIG027_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3452 #define DMA0_TRIG028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3453 #define DMA0_TRIG029_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3454 #define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3455 #define DMA0_TRIG030_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3456 #define DMA0_TRIG031_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3457 #define DMA0_TRIG032_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3458 #define DMA0_TRIG033_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3459 #define DMA0_TRIG034_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3460 #define DMA0_TRIG035_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3461 #define DMA0_TRIG036_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3462 #define DMA0_TRIG037_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3463 #define DMA0_TRIG038_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3464 #define DMA0_TRIG039_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3465 #define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3466 #define DMA0_TRIG040_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3467 #define DMA0_TRIG041_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3468 #define DMA0_TRIG042_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3469 #define DMA0_TRIG043_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3470 #define DMA0_TRIG044_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3471 #define DMA0_TRIG045_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3472 #define DMA0_TRIG046_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3473 #define DMA0_TRIG047_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3474 #define DMA0_TRIG048_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3475 #define DMA0_TRIG049_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3476 #define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3477 #define DMA0_TRIG050_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3478 #define DMA0_TRIG051_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3479 #define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3480 #define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3481 #define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3482 #define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3483 #define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3484 #define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3485 #define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3486 #define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3487 #define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3488 #define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3489 #define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3490 #define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3491 #define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3492 #define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3493 #define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3494 #define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */
3495 #define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3496 #define I3C0_PUR_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 8) /* PIO0_28 */
3497 #define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3498 #define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3499 #define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3500 #define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3501 #define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3502 #define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3503 #define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3504 #define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3505 #define PIO0_28_PIO0_28_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3506 #define PWM0_A2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 11) /* PIO0_28 */
3507 #define QSPI_CS0_DIS_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 12) /* PIO0_28 */
3508 #define RTC_TAMPER1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */
3509 #define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */
3510 #define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */
3511 #define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */
3512 #define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */
3513 #define SWD_TRACEDATA3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 5) /* PIO0_28 */
3514 #define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */
3515 #define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3516 #define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3517 #define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3518 #define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3519 #define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3520 #define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3521 #define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3522 #define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3523 #define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3524 #define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3525 #define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3526 #define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3527 #define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3528 #define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3529 #define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3530 #define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3531 #define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3532 #define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3533 #define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3534 #define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3535 #define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3536 #define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3537 #define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3538 #define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3539 #define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3540 #define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3541 #define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3542 #define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3543 #define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3544 #define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3545 #define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3546 #define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3547 #define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3548 #define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3549 #define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3550 #define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3551 #define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3552 #define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3553 #define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3554 #define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3555 #define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */
3556 #define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */
3557 #define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3558 #define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3559 #define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3560 #define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3561 #define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3562 #define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3563 #define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3564 #define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3565 #define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3566 #define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3567 #define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3568 #define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3569 #define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3570 #define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3571 #define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3572 #define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3573 #define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3574 #define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3575 #define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3576 #define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3577 #define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3578 #define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3579 #define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3580 #define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3581 #define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3582 #define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3583 #define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3584 #define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3585 #define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3586 #define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3587 #define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3588 #define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3589 #define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3590 #define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3591 #define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3592 #define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3593 #define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3594 #define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3595 #define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3596 #define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3597 #define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3598 #define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3599 #define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3600 #define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3601 #define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3602 #define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3603 #define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3604 #define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3605 #define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3606 #define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3607 #define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3608 #define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3609 #define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3610 #define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3611 #define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3612 #define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3613 #define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3614 #define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3615 #define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3616 #define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3617 #define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3618 #define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3619 #define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3620 #define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3621 #define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3622 #define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3623 #define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3624 #define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */
3625 #define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */
3626 #define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3627 #define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3628 #define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3629 #define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3630 #define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3631 #define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3632 #define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3633 #define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3634 #define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3635 #define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */
3636 #define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */
3637 #define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3638 #define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3639 #define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3640 #define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3641 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3642 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3643 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3644 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3645 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3646 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3647 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3648 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3649 #define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3650 #define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3651 #define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3652 #define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3653 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3654 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3655 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3656 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3657 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3658 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3659 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3660 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */
3661 #define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */
3662 #define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */
3663 #define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */
3664 #define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */
3665 #define SPI_DIN_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 12) /* PIO0_29 */
3666 #define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */
3667 #define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3668 #define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3669 #define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3670 #define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3671 #define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3672 #define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3673 #define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3674 #define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3675 #define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */
3676 #define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */
3677 #define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */
3678 #define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3679 #define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3680 #define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3681 #define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3682 #define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3683 #define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3684 #define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3685 #define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3686 #define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3687 #define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3688 #define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3689 #define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3690 #define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3691 #define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3692 #define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3693 #define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3694 #define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3695 #define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3696 #define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3697 #define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3698 #define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3699 #define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3700 #define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3701 #define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3702 #define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3703 #define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3704 #define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3705 #define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3706 #define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3707 #define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3708 #define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3709 #define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3710 #define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3711 #define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3712 #define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3713 #define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3714 #define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3715 #define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3716 #define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3717 #define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3718 #define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3719 #define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3720 #define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3721 #define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3722 #define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3723 #define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3724 #define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3725 #define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3726 #define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3727 #define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3728 #define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3729 #define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3730 #define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3731 #define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3732 #define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3733 #define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3734 #define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3735 #define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3736 #define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3737 #define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3738 #define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3739 #define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3740 #define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */
3741 #define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */
3742 #define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3743 #define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3744 #define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3745 #define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3746 #define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3747 #define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3748 #define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3749 #define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3750 #define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3751 #define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */
3752 #define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */
3753 #define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */
3754 #define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */
3755 #define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */
3756 #define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */
3757 #define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */
3758 #define ADC0_CH8A_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3759 #define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3760 #define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3761 #define ADC0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3762 #define ADC0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3763 #define ADC1_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3764 #define ADC1_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3765 #define ADC1_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3766 #define ADC1_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3767 #define AOI0_OUT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 12) /* PIO0_31 */
3768 #define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */
3769 #define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3770 #define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3771 #define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3772 #define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3773 #define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3774 #define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3775 #define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3776 #define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3777 #define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3778 #define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3779 #define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3780 #define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3781 #define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3782 #define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3783 #define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3784 #define DMA0_TRIG023_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3785 #define DMA0_TRIG024_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3786 #define DMA0_TRIG025_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3787 #define DMA0_TRIG026_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3788 #define DMA0_TRIG027_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3789 #define DMA0_TRIG028_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3790 #define DMA0_TRIG029_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3791 #define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3792 #define DMA0_TRIG030_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3793 #define DMA0_TRIG031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3794 #define DMA0_TRIG032_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3795 #define DMA0_TRIG033_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3796 #define DMA0_TRIG034_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3797 #define DMA0_TRIG035_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3798 #define DMA0_TRIG036_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3799 #define DMA0_TRIG037_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3800 #define DMA0_TRIG038_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3801 #define DMA0_TRIG039_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3802 #define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3803 #define DMA0_TRIG040_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3804 #define DMA0_TRIG041_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3805 #define DMA0_TRIG042_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3806 #define DMA0_TRIG043_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3807 #define DMA0_TRIG044_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3808 #define DMA0_TRIG045_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3809 #define DMA0_TRIG046_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3810 #define DMA0_TRIG047_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3811 #define DMA0_TRIG048_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3812 #define DMA0_TRIG049_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3813 #define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3814 #define DMA0_TRIG050_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3815 #define DMA0_TRIG051_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3816 #define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3817 #define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3818 #define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3819 #define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3820 #define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3821 #define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3822 #define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3823 #define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3824 #define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3825 #define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3826 #define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3827 #define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3828 #define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3829 #define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3830 #define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3831 #define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */
3832 #define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3833 #define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3834 #define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3835 #define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3836 #define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3837 #define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3838 #define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3839 #define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3840 #define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3841 #define PIO0_31_PIO0_31_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */
3842 #define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */
3843 #define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */
3844 #define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */
3845 #define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */
3846 #define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3847 #define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3848 #define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3849 #define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3850 #define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3851 #define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3852 #define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3853 #define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3854 #define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3855 #define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */
3856 #define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3857 #define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3858 #define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3859 #define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3860 #define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3861 #define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3862 #define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3863 #define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3864 #define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3865 #define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3866 #define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3867 #define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3868 #define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3869 #define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3870 #define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3871 #define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3872 #define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3873 #define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3874 #define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3875 #define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3876 #define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */
3877 #define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3878 #define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3879 #define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3880 #define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3881 #define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3882 #define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3883 #define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3884 #define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3885 #define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3886 #define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3887 #define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3888 #define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3889 #define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3890 #define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3891 #define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3892 #define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3893 #define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3894 #define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3895 #define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3896 #define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3897 #define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3898 #define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3899 #define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3900 #define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3901 #define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3902 #define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3903 #define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3904 #define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3905 #define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3906 #define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3907 #define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3908 #define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3909 #define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3910 #define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3911 #define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3912 #define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3913 #define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3914 #define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3915 #define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3916 #define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3917 #define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3918 #define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3919 #define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3920 #define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3921 #define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3922 #define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3923 #define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3924 #define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3925 #define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3926 #define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3927 #define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3928 #define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3929 #define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3930 #define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3931 #define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3932 #define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3933 #define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3934 #define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3935 #define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3936 #define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3937 #define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3938 #define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3939 #define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */
3940 #define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3941 #define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3942 #define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3943 #define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3944 #define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3945 #define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3946 #define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3947 #define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3948 #define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3949 #define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */
3950 #define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
3951 #define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
3952 #define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
3953 #define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
3954 #define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
3955 #define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
3956 #define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */
3957 #define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3958 #define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3959 #define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3960 #define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3961 #define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3962 #define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3963 #define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3964 #define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3965 #define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3966 #define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3967 #define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3968 #define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3969 #define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3970 #define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3971 #define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3972 #define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3973 #define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3974 #define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3975 #define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3976 #define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3977 #define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3978 #define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3979 #define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3980 #define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3981 #define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3982 #define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3983 #define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3984 #define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3985 #define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */
3986 #define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3987 #define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3988 #define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3989 #define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3990 #define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3991 #define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3992 #define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3993 #define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3994 #define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3995 #define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3996 #define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3997 #define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3998 #define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
3999 #define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4000 #define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4001 #define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4002 #define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4003 #define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4004 #define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4005 #define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4006 #define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4007 #define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4008 #define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4009 #define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4010 #define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4011 #define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4012 #define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4013 #define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4014 #define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4015 #define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4016 #define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4017 #define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4018 #define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4019 #define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4020 #define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4021 #define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4022 #define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4023 #define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4024 #define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4025 #define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4026 #define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4027 #define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4028 #define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4029 #define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4030 #define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4031 #define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4032 #define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4033 #define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4034 #define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4035 #define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4036 #define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4037 #define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4038 #define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4039 #define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4040 #define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4041 #define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4042 #define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4043 #define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4044 #define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4045 #define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4046 #define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4047 #define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4048 #define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */
4049 #define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4050 #define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */
4051 #define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4052 #define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4053 #define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4054 #define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4055 #define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4056 #define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4057 #define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4058 #define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4059 #define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4060 #define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 12) /* PIO1_1 */
4061 #define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */
4062 #define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */
4063 #define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
4064 #define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
4065 #define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
4066 #define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
4067 #define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
4068 #define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
4069 #define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */
4070 #define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */
4071 #define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4072 #define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4073 #define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4074 #define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4075 #define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4076 #define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4077 #define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4078 #define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4079 #define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */
4080 #define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */
4081 #define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */
4082 #define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4083 #define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4084 #define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4085 #define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4086 #define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4087 #define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4088 #define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4089 #define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4090 #define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4091 #define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4092 #define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4093 #define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4094 #define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4095 #define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4096 #define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4097 #define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4098 #define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4099 #define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4100 #define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4101 #define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4102 #define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4103 #define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4104 #define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4105 #define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4106 #define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4107 #define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4108 #define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4109 #define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4110 #define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4111 #define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4112 #define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4113 #define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4114 #define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4115 #define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4116 #define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4117 #define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4118 #define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4119 #define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4120 #define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4121 #define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4122 #define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4123 #define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4124 #define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4125 #define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4126 #define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4127 #define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4128 #define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4129 #define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4130 #define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4131 #define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4132 #define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4133 #define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4134 #define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4135 #define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4136 #define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4137 #define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4138 #define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4139 #define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4140 #define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4141 #define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4142 #define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4143 #define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4144 #define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */
4145 #define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4146 #define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */
4147 #define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4148 #define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4149 #define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4150 #define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4151 #define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4152 #define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4153 #define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4154 #define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4155 #define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */
4156 #define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */
4157 #define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
4158 #define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
4159 #define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
4160 #define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
4161 #define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
4162 #define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
4163 #define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */
4164 #define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4165 #define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4166 #define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4167 #define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4168 #define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4169 #define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4170 #define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4171 #define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4172 #define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */
4173 #define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4174 #define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4175 #define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4176 #define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4177 #define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4178 #define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4179 #define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4180 #define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4181 #define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4182 #define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4183 #define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4184 #define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4185 #define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4186 #define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4187 #define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4188 #define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4189 #define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4190 #define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4191 #define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4192 #define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4193 #define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4194 #define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4195 #define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4196 #define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4197 #define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4198 #define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4199 #define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4200 #define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4201 #define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4202 #define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4203 #define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4204 #define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4205 #define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4206 #define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4207 #define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4208 #define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4209 #define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4210 #define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4211 #define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4212 #define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4213 #define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4214 #define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4215 #define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4216 #define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4217 #define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4218 #define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4219 #define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4220 #define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4221 #define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4222 #define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4223 #define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4224 #define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4225 #define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4226 #define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4227 #define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4228 #define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4229 #define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4230 #define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4231 #define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4232 #define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4233 #define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4234 #define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4235 #define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */
4236 #define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */
4237 #define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4238 #define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */
4239 #define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4240 #define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4241 #define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4242 #define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4243 #define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4244 #define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4245 #define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4246 #define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4247 #define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */
4248 #define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */
4249 #define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */
4250 #define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */
4251 #define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4252 #define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4253 #define ADC0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4254 #define ADC0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4255 #define ADC1_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4256 #define ADC1_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4257 #define ADC1_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4258 #define ADC1_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4259 #define AOI0_TRIGOUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 12) /* PIO1_4 */
4260 #define AOI1_TRIGOUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 12) /* PIO1_4 */
4261 #define CTIMER2_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */
4262 #define DMA0_TRIG00_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4263 #define DMA0_TRIG010_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4264 #define DMA0_TRIG011_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4265 #define DMA0_TRIG012_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4266 #define DMA0_TRIG013_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4267 #define DMA0_TRIG014_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4268 #define DMA0_TRIG015_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4269 #define DMA0_TRIG016_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4270 #define DMA0_TRIG017_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4271 #define DMA0_TRIG018_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4272 #define DMA0_TRIG019_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4273 #define DMA0_TRIG01_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4274 #define DMA0_TRIG020_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4275 #define DMA0_TRIG021_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4276 #define DMA0_TRIG022_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4277 #define DMA0_TRIG023_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4278 #define DMA0_TRIG024_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4279 #define DMA0_TRIG025_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4280 #define DMA0_TRIG026_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4281 #define DMA0_TRIG027_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4282 #define DMA0_TRIG028_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4283 #define DMA0_TRIG029_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4284 #define DMA0_TRIG02_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4285 #define DMA0_TRIG030_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4286 #define DMA0_TRIG031_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4287 #define DMA0_TRIG032_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4288 #define DMA0_TRIG033_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4289 #define DMA0_TRIG034_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4290 #define DMA0_TRIG035_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4291 #define DMA0_TRIG036_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4292 #define DMA0_TRIG037_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4293 #define DMA0_TRIG038_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4294 #define DMA0_TRIG039_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4295 #define DMA0_TRIG03_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4296 #define DMA0_TRIG040_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4297 #define DMA0_TRIG041_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4298 #define DMA0_TRIG042_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4299 #define DMA0_TRIG043_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4300 #define DMA0_TRIG044_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4301 #define DMA0_TRIG045_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4302 #define DMA0_TRIG046_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4303 #define DMA0_TRIG047_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4304 #define DMA0_TRIG048_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4305 #define DMA0_TRIG049_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4306 #define DMA0_TRIG04_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4307 #define DMA0_TRIG050_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4308 #define DMA0_TRIG051_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4309 #define DMA0_TRIG05_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4310 #define DMA0_TRIG06_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4311 #define DMA0_TRIG07_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4312 #define DMA0_TRIG08_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4313 #define DMA0_TRIG09_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4314 #define DMA1_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4315 #define DMA1_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4316 #define DMA1_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4317 #define DMA1_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4318 #define DMA1_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4319 #define DMA1_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4320 #define DMA1_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4321 #define DMA1_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4322 #define DMA1_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4323 #define DMA1_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4324 #define ENC0_PHASEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4325 #define ENC0_PHASEB_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4326 #define ENC1_PHASEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4327 #define ENC1_PHASEB_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4328 #define EXTTRIG_IN8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4329 #define FC0_SCK_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 1) /* PIO1_4 */
4330 #define FC4_TXD_SCL_MISO_WS_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 7) /* PIO1_4 */
4331 #define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4332 #define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4333 #define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4334 #define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4335 #define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4336 #define PINT_PINT4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4337 #define PINT_PINT5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4338 #define PINT_PINT6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4339 #define PINT_PINT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4340 #define PIO1_4_PIO1_4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */
4341 #define PWM0_B2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 11) /* PIO1_4 */
4342 #define PWM0_EXTA0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4343 #define PWM0_EXTA1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4344 #define PWM0_EXTA2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4345 #define PWM0_EXTA3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4346 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4347 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4348 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4349 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4350 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4351 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4352 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4353 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4354 #define PWM1_EXTA0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4355 #define PWM1_EXTA1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4356 #define PWM1_EXTA2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4357 #define PWM1_EXTA3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4358 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4359 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4360 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4361 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4362 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4363 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4364 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4365 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 13) /* PIO1_4 */
4366 #define SCT0_OUT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 4) /* PIO1_4 */
4367 #define SPI_DIN_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 10) /* PIO1_4 */
4368 #define SYSCON_FREQMEA_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */
4369 #define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4370 #define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4371 #define ADC0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4372 #define ADC0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4373 #define ADC1_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4374 #define ADC1_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4375 #define ADC1_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4376 #define ADC1_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4377 #define AOI0_TRIGOUT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 12) /* PIO1_5 */
4378 #define AOI1_TRIGOUT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 12) /* PIO1_5 */
4379 #define CTIMER2_MATCH0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 3) /* PIO1_5 */
4380 #define DMA0_TRIG00_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4381 #define DMA0_TRIG010_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4382 #define DMA0_TRIG011_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4383 #define DMA0_TRIG012_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4384 #define DMA0_TRIG013_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4385 #define DMA0_TRIG014_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4386 #define DMA0_TRIG015_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4387 #define DMA0_TRIG016_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4388 #define DMA0_TRIG017_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4389 #define DMA0_TRIG018_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4390 #define DMA0_TRIG019_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4391 #define DMA0_TRIG01_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4392 #define DMA0_TRIG020_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4393 #define DMA0_TRIG021_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4394 #define DMA0_TRIG022_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4395 #define DMA0_TRIG023_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4396 #define DMA0_TRIG024_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4397 #define DMA0_TRIG025_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4398 #define DMA0_TRIG026_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4399 #define DMA0_TRIG027_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4400 #define DMA0_TRIG028_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4401 #define DMA0_TRIG029_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4402 #define DMA0_TRIG02_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4403 #define DMA0_TRIG030_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4404 #define DMA0_TRIG031_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4405 #define DMA0_TRIG032_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4406 #define DMA0_TRIG033_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4407 #define DMA0_TRIG034_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4408 #define DMA0_TRIG035_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4409 #define DMA0_TRIG036_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4410 #define DMA0_TRIG037_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4411 #define DMA0_TRIG038_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4412 #define DMA0_TRIG039_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4413 #define DMA0_TRIG03_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4414 #define DMA0_TRIG040_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4415 #define DMA0_TRIG041_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4416 #define DMA0_TRIG042_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4417 #define DMA0_TRIG043_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4418 #define DMA0_TRIG044_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4419 #define DMA0_TRIG045_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4420 #define DMA0_TRIG046_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4421 #define DMA0_TRIG047_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4422 #define DMA0_TRIG048_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4423 #define DMA0_TRIG049_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4424 #define DMA0_TRIG04_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4425 #define DMA0_TRIG050_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4426 #define DMA0_TRIG051_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4427 #define DMA0_TRIG05_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4428 #define DMA0_TRIG06_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4429 #define DMA0_TRIG07_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4430 #define DMA0_TRIG08_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4431 #define DMA0_TRIG09_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4432 #define DMA1_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4433 #define DMA1_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4434 #define DMA1_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4435 #define DMA1_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4436 #define DMA1_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4437 #define DMA1_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4438 #define DMA1_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4439 #define DMA1_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4440 #define DMA1_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4441 #define DMA1_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4442 #define FC0_RXD_SDA_MOSI_DATA_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 1) /* PIO1_5 */
4443 #define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4444 #define HSCMP0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4445 #define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4446 #define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4447 #define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4448 #define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4449 #define PINT_PINT4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4450 #define PINT_PINT5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4451 #define PINT_PINT6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4452 #define PINT_PINT7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4453 #define PIO1_5_PIO1_5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 0) /* PIO1_5 */
4454 #define PWM1_A3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 11) /* PIO1_5 */
4455 #define SCT0_IN0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
4456 #define SCT0_IN1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
4457 #define SCT0_IN2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
4458 #define SCT0_IN3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
4459 #define SCT0_IN4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
4460 #define SCT0_IN5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
4461 #define SCT0_IN6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_A, 4) /* PIO1_5 */
4462 #define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4463 #define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4464 #define ADC0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4465 #define ADC0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4466 #define ADC1_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4467 #define ADC1_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4468 #define ADC1_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4469 #define ADC1_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4470 #define AOI0_TRIGOUT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 12) /* PIO1_6 */
4471 #define AOI1_TRIGOUT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 12) /* PIO1_6 */
4472 #define CTIMER2_MATCH1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */
4473 #define DMA0_TRIG00_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4474 #define DMA0_TRIG010_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4475 #define DMA0_TRIG011_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4476 #define DMA0_TRIG012_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4477 #define DMA0_TRIG013_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4478 #define DMA0_TRIG014_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4479 #define DMA0_TRIG015_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4480 #define DMA0_TRIG016_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4481 #define DMA0_TRIG017_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4482 #define DMA0_TRIG018_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4483 #define DMA0_TRIG019_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4484 #define DMA0_TRIG01_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4485 #define DMA0_TRIG020_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4486 #define DMA0_TRIG021_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4487 #define DMA0_TRIG022_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4488 #define DMA0_TRIG023_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4489 #define DMA0_TRIG024_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4490 #define DMA0_TRIG025_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4491 #define DMA0_TRIG026_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4492 #define DMA0_TRIG027_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4493 #define DMA0_TRIG028_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4494 #define DMA0_TRIG029_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4495 #define DMA0_TRIG02_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4496 #define DMA0_TRIG030_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4497 #define DMA0_TRIG031_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4498 #define DMA0_TRIG032_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4499 #define DMA0_TRIG033_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4500 #define DMA0_TRIG034_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4501 #define DMA0_TRIG035_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4502 #define DMA0_TRIG036_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4503 #define DMA0_TRIG037_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4504 #define DMA0_TRIG038_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4505 #define DMA0_TRIG039_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4506 #define DMA0_TRIG03_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4507 #define DMA0_TRIG040_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4508 #define DMA0_TRIG041_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4509 #define DMA0_TRIG042_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4510 #define DMA0_TRIG043_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4511 #define DMA0_TRIG044_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4512 #define DMA0_TRIG045_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4513 #define DMA0_TRIG046_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4514 #define DMA0_TRIG047_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4515 #define DMA0_TRIG048_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4516 #define DMA0_TRIG049_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4517 #define DMA0_TRIG04_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4518 #define DMA0_TRIG050_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4519 #define DMA0_TRIG051_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4520 #define DMA0_TRIG05_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4521 #define DMA0_TRIG06_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4522 #define DMA0_TRIG07_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4523 #define DMA0_TRIG08_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4524 #define DMA0_TRIG09_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4525 #define DMA1_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4526 #define DMA1_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4527 #define DMA1_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4528 #define DMA1_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4529 #define DMA1_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4530 #define DMA1_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4531 #define DMA1_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4532 #define DMA1_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4533 #define DMA1_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4534 #define DMA1_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4535 #define FC0_TXD_SCL_MISO_WS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 1) /* PIO1_6 */
4536 #define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4537 #define HSCMP0_OUT_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 13) /* PIO1_6 */
4538 #define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4539 #define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4540 #define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4541 #define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4542 #define PINT_PINT4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4543 #define PINT_PINT5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4544 #define PINT_PINT6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4545 #define PINT_PINT7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4546 #define PIO1_6_PIO1_6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */
4547 #define PWM0_A1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 11) /* PIO1_6 */
4548 #define SCT0_IN0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
4549 #define SCT0_IN1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
4550 #define SCT0_IN2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
4551 #define SCT0_IN3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
4552 #define SCT0_IN4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
4553 #define SCT0_IN5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
4554 #define SCT0_IN6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 4) /* PIO1_6 */
4555 #define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4556 #define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4557 #define ADC0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4558 #define ADC0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4559 #define ADC1_CH3B_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4560 #define ADC1_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4561 #define ADC1_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4562 #define ADC1_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4563 #define ADC1_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4564 #define AOI1_OUT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 12) /* PIO1_7 */
4565 #define CTIMER2_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */
4566 #define DMA0_TRIG00_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4567 #define DMA0_TRIG010_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4568 #define DMA0_TRIG011_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4569 #define DMA0_TRIG012_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4570 #define DMA0_TRIG013_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4571 #define DMA0_TRIG014_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4572 #define DMA0_TRIG015_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4573 #define DMA0_TRIG016_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4574 #define DMA0_TRIG017_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4575 #define DMA0_TRIG018_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4576 #define DMA0_TRIG019_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4577 #define DMA0_TRIG01_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4578 #define DMA0_TRIG020_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4579 #define DMA0_TRIG021_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4580 #define DMA0_TRIG022_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4581 #define DMA0_TRIG023_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4582 #define DMA0_TRIG024_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4583 #define DMA0_TRIG025_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4584 #define DMA0_TRIG026_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4585 #define DMA0_TRIG027_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4586 #define DMA0_TRIG028_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4587 #define DMA0_TRIG029_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4588 #define DMA0_TRIG02_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4589 #define DMA0_TRIG030_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4590 #define DMA0_TRIG031_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4591 #define DMA0_TRIG032_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4592 #define DMA0_TRIG033_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4593 #define DMA0_TRIG034_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4594 #define DMA0_TRIG035_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4595 #define DMA0_TRIG036_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4596 #define DMA0_TRIG037_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4597 #define DMA0_TRIG038_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4598 #define DMA0_TRIG039_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4599 #define DMA0_TRIG03_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4600 #define DMA0_TRIG040_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4601 #define DMA0_TRIG041_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4602 #define DMA0_TRIG042_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4603 #define DMA0_TRIG043_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4604 #define DMA0_TRIG044_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4605 #define DMA0_TRIG045_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4606 #define DMA0_TRIG046_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4607 #define DMA0_TRIG047_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4608 #define DMA0_TRIG048_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4609 #define DMA0_TRIG049_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4610 #define DMA0_TRIG04_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4611 #define DMA0_TRIG050_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4612 #define DMA0_TRIG051_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4613 #define DMA0_TRIG05_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4614 #define DMA0_TRIG06_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4615 #define DMA0_TRIG07_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4616 #define DMA0_TRIG08_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4617 #define DMA0_TRIG09_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4618 #define DMA1_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4619 #define DMA1_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4620 #define DMA1_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4621 #define DMA1_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4622 #define DMA1_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4623 #define DMA1_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4624 #define DMA1_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4625 #define DMA1_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4626 #define DMA1_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4627 #define DMA1_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4628 #define FC0_RTS_SCL_SSEL1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 1) /* PIO1_7 */
4629 #define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4630 #define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4631 #define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4632 #define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4633 #define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4634 #define PINT_PINT4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4635 #define PINT_PINT5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4636 #define PINT_PINT6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4637 #define PINT_PINT7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4638 #define PIO1_7_PIO1_7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */
4639 #define SCT0_IN0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
4640 #define SCT0_IN1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
4641 #define SCT0_IN2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
4642 #define SCT0_IN3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
4643 #define SCT0_IN4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
4644 #define SCT0_IN5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
4645 #define SCT0_IN6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 4) /* PIO1_7 */
4646 #define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4647 #define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4648 #define ADC0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4649 #define ADC0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4650 #define ADC1_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4651 #define ADC1_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4652 #define ADC1_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4653 #define ADC1_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4654 #define AOI0_TRIGOUT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 13) /* PIO1_8 */
4655 #define AOI1_OUT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 12) /* PIO1_8 */
4656 #define AOI1_TRIGOUT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 13) /* PIO1_8 */
4657 #define DMA0_TRIG00_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4658 #define DMA0_TRIG010_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4659 #define DMA0_TRIG011_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4660 #define DMA0_TRIG012_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4661 #define DMA0_TRIG013_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4662 #define DMA0_TRIG014_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4663 #define DMA0_TRIG015_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4664 #define DMA0_TRIG016_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4665 #define DMA0_TRIG017_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4666 #define DMA0_TRIG018_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4667 #define DMA0_TRIG019_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4668 #define DMA0_TRIG01_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4669 #define DMA0_TRIG020_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4670 #define DMA0_TRIG021_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4671 #define DMA0_TRIG022_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4672 #define DMA0_TRIG023_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4673 #define DMA0_TRIG024_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4674 #define DMA0_TRIG025_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4675 #define DMA0_TRIG026_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4676 #define DMA0_TRIG027_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4677 #define DMA0_TRIG028_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4678 #define DMA0_TRIG029_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4679 #define DMA0_TRIG02_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4680 #define DMA0_TRIG030_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4681 #define DMA0_TRIG031_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4682 #define DMA0_TRIG032_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4683 #define DMA0_TRIG033_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4684 #define DMA0_TRIG034_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4685 #define DMA0_TRIG035_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4686 #define DMA0_TRIG036_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4687 #define DMA0_TRIG037_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4688 #define DMA0_TRIG038_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4689 #define DMA0_TRIG039_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4690 #define DMA0_TRIG03_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4691 #define DMA0_TRIG040_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4692 #define DMA0_TRIG041_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4693 #define DMA0_TRIG042_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4694 #define DMA0_TRIG043_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4695 #define DMA0_TRIG044_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4696 #define DMA0_TRIG045_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4697 #define DMA0_TRIG046_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4698 #define DMA0_TRIG047_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4699 #define DMA0_TRIG048_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4700 #define DMA0_TRIG049_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4701 #define DMA0_TRIG04_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4702 #define DMA0_TRIG050_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4703 #define DMA0_TRIG051_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4704 #define DMA0_TRIG05_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4705 #define DMA0_TRIG06_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4706 #define DMA0_TRIG07_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4707 #define DMA0_TRIG08_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4708 #define DMA0_TRIG09_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4709 #define DMA1_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4710 #define DMA1_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4711 #define DMA1_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4712 #define DMA1_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4713 #define DMA1_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4714 #define DMA1_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4715 #define DMA1_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4716 #define DMA1_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4717 #define DMA1_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4718 #define DMA1_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4719 #define FC0_CTS_SDA_SSEL0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 1) /* PIO1_8 */
4720 #define FC1_SCK_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 7) /* PIO1_8 */
4721 #define FC4_SSEL2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */
4722 #define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4723 #define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4724 #define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4725 #define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4726 #define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4727 #define PINT_PINT4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4728 #define PINT_PINT5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4729 #define PINT_PINT6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4730 #define PINT_PINT7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4731 #define PIO1_8_PIO1_8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */
4732 #define PWM0_A2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 11) /* PIO1_8 */
4733 #define SCT0_OUT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 4) /* PIO1_8 */
4734 #define ADC0_CH0A_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4735 #define ADC0_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4736 #define ADC0_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4737 #define ADC0_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4738 #define ADC0_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4739 #define ADC1_TRIG0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4740 #define ADC1_TRIG1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4741 #define ADC1_TRIG2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4742 #define ADC1_TRIG3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4743 #define AOI1_OUT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 12) /* PIO1_9 */
4744 #define CTIMER0_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4745 #define CTIMER0_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4746 #define CTIMER0_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4747 #define CTIMER0_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4748 #define CTIMER1_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4749 #define CTIMER1_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4750 #define CTIMER1_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4751 #define CTIMER1_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4752 #define CTIMER2_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4753 #define CTIMER2_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4754 #define CTIMER2_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4755 #define CTIMER2_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4756 #define CTIMER3_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4757 #define CTIMER3_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4758 #define CTIMER3_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4759 #define CTIMER3_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4760 #define CTIMER4_CAPTURE0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4761 #define CTIMER4_CAPTURE1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4762 #define CTIMER4_CAPTURE2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4763 #define CTIMER4_CAPTURE3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4764 #define CT_INP4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 3) /* PIO1_9 */
4765 #define DMA0_TRIG00_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4766 #define DMA0_TRIG010_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4767 #define DMA0_TRIG011_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4768 #define DMA0_TRIG012_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4769 #define DMA0_TRIG013_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4770 #define DMA0_TRIG014_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4771 #define DMA0_TRIG015_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4772 #define DMA0_TRIG016_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4773 #define DMA0_TRIG017_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4774 #define DMA0_TRIG018_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4775 #define DMA0_TRIG019_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4776 #define DMA0_TRIG01_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4777 #define DMA0_TRIG020_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4778 #define DMA0_TRIG021_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4779 #define DMA0_TRIG022_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4780 #define DMA0_TRIG023_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4781 #define DMA0_TRIG024_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4782 #define DMA0_TRIG025_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4783 #define DMA0_TRIG026_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4784 #define DMA0_TRIG027_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4785 #define DMA0_TRIG028_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4786 #define DMA0_TRIG029_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4787 #define DMA0_TRIG02_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4788 #define DMA0_TRIG030_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4789 #define DMA0_TRIG031_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4790 #define DMA0_TRIG032_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4791 #define DMA0_TRIG033_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4792 #define DMA0_TRIG034_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4793 #define DMA0_TRIG035_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4794 #define DMA0_TRIG036_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4795 #define DMA0_TRIG037_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4796 #define DMA0_TRIG038_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4797 #define DMA0_TRIG039_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4798 #define DMA0_TRIG03_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4799 #define DMA0_TRIG040_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4800 #define DMA0_TRIG041_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4801 #define DMA0_TRIG042_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4802 #define DMA0_TRIG043_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4803 #define DMA0_TRIG044_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4804 #define DMA0_TRIG045_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4805 #define DMA0_TRIG046_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4806 #define DMA0_TRIG047_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4807 #define DMA0_TRIG048_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4808 #define DMA0_TRIG049_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4809 #define DMA0_TRIG04_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4810 #define DMA0_TRIG050_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4811 #define DMA0_TRIG051_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4812 #define DMA0_TRIG05_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4813 #define DMA0_TRIG06_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4814 #define DMA0_TRIG07_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4815 #define DMA0_TRIG08_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4816 #define DMA0_TRIG09_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4817 #define DMA1_TRIG10_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4818 #define DMA1_TRIG11_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4819 #define DMA1_TRIG12_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4820 #define DMA1_TRIG13_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4821 #define DMA1_TRIG14_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4822 #define DMA1_TRIG15_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4823 #define DMA1_TRIG16_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4824 #define DMA1_TRIG17_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4825 #define DMA1_TRIG18_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4826 #define DMA1_TRIG19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4827 #define FC1_SCK_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 2) /* PIO1_9 */
4828 #define FC4_CTS_SDA_SSEL0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 5) /* PIO1_9 */
4829 #define GPIO_PIO19_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4830 #define HSCMP0_IN4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4831 #define OPAMP0_OUT_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4832 #define PINT_PINT0_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4833 #define PINT_PINT1_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4834 #define PINT_PINT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4835 #define PINT_PINT3_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4836 #define PINT_PINT4_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4837 #define PINT_PINT5_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4838 #define PINT_PINT6_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4839 #define PINT_PINT7_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4840 #define PIO1_9_PIO1_9_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 0) /* PIO1_9 */
4841 #define SCT0_OUT2_PIO1_9 IOCON_MUX(41, IOCON_TYPE_A, 4) /* PIO1_9 */
4842 #define ADC0_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4843 #define ADC0_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4844 #define ADC0_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4845 #define ADC0_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4846 #define ADC1_TRIG0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4847 #define ADC1_TRIG1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4848 #define ADC1_TRIG2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4849 #define ADC1_TRIG3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4850 #define AOI0_TRIGOUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 12) /* PIO1_10 */
4851 #define AOI1_TRIGOUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 12) /* PIO1_10 */
4852 #define CTIMER1_MATCH0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 3) /* PIO1_10 */
4853 #define DMA0_TRIG00_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4854 #define DMA0_TRIG010_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4855 #define DMA0_TRIG011_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4856 #define DMA0_TRIG012_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4857 #define DMA0_TRIG013_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4858 #define DMA0_TRIG014_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4859 #define DMA0_TRIG015_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4860 #define DMA0_TRIG016_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4861 #define DMA0_TRIG017_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4862 #define DMA0_TRIG018_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4863 #define DMA0_TRIG019_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4864 #define DMA0_TRIG01_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4865 #define DMA0_TRIG020_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4866 #define DMA0_TRIG021_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4867 #define DMA0_TRIG022_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4868 #define DMA0_TRIG023_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4869 #define DMA0_TRIG024_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4870 #define DMA0_TRIG025_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4871 #define DMA0_TRIG026_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4872 #define DMA0_TRIG027_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4873 #define DMA0_TRIG028_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4874 #define DMA0_TRIG029_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4875 #define DMA0_TRIG02_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4876 #define DMA0_TRIG030_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4877 #define DMA0_TRIG031_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4878 #define DMA0_TRIG032_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4879 #define DMA0_TRIG033_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4880 #define DMA0_TRIG034_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4881 #define DMA0_TRIG035_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4882 #define DMA0_TRIG036_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4883 #define DMA0_TRIG037_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4884 #define DMA0_TRIG038_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4885 #define DMA0_TRIG039_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4886 #define DMA0_TRIG03_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4887 #define DMA0_TRIG040_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4888 #define DMA0_TRIG041_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4889 #define DMA0_TRIG042_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4890 #define DMA0_TRIG043_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4891 #define DMA0_TRIG044_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4892 #define DMA0_TRIG045_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4893 #define DMA0_TRIG046_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4894 #define DMA0_TRIG047_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4895 #define DMA0_TRIG048_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4896 #define DMA0_TRIG049_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4897 #define DMA0_TRIG04_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4898 #define DMA0_TRIG050_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4899 #define DMA0_TRIG051_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4900 #define DMA0_TRIG05_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4901 #define DMA0_TRIG06_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4902 #define DMA0_TRIG07_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4903 #define DMA0_TRIG08_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4904 #define DMA0_TRIG09_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4905 #define DMA1_TRIG10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4906 #define DMA1_TRIG11_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4907 #define DMA1_TRIG12_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4908 #define DMA1_TRIG13_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4909 #define DMA1_TRIG14_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4910 #define DMA1_TRIG15_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4911 #define DMA1_TRIG16_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4912 #define DMA1_TRIG17_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4913 #define DMA1_TRIG18_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4914 #define DMA1_TRIG19_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4915 #define FC1_RXD_SDA_MOSI_DATA_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 2) /* PIO1_10 */
4916 #define GPIO_PIO110_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4917 #define HSCMP1_IN3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4918 #define HSCMP2_OUT_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 13) /* PIO1_10 */
4919 #define PINT_PINT0_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4920 #define PINT_PINT1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4921 #define PINT_PINT2_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4922 #define PINT_PINT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4923 #define PINT_PINT4_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4924 #define PINT_PINT5_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4925 #define PINT_PINT6_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4926 #define PINT_PINT7_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4927 #define PIO1_10_PIO1_10_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 0) /* PIO1_10 */
4928 #define PWM0_X1_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 11) /* PIO1_10 */
4929 #define SCT0_OUT3_PIO1_10 IOCON_MUX(42, IOCON_TYPE_A, 4) /* PIO1_10 */
4930 #define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4931 #define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4932 #define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4933 #define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4934 #define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4935 #define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4936 #define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4937 #define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4938 #define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4939 #define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4940 #define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4941 #define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4942 #define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4943 #define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4944 #define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4945 #define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4946 #define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4947 #define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4948 #define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4949 #define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4950 #define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4951 #define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4952 #define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4953 #define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4954 #define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4955 #define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4956 #define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4957 #define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4958 #define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */
4959 #define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4960 #define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4961 #define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4962 #define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4963 #define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4964 #define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4965 #define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4966 #define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4967 #define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4968 #define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4969 #define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4970 #define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4971 #define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4972 #define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4973 #define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4974 #define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4975 #define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4976 #define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4977 #define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4978 #define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4979 #define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4980 #define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4981 #define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4982 #define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4983 #define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4984 #define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4985 #define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4986 #define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4987 #define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4988 #define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4989 #define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4990 #define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4991 #define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4992 #define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4993 #define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4994 #define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4995 #define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4996 #define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4997 #define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4998 #define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
4999 #define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5000 #define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5001 #define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5002 #define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5003 #define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5004 #define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5005 #define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5006 #define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5007 #define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5008 #define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5009 #define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5010 #define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5011 #define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5012 #define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5013 #define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5014 #define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5015 #define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5016 #define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5017 #define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5018 #define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5019 #define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5020 #define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5021 #define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5022 #define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5023 #define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5024 #define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5025 #define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5026 #define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */
5027 #define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */
5028 #define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5029 #define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */
5030 #define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5031 #define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5032 #define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5033 #define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5034 #define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5035 #define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5036 #define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5037 #define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5038 #define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */
5039 #define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */
5040 #define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5041 #define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5042 #define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5043 #define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5044 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5045 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5046 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5047 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5048 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5049 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5050 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5051 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5052 #define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5053 #define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5054 #define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5055 #define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5056 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5057 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5058 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5059 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5060 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5061 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5062 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5063 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */
5064 #define SPI_SCLK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 12) /* PIO1_11 */
5065 #define USB0_VBUS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 4) /* PIO1_11 */
5066 #define ADC0_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5067 #define ADC0_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5068 #define ADC0_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5069 #define ADC0_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5070 #define ADC1_TRIG0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5071 #define ADC1_TRIG1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5072 #define ADC1_TRIG2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5073 #define ADC1_TRIG3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5074 #define AOI0_OUT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 12) /* PIO1_12 */
5075 #define CTIMER1_MATCH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 3) /* PIO1_12 */
5076 #define DMA0_TRIG00_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5077 #define DMA0_TRIG010_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5078 #define DMA0_TRIG011_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5079 #define DMA0_TRIG012_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5080 #define DMA0_TRIG013_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5081 #define DMA0_TRIG014_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5082 #define DMA0_TRIG015_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5083 #define DMA0_TRIG016_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5084 #define DMA0_TRIG017_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5085 #define DMA0_TRIG018_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5086 #define DMA0_TRIG019_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5087 #define DMA0_TRIG01_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5088 #define DMA0_TRIG020_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5089 #define DMA0_TRIG021_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5090 #define DMA0_TRIG022_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5091 #define DMA0_TRIG023_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5092 #define DMA0_TRIG024_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5093 #define DMA0_TRIG025_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5094 #define DMA0_TRIG026_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5095 #define DMA0_TRIG027_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5096 #define DMA0_TRIG028_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5097 #define DMA0_TRIG029_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5098 #define DMA0_TRIG02_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5099 #define DMA0_TRIG030_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5100 #define DMA0_TRIG031_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5101 #define DMA0_TRIG032_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5102 #define DMA0_TRIG033_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5103 #define DMA0_TRIG034_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5104 #define DMA0_TRIG035_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5105 #define DMA0_TRIG036_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5106 #define DMA0_TRIG037_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5107 #define DMA0_TRIG038_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5108 #define DMA0_TRIG039_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5109 #define DMA0_TRIG03_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5110 #define DMA0_TRIG040_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5111 #define DMA0_TRIG041_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5112 #define DMA0_TRIG042_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5113 #define DMA0_TRIG043_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5114 #define DMA0_TRIG044_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5115 #define DMA0_TRIG045_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5116 #define DMA0_TRIG046_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5117 #define DMA0_TRIG047_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5118 #define DMA0_TRIG048_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5119 #define DMA0_TRIG049_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5120 #define DMA0_TRIG04_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5121 #define DMA0_TRIG050_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5122 #define DMA0_TRIG051_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5123 #define DMA0_TRIG05_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5124 #define DMA0_TRIG06_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5125 #define DMA0_TRIG07_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5126 #define DMA0_TRIG08_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5127 #define DMA0_TRIG09_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5128 #define DMA1_TRIG10_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5129 #define DMA1_TRIG11_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5130 #define DMA1_TRIG12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5131 #define DMA1_TRIG13_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5132 #define DMA1_TRIG14_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5133 #define DMA1_TRIG15_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5134 #define DMA1_TRIG16_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5135 #define DMA1_TRIG17_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5136 #define DMA1_TRIG18_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5137 #define DMA1_TRIG19_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5138 #define ENC0_PHASEA_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5139 #define ENC0_PHASEB_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5140 #define ENC1_PHASEA_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5141 #define ENC1_PHASEB_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5142 #define EXTTRIG_IN9_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5143 #define FC6_SCK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 2) /* PIO1_12 */
5144 #define GPIO_PIO112_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5145 #define HSCMP0_IN1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5146 #define HS_SPI_SSEL2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 5) /* PIO1_12 */
5147 #define PINT_PINT0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5148 #define PINT_PINT1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5149 #define PINT_PINT2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5150 #define PINT_PINT3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5151 #define PINT_PINT4_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5152 #define PINT_PINT5_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5153 #define PINT_PINT6_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5154 #define PINT_PINT7_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5155 #define PIO1_12_PIO1_12_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 0) /* PIO1_12 */
5156 #define PWM0_A3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 11) /* PIO1_12 */
5157 #define PWM0_EXTA0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5158 #define PWM0_EXTA1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5159 #define PWM0_EXTA2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5160 #define PWM0_EXTA3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5161 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5162 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5163 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5164 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5165 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5166 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5167 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5168 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5169 #define PWM1_EXTA0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5170 #define PWM1_EXTA1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5171 #define PWM1_EXTA2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5172 #define PWM1_EXTA3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5173 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5174 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5175 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5176 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5177 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5178 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5179 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5180 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 13) /* PIO1_12 */
5181 #define QSPI_SCLK_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 10) /* PIO1_12 */
5182 #define USB0_PORTPWRN_PIO1_12 IOCON_MUX(44, IOCON_TYPE_A, 4) /* PIO1_12 */
5183 #define ACMP0VREF_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5184 #define ADC0_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5185 #define ADC0_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5186 #define ADC0_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5187 #define ADC0_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5188 #define ADC1_TRIG0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5189 #define ADC1_TRIG1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5190 #define ADC1_TRIG2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5191 #define ADC1_TRIG3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5192 #define AOI0_OUT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 12) /* PIO1_13 */
5193 #define CTIMER0_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5194 #define CTIMER0_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5195 #define CTIMER0_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5196 #define CTIMER0_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5197 #define CTIMER1_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5198 #define CTIMER1_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5199 #define CTIMER1_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5200 #define CTIMER1_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5201 #define CTIMER2_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5202 #define CTIMER2_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5203 #define CTIMER2_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5204 #define CTIMER2_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5205 #define CTIMER3_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5206 #define CTIMER3_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5207 #define CTIMER3_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5208 #define CTIMER3_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5209 #define CTIMER4_CAPTURE0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5210 #define CTIMER4_CAPTURE1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5211 #define CTIMER4_CAPTURE2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5212 #define CTIMER4_CAPTURE3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5213 #define CT_INP6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 3) /* PIO1_13 */
5214 #define DMA0_TRIG00_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5215 #define DMA0_TRIG010_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5216 #define DMA0_TRIG011_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5217 #define DMA0_TRIG012_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5218 #define DMA0_TRIG013_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5219 #define DMA0_TRIG014_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5220 #define DMA0_TRIG015_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5221 #define DMA0_TRIG016_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5222 #define DMA0_TRIG017_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5223 #define DMA0_TRIG018_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5224 #define DMA0_TRIG019_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5225 #define DMA0_TRIG01_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5226 #define DMA0_TRIG020_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5227 #define DMA0_TRIG021_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5228 #define DMA0_TRIG022_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5229 #define DMA0_TRIG023_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5230 #define DMA0_TRIG024_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5231 #define DMA0_TRIG025_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5232 #define DMA0_TRIG026_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5233 #define DMA0_TRIG027_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5234 #define DMA0_TRIG028_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5235 #define DMA0_TRIG029_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5236 #define DMA0_TRIG02_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5237 #define DMA0_TRIG030_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5238 #define DMA0_TRIG031_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5239 #define DMA0_TRIG032_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5240 #define DMA0_TRIG033_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5241 #define DMA0_TRIG034_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5242 #define DMA0_TRIG035_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5243 #define DMA0_TRIG036_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5244 #define DMA0_TRIG037_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5245 #define DMA0_TRIG038_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5246 #define DMA0_TRIG039_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5247 #define DMA0_TRIG03_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5248 #define DMA0_TRIG040_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5249 #define DMA0_TRIG041_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5250 #define DMA0_TRIG042_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5251 #define DMA0_TRIG043_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5252 #define DMA0_TRIG044_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5253 #define DMA0_TRIG045_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5254 #define DMA0_TRIG046_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5255 #define DMA0_TRIG047_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5256 #define DMA0_TRIG048_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5257 #define DMA0_TRIG049_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5258 #define DMA0_TRIG04_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5259 #define DMA0_TRIG050_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5260 #define DMA0_TRIG051_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5261 #define DMA0_TRIG05_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5262 #define DMA0_TRIG06_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5263 #define DMA0_TRIG07_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5264 #define DMA0_TRIG08_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5265 #define DMA0_TRIG09_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5266 #define DMA1_TRIG10_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5267 #define DMA1_TRIG11_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5268 #define DMA1_TRIG12_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5269 #define DMA1_TRIG13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5270 #define DMA1_TRIG14_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5271 #define DMA1_TRIG15_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5272 #define DMA1_TRIG16_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5273 #define DMA1_TRIG17_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5274 #define DMA1_TRIG18_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5275 #define DMA1_TRIG19_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5276 #define FC6_RXD_SDA_MOSI_DATA_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 2) /* PIO1_13 */
5277 #define GPIO_PIO113_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5278 #define PINT_PINT0_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5279 #define PINT_PINT1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5280 #define PINT_PINT2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5281 #define PINT_PINT3_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5282 #define PINT_PINT4_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5283 #define PINT_PINT5_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5284 #define PINT_PINT6_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5285 #define PINT_PINT7_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5286 #define PIO1_13_PIO1_13_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 0) /* PIO1_13 */
5287 #define PWM1_X1_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 11) /* PIO1_13 */
5288 #define QSPI_DIN2_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 10) /* PIO1_13 */
5289 #define SCT0_OUT8_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 8) /* PIO1_13 */
5290 #define USB0_FRAME_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 5) /* PIO1_13 */
5291 #define USB0_OVERCURRENTN_PIO1_13 IOCON_MUX(45, IOCON_TYPE_A, 4) /* PIO1_13 */
5292 #define ADC0_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5293 #define ADC0_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5294 #define ADC0_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5295 #define ADC0_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5296 #define ADC1_TRIG0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5297 #define ADC1_TRIG1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5298 #define ADC1_TRIG2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5299 #define ADC1_TRIG3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5300 #define CTIMER1_MATCH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 3) /* PIO1_14 */
5301 #define DMA0_TRIG00_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5302 #define DMA0_TRIG010_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5303 #define DMA0_TRIG011_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5304 #define DMA0_TRIG012_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5305 #define DMA0_TRIG013_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5306 #define DMA0_TRIG014_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5307 #define DMA0_TRIG015_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5308 #define DMA0_TRIG016_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5309 #define DMA0_TRIG017_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5310 #define DMA0_TRIG018_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5311 #define DMA0_TRIG019_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5312 #define DMA0_TRIG01_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5313 #define DMA0_TRIG020_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5314 #define DMA0_TRIG021_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5315 #define DMA0_TRIG022_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5316 #define DMA0_TRIG023_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5317 #define DMA0_TRIG024_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5318 #define DMA0_TRIG025_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5319 #define DMA0_TRIG026_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5320 #define DMA0_TRIG027_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5321 #define DMA0_TRIG028_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5322 #define DMA0_TRIG029_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5323 #define DMA0_TRIG02_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5324 #define DMA0_TRIG030_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5325 #define DMA0_TRIG031_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5326 #define DMA0_TRIG032_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5327 #define DMA0_TRIG033_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5328 #define DMA0_TRIG034_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5329 #define DMA0_TRIG035_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5330 #define DMA0_TRIG036_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5331 #define DMA0_TRIG037_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5332 #define DMA0_TRIG038_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5333 #define DMA0_TRIG039_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5334 #define DMA0_TRIG03_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5335 #define DMA0_TRIG040_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5336 #define DMA0_TRIG041_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5337 #define DMA0_TRIG042_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5338 #define DMA0_TRIG043_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5339 #define DMA0_TRIG044_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5340 #define DMA0_TRIG045_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5341 #define DMA0_TRIG046_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5342 #define DMA0_TRIG047_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5343 #define DMA0_TRIG048_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5344 #define DMA0_TRIG049_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5345 #define DMA0_TRIG04_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5346 #define DMA0_TRIG050_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5347 #define DMA0_TRIG051_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5348 #define DMA0_TRIG05_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5349 #define DMA0_TRIG06_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5350 #define DMA0_TRIG07_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5351 #define DMA0_TRIG08_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5352 #define DMA0_TRIG09_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5353 #define DMA1_TRIG10_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5354 #define DMA1_TRIG11_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5355 #define DMA1_TRIG12_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5356 #define DMA1_TRIG13_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5357 #define DMA1_TRIG14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5358 #define DMA1_TRIG15_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5359 #define DMA1_TRIG16_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5360 #define DMA1_TRIG17_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5361 #define DMA1_TRIG18_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5362 #define DMA1_TRIG19_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5363 #define ENC0_PHASEA_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5364 #define ENC0_PHASEB_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5365 #define ENC1_PHASEA_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5366 #define ENC1_PHASEB_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5367 #define EXTTRIG_IN9_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5368 #define FC5_CTS_SDA_SSEL0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 4) /* PIO1_14 */
5369 #define GPIO_PIO114_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5370 #define PINT_PINT0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5371 #define PINT_PINT1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5372 #define PINT_PINT2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5373 #define PINT_PINT3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5374 #define PINT_PINT4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5375 #define PINT_PINT5_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5376 #define PINT_PINT6_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5377 #define PINT_PINT7_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5378 #define PIO1_14_PIO1_14_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5379 #define PMC_ACMP_IN4_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 0) /* PIO1_14 */
5380 #define PWM0_B3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 11) /* PIO1_14 */
5381 #define PWM0_EXTA0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5382 #define PWM0_EXTA1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5383 #define PWM0_EXTA2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5384 #define PWM0_EXTA3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5385 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5386 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5387 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5388 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5389 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5390 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5391 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5392 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5393 #define PWM1_EXTA0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5394 #define PWM1_EXTA1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5395 #define PWM1_EXTA2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5396 #define PWM1_EXTA3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5397 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5398 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5399 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5400 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5401 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5402 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5403 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5404 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 13) /* PIO1_14 */
5405 #define QSPI_DIN0_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 12) /* PIO1_14 */
5406 #define USB0_LEDN_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 5) /* PIO1_14 */
5407 #define UTICK0_CAPTURE2_PIO1_14 IOCON_MUX(46, IOCON_TYPE_A, 2) /* PIO1_14 */
5408 #define ADC0_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5409 #define ADC0_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5410 #define ADC0_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5411 #define ADC0_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5412 #define ADC1_TRIG0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5413 #define ADC1_TRIG1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5414 #define ADC1_TRIG2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5415 #define ADC1_TRIG3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5416 #define CTIMER0_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5417 #define CTIMER0_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5418 #define CTIMER0_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5419 #define CTIMER0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5420 #define CTIMER1_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5421 #define CTIMER1_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5422 #define CTIMER1_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5423 #define CTIMER1_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5424 #define CTIMER2_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5425 #define CTIMER2_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5426 #define CTIMER2_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5427 #define CTIMER2_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5428 #define CTIMER3_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5429 #define CTIMER3_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5430 #define CTIMER3_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5431 #define CTIMER3_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5432 #define CTIMER4_CAPTURE0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5433 #define CTIMER4_CAPTURE1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5434 #define CTIMER4_CAPTURE2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5435 #define CTIMER4_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5436 #define CT_INP7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 3) /* PIO1_15 */
5437 #define DMA0_TRIG00_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5438 #define DMA0_TRIG010_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5439 #define DMA0_TRIG011_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5440 #define DMA0_TRIG012_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5441 #define DMA0_TRIG013_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5442 #define DMA0_TRIG014_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5443 #define DMA0_TRIG015_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5444 #define DMA0_TRIG016_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5445 #define DMA0_TRIG017_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5446 #define DMA0_TRIG018_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5447 #define DMA0_TRIG019_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5448 #define DMA0_TRIG01_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5449 #define DMA0_TRIG020_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5450 #define DMA0_TRIG021_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5451 #define DMA0_TRIG022_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5452 #define DMA0_TRIG023_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5453 #define DMA0_TRIG024_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5454 #define DMA0_TRIG025_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5455 #define DMA0_TRIG026_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5456 #define DMA0_TRIG027_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5457 #define DMA0_TRIG028_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5458 #define DMA0_TRIG029_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5459 #define DMA0_TRIG02_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5460 #define DMA0_TRIG030_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5461 #define DMA0_TRIG031_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5462 #define DMA0_TRIG032_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5463 #define DMA0_TRIG033_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5464 #define DMA0_TRIG034_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5465 #define DMA0_TRIG035_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5466 #define DMA0_TRIG036_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5467 #define DMA0_TRIG037_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5468 #define DMA0_TRIG038_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5469 #define DMA0_TRIG039_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5470 #define DMA0_TRIG03_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5471 #define DMA0_TRIG040_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5472 #define DMA0_TRIG041_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5473 #define DMA0_TRIG042_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5474 #define DMA0_TRIG043_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5475 #define DMA0_TRIG044_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5476 #define DMA0_TRIG045_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5477 #define DMA0_TRIG046_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5478 #define DMA0_TRIG047_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5479 #define DMA0_TRIG048_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5480 #define DMA0_TRIG049_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5481 #define DMA0_TRIG04_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5482 #define DMA0_TRIG050_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5483 #define DMA0_TRIG051_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5484 #define DMA0_TRIG05_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5485 #define DMA0_TRIG06_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5486 #define DMA0_TRIG07_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5487 #define DMA0_TRIG08_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5488 #define DMA0_TRIG09_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5489 #define DMA1_TRIG10_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5490 #define DMA1_TRIG11_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5491 #define DMA1_TRIG12_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5492 #define DMA1_TRIG13_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5493 #define DMA1_TRIG14_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5494 #define DMA1_TRIG15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5495 #define DMA1_TRIG16_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5496 #define DMA1_TRIG17_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5497 #define DMA1_TRIG18_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5498 #define DMA1_TRIG19_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5499 #define ENC0_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5500 #define ENC0_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5501 #define ENC1_PHASEA_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5502 #define ENC1_PHASEB_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5503 #define EXTTRIG_IN8_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5504 #define FC1_SCK_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 9) /* PIO1_15 */
5505 #define FC4_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 5) /* PIO1_15 */
5506 #define FC5_RTS_SCL_SSEL1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 4) /* PIO1_15 */
5507 #define FLEXSPI0_DATA5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 8) /* PIO1_15 */
5508 #define GPIO_PIO115_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5509 #define PINT_PINT0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5510 #define PINT_PINT1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5511 #define PINT_PINT2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5512 #define PINT_PINT3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5513 #define PINT_PINT4_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5514 #define PINT_PINT5_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5515 #define PINT_PINT6_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5516 #define PINT_PINT7_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5517 #define PIO1_15_PIO1_15_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 0) /* PIO1_15 */
5518 #define PWM0_B0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 11) /* PIO1_15 */
5519 #define PWM0_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5520 #define PWM0_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5521 #define PWM0_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5522 #define PWM0_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5523 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5524 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5525 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5526 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5527 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5528 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5529 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5530 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5531 #define PWM1_EXTA0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5532 #define PWM1_EXTA1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5533 #define PWM1_EXTA2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5534 #define PWM1_EXTA3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5535 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5536 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5537 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5538 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5539 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5540 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5541 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5542 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 13) /* PIO1_15 */
5543 #define QSPI_CS0_DIS_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 10) /* PIO1_15 */
5544 #define UTICK0_CAPTURE3_PIO1_15 IOCON_MUX(47, IOCON_TYPE_D, 2) /* PIO1_15 */
5545 #define ADC0_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5546 #define ADC0_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5547 #define ADC0_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5548 #define ADC0_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5549 #define ADC1_TRIG0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5550 #define ADC1_TRIG1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5551 #define ADC1_TRIG2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5552 #define ADC1_TRIG3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5553 #define CTIMER1_MATCH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 3) /* PIO1_16 */
5554 #define DMA0_TRIG00_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5555 #define DMA0_TRIG010_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5556 #define DMA0_TRIG011_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5557 #define DMA0_TRIG012_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5558 #define DMA0_TRIG013_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5559 #define DMA0_TRIG014_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5560 #define DMA0_TRIG015_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5561 #define DMA0_TRIG016_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5562 #define DMA0_TRIG017_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5563 #define DMA0_TRIG018_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5564 #define DMA0_TRIG019_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5565 #define DMA0_TRIG01_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5566 #define DMA0_TRIG020_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5567 #define DMA0_TRIG021_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5568 #define DMA0_TRIG022_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5569 #define DMA0_TRIG023_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5570 #define DMA0_TRIG024_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5571 #define DMA0_TRIG025_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5572 #define DMA0_TRIG026_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5573 #define DMA0_TRIG027_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5574 #define DMA0_TRIG028_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5575 #define DMA0_TRIG029_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5576 #define DMA0_TRIG02_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5577 #define DMA0_TRIG030_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5578 #define DMA0_TRIG031_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5579 #define DMA0_TRIG032_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5580 #define DMA0_TRIG033_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5581 #define DMA0_TRIG034_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5582 #define DMA0_TRIG035_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5583 #define DMA0_TRIG036_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5584 #define DMA0_TRIG037_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5585 #define DMA0_TRIG038_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5586 #define DMA0_TRIG039_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5587 #define DMA0_TRIG03_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5588 #define DMA0_TRIG040_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5589 #define DMA0_TRIG041_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5590 #define DMA0_TRIG042_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5591 #define DMA0_TRIG043_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5592 #define DMA0_TRIG044_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5593 #define DMA0_TRIG045_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5594 #define DMA0_TRIG046_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5595 #define DMA0_TRIG047_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5596 #define DMA0_TRIG048_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5597 #define DMA0_TRIG049_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5598 #define DMA0_TRIG04_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5599 #define DMA0_TRIG050_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5600 #define DMA0_TRIG051_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5601 #define DMA0_TRIG05_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5602 #define DMA0_TRIG06_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5603 #define DMA0_TRIG07_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5604 #define DMA0_TRIG08_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5605 #define DMA0_TRIG09_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5606 #define DMA1_TRIG10_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5607 #define DMA1_TRIG11_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5608 #define DMA1_TRIG12_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5609 #define DMA1_TRIG13_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5610 #define DMA1_TRIG14_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5611 #define DMA1_TRIG15_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5612 #define DMA1_TRIG16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5613 #define DMA1_TRIG17_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5614 #define DMA1_TRIG18_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5615 #define DMA1_TRIG19_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5616 #define ENC0_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5617 #define ENC0_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5618 #define ENC1_PHASEA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5619 #define ENC1_PHASEB_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5620 #define EXTTRIG_IN7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5621 #define FC1_RXD_SDA_MOSI_DATA_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 9) /* PIO1_16 */
5622 #define FC6_TXD_SCL_MISO_WS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 2) /* PIO1_16 */
5623 #define FLEXSPI0_DATA4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 8) /* PIO1_16 */
5624 #define GPIO_PIO116_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5625 #define PINT_PINT0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5626 #define PINT_PINT1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5627 #define PINT_PINT2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5628 #define PINT_PINT3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5629 #define PINT_PINT4_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5630 #define PINT_PINT5_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5631 #define PINT_PINT6_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5632 #define PINT_PINT7_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5633 #define PIO1_16_PIO1_16_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 0) /* PIO1_16 */
5634 #define PWM0_B2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 11) /* PIO1_16 */
5635 #define PWM0_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5636 #define PWM0_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5637 #define PWM0_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5638 #define PWM0_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5639 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5640 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5641 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5642 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5643 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5644 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5645 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5646 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5647 #define PWM1_EXTA0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5648 #define PWM1_EXTA1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5649 #define PWM1_EXTA2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5650 #define PWM1_EXTA3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5651 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5652 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5653 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5654 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5655 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5656 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5657 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5658 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 13) /* PIO1_16 */
5659 #define QSPI_CS1_DIS_PIO1_16 IOCON_MUX(48, IOCON_TYPE_D, 10) /* PIO1_16 */
5660 #define ADC0_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5661 #define ADC0_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5662 #define ADC0_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5663 #define ADC0_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5664 #define ADC1_TRIG0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5665 #define ADC1_TRIG1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5666 #define ADC1_TRIG2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5667 #define ADC1_TRIG3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5668 #define AOI1_OUT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 12) /* PIO1_17 */
5669 #define DMA0_TRIG00_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5670 #define DMA0_TRIG010_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5671 #define DMA0_TRIG011_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5672 #define DMA0_TRIG012_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5673 #define DMA0_TRIG013_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5674 #define DMA0_TRIG014_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5675 #define DMA0_TRIG015_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5676 #define DMA0_TRIG016_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5677 #define DMA0_TRIG017_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5678 #define DMA0_TRIG018_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5679 #define DMA0_TRIG019_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5680 #define DMA0_TRIG01_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5681 #define DMA0_TRIG020_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5682 #define DMA0_TRIG021_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5683 #define DMA0_TRIG022_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5684 #define DMA0_TRIG023_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5685 #define DMA0_TRIG024_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5686 #define DMA0_TRIG025_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5687 #define DMA0_TRIG026_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5688 #define DMA0_TRIG027_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5689 #define DMA0_TRIG028_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5690 #define DMA0_TRIG029_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5691 #define DMA0_TRIG02_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5692 #define DMA0_TRIG030_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5693 #define DMA0_TRIG031_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5694 #define DMA0_TRIG032_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5695 #define DMA0_TRIG033_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5696 #define DMA0_TRIG034_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5697 #define DMA0_TRIG035_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5698 #define DMA0_TRIG036_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5699 #define DMA0_TRIG037_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5700 #define DMA0_TRIG038_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5701 #define DMA0_TRIG039_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5702 #define DMA0_TRIG03_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5703 #define DMA0_TRIG040_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5704 #define DMA0_TRIG041_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5705 #define DMA0_TRIG042_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5706 #define DMA0_TRIG043_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5707 #define DMA0_TRIG044_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5708 #define DMA0_TRIG045_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5709 #define DMA0_TRIG046_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5710 #define DMA0_TRIG047_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5711 #define DMA0_TRIG048_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5712 #define DMA0_TRIG049_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5713 #define DMA0_TRIG04_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5714 #define DMA0_TRIG050_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5715 #define DMA0_TRIG051_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5716 #define DMA0_TRIG05_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5717 #define DMA0_TRIG06_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5718 #define DMA0_TRIG07_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5719 #define DMA0_TRIG08_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5720 #define DMA0_TRIG09_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5721 #define DMA1_TRIG10_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5722 #define DMA1_TRIG11_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5723 #define DMA1_TRIG12_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5724 #define DMA1_TRIG13_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5725 #define DMA1_TRIG14_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5726 #define DMA1_TRIG15_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5727 #define DMA1_TRIG16_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5728 #define DMA1_TRIG17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5729 #define DMA1_TRIG18_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5730 #define DMA1_TRIG19_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5731 #define FC6_RTS_SCL_SSEL1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 3) /* PIO1_17 */
5732 #define GPIO_PIO117_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5733 #define PINT_PINT0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5734 #define PINT_PINT1_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5735 #define PINT_PINT2_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5736 #define PINT_PINT3_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5737 #define PINT_PINT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5738 #define PINT_PINT5_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5739 #define PINT_PINT6_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5740 #define PINT_PINT7_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5741 #define PIO1_17_PIO1_17_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 0) /* PIO1_17 */
5742 #define PWM0_B0_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 11) /* PIO1_17 */
5743 #define SCT0_OUT4_PIO1_17 IOCON_MUX(49, IOCON_TYPE_D, 4) /* PIO1_17 */
5744 #define ADC0_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5745 #define ADC0_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5746 #define ADC0_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5747 #define ADC0_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5748 #define ADC1_TRIG0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5749 #define ADC1_TRIG1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5750 #define ADC1_TRIG2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5751 #define ADC1_TRIG3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5752 #define DMA0_TRIG00_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5753 #define DMA0_TRIG010_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5754 #define DMA0_TRIG011_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5755 #define DMA0_TRIG012_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5756 #define DMA0_TRIG013_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5757 #define DMA0_TRIG014_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5758 #define DMA0_TRIG015_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5759 #define DMA0_TRIG016_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5760 #define DMA0_TRIG017_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5761 #define DMA0_TRIG018_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5762 #define DMA0_TRIG019_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5763 #define DMA0_TRIG01_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5764 #define DMA0_TRIG020_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5765 #define DMA0_TRIG021_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5766 #define DMA0_TRIG022_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5767 #define DMA0_TRIG023_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5768 #define DMA0_TRIG024_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5769 #define DMA0_TRIG025_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5770 #define DMA0_TRIG026_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5771 #define DMA0_TRIG027_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5772 #define DMA0_TRIG028_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5773 #define DMA0_TRIG029_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5774 #define DMA0_TRIG02_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5775 #define DMA0_TRIG030_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5776 #define DMA0_TRIG031_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5777 #define DMA0_TRIG032_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5778 #define DMA0_TRIG033_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5779 #define DMA0_TRIG034_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5780 #define DMA0_TRIG035_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5781 #define DMA0_TRIG036_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5782 #define DMA0_TRIG037_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5783 #define DMA0_TRIG038_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5784 #define DMA0_TRIG039_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5785 #define DMA0_TRIG03_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5786 #define DMA0_TRIG040_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5787 #define DMA0_TRIG041_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5788 #define DMA0_TRIG042_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5789 #define DMA0_TRIG043_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5790 #define DMA0_TRIG044_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5791 #define DMA0_TRIG045_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5792 #define DMA0_TRIG046_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5793 #define DMA0_TRIG047_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5794 #define DMA0_TRIG048_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5795 #define DMA0_TRIG049_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5796 #define DMA0_TRIG04_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5797 #define DMA0_TRIG050_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5798 #define DMA0_TRIG051_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5799 #define DMA0_TRIG05_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5800 #define DMA0_TRIG06_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5801 #define DMA0_TRIG07_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5802 #define DMA0_TRIG08_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5803 #define DMA0_TRIG09_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5804 #define DMA1_TRIG10_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5805 #define DMA1_TRIG11_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5806 #define DMA1_TRIG12_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5807 #define DMA1_TRIG13_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5808 #define DMA1_TRIG14_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5809 #define DMA1_TRIG15_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5810 #define DMA1_TRIG16_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5811 #define DMA1_TRIG17_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5812 #define DMA1_TRIG18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5813 #define DMA1_TRIG19_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5814 #define GPIO_PIO118_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5815 #define HSCMP2_OUT_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 13) /* PIO1_18 */
5816 #define PINT_PINT0_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5817 #define PINT_PINT1_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5818 #define PINT_PINT2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5819 #define PINT_PINT3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5820 #define PINT_PINT4_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5821 #define PINT_PINT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5822 #define PINT_PINT6_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5823 #define PINT_PINT7_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5824 #define PIO1_18_PIO1_18_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5825 #define PWM0_A2_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 11) /* PIO1_18 */
5826 #define QSPI_DIN3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 12) /* PIO1_18 */
5827 #define RTC_ALARMOUT_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 8) /* PIO1_18 */
5828 #define RTC_TAMPER3_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 0) /* PIO1_18 */
5829 #define SCT0_OUT5_PIO1_18 IOCON_MUX(50, IOCON_TYPE_D, 4) /* PIO1_18 */
5830 #define ADC0_CH4B_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5831 #define ADC0_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5832 #define ADC0_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5833 #define ADC0_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5834 #define ADC0_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5835 #define ADC1_TRIG0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5836 #define ADC1_TRIG1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5837 #define ADC1_TRIG2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5838 #define ADC1_TRIG3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5839 #define AOI1_OUT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 13) /* PIO1_19 */
5840 #define CTIMER3_MATCH1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 3) /* PIO1_19 */
5841 #define DAC1_OUT_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5842 #define DMA0_TRIG00_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5843 #define DMA0_TRIG010_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5844 #define DMA0_TRIG011_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5845 #define DMA0_TRIG012_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5846 #define DMA0_TRIG013_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5847 #define DMA0_TRIG014_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5848 #define DMA0_TRIG015_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5849 #define DMA0_TRIG016_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5850 #define DMA0_TRIG017_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5851 #define DMA0_TRIG018_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5852 #define DMA0_TRIG019_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5853 #define DMA0_TRIG01_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5854 #define DMA0_TRIG020_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5855 #define DMA0_TRIG021_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5856 #define DMA0_TRIG022_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5857 #define DMA0_TRIG023_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5858 #define DMA0_TRIG024_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5859 #define DMA0_TRIG025_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5860 #define DMA0_TRIG026_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5861 #define DMA0_TRIG027_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5862 #define DMA0_TRIG028_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5863 #define DMA0_TRIG029_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5864 #define DMA0_TRIG02_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5865 #define DMA0_TRIG030_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5866 #define DMA0_TRIG031_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5867 #define DMA0_TRIG032_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5868 #define DMA0_TRIG033_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5869 #define DMA0_TRIG034_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5870 #define DMA0_TRIG035_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5871 #define DMA0_TRIG036_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5872 #define DMA0_TRIG037_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5873 #define DMA0_TRIG038_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5874 #define DMA0_TRIG039_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5875 #define DMA0_TRIG03_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5876 #define DMA0_TRIG040_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5877 #define DMA0_TRIG041_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5878 #define DMA0_TRIG042_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5879 #define DMA0_TRIG043_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5880 #define DMA0_TRIG044_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5881 #define DMA0_TRIG045_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5882 #define DMA0_TRIG046_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5883 #define DMA0_TRIG047_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5884 #define DMA0_TRIG048_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5885 #define DMA0_TRIG049_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5886 #define DMA0_TRIG04_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5887 #define DMA0_TRIG050_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5888 #define DMA0_TRIG051_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5889 #define DMA0_TRIG05_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5890 #define DMA0_TRIG06_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5891 #define DMA0_TRIG07_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5892 #define DMA0_TRIG08_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5893 #define DMA0_TRIG09_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5894 #define DMA1_TRIG10_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5895 #define DMA1_TRIG11_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5896 #define DMA1_TRIG12_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5897 #define DMA1_TRIG13_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5898 #define DMA1_TRIG14_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5899 #define DMA1_TRIG15_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5900 #define DMA1_TRIG16_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5901 #define DMA1_TRIG17_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5902 #define DMA1_TRIG18_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5903 #define DMA1_TRIG19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5904 #define FC4_SCK_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 5) /* PIO1_19 */
5905 #define GPIO_PIO119_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5906 #define HSCMP1_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5907 #define PINT_PINT0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5908 #define PINT_PINT1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5909 #define PINT_PINT2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5910 #define PINT_PINT3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5911 #define PINT_PINT4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5912 #define PINT_PINT5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5913 #define PINT_PINT6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5914 #define PINT_PINT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5915 #define PIO1_19_PIO1_19_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 0) /* PIO1_19 */
5916 #define QSPI_DIN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 10) /* PIO1_19 */
5917 #define SCT0_IN0_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
5918 #define SCT0_IN1_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
5919 #define SCT0_IN2_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
5920 #define SCT0_IN3_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
5921 #define SCT0_IN4_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
5922 #define SCT0_IN5_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
5923 #define SCT0_IN6_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 4) /* PIO1_19 */
5924 #define SCT0_OUT7_PIO1_19 IOCON_MUX(51, IOCON_TYPE_D, 2) /* PIO1_19 */
5925 #define ADC0_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5926 #define ADC0_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5927 #define ADC0_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5928 #define ADC0_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5929 #define ADC1_CH8A_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5930 #define ADC1_TRIG0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5931 #define ADC1_TRIG1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5932 #define ADC1_TRIG2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5933 #define ADC1_TRIG3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5934 #define AOI0_OUT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 12) /* PIO1_20 */
5935 #define CTIMER0_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5936 #define CTIMER0_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5937 #define CTIMER0_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5938 #define CTIMER0_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5939 #define CTIMER1_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5940 #define CTIMER1_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5941 #define CTIMER1_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5942 #define CTIMER1_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5943 #define CTIMER2_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5944 #define CTIMER2_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5945 #define CTIMER2_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5946 #define CTIMER2_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5947 #define CTIMER3_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5948 #define CTIMER3_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5949 #define CTIMER3_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5950 #define CTIMER3_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5951 #define CTIMER4_CAPTURE0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5952 #define CTIMER4_CAPTURE1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5953 #define CTIMER4_CAPTURE2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5954 #define CTIMER4_CAPTURE3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5955 #define CT_INP14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 3) /* PIO1_20 */
5956 #define DMA0_TRIG00_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5957 #define DMA0_TRIG010_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5958 #define DMA0_TRIG011_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5959 #define DMA0_TRIG012_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5960 #define DMA0_TRIG013_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5961 #define DMA0_TRIG014_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5962 #define DMA0_TRIG015_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5963 #define DMA0_TRIG016_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5964 #define DMA0_TRIG017_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5965 #define DMA0_TRIG018_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5966 #define DMA0_TRIG019_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5967 #define DMA0_TRIG01_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5968 #define DMA0_TRIG020_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5969 #define DMA0_TRIG021_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5970 #define DMA0_TRIG022_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5971 #define DMA0_TRIG023_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5972 #define DMA0_TRIG024_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5973 #define DMA0_TRIG025_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5974 #define DMA0_TRIG026_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5975 #define DMA0_TRIG027_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5976 #define DMA0_TRIG028_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5977 #define DMA0_TRIG029_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5978 #define DMA0_TRIG02_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5979 #define DMA0_TRIG030_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5980 #define DMA0_TRIG031_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5981 #define DMA0_TRIG032_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5982 #define DMA0_TRIG033_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5983 #define DMA0_TRIG034_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5984 #define DMA0_TRIG035_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5985 #define DMA0_TRIG036_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5986 #define DMA0_TRIG037_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5987 #define DMA0_TRIG038_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5988 #define DMA0_TRIG039_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5989 #define DMA0_TRIG03_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5990 #define DMA0_TRIG040_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5991 #define DMA0_TRIG041_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5992 #define DMA0_TRIG042_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5993 #define DMA0_TRIG043_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5994 #define DMA0_TRIG044_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5995 #define DMA0_TRIG045_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5996 #define DMA0_TRIG046_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5997 #define DMA0_TRIG047_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5998 #define DMA0_TRIG048_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
5999 #define DMA0_TRIG049_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6000 #define DMA0_TRIG04_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6001 #define DMA0_TRIG050_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6002 #define DMA0_TRIG051_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6003 #define DMA0_TRIG05_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6004 #define DMA0_TRIG06_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6005 #define DMA0_TRIG07_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6006 #define DMA0_TRIG08_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6007 #define DMA0_TRIG09_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6008 #define DMA1_TRIG10_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6009 #define DMA1_TRIG11_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6010 #define DMA1_TRIG12_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6011 #define DMA1_TRIG13_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6012 #define DMA1_TRIG14_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6013 #define DMA1_TRIG15_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6014 #define DMA1_TRIG16_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6015 #define DMA1_TRIG17_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6016 #define DMA1_TRIG18_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6017 #define DMA1_TRIG19_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6018 #define FC4_TXD_SCL_MISO_WS_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 5) /* PIO1_20 */
6019 #define FC7_RTS_SCL_SSEL1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 1) /* PIO1_20 */
6020 #define GPIO_PIO120_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6021 #define PINT_PINT0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6022 #define PINT_PINT1_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6023 #define PINT_PINT2_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6024 #define PINT_PINT3_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6025 #define PINT_PINT4_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6026 #define PINT_PINT5_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6027 #define PINT_PINT6_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6028 #define PINT_PINT7_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6029 #define PIO1_20_PIO1_20_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 0) /* PIO1_20 */
6030 #define PWM0_A0_PIO1_20 IOCON_MUX(52, IOCON_TYPE_A, 11) /* PIO1_20 */
6031 #define ADC0_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6032 #define ADC0_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6033 #define ADC0_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6034 #define ADC0_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6035 #define ADC1_TRIG0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6036 #define ADC1_TRIG1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6037 #define ADC1_TRIG2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6038 #define ADC1_TRIG3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6039 #define AOI0_TRIGOUT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 12) /* PIO1_21 */
6040 #define AOI1_TRIGOUT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 12) /* PIO1_21 */
6041 #define CTIMER3_MATCH2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 3) /* PIO1_21 */
6042 #define DMA0_TRIG00_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6043 #define DMA0_TRIG010_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6044 #define DMA0_TRIG011_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6045 #define DMA0_TRIG012_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6046 #define DMA0_TRIG013_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6047 #define DMA0_TRIG014_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6048 #define DMA0_TRIG015_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6049 #define DMA0_TRIG016_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6050 #define DMA0_TRIG017_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6051 #define DMA0_TRIG018_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6052 #define DMA0_TRIG019_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6053 #define DMA0_TRIG01_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6054 #define DMA0_TRIG020_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6055 #define DMA0_TRIG021_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6056 #define DMA0_TRIG022_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6057 #define DMA0_TRIG023_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6058 #define DMA0_TRIG024_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6059 #define DMA0_TRIG025_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6060 #define DMA0_TRIG026_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6061 #define DMA0_TRIG027_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6062 #define DMA0_TRIG028_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6063 #define DMA0_TRIG029_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6064 #define DMA0_TRIG02_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6065 #define DMA0_TRIG030_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6066 #define DMA0_TRIG031_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6067 #define DMA0_TRIG032_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6068 #define DMA0_TRIG033_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6069 #define DMA0_TRIG034_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6070 #define DMA0_TRIG035_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6071 #define DMA0_TRIG036_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6072 #define DMA0_TRIG037_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6073 #define DMA0_TRIG038_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6074 #define DMA0_TRIG039_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6075 #define DMA0_TRIG03_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6076 #define DMA0_TRIG040_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6077 #define DMA0_TRIG041_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6078 #define DMA0_TRIG042_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6079 #define DMA0_TRIG043_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6080 #define DMA0_TRIG044_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6081 #define DMA0_TRIG045_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6082 #define DMA0_TRIG046_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6083 #define DMA0_TRIG047_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6084 #define DMA0_TRIG048_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6085 #define DMA0_TRIG049_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6086 #define DMA0_TRIG04_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6087 #define DMA0_TRIG050_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6088 #define DMA0_TRIG051_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6089 #define DMA0_TRIG05_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6090 #define DMA0_TRIG06_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6091 #define DMA0_TRIG07_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6092 #define DMA0_TRIG08_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6093 #define DMA0_TRIG09_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6094 #define DMA1_TRIG10_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6095 #define DMA1_TRIG11_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6096 #define DMA1_TRIG12_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6097 #define DMA1_TRIG13_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6098 #define DMA1_TRIG14_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6099 #define DMA1_TRIG15_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6100 #define DMA1_TRIG16_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6101 #define DMA1_TRIG17_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6102 #define DMA1_TRIG18_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6103 #define DMA1_TRIG19_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6104 #define FC4_RXD_SDA_MOSI_DATA_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 5) /* PIO1_21 */
6105 #define FC7_CTS_SDA_SSEL0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 1) /* PIO1_21 */
6106 #define GPIO_PIO121_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6107 #define PINT_PINT0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6108 #define PINT_PINT1_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6109 #define PINT_PINT2_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6110 #define PINT_PINT3_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6111 #define PINT_PINT4_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6112 #define PINT_PINT5_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6113 #define PINT_PINT6_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6114 #define PINT_PINT7_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6115 #define PIO1_21_PIO1_21_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 0) /* PIO1_21 */
6116 #define PWM1_A0_PIO1_21 IOCON_MUX(53, IOCON_TYPE_D, 11) /* PIO1_21 */
6117 #define ADC0_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6118 #define ADC0_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6119 #define ADC0_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6120 #define ADC0_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6121 #define ADC1_TRIG0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6122 #define ADC1_TRIG1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6123 #define ADC1_TRIG2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6124 #define ADC1_TRIG3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6125 #define AOI0_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */
6126 #define AOI1_TRIGOUT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 12) /* PIO1_22 */
6127 #define CAN0_RD_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 9) /* PIO1_22 */
6128 #define CTIMER2_MATCH3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 3) /* PIO1_22 */
6129 #define DAC0_OUT_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6130 #define DMA0_TRIG00_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6131 #define DMA0_TRIG010_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6132 #define DMA0_TRIG011_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6133 #define DMA0_TRIG012_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6134 #define DMA0_TRIG013_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6135 #define DMA0_TRIG014_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6136 #define DMA0_TRIG015_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6137 #define DMA0_TRIG016_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6138 #define DMA0_TRIG017_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6139 #define DMA0_TRIG018_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6140 #define DMA0_TRIG019_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6141 #define DMA0_TRIG01_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6142 #define DMA0_TRIG020_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6143 #define DMA0_TRIG021_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6144 #define DMA0_TRIG022_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6145 #define DMA0_TRIG023_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6146 #define DMA0_TRIG024_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6147 #define DMA0_TRIG025_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6148 #define DMA0_TRIG026_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6149 #define DMA0_TRIG027_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6150 #define DMA0_TRIG028_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6151 #define DMA0_TRIG029_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6152 #define DMA0_TRIG02_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6153 #define DMA0_TRIG030_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6154 #define DMA0_TRIG031_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6155 #define DMA0_TRIG032_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6156 #define DMA0_TRIG033_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6157 #define DMA0_TRIG034_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6158 #define DMA0_TRIG035_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6159 #define DMA0_TRIG036_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6160 #define DMA0_TRIG037_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6161 #define DMA0_TRIG038_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6162 #define DMA0_TRIG039_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6163 #define DMA0_TRIG03_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6164 #define DMA0_TRIG040_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6165 #define DMA0_TRIG041_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6166 #define DMA0_TRIG042_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6167 #define DMA0_TRIG043_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6168 #define DMA0_TRIG044_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6169 #define DMA0_TRIG045_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6170 #define DMA0_TRIG046_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6171 #define DMA0_TRIG047_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6172 #define DMA0_TRIG048_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6173 #define DMA0_TRIG049_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6174 #define DMA0_TRIG04_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6175 #define DMA0_TRIG050_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6176 #define DMA0_TRIG051_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6177 #define DMA0_TRIG05_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6178 #define DMA0_TRIG06_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6179 #define DMA0_TRIG07_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6180 #define DMA0_TRIG08_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6181 #define DMA0_TRIG09_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6182 #define DMA1_TRIG10_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6183 #define DMA1_TRIG11_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6184 #define DMA1_TRIG12_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6185 #define DMA1_TRIG13_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6186 #define DMA1_TRIG14_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6187 #define DMA1_TRIG15_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6188 #define DMA1_TRIG16_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6189 #define DMA1_TRIG17_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6190 #define DMA1_TRIG18_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6191 #define DMA1_TRIG19_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6192 #define FC4_SSEL3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 5) /* PIO1_22 */
6193 #define GPIO_PIO122_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6194 #define HSCMP1_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6195 #define PINT_PINT0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6196 #define PINT_PINT1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6197 #define PINT_PINT2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6198 #define PINT_PINT3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6199 #define PINT_PINT4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6200 #define PINT_PINT5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6201 #define PINT_PINT6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6202 #define PINT_PINT7_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6203 #define PIO1_22_PIO1_22_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 0) /* PIO1_22 */
6204 #define PWM0_B1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 11) /* PIO1_22 */
6205 #define QSPI_DIN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 10) /* PIO1_22 */
6206 #define SCT0_IN0_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
6207 #define SCT0_IN1_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
6208 #define SCT0_IN2_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
6209 #define SCT0_IN3_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
6210 #define SCT0_IN4_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
6211 #define SCT0_IN5_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
6212 #define SCT0_IN6_PIO1_22 IOCON_MUX(54, IOCON_TYPE_A, 4) /* PIO1_22 */
6213 #define ADC0_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6214 #define ADC0_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6215 #define ADC0_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6216 #define ADC0_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6217 #define ADC1_TRIG0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6218 #define ADC1_TRIG1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6219 #define ADC1_TRIG2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6220 #define ADC1_TRIG3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6221 #define AOI0_TRIGOUT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 12) /* PIO1_23 */
6222 #define AOI1_TRIGOUT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 12) /* PIO1_23 */
6223 #define DMA0_TRIG00_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6224 #define DMA0_TRIG010_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6225 #define DMA0_TRIG011_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6226 #define DMA0_TRIG012_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6227 #define DMA0_TRIG013_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6228 #define DMA0_TRIG014_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6229 #define DMA0_TRIG015_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6230 #define DMA0_TRIG016_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6231 #define DMA0_TRIG017_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6232 #define DMA0_TRIG018_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6233 #define DMA0_TRIG019_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6234 #define DMA0_TRIG01_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6235 #define DMA0_TRIG020_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6236 #define DMA0_TRIG021_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6237 #define DMA0_TRIG022_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6238 #define DMA0_TRIG023_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6239 #define DMA0_TRIG024_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6240 #define DMA0_TRIG025_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6241 #define DMA0_TRIG026_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6242 #define DMA0_TRIG027_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6243 #define DMA0_TRIG028_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6244 #define DMA0_TRIG029_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6245 #define DMA0_TRIG02_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6246 #define DMA0_TRIG030_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6247 #define DMA0_TRIG031_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6248 #define DMA0_TRIG032_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6249 #define DMA0_TRIG033_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6250 #define DMA0_TRIG034_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6251 #define DMA0_TRIG035_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6252 #define DMA0_TRIG036_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6253 #define DMA0_TRIG037_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6254 #define DMA0_TRIG038_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6255 #define DMA0_TRIG039_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6256 #define DMA0_TRIG03_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6257 #define DMA0_TRIG040_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6258 #define DMA0_TRIG041_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6259 #define DMA0_TRIG042_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6260 #define DMA0_TRIG043_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6261 #define DMA0_TRIG044_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6262 #define DMA0_TRIG045_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6263 #define DMA0_TRIG046_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6264 #define DMA0_TRIG047_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6265 #define DMA0_TRIG048_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6266 #define DMA0_TRIG049_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6267 #define DMA0_TRIG04_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6268 #define DMA0_TRIG050_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6269 #define DMA0_TRIG051_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6270 #define DMA0_TRIG05_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6271 #define DMA0_TRIG06_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6272 #define DMA0_TRIG07_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6273 #define DMA0_TRIG08_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6274 #define DMA0_TRIG09_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6275 #define DMA1_TRIG10_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6276 #define DMA1_TRIG11_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6277 #define DMA1_TRIG12_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6278 #define DMA1_TRIG13_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6279 #define DMA1_TRIG14_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6280 #define DMA1_TRIG15_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6281 #define DMA1_TRIG16_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6282 #define DMA1_TRIG17_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6283 #define DMA1_TRIG18_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6284 #define DMA1_TRIG19_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6285 #define FC2_SCK_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 1) /* PIO1_23 */
6286 #define FC3_SSEL2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 5) /* PIO1_23 */
6287 #define GPIO_PIO123_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6288 #define HSCMP2_IN1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6289 #define PINT_PINT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6290 #define PINT_PINT1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6291 #define PINT_PINT2_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6292 #define PINT_PINT3_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6293 #define PINT_PINT4_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6294 #define PINT_PINT5_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6295 #define PINT_PINT6_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6296 #define PINT_PINT7_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6297 #define PIO1_23_PIO1_23_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 0) /* PIO1_23 */
6298 #define PWM1_A1_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 11) /* PIO1_23 */
6299 #define SCT0_OUT0_PIO1_23 IOCON_MUX(55, IOCON_TYPE_A, 2) /* PIO1_23 */
6300 #define ADC0_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6301 #define ADC0_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6302 #define ADC0_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6303 #define ADC0_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6304 #define ADC1_CH8B_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6305 #define ADC1_TRIG0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6306 #define ADC1_TRIG1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6307 #define ADC1_TRIG2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6308 #define ADC1_TRIG3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6309 #define AOI0_OUT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 12) /* PIO1_24 */
6310 #define DMA0_TRIG00_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6311 #define DMA0_TRIG010_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6312 #define DMA0_TRIG011_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6313 #define DMA0_TRIG012_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6314 #define DMA0_TRIG013_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6315 #define DMA0_TRIG014_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6316 #define DMA0_TRIG015_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6317 #define DMA0_TRIG016_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6318 #define DMA0_TRIG017_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6319 #define DMA0_TRIG018_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6320 #define DMA0_TRIG019_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6321 #define DMA0_TRIG01_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6322 #define DMA0_TRIG020_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6323 #define DMA0_TRIG021_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6324 #define DMA0_TRIG022_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6325 #define DMA0_TRIG023_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6326 #define DMA0_TRIG024_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6327 #define DMA0_TRIG025_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6328 #define DMA0_TRIG026_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6329 #define DMA0_TRIG027_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6330 #define DMA0_TRIG028_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6331 #define DMA0_TRIG029_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6332 #define DMA0_TRIG02_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6333 #define DMA0_TRIG030_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6334 #define DMA0_TRIG031_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6335 #define DMA0_TRIG032_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6336 #define DMA0_TRIG033_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6337 #define DMA0_TRIG034_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6338 #define DMA0_TRIG035_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6339 #define DMA0_TRIG036_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6340 #define DMA0_TRIG037_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6341 #define DMA0_TRIG038_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6342 #define DMA0_TRIG039_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6343 #define DMA0_TRIG03_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6344 #define DMA0_TRIG040_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6345 #define DMA0_TRIG041_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6346 #define DMA0_TRIG042_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6347 #define DMA0_TRIG043_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6348 #define DMA0_TRIG044_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6349 #define DMA0_TRIG045_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6350 #define DMA0_TRIG046_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6351 #define DMA0_TRIG047_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6352 #define DMA0_TRIG048_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6353 #define DMA0_TRIG049_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6354 #define DMA0_TRIG04_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6355 #define DMA0_TRIG050_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6356 #define DMA0_TRIG051_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6357 #define DMA0_TRIG05_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6358 #define DMA0_TRIG06_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6359 #define DMA0_TRIG07_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6360 #define DMA0_TRIG08_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6361 #define DMA0_TRIG09_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6362 #define DMA1_TRIG10_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6363 #define DMA1_TRIG11_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6364 #define DMA1_TRIG12_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6365 #define DMA1_TRIG13_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6366 #define DMA1_TRIG14_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6367 #define DMA1_TRIG15_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6368 #define DMA1_TRIG16_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6369 #define DMA1_TRIG17_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6370 #define DMA1_TRIG18_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6371 #define DMA1_TRIG19_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6372 #define FC2_RXD_SDA_MOSI_DATA_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 1) /* PIO1_24 */
6373 #define FC3_SSEL3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 5) /* PIO1_24 */
6374 #define GPIO_PIO124_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6375 #define PINT_PINT0_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6376 #define PINT_PINT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6377 #define PINT_PINT2_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6378 #define PINT_PINT3_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6379 #define PINT_PINT4_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6380 #define PINT_PINT5_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6381 #define PINT_PINT6_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6382 #define PINT_PINT7_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6383 #define PIO1_24_PIO1_24_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 0) /* PIO1_24 */
6384 #define SCT0_OUT1_PIO1_24 IOCON_MUX(56, IOCON_TYPE_A, 2) /* PIO1_24 */
6385 #define ADC0_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6386 #define ADC0_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6387 #define ADC0_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6388 #define ADC0_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6389 #define ADC1_TRIG0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6390 #define ADC1_TRIG1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6391 #define ADC1_TRIG2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6392 #define ADC1_TRIG3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6393 #define AOI0_OUT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 13) /* PIO1_25 */
6394 #define DMA0_TRIG00_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6395 #define DMA0_TRIG010_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6396 #define DMA0_TRIG011_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6397 #define DMA0_TRIG012_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6398 #define DMA0_TRIG013_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6399 #define DMA0_TRIG014_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6400 #define DMA0_TRIG015_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6401 #define DMA0_TRIG016_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6402 #define DMA0_TRIG017_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6403 #define DMA0_TRIG018_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6404 #define DMA0_TRIG019_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6405 #define DMA0_TRIG01_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6406 #define DMA0_TRIG020_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6407 #define DMA0_TRIG021_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6408 #define DMA0_TRIG022_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6409 #define DMA0_TRIG023_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6410 #define DMA0_TRIG024_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6411 #define DMA0_TRIG025_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6412 #define DMA0_TRIG026_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6413 #define DMA0_TRIG027_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6414 #define DMA0_TRIG028_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6415 #define DMA0_TRIG029_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6416 #define DMA0_TRIG02_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6417 #define DMA0_TRIG030_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6418 #define DMA0_TRIG031_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6419 #define DMA0_TRIG032_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6420 #define DMA0_TRIG033_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6421 #define DMA0_TRIG034_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6422 #define DMA0_TRIG035_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6423 #define DMA0_TRIG036_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6424 #define DMA0_TRIG037_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6425 #define DMA0_TRIG038_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6426 #define DMA0_TRIG039_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6427 #define DMA0_TRIG03_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6428 #define DMA0_TRIG040_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6429 #define DMA0_TRIG041_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6430 #define DMA0_TRIG042_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6431 #define DMA0_TRIG043_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6432 #define DMA0_TRIG044_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6433 #define DMA0_TRIG045_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6434 #define DMA0_TRIG046_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6435 #define DMA0_TRIG047_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6436 #define DMA0_TRIG048_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6437 #define DMA0_TRIG049_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6438 #define DMA0_TRIG04_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6439 #define DMA0_TRIG050_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6440 #define DMA0_TRIG051_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6441 #define DMA0_TRIG05_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6442 #define DMA0_TRIG06_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6443 #define DMA0_TRIG07_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6444 #define DMA0_TRIG08_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6445 #define DMA0_TRIG09_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6446 #define DMA1_TRIG10_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6447 #define DMA1_TRIG11_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6448 #define DMA1_TRIG12_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6449 #define DMA1_TRIG13_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6450 #define DMA1_TRIG14_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6451 #define DMA1_TRIG15_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6452 #define DMA1_TRIG16_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6453 #define DMA1_TRIG17_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6454 #define DMA1_TRIG18_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6455 #define DMA1_TRIG19_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6456 #define FC2_TXD_SCL_MISO_WS_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 1) /* PIO1_25 */
6457 #define GPIO_PIO125_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6458 #define PINT_PINT0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6459 #define PINT_PINT1_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6460 #define PINT_PINT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6461 #define PINT_PINT3_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6462 #define PINT_PINT4_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6463 #define PINT_PINT5_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6464 #define PINT_PINT6_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6465 #define PINT_PINT7_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6466 #define PIO1_25_PIO1_25_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 0) /* PIO1_25 */
6467 #define PWM1_A2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 11) /* PIO1_25 */
6468 #define SCT0_OUT2_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 2) /* PIO1_25 */
6469 #define SPI_SCLK_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 12) /* PIO1_25 */
6470 #define UTICK0_CAPTURE0_PIO1_25 IOCON_MUX(57, IOCON_TYPE_D, 4) /* PIO1_25 */
6471 #define ADC0_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6472 #define ADC0_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6473 #define ADC0_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6474 #define ADC0_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6475 #define ADC1_TRIG0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6476 #define ADC1_TRIG1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6477 #define ADC1_TRIG2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6478 #define ADC1_TRIG3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6479 #define AOI1_OUT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 13) /* PIO1_26 */
6480 #define CTIMER0_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6481 #define CTIMER0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6482 #define CTIMER0_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6483 #define CTIMER0_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6484 #define CTIMER1_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6485 #define CTIMER1_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6486 #define CTIMER1_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6487 #define CTIMER1_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6488 #define CTIMER2_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6489 #define CTIMER2_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6490 #define CTIMER2_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6491 #define CTIMER2_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6492 #define CTIMER3_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6493 #define CTIMER3_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6494 #define CTIMER3_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6495 #define CTIMER3_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6496 #define CTIMER4_CAPTURE0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6497 #define CTIMER4_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6498 #define CTIMER4_CAPTURE2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6499 #define CTIMER4_CAPTURE3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6500 #define CT_INP3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 3) /* PIO1_26 */
6501 #define DMA0_TRIG00_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6502 #define DMA0_TRIG010_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6503 #define DMA0_TRIG011_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6504 #define DMA0_TRIG012_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6505 #define DMA0_TRIG013_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6506 #define DMA0_TRIG014_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6507 #define DMA0_TRIG015_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6508 #define DMA0_TRIG016_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6509 #define DMA0_TRIG017_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6510 #define DMA0_TRIG018_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6511 #define DMA0_TRIG019_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6512 #define DMA0_TRIG01_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6513 #define DMA0_TRIG020_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6514 #define DMA0_TRIG021_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6515 #define DMA0_TRIG022_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6516 #define DMA0_TRIG023_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6517 #define DMA0_TRIG024_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6518 #define DMA0_TRIG025_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6519 #define DMA0_TRIG026_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6520 #define DMA0_TRIG027_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6521 #define DMA0_TRIG028_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6522 #define DMA0_TRIG029_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6523 #define DMA0_TRIG02_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6524 #define DMA0_TRIG030_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6525 #define DMA0_TRIG031_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6526 #define DMA0_TRIG032_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6527 #define DMA0_TRIG033_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6528 #define DMA0_TRIG034_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6529 #define DMA0_TRIG035_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6530 #define DMA0_TRIG036_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6531 #define DMA0_TRIG037_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6532 #define DMA0_TRIG038_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6533 #define DMA0_TRIG039_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6534 #define DMA0_TRIG03_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6535 #define DMA0_TRIG040_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6536 #define DMA0_TRIG041_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6537 #define DMA0_TRIG042_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6538 #define DMA0_TRIG043_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6539 #define DMA0_TRIG044_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6540 #define DMA0_TRIG045_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6541 #define DMA0_TRIG046_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6542 #define DMA0_TRIG047_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6543 #define DMA0_TRIG048_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6544 #define DMA0_TRIG049_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6545 #define DMA0_TRIG04_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6546 #define DMA0_TRIG050_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6547 #define DMA0_TRIG051_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6548 #define DMA0_TRIG05_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6549 #define DMA0_TRIG06_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6550 #define DMA0_TRIG07_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6551 #define DMA0_TRIG08_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6552 #define DMA0_TRIG09_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6553 #define DMA1_TRIG10_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6554 #define DMA1_TRIG11_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6555 #define DMA1_TRIG12_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6556 #define DMA1_TRIG13_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6557 #define DMA1_TRIG14_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6558 #define DMA1_TRIG15_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6559 #define DMA1_TRIG16_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6560 #define DMA1_TRIG17_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6561 #define DMA1_TRIG18_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6562 #define DMA1_TRIG19_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6563 #define FC2_CTS_SDA_SSEL0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 1) /* PIO1_26 */
6564 #define GPIO_PIO126_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6565 #define HS_SPI_SSEL3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 5) /* PIO1_26 */
6566 #define PINT_PINT0_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6567 #define PINT_PINT1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6568 #define PINT_PINT2_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6569 #define PINT_PINT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6570 #define PINT_PINT4_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6571 #define PINT_PINT5_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6572 #define PINT_PINT6_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6573 #define PINT_PINT7_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6574 #define PIO1_26_PIO1_26_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 0) /* PIO1_26 */
6575 #define PWM0_A1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 11) /* PIO1_26 */
6576 #define QSPI_CS1_DIS_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 12) /* PIO1_26 */
6577 #define SCT0_OUT3_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 2) /* PIO1_26 */
6578 #define UTICK0_CAPTURE1_PIO1_26 IOCON_MUX(58, IOCON_TYPE_D, 4) /* PIO1_26 */
6579 #define ADC0_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6580 #define ADC0_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6581 #define ADC0_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6582 #define ADC0_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6583 #define ADC1_TRIG0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6584 #define ADC1_TRIG1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6585 #define ADC1_TRIG2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6586 #define ADC1_TRIG3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6587 #define CAN0_TD_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 9) /* PIO1_27 */
6588 #define CLKOUT_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 4) /* PIO1_27 */
6589 #define CTIMER0_MATCH3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 3) /* PIO1_27 */
6590 #define DMA0_TRIG00_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6591 #define DMA0_TRIG010_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6592 #define DMA0_TRIG011_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6593 #define DMA0_TRIG012_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6594 #define DMA0_TRIG013_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6595 #define DMA0_TRIG014_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6596 #define DMA0_TRIG015_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6597 #define DMA0_TRIG016_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6598 #define DMA0_TRIG017_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6599 #define DMA0_TRIG018_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6600 #define DMA0_TRIG019_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6601 #define DMA0_TRIG01_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6602 #define DMA0_TRIG020_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6603 #define DMA0_TRIG021_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6604 #define DMA0_TRIG022_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6605 #define DMA0_TRIG023_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6606 #define DMA0_TRIG024_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6607 #define DMA0_TRIG025_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6608 #define DMA0_TRIG026_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6609 #define DMA0_TRIG027_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6610 #define DMA0_TRIG028_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6611 #define DMA0_TRIG029_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6612 #define DMA0_TRIG02_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6613 #define DMA0_TRIG030_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6614 #define DMA0_TRIG031_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6615 #define DMA0_TRIG032_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6616 #define DMA0_TRIG033_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6617 #define DMA0_TRIG034_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6618 #define DMA0_TRIG035_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6619 #define DMA0_TRIG036_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6620 #define DMA0_TRIG037_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6621 #define DMA0_TRIG038_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6622 #define DMA0_TRIG039_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6623 #define DMA0_TRIG03_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6624 #define DMA0_TRIG040_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6625 #define DMA0_TRIG041_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6626 #define DMA0_TRIG042_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6627 #define DMA0_TRIG043_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6628 #define DMA0_TRIG044_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6629 #define DMA0_TRIG045_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6630 #define DMA0_TRIG046_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6631 #define DMA0_TRIG047_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6632 #define DMA0_TRIG048_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6633 #define DMA0_TRIG049_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6634 #define DMA0_TRIG04_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6635 #define DMA0_TRIG050_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6636 #define DMA0_TRIG051_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6637 #define DMA0_TRIG05_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6638 #define DMA0_TRIG06_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6639 #define DMA0_TRIG07_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6640 #define DMA0_TRIG08_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6641 #define DMA0_TRIG09_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6642 #define DMA1_TRIG10_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6643 #define DMA1_TRIG11_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6644 #define DMA1_TRIG12_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6645 #define DMA1_TRIG13_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6646 #define DMA1_TRIG14_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6647 #define DMA1_TRIG15_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6648 #define DMA1_TRIG16_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6649 #define DMA1_TRIG17_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6650 #define DMA1_TRIG18_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6651 #define DMA1_TRIG19_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6652 #define FC2_RTS_SCL_SSEL1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 1) /* PIO1_27 */
6653 #define FLEXSPI0_DATA6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 8) /* PIO1_27 */
6654 #define GPIO_PIO127_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6655 #define PINT_PINT0_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6656 #define PINT_PINT1_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6657 #define PINT_PINT2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6658 #define PINT_PINT3_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6659 #define PINT_PINT4_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6660 #define PINT_PINT5_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6661 #define PINT_PINT6_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6662 #define PINT_PINT7_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6663 #define PIO1_27_PIO1_27_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 0) /* PIO1_27 */
6664 #define PWM1_B2_PIO1_27 IOCON_MUX(59, IOCON_TYPE_D, 11) /* PIO1_27 */
6665 #define ADC0_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6666 #define ADC0_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6667 #define ADC0_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6668 #define ADC0_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6669 #define ADC1_TRIG0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6670 #define ADC1_TRIG1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6671 #define ADC1_TRIG2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6672 #define ADC1_TRIG3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6673 #define AOI0_TRIGOUT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 10) /* PIO1_28 */
6674 #define AOI1_TRIGOUT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 10) /* PIO1_28 */
6675 #define CTIMER0_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6676 #define CTIMER0_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6677 #define CTIMER0_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6678 #define CTIMER0_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6679 #define CTIMER1_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6680 #define CTIMER1_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6681 #define CTIMER1_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6682 #define CTIMER1_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6683 #define CTIMER2_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6684 #define CTIMER2_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6685 #define CTIMER2_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6686 #define CTIMER2_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6687 #define CTIMER3_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6688 #define CTIMER3_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6689 #define CTIMER3_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6690 #define CTIMER3_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6691 #define CTIMER4_CAPTURE0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6692 #define CTIMER4_CAPTURE1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6693 #define CTIMER4_CAPTURE2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6694 #define CTIMER4_CAPTURE3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6695 #define CT_INP2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 3) /* PIO1_28 */
6696 #define DMA0_TRIG00_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6697 #define DMA0_TRIG010_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6698 #define DMA0_TRIG011_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6699 #define DMA0_TRIG012_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6700 #define DMA0_TRIG013_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6701 #define DMA0_TRIG014_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6702 #define DMA0_TRIG015_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6703 #define DMA0_TRIG016_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6704 #define DMA0_TRIG017_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6705 #define DMA0_TRIG018_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6706 #define DMA0_TRIG019_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6707 #define DMA0_TRIG01_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6708 #define DMA0_TRIG020_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6709 #define DMA0_TRIG021_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6710 #define DMA0_TRIG022_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6711 #define DMA0_TRIG023_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6712 #define DMA0_TRIG024_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6713 #define DMA0_TRIG025_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6714 #define DMA0_TRIG026_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6715 #define DMA0_TRIG027_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6716 #define DMA0_TRIG028_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6717 #define DMA0_TRIG029_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6718 #define DMA0_TRIG02_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6719 #define DMA0_TRIG030_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6720 #define DMA0_TRIG031_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6721 #define DMA0_TRIG032_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6722 #define DMA0_TRIG033_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6723 #define DMA0_TRIG034_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6724 #define DMA0_TRIG035_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6725 #define DMA0_TRIG036_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6726 #define DMA0_TRIG037_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6727 #define DMA0_TRIG038_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6728 #define DMA0_TRIG039_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6729 #define DMA0_TRIG03_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6730 #define DMA0_TRIG040_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6731 #define DMA0_TRIG041_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6732 #define DMA0_TRIG042_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6733 #define DMA0_TRIG043_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6734 #define DMA0_TRIG044_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6735 #define DMA0_TRIG045_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6736 #define DMA0_TRIG046_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6737 #define DMA0_TRIG047_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6738 #define DMA0_TRIG048_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6739 #define DMA0_TRIG049_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6740 #define DMA0_TRIG04_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6741 #define DMA0_TRIG050_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6742 #define DMA0_TRIG051_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6743 #define DMA0_TRIG05_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6744 #define DMA0_TRIG06_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6745 #define DMA0_TRIG07_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6746 #define DMA0_TRIG08_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6747 #define DMA0_TRIG09_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6748 #define DMA1_TRIG10_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6749 #define DMA1_TRIG11_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6750 #define DMA1_TRIG12_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6751 #define DMA1_TRIG13_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6752 #define DMA1_TRIG14_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6753 #define DMA1_TRIG15_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6754 #define DMA1_TRIG16_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6755 #define DMA1_TRIG17_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6756 #define DMA1_TRIG18_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6757 #define DMA1_TRIG19_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6758 #define FC7_SCK_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 1) /* PIO1_28 */
6759 #define GPIO_PIO128_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6760 #define HSCMP1_OUT_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 13) /* PIO1_28 */
6761 #define PINT_PINT0_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6762 #define PINT_PINT1_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6763 #define PINT_PINT2_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6764 #define PINT_PINT3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6765 #define PINT_PINT4_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6766 #define PINT_PINT5_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6767 #define PINT_PINT6_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6768 #define PINT_PINT7_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6769 #define PIO1_28_PIO1_28_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 0) /* PIO1_28 */
6770 #define PWM1_X3_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 11) /* PIO1_28 */
6771 #define SPI_CS1_DIS_PIO1_28 IOCON_MUX(60, IOCON_TYPE_D, 12) /* PIO1_28 */
6772 #define ADC0_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6773 #define ADC0_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6774 #define ADC0_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6775 #define ADC0_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6776 #define ADC1_TRIG0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6777 #define ADC1_TRIG1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6778 #define ADC1_TRIG2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6779 #define ADC1_TRIG3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6780 #define DMA0_TRIG00_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6781 #define DMA0_TRIG010_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6782 #define DMA0_TRIG011_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6783 #define DMA0_TRIG012_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6784 #define DMA0_TRIG013_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6785 #define DMA0_TRIG014_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6786 #define DMA0_TRIG015_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6787 #define DMA0_TRIG016_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6788 #define DMA0_TRIG017_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6789 #define DMA0_TRIG018_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6790 #define DMA0_TRIG019_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6791 #define DMA0_TRIG01_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6792 #define DMA0_TRIG020_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6793 #define DMA0_TRIG021_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6794 #define DMA0_TRIG022_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6795 #define DMA0_TRIG023_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6796 #define DMA0_TRIG024_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6797 #define DMA0_TRIG025_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6798 #define DMA0_TRIG026_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6799 #define DMA0_TRIG027_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6800 #define DMA0_TRIG028_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6801 #define DMA0_TRIG029_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6802 #define DMA0_TRIG02_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6803 #define DMA0_TRIG030_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6804 #define DMA0_TRIG031_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6805 #define DMA0_TRIG032_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6806 #define DMA0_TRIG033_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6807 #define DMA0_TRIG034_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6808 #define DMA0_TRIG035_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6809 #define DMA0_TRIG036_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6810 #define DMA0_TRIG037_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6811 #define DMA0_TRIG038_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6812 #define DMA0_TRIG039_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6813 #define DMA0_TRIG03_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6814 #define DMA0_TRIG040_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6815 #define DMA0_TRIG041_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6816 #define DMA0_TRIG042_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6817 #define DMA0_TRIG043_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6818 #define DMA0_TRIG044_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6819 #define DMA0_TRIG045_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6820 #define DMA0_TRIG046_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6821 #define DMA0_TRIG047_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6822 #define DMA0_TRIG048_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6823 #define DMA0_TRIG049_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6824 #define DMA0_TRIG04_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6825 #define DMA0_TRIG050_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6826 #define DMA0_TRIG051_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6827 #define DMA0_TRIG05_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6828 #define DMA0_TRIG06_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6829 #define DMA0_TRIG07_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6830 #define DMA0_TRIG08_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6831 #define DMA0_TRIG09_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6832 #define DMA1_TRIG10_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6833 #define DMA1_TRIG11_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6834 #define DMA1_TRIG12_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6835 #define DMA1_TRIG13_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6836 #define DMA1_TRIG14_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6837 #define DMA1_TRIG15_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6838 #define DMA1_TRIG16_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6839 #define DMA1_TRIG17_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6840 #define DMA1_TRIG18_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6841 #define DMA1_TRIG19_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6842 #define ENC0_PHASEA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6843 #define ENC0_PHASEB_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6844 #define ENC1_PHASEA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6845 #define ENC1_PHASEB_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6846 #define EXTTRIG_IN9_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6847 #define FC7_RXD_SDA_MOSI_DATA_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 1) /* PIO1_29 */
6848 #define FLEXSPI0_DATA7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 8) /* PIO1_29 */
6849 #define GPIO_PIO129_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6850 #define PINT_PINT0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6851 #define PINT_PINT1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6852 #define PINT_PINT2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6853 #define PINT_PINT3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6854 #define PINT_PINT4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6855 #define PINT_PINT5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6856 #define PINT_PINT6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6857 #define PINT_PINT7_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6858 #define PIO1_29_PIO1_29_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 0) /* PIO1_29 */
6859 #define PWM0_EXTA0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6860 #define PWM0_EXTA1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6861 #define PWM0_EXTA2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6862 #define PWM0_EXTA3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6863 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6864 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6865 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6866 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6867 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6868 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6869 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6870 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6871 #define PWM0_X2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 11) /* PIO1_29 */
6872 #define PWM1_EXTA0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6873 #define PWM1_EXTA1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6874 #define PWM1_EXTA2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6875 #define PWM1_EXTA3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6876 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6877 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6878 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6879 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6880 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6881 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6882 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6883 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 13) /* PIO1_29 */
6884 #define SCT0_IN0_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
6885 #define SCT0_IN1_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
6886 #define SCT0_IN2_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
6887 #define SCT0_IN3_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
6888 #define SCT0_IN4_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
6889 #define SCT0_IN5_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
6890 #define SCT0_IN6_PIO1_29 IOCON_MUX(61, IOCON_TYPE_D, 3) /* PIO1_29 */
6891 #define ADC0_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6892 #define ADC0_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6893 #define ADC0_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6894 #define ADC0_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6895 #define ADC1_TRIG0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6896 #define ADC1_TRIG1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6897 #define ADC1_TRIG2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6898 #define ADC1_TRIG3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6899 #define AOI1_OUT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 12) /* PIO1_30 */
6900 #define DMA0_TRIG00_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6901 #define DMA0_TRIG010_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6902 #define DMA0_TRIG011_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6903 #define DMA0_TRIG012_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6904 #define DMA0_TRIG013_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6905 #define DMA0_TRIG014_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6906 #define DMA0_TRIG015_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6907 #define DMA0_TRIG016_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6908 #define DMA0_TRIG017_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6909 #define DMA0_TRIG018_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6910 #define DMA0_TRIG019_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6911 #define DMA0_TRIG01_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6912 #define DMA0_TRIG020_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6913 #define DMA0_TRIG021_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6914 #define DMA0_TRIG022_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6915 #define DMA0_TRIG023_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6916 #define DMA0_TRIG024_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6917 #define DMA0_TRIG025_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6918 #define DMA0_TRIG026_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6919 #define DMA0_TRIG027_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6920 #define DMA0_TRIG028_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6921 #define DMA0_TRIG029_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6922 #define DMA0_TRIG02_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6923 #define DMA0_TRIG030_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6924 #define DMA0_TRIG031_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6925 #define DMA0_TRIG032_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6926 #define DMA0_TRIG033_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6927 #define DMA0_TRIG034_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6928 #define DMA0_TRIG035_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6929 #define DMA0_TRIG036_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6930 #define DMA0_TRIG037_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6931 #define DMA0_TRIG038_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6932 #define DMA0_TRIG039_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6933 #define DMA0_TRIG03_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6934 #define DMA0_TRIG040_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6935 #define DMA0_TRIG041_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6936 #define DMA0_TRIG042_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6937 #define DMA0_TRIG043_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6938 #define DMA0_TRIG044_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6939 #define DMA0_TRIG045_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6940 #define DMA0_TRIG046_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6941 #define DMA0_TRIG047_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6942 #define DMA0_TRIG048_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6943 #define DMA0_TRIG049_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6944 #define DMA0_TRIG04_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6945 #define DMA0_TRIG050_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6946 #define DMA0_TRIG051_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6947 #define DMA0_TRIG05_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6948 #define DMA0_TRIG06_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6949 #define DMA0_TRIG07_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6950 #define DMA0_TRIG08_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6951 #define DMA0_TRIG09_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6952 #define DMA1_TRIG10_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6953 #define DMA1_TRIG11_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6954 #define DMA1_TRIG12_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6955 #define DMA1_TRIG13_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6956 #define DMA1_TRIG14_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6957 #define DMA1_TRIG15_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6958 #define DMA1_TRIG16_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6959 #define DMA1_TRIG17_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6960 #define DMA1_TRIG18_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6961 #define DMA1_TRIG19_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6962 #define FC7_TXD_SCL_MISO_WS_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 1) /* PIO1_30 */
6963 #define GPIO_PIO130_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6964 #define HSCMP0_OUT_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 13) /* PIO1_30 */
6965 #define PINT_PINT0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6966 #define PINT_PINT1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6967 #define PINT_PINT2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6968 #define PINT_PINT3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6969 #define PINT_PINT4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6970 #define PINT_PINT5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6971 #define PINT_PINT6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6972 #define PINT_PINT7_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6973 #define PIO1_30_PIO1_30_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 0) /* PIO1_30 */
6974 #define PWM0_X3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 11) /* PIO1_30 */
6975 #define QSPI_CS0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 10) /* PIO1_30 */
6976 #define SCT0_IN0_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
6977 #define SCT0_IN1_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
6978 #define SCT0_IN2_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
6979 #define SCT0_IN3_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
6980 #define SCT0_IN4_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
6981 #define SCT0_IN5_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
6982 #define SCT0_IN6_PIO1_30 IOCON_MUX(62, IOCON_TYPE_D, 3) /* PIO1_30 */
6983 #define ADC0_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
6984 #define ADC0_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
6985 #define ADC0_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
6986 #define ADC0_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
6987 #define ADC1_TRIG0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
6988 #define ADC1_TRIG1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
6989 #define ADC1_TRIG2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
6990 #define ADC1_TRIG3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
6991 #define AOI0_IN0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
6992 #define AOI0_IN10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
6993 #define AOI0_IN11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
6994 #define AOI0_IN12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
6995 #define AOI0_IN13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
6996 #define AOI0_IN14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
6997 #define AOI0_IN15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
6998 #define AOI0_IN1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
6999 #define AOI0_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7000 #define AOI0_IN3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7001 #define AOI0_IN4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7002 #define AOI0_IN5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7003 #define AOI0_IN6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7004 #define AOI0_IN7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7005 #define AOI0_IN8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7006 #define AOI0_IN9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7007 #define AOI1_IN0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7008 #define AOI1_IN10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7009 #define AOI1_IN11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7010 #define AOI1_IN12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7011 #define AOI1_IN13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7012 #define AOI1_IN14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7013 #define AOI1_IN15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7014 #define AOI1_IN1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7015 #define AOI1_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7016 #define AOI1_IN3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7017 #define AOI1_IN4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7018 #define AOI1_IN5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7019 #define AOI1_IN6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7020 #define AOI1_IN7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7021 #define AOI1_IN8_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7022 #define AOI1_IN9_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7023 #define CTIMER0_MATCH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 3) /* PIO1_31 */
7024 #define DMA0_TRIG00_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7025 #define DMA0_TRIG010_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7026 #define DMA0_TRIG011_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7027 #define DMA0_TRIG012_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7028 #define DMA0_TRIG013_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7029 #define DMA0_TRIG014_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7030 #define DMA0_TRIG015_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7031 #define DMA0_TRIG016_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7032 #define DMA0_TRIG017_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7033 #define DMA0_TRIG018_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7034 #define DMA0_TRIG019_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7035 #define DMA0_TRIG01_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7036 #define DMA0_TRIG020_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7037 #define DMA0_TRIG021_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7038 #define DMA0_TRIG022_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7039 #define DMA0_TRIG023_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7040 #define DMA0_TRIG024_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7041 #define DMA0_TRIG025_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7042 #define DMA0_TRIG026_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7043 #define DMA0_TRIG027_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7044 #define DMA0_TRIG028_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7045 #define DMA0_TRIG029_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7046 #define DMA0_TRIG02_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7047 #define DMA0_TRIG030_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7048 #define DMA0_TRIG031_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7049 #define DMA0_TRIG032_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7050 #define DMA0_TRIG033_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7051 #define DMA0_TRIG034_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7052 #define DMA0_TRIG035_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7053 #define DMA0_TRIG036_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7054 #define DMA0_TRIG037_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7055 #define DMA0_TRIG038_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7056 #define DMA0_TRIG039_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7057 #define DMA0_TRIG03_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7058 #define DMA0_TRIG040_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7059 #define DMA0_TRIG041_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7060 #define DMA0_TRIG042_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7061 #define DMA0_TRIG043_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7062 #define DMA0_TRIG044_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7063 #define DMA0_TRIG045_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7064 #define DMA0_TRIG046_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7065 #define DMA0_TRIG047_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7066 #define DMA0_TRIG048_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7067 #define DMA0_TRIG049_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7068 #define DMA0_TRIG04_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7069 #define DMA0_TRIG050_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7070 #define DMA0_TRIG051_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7071 #define DMA0_TRIG05_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7072 #define DMA0_TRIG06_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7073 #define DMA0_TRIG07_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7074 #define DMA0_TRIG08_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7075 #define DMA0_TRIG09_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7076 #define DMA1_TRIG10_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7077 #define DMA1_TRIG11_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7078 #define DMA1_TRIG12_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7079 #define DMA1_TRIG13_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7080 #define DMA1_TRIG14_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7081 #define DMA1_TRIG15_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7082 #define DMA1_TRIG16_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7083 #define DMA1_TRIG17_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7084 #define DMA1_TRIG18_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7085 #define DMA1_TRIG19_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7086 #define ENC0_PHASEA_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7087 #define ENC0_PHASEB_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7088 #define ENC1_PHASEA_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7089 #define ENC1_PHASEB_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7090 #define EXTTRIG_IN2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7091 #define GPIO_PIO131_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7092 #define MCLK_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 1) /* PIO1_31 */
7093 #define PINT_PINT0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7094 #define PINT_PINT1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7095 #define PINT_PINT2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7096 #define PINT_PINT3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7097 #define PINT_PINT4_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7098 #define PINT_PINT5_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7099 #define PINT_PINT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7100 #define PINT_PINT7_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7101 #define PIO1_31_PIO1_31_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 0) /* PIO1_31 */
7102 #define PWM0_EXTA0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7103 #define PWM0_EXTA1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7104 #define PWM0_EXTA2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7105 #define PWM0_EXTA3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7106 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7107 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7108 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7109 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7110 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7111 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7112 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7113 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7114 #define PWM1_B2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 11) /* PIO1_31 */
7115 #define PWM1_EXTA0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7116 #define PWM1_EXTA1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7117 #define PWM1_EXTA2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7118 #define PWM1_EXTA3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7119 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7120 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7121 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7122 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7123 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7124 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7125 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7126 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 13) /* PIO1_31 */
7127 #define SCT0_OUT6_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 4) /* PIO1_31 */
7128 #define USB0_VBUS_PIO1_31 IOCON_MUX(63, IOCON_TYPE_D, 7) /* PIO1_31 */
7129 #define ADC0_CH9A_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 0) /* PIO2_0 */
7130 #define AOI0_OUT0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 12) /* PIO2_0 */
7131 #define CTIMER0_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7132 #define CTIMER0_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7133 #define CTIMER0_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7134 #define CTIMER0_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7135 #define CTIMER1_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7136 #define CTIMER1_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7137 #define CTIMER1_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7138 #define CTIMER1_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7139 #define CTIMER2_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7140 #define CTIMER2_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7141 #define CTIMER2_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7142 #define CTIMER2_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7143 #define CTIMER3_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7144 #define CTIMER3_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7145 #define CTIMER3_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7146 #define CTIMER3_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7147 #define CTIMER4_CAPTURE0_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7148 #define CTIMER4_CAPTURE1_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7149 #define CTIMER4_CAPTURE2_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7150 #define CTIMER4_CAPTURE3_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7151 #define CT_INP4_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 4) /* PIO2_0 */
7152 #define FC0_RXD_SDA_MOSI_DATA_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 2) /* PIO2_0 */
7153 #define GPIO_PIO20_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 0) /* PIO2_0 */
7154 #define I3C0_PUR_PIO2_0 IOCON_MUX(64, IOCON_TYPE_A, 5) /* PIO2_0 */
7155 #define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */
7156 #define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */
7157 #define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */
7158 #define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */
7159 #define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */
7160 #define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */
7161 
7162 #endif
7163