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Searched refs:DISR0 (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/Icu/src/
DSiul2_Icu_Ip_Irq.c190 u32RegFlags = Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE]->DISR0; in Siul2_Icu_Ip_ProcessSingleInterrupt()
196 u32RegFlags = Siul2_Icu_Ip_pBase[instance]->DISR0; in Siul2_Icu_Ip_ProcessSingleInterrupt()
214 … Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE]->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessSingleInterrupt()
220 Siul2_Icu_Ip_pBase[instance]->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessSingleInterrupt()
236 … Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE]->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessSingleInterrupt()
242 Siul2_Icu_Ip_pBase[instance]->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessSingleInterrupt()
278 uint32 u32RegFlags = (Siul2_Icu_Ip_pBase[instance])->DISR0; in Siul2_Icu_Ip_ProcessInterrupt()
289 (Siul2_Icu_Ip_pBase[instance])->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessInterrupt()
DSiul2_Icu_Ip.c431 baseAe->DISR0 |= pinIntValue; in Siul2_Icu_Ip_Init()
479 base->DISR0 |= pinIntValue; in Siul2_Icu_Ip_Init()
598 …flag = (Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE])->DISR0 & ((uint32)1U << hwCha… in Siul2_Icu_Ip_GetInputState()
605 (Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE])->DISR0 = flag; in Siul2_Icu_Ip_GetInputState()
612 flag = (Siul2_Icu_Ip_pBase[instance])->DISR0 & ((uint32)1U << hwChannel); in Siul2_Icu_Ip_GetInputState()
619 (Siul2_Icu_Ip_pBase[instance])->DISR0 = flag; in Siul2_Icu_Ip_GetInputState()
660 … (Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE])->DISR0 = ((uint32)1U << hwChannel); in Siul2_Icu_Ip_EnableInterrupt()
668 (Siul2_Icu_Ip_pBase[instance])->DISR0 = ((uint32)1U << hwChannel); in Siul2_Icu_Ip_EnableInterrupt()
690 … (Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE])->DISR0 = ((uint32)1U << hwChannel); in Siul2_Icu_Ip_DisableInterrupt()
698 (Siul2_Icu_Ip_pBase[instance])->DISR0 = ((uint32)1U << hwChannel); in Siul2_Icu_Ip_DisableInterrupt()
/hal_nxp-3.6.0/s32/drivers/s32k3/Icu/src/
DSiul2_Icu_Ip.c356 base->DISR0 |= pinIntValue; in Siul2_Icu_Ip_Init()
415 flag = (Siul2_Icu_Ip_pBase[instance])->DISR0 & ((uint32)1U << hwChannel); in Siul2_Icu_Ip_GetInputState()
422 (Siul2_Icu_Ip_pBase[instance])->DISR0 = flag; in Siul2_Icu_Ip_GetInputState()
458 (Siul2_Icu_Ip_pBase[instance])->DISR0 = ((uint32)1U << hwChannel); in Siul2_Icu_Ip_EnableInterrupt()
474 (Siul2_Icu_Ip_pBase[instance])->DISR0 = ((uint32)1U << hwChannel); in Siul2_Icu_Ip_DisableInterrupt()
DSiul2_Icu_Ip_Irq.c185 uint32 u32RegFlags = Siul2_Icu_Ip_pBase[instance]->DISR0; in Siul2_Icu_Ip_ProcessSingleInterrupt()
196 Siul2_Icu_Ip_pBase[instance]->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessSingleInterrupt()
228 uint32 u32RegFlags = (Siul2_Icu_Ip_pBase[instance])->DISR0; in Siul2_Icu_Ip_ProcessInterrupt()
239 (Siul2_Icu_Ip_pBase[instance])->DISR0 = u32RegFlags & u32ChannelMask; in Siul2_Icu_Ip_ProcessInterrupt()
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_SIUL2.h83 …__IO uint32_t DISR0; /**< SIUL2 DMA/Interrupt Status Flag 0, offset: 0… member
/hal_nxp-3.6.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_SIUL2.h83 …__IO uint32_t DISR0; /**< SIUL2 DMA/Interrupt Status Flag Register0, o… member