Searched refs:DIRER0 (Results 1 – 6 of 6) sorted by relevance
489 baseAe->DIRER0 &= ~pinIntValue; in Siul2_Icu_Ip_Init()495 base->DIRER0 &= ~pinIntValue; in Siul2_Icu_Ip_Init()599 …irqEnable = (Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE])->DIRER0 & ((uint32)1U <<… in Siul2_Icu_Ip_GetInputState()613 irqEnable = (Siul2_Icu_Ip_pBase[instance])->DIRER0 & ((uint32)1U << hwChannel); in Siul2_Icu_Ip_GetInputState()662 …(Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE])->DIRER0 |= ((uint32)1U << hwChannel); in Siul2_Icu_Ip_EnableInterrupt()670 (Siul2_Icu_Ip_pBase[instance])->DIRER0 |= ((uint32)1U << hwChannel); in Siul2_Icu_Ip_EnableInterrupt()688 …(Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE])->DIRER0 &= ~((uint32)1U << hwChannel… in Siul2_Icu_Ip_DisableInterrupt()696 (Siul2_Icu_Ip_pBase[instance])->DIRER0 &= ~((uint32)1U << hwChannel); in Siul2_Icu_Ip_DisableInterrupt()
191 u32RegIrqEn = Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE]->DIRER0; in Siul2_Icu_Ip_ProcessSingleInterrupt()197 u32RegIrqEn = Siul2_Icu_Ip_pBase[instance]->DIRER0; in Siul2_Icu_Ip_ProcessSingleInterrupt()279 uint32 u32RegIrqEn = (Siul2_Icu_Ip_pBase[instance])->DIRER0; in Siul2_Icu_Ip_ProcessInterrupt()
360 base->DIRER0 &= ~pinIntValue; in Siul2_Icu_Ip_Init()416 irqEnable = (Siul2_Icu_Ip_pBase[instance])->DIRER0 & ((uint32)1U << hwChannel); in Siul2_Icu_Ip_GetInputState()460 (Siul2_Icu_Ip_pBase[instance])->DIRER0 |= ((uint32)1U << hwChannel); in Siul2_Icu_Ip_EnableInterrupt()472 (Siul2_Icu_Ip_pBase[instance])->DIRER0 &= ~((uint32)1U << hwChannel); in Siul2_Icu_Ip_DisableInterrupt()
186 uint32 u32RegIrqEn = Siul2_Icu_Ip_pBase[instance]->DIRER0; in Siul2_Icu_Ip_ProcessSingleInterrupt()229 uint32 u32RegIrqEn = (Siul2_Icu_Ip_pBase[instance])->DIRER0; in Siul2_Icu_Ip_ProcessInterrupt()
85 …__IO uint32_t DIRER0; /**< SIUL2 DMA/Interrupt Request Enable 0, offset… member
85 …__IO uint32_t DIRER0; /**< SIUL2 DMA/Interrupt Request Enable Register0… member
