1 /* 2 * Copyright 2017 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 /** 8 * @file diff_p.h 9 * @brief The diff_p.h contains the DIFF_P Pressure sensor register definitions, access macros, and 10 * its bit mask. 11 */ 12 #ifndef DIFF_P_H_ 13 #define DIFF_P_H_ 14 15 /** 16 ** 17 ** DIFF_P Sensor Internal Registers 18 */ 19 enum { 20 DIFF_P_INT_STATUS_0 = 0x00, 21 DIFF_P_INT_STATUS_1 = 0x01, 22 DIFF_P_OUT_P_LSB = 0x02, 23 DIFF_P_OUT_P_MSB = 0x03, 24 DIFF_P_OUT_T = 0x04, 25 DIFF_P_P_MIN_LSB = 0x05, 26 DIFF_P_P_MIN_MSB = 0x06, 27 DIFF_P_T_MIN = 0x07, 28 DIFF_P_P_MAX_LSB = 0x08, 29 DIFF_P_P_MAX_MSB = 0x09, 30 DIFF_P_T_MAX = 0x0A, 31 DIFF_P_INT_MASK0 = 0x0B, 32 DIFF_P_INT_MASK1 = 0x0C, 33 /* Reserved: 0x0D - 0x11 */ 34 DIFF_P_STATUS = 0x12, 35 DIFF_P_WHO_AM_I = 0x13, 36 DIFF_P_OFF_P_LSB = 0x14, 37 DIFF_P_OFF_P_MSB = 0x15, 38 DIFF_P_OFF_CAL_P_LSB = 0x16, 39 DIFF_P_OFF_CAL_P_MSB = 0x17, 40 DIFF_P_OFF_T = 0x18, 41 DIFF_P_P_TGT0_LSB = 0x19, 42 DIFF_P_P_TGT0_MSB = 0x1A, 43 DIFF_P_P_TGT1_LSB = 0x1B, 44 DIFF_P_P_TGT1_MSB = 0x1C, 45 DIFF_P_P_TGT2_LSB = 0x1D, 46 DIFF_P_P_TGT2_MSB = 0x1E, 47 DIFF_P_T_TGT = 0x1F, 48 DIFF_P_CTRL_REG1 = 0x20, 49 DIFF_P_CTRL_REG2 = 0x21, 50 DIFF_P_CTRL_REG3 = 0x22, 51 DIFF_P_INT_ROUTE0 = 0x23, 52 DIFF_P_INT_ROUTE1 = 0x24, 53 /* Reserved: 0x25 - 0x5F */ 54 DIFF_P_I2C_ADDRESS = 0x61, 55 DIFF_P_WHO_AM_I_ = 0x62, 56 DIFF_P_PROD_REV = 0x63, 57 DIFF_P_OFF_MOP_LSB = 0x64, 58 DIFF_P_OFF_MOP_MSB = 0x65, 59 DIFF_P_SERIALNUMBER_BYTE7 = 0x66, 60 DIFF_P_SERIALNUMBER_BYTE6 = 0x67, 61 DIFF_P_SERIALNUMBER_BYTE5 = 0x68, 62 DIFF_P_SERIALNUMBER_BYTE4 = 0x69, 63 DIFF_P_SERIALNUMBER_BYTE3 = 0x6A, 64 DIFF_P_SERIALNUMBER_BYTE2 = 0x6B, 65 DIFF_P_SERIALNUMBER_BYTE1 = 0x6C, 66 DIFF_P_SERIALNUMBER_BYTE0 = 0x6D, 67 /* Reserved: 0x6E - 0x7F */ 68 }; 69 70 #define DIFF_P_NPS3000VV_WHOAMI_VALUE (0xD0) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */ 71 #define DIFF_P_NPS3001DV_WHOAMI_VALUE (0xD1) /* DIFF_P Who_Am_I Value of Part Number NPS3001DV. */ 72 #define DIFF_P_NPS3002VV_WHOAMI_VALUE (0xD2) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */ 73 #define DIFF_P_NPS3005DV_WHOAMI_VALUE (0xD3) /* DIFF_P Who_Am_I Value of Part Number NPS3000VV. */ 74 75 76 /*-------------------------------- 77 ** Register: INT_STATUS_0 78 ** Enum: DIFF_P_INT_STATUS_0 79 ** -- 80 ** Offset : 0x00 - Sensor Status Information Register 1. 81 ** ------------------------------*/ 82 typedef union { 83 struct { 84 uint8_t pdu : 1; /* Pressure data underflow. Pressure exceeded lower limit of operating */ 85 /* range.. */ 86 87 uint8_t pdo : 1; /* Pressure data overflow. Pressure exceeded upper limit of operating range. */ 88 89 uint8_t _reserved_ : 1; 90 uint8_t verra : 1; /* Analog voltage brown-out error status bit. This bit is only set when */ 91 /* BRWNOUT_EN bit in CTRL_REG2 is set to 1 enabling brownout detection. */ 92 93 uint8_t tdr : 1; /* Temperature new Data Ready. TDR is set to logic 1 whenever a Temperature */ 94 /* data acquisition is completed. */ 95 96 uint8_t pdr : 1; /* Pressure new Data Ready. PDR is set to logic 1 whenever a new Pressure */ 97 /* data acquisition is completed.. */ 98 99 uint8_t tow : 1; /* Temperature Data Overwrite. TOW is set to logic 1 whenever a new */ 100 /* Temperature acquisition is completed before the TDR flag is cleared. */ 101 102 uint8_t pow : 1; /* Pressure Data Overwrite. POW is set to logic 1 whenever a new Pressure */ 103 /* acquisition is completed before the PDR flag has been cleared. */ 104 105 } b; 106 uint8_t w; 107 } DIFF_P_INT_STATUS_0_t; 108 109 110 /* 111 ** INT_STATUS_0 - Bit field mask definitions 112 */ 113 #define DIFF_P_INT_STATUS_0_PDU_MASK ((uint8_t) 0x01) 114 #define DIFF_P_INT_STATUS_0_PDU_SHIFT ((uint8_t) 0) 115 116 #define DIFF_P_INT_STATUS_0_PDO_MASK ((uint8_t) 0x02) 117 #define DIFF_P_INT_STATUS_0_PDO_SHIFT ((uint8_t) 1) 118 119 #define DIFF_P_INT_STATUS_0_VERRA_MASK ((uint8_t) 0x08) 120 #define DIFF_P_INT_STATUS_0_VERRA_SHIFT ((uint8_t) 3) 121 122 #define DIFF_P_INT_STATUS_0_TDR_MASK ((uint8_t) 0x10) 123 #define DIFF_P_INT_STATUS_0_TDR_SHIFT ((uint8_t) 4) 124 125 #define DIFF_P_INT_STATUS_0_PDR_MASK ((uint8_t) 0x20) 126 #define DIFF_P_INT_STATUS_0_PDR_SHIFT ((uint8_t) 5) 127 128 #define DIFF_P_INT_STATUS_0_TOW_MASK ((uint8_t) 0x40) 129 #define DIFF_P_INT_STATUS_0_TOW_SHIFT ((uint8_t) 6) 130 131 #define DIFF_P_INT_STATUS_0_POW_MASK ((uint8_t) 0x80) 132 #define DIFF_P_INT_STATUS_0_POW_SHIFT ((uint8_t) 7) 133 134 135 /* 136 ** INT_STATUS_0 - Bit field value definitions 137 */ 138 #define DIFF_P_INT_STATUS_0_PDU_UNDERFLOW ((uint8_t) 0x01) /* Underflow occurred. */ 139 #define DIFF_P_INT_STATUS_0_PDU_NO_UNDERFLOW ((uint8_t) 0x00) /* No Underflow occurred. */ 140 #define DIFF_P_INT_STATUS_0_PDO_OVERFLOW ((uint8_t) 0x02) /* Overflow occurred. */ 141 #define DIFF_P_INT_STATUS_0_PDO_NO_OVERFLOW ((uint8_t) 0x00) /* No overflow occurred. */ 142 #define DIFF_P_INT_STATUS_0_VERRA_BRWNOUT ((uint8_t) 0x08) /* Analog voltage brownout occurred. */ 143 #define DIFF_P_INT_STATUS_0_VERRA_NO_BRWNOUT ((uint8_t) 0x00) /* No brownout occurred. */ 144 #define DIFF_P_INT_STATUS_0_TDR_DRDY ((uint8_t) 0x10) /* A new Temperature data is ready. */ 145 #define DIFF_P_INT_STATUS_0_PDR_DRDY ((uint8_t) 0x20) /* A new set of Pressure data is ready. */ 146 #define DIFF_P_INT_STATUS_0_TOW_OWR ((uint8_t) 0x40) /* Previous Temperature data was overwritten by new */ 147 /* Temperature data before it was read. */ 148 #define DIFF_P_INT_STATUS_0_POW_OWR ((uint8_t) 0x80) /* Previous Pressure data was overwritten by new */ 149 /* Pressure data before it was read. */ 150 /*------------------------------*/ 151 152 153 154 /*-------------------------------- 155 ** Register: INT_STATUS_1 156 ** Enum: DIFF_P_INT_STATUS_1 157 ** -- 158 ** Offset : 0x01 - Sensor Status Information Register 2. 159 ** ------------------------------*/ 160 typedef union { 161 struct { 162 uint8_t _reserved_ : 1; 163 uint8_t p_wchg : 1; /* Window threshold interrupt. */ 164 165 uint8_t p_tgt2 : 1; /* Pressure target value 2. */ 166 167 uint8_t p_tgt1 : 1; /* Pressure target value 1. */ 168 169 uint8_t p_tgt0 : 1; /* Pressure target value 0. */ 170 171 uint8_t t_tgt : 1; /* Temperature target value. */ 172 173 uint8_t tdu : 1; /* Temperature data underflow. Temperature exceeded lower limit of operating */ 174 /* range. */ 175 176 uint8_t tdo : 1; /* Temperature data overflow. Temperature exceeded upper limit of operating */ 177 /* range. */ 178 179 } b; 180 uint8_t w; 181 } DIFF_P_INT_STATUS_1_t; 182 183 184 /* 185 ** INT_STATUS_1 - Bit field mask definitions 186 */ 187 #define DIFF_P_INT_STATUS_1_P_WCHG_MASK ((uint8_t) 0x02) 188 #define DIFF_P_INT_STATUS_1_P_WCHG_SHIFT ((uint8_t) 1) 189 190 #define DIFF_P_INT_STATUS_1_P_TGT2_MASK ((uint8_t) 0x04) 191 #define DIFF_P_INT_STATUS_1_P_TGT2_SHIFT ((uint8_t) 2) 192 193 #define DIFF_P_INT_STATUS_1_P_TGT1_MASK ((uint8_t) 0x08) 194 #define DIFF_P_INT_STATUS_1_P_TGT1_SHIFT ((uint8_t) 3) 195 196 #define DIFF_P_INT_STATUS_1_P_TGT0_MASK ((uint8_t) 0x10) 197 #define DIFF_P_INT_STATUS_1_P_TGT0_SHIFT ((uint8_t) 4) 198 199 #define DIFF_P_INT_STATUS_1_T_TGT_MASK ((uint8_t) 0x20) 200 #define DIFF_P_INT_STATUS_1_T_TGT_SHIFT ((uint8_t) 5) 201 202 #define DIFF_P_INT_STATUS_1_TDU_MASK ((uint8_t) 0x40) 203 #define DIFF_P_INT_STATUS_1_TDU_SHIFT ((uint8_t) 6) 204 205 #define DIFF_P_INT_STATUS_1_TDO_MASK ((uint8_t) 0x80) 206 #define DIFF_P_INT_STATUS_1_TDO_SHIFT ((uint8_t) 7) 207 208 209 /* 210 ** INT_STATUS_1 - Bit field value definitions 211 */ 212 #define DIFF_P_INT_STATUS_1_P_WCHG_TH_CROSSED ((uint8_t) 0x02) /* pressure has crossed the window threshold defined */ 213 /* by P_TGT1 and P_TGT2. */ 214 #define DIFF_P_INT_STATUS_1_P_TGT2_REACHED ((uint8_t) 0x04) /* Temperature target reached. */ 215 #define DIFF_P_INT_STATUS_1_P_TGT1_REACHED ((uint8_t) 0x08) /* Temperature target reached. */ 216 #define DIFF_P_INT_STATUS_1_P_TGT0_REACHED ((uint8_t) 0x10) /* Temperature target reached. */ 217 #define DIFF_P_INT_STATUS_1_T_TGT_REACHED ((uint8_t) 0x20) /* Temperature target reached. */ 218 #define DIFF_P_INT_STATUS_1_TDU_UNDERFLOW ((uint8_t) 0x40) /* Underflow occurred. */ 219 #define DIFF_P_INT_STATUS_1_TDU_NO_UNDERFLOW ((uint8_t) 0x00) /* No Underflow occurred. */ 220 #define DIFF_P_INT_STATUS_1_TDO_OVERFLOW ((uint8_t) 0x80) /* Overflow occurred. */ 221 #define DIFF_P_INT_STATUS_1_TDO_NO_OVERFLOW ((uint8_t) 0x00) /* No overflow occurred. */ 222 /*------------------------------*/ 223 224 225 226 /*-------------------------------- 227 ** Register: OUT_P_LSB 228 ** Enum: DIFF_P_OUT_P_LSB 229 ** -- 230 ** Offset : 0x02 - 8 LSBs of 16 bit Pressure Data LSB. 231 ** ------------------------------*/ 232 typedef uint8_t DIFF_P_OUT_P_LSB_t; 233 234 235 /*-------------------------------- 236 ** Register: OUT_P_MSB 237 ** Enum: DIFF_P_OUT_P_MSB 238 ** -- 239 ** Offset : 0x03 - 8 MSBs of 16 bit Pressure Data MSB. 240 ** ------------------------------*/ 241 typedef uint8_t DIFF_P_OUT_P_MSB_t; 242 243 244 /*-------------------------------- 245 ** Register: OUT_T 246 ** Enum: DIFF_P_OUT_T 247 ** -- 248 ** Offset : 0x04 - Temperature Data. 249 ** ------------------------------*/ 250 typedef uint8_t DIFF_P_OUT_T_t; 251 252 253 254 /*-------------------------------- 255 ** Register: P_MIN_LSB 256 ** Enum: DIFF_P_P_MIN_LSB 257 ** -- 258 ** Offset : 0x05 - 8 LSBs of 16 bit Minimum Pressure Data LSB. 259 ** ------------------------------*/ 260 typedef uint8_t DIFF_P_P_MIN_LSB_t; 261 262 263 /*-------------------------------- 264 ** Register: P_MIN_MSB 265 ** Enum: DIFF_P_P_MIN_MSB 266 ** -- 267 ** Offset : 0x06 - 8 MSBs of 16 bit Minimum Pressure Data MSB. 268 ** ------------------------------*/ 269 typedef uint8_t DIFF_P_P_MIN_MSB_t; 270 271 272 /*-------------------------------- 273 ** Register: T_MIN 274 ** Enum: DIFF_P_T_MIN 275 ** -- 276 ** Offset : 0x07 - Minimum Temperature Data. 277 ** ------------------------------*/ 278 typedef uint8_t DIFF_P_T_MIN_t; 279 280 281 282 /*-------------------------------- 283 ** Register: P_MAX_LSB 284 ** Enum: DIFF_P_P_MAX_LSB 285 ** -- 286 ** Offset : 0x08 - 8 LSBs of 16 bit Maximum Pressure Data LSB. 287 ** ------------------------------*/ 288 typedef uint8_t DIFF_P_P_MAX_LSB_t; 289 290 291 /*-------------------------------- 292 ** Register: P_MAX_MSB 293 ** Enum: DIFF_P_P_MAX_MSB 294 ** -- 295 ** Offset : 0x09 - 8 MSBs of 16 bit Maximum Pressure Data MSB. 296 ** ------------------------------*/ 297 typedef uint8_t DIFF_P_P_MAX_MSB_t; 298 299 300 /*-------------------------------- 301 ** Register: T_MAX 302 ** Enum: DIFF_P_T_MAX 303 ** -- 304 ** Offset : 0x0A - Maximum Temperature Data. 305 ** ------------------------------*/ 306 typedef uint8_t DIFF_P_T_MAX_t; 307 308 309 310 /*-------------------------------- 311 ** Register: INT_MASK0 312 ** Enum: DIFF_P_INT_MASK0 313 ** -- 314 ** Offset : 0x0B - Interrupt Mask Register 1. 315 ** ------------------------------*/ 316 typedef union { 317 struct { 318 uint8_t pdu : 1; /* Interrupt Mask for PDU interrupt. */ 319 320 uint8_t pdo : 1; /* Interrupt Mask for PDO interrupt. */ 321 322 uint8_t _reserved_ : 1; 323 uint8_t verra : 1; /* Interrupt Mask for VERRA interrupt. */ 324 325 uint8_t tdr : 1; /* Interrupt Mask for TDR interrupt. */ 326 327 uint8_t pdr : 1; /* Interrupt Mask for PDR interrupt. */ 328 329 uint8_t tow : 1; /* Interrupt Mask for TOW interrupt. */ 330 331 uint8_t pow : 1; /* Interrupt Mask for POW interrupt. */ 332 333 } b; 334 uint8_t w; 335 } DIFF_P_INT_MASK0_t; 336 337 338 /* 339 ** INT_MASK0 - Bit field mask definitions 340 */ 341 #define DIFF_P_INT_MASK0_PDU_MASK ((uint8_t) 0x01) 342 #define DIFF_P_INT_MASK0_PDU_SHIFT ((uint8_t) 0) 343 344 #define DIFF_P_INT_MASK0_PDO_MASK ((uint8_t) 0x02) 345 #define DIFF_P_INT_MASK0_PDO_SHIFT ((uint8_t) 1) 346 347 #define DIFF_P_INT_MASK0_VERRA_MASK ((uint8_t) 0x08) 348 #define DIFF_P_INT_MASK0_VERRA_SHIFT ((uint8_t) 3) 349 350 #define DIFF_P_INT_MASK0_TDR_MASK ((uint8_t) 0x10) 351 #define DIFF_P_INT_MASK0_TDR_SHIFT ((uint8_t) 4) 352 353 #define DIFF_P_INT_MASK0_PDR_MASK ((uint8_t) 0x20) 354 #define DIFF_P_INT_MASK0_PDR_SHIFT ((uint8_t) 5) 355 356 #define DIFF_P_INT_MASK0_TOW_MASK ((uint8_t) 0x40) 357 #define DIFF_P_INT_MASK0_TOW_SHIFT ((uint8_t) 6) 358 359 #define DIFF_P_INT_MASK0_POW_MASK ((uint8_t) 0x80) 360 #define DIFF_P_INT_MASK0_POW_SHIFT ((uint8_t) 7) 361 362 363 /* 364 ** INT_MASK0 - Bit field value definitions 365 */ 366 #define DIFF_P_INT_MASK0_PDU_INT_EN ((uint8_t) 0x01) /* Interrupt Enabled. */ 367 #define DIFF_P_INT_MASK0_PDO_INT_EN ((uint8_t) 0x02) /* Interrupt Enabled. */ 368 #define DIFF_P_INT_MASK0_VERRA_INT_EN ((uint8_t) 0x08) /* Interrupt Enabled. */ 369 #define DIFF_P_INT_MASK0_TDR_INT_EN ((uint8_t) 0x10) /* Interrupt Enabled. */ 370 #define DIFF_P_INT_MASK0_PDR_INT_EN ((uint8_t) 0x20) /* Interrupt Enabled. */ 371 #define DIFF_P_INT_MASK0_TOW_INT_EN ((uint8_t) 0x40) /* Interrupt Enabled. */ 372 #define DIFF_P_INT_MASK0_POW_INT_EN ((uint8_t) 0x80) /* Interrupt Enabled. */ 373 /*------------------------------*/ 374 375 376 377 /*-------------------------------- 378 ** Register: INT_MASK1 379 ** Enum: DIFF_P_INT_MASK1 380 ** -- 381 ** Offset : 0x0C - Interrupt Mask Register 2. 382 ** ------------------------------*/ 383 typedef union { 384 struct { 385 uint8_t _reserved_ : 1; 386 uint8_t p_wchg : 1; /* Interrupt Mask for P_WCHG interrupt. */ 387 388 uint8_t p_tgt2 : 1; /* Interrupt Mask for P_TGT2 interrupt. */ 389 390 uint8_t p_tgt1 : 1; /* Interrupt Mask for P_TGT1 interrupt. */ 391 392 uint8_t p_tgt0 : 1; /* Interrupt Mask for P_TGT0 interrupt. */ 393 394 uint8_t t_tgt : 1; /* Interrupt Mask for T_TGT interrupt. */ 395 396 uint8_t tdu : 1; /* Interrupt Mask for TDU interrupt. */ 397 398 uint8_t tdo : 1; /* Interrupt Mask for TDO interrupt. */ 399 400 } b; 401 uint8_t w; 402 } DIFF_P_INT_MASK1_t; 403 404 405 /* 406 ** INT_MASK1 - Bit field mask definitions 407 */ 408 #define DIFF_P_INT_MASK1_P_WCHG_MASK ((uint8_t) 0x02) 409 #define DIFF_P_INT_MASK1_P_WCHG_SHIFT ((uint8_t) 1) 410 411 #define DIFF_P_INT_MASK1_P_TGT2_MASK ((uint8_t) 0x04) 412 #define DIFF_P_INT_MASK1_P_TGT2_SHIFT ((uint8_t) 2) 413 414 #define DIFF_P_INT_MASK1_P_TGT1_MASK ((uint8_t) 0x08) 415 #define DIFF_P_INT_MASK1_P_TGT1_SHIFT ((uint8_t) 3) 416 417 #define DIFF_P_INT_MASK1_P_TGT0_MASK ((uint8_t) 0x10) 418 #define DIFF_P_INT_MASK1_P_TGT0_SHIFT ((uint8_t) 4) 419 420 #define DIFF_P_INT_MASK1_T_TGT_MASK ((uint8_t) 0x20) 421 #define DIFF_P_INT_MASK1_T_TGT_SHIFT ((uint8_t) 5) 422 423 #define DIFF_P_INT_MASK1_TDU_MASK ((uint8_t) 0x40) 424 #define DIFF_P_INT_MASK1_TDU_SHIFT ((uint8_t) 6) 425 426 #define DIFF_P_INT_MASK1_TDO_MASK ((uint8_t) 0x80) 427 #define DIFF_P_INT_MASK1_TDO_SHIFT ((uint8_t) 7) 428 429 430 /* 431 ** INT_MASK1 - Bit field value definitions 432 */ 433 #define DIFF_P_INT_MASK1_P_WCHG_INT_EN ((uint8_t) 0x02) /* Interrupt Enabled. */ 434 #define DIFF_P_INT_MASK1_P_TGT2_INT_EN ((uint8_t) 0x04) /* Interrupt Enabled. */ 435 #define DIFF_P_INT_MASK1_P_TGT1_INT_EN ((uint8_t) 0x08) /* Interrupt Enabled. */ 436 #define DIFF_P_INT_MASK1_P_TGT0_INT_EN ((uint8_t) 0x10) /* Interrupt Enabled. */ 437 #define DIFF_P_INT_MASK1_T_TGT_INT_EN ((uint8_t) 0x20) /* Interrupt Enabled. */ 438 #define DIFF_P_INT_MASK1_TDU_INT_EN ((uint8_t) 0x40) /* Interrupt Enabled. */ 439 #define DIFF_P_INT_MASK1_TDO_INT_EN ((uint8_t) 0x80) /* Interrupt Enabled. */ 440 /*------------------------------*/ 441 442 443 444 /*-------------------------------- 445 ** Register: STATUS 446 ** Enum: DIFF_P_STATUS 447 ** -- 448 ** Offset : 0x12 - Calibration and I2C reprogram status. 449 ** ------------------------------*/ 450 typedef union { 451 struct { 452 uint8_t rst_status : 1; /* This bit is set whenever the part comes out of POR. */ 453 454 uint8_t osr_err : 1; /* OSR Error. Bit is set on illegal combination of OSR and ODR.. */ 455 456 uint8_t stat_cplt : 1; /* Completion Status. STAT_CPLT notifies the user when the calibration */ 457 /* routine has successfully completed. */ 458 459 uint8_t stat_ep : 1; /* Existing Pressure Status. STAT_EP is set to logic 1 when the calibration */ 460 /* routine detects an existing pressure condition in the system. */ 461 462 uint8_t i2c_rpg_status : 1; /* I2C Address Reprograming status bit. Bit is set to logic 1 at the */ 463 /* beginning of the reprograming cycle. */ 464 465 uint8_t i2c_rpg : 1; /* Completion Status of I2C Address Reprograming. This notifies the user that */ 466 /* the I2C reprograming has been completed successfully. */ 467 468 uint8_t i2c_rpg_cnt : 1; /* I2C Reprograming count status bit. */ 469 470 uint8_t active_mode : 1; /* Active mode status bit. */ 471 472 } b; 473 uint8_t w; 474 } DIFF_P_STATUS_t; 475 476 477 /* 478 ** STATUS - Bit field mask definitions 479 */ 480 #define DIFF_P_STATUS_RST_STATUS_MASK ((uint8_t) 0x01) 481 #define DIFF_P_STATUS_RST_STATUS_SHIFT ((uint8_t) 0) 482 483 #define DIFF_P_STATUS_OSR_ERR_MASK ((uint8_t) 0x02) 484 #define DIFF_P_STATUS_OSR_ERR_SHIFT ((uint8_t) 1) 485 486 #define DIFF_P_STATUS_STAT_CPLT_MASK ((uint8_t) 0x04) 487 #define DIFF_P_STATUS_STAT_CPLT_SHIFT ((uint8_t) 2) 488 489 #define DIFF_P_STATUS_STAT_EP_MASK ((uint8_t) 0x08) 490 #define DIFF_P_STATUS_STAT_EP_SHIFT ((uint8_t) 3) 491 492 #define DIFF_P_STATUS_I2C_RPG_STATUS_MASK ((uint8_t) 0x10) 493 #define DIFF_P_STATUS_I2C_RPG_STATUS_SHIFT ((uint8_t) 4) 494 495 #define DIFF_P_STATUS_I2C_RPG_MASK ((uint8_t) 0x20) 496 #define DIFF_P_STATUS_I2C_RPG_SHIFT ((uint8_t) 5) 497 498 #define DIFF_P_STATUS_I2C_RPG_CNT_MASK ((uint8_t) 0x40) 499 #define DIFF_P_STATUS_I2C_RPG_CNT_SHIFT ((uint8_t) 6) 500 501 #define DIFF_P_STATUS_ACTIVE_MODE_MASK ((uint8_t) 0x80) 502 #define DIFF_P_STATUS_ACTIVE_MODE_SHIFT ((uint8_t) 7) 503 504 505 /* 506 ** STATUS - Bit field value definitions 507 */ 508 #define DIFF_P_STATUS_RST_STATUS_RST ((uint8_t) 0x01) /* Part has come out of POR, brownout or soft reset. */ 509 #define DIFF_P_STATUS_RST_STATUS_NO_RST ((uint8_t) 0x00) /* No POR, brownout or soft reset has occurred. */ 510 #define DIFF_P_STATUS_OSR_ERR_ERR ((uint8_t) 0x02) /* Illegal ODR/OSR combination. */ 511 #define DIFF_P_STATUS_OSR_ERR_NO_ERR ((uint8_t) 0x00) /* No Error. */ 512 #define DIFF_P_STATUS_STAT_CPLT_SUCCESS ((uint8_t) 0x04) /* Calibration routine was successful. */ 513 #define DIFF_P_STATUS_STAT_CPLT_NO_SUCCESS ((uint8_t) 0x00) /* Calibration routine was not successful. */ 514 #define DIFF_P_STATUS_STAT_EP_DETECTED ((uint8_t) 0x08) /* Existing pressure has been detected. */ 515 #define DIFF_P_STATUS_STAT_EP_NOTDETECTED ((uint8_t) 0x00) /* No existing pressure detected. */ 516 #define DIFF_P_STATUS_I2C_RPG_STATUS_RPG_INIT ((uint8_t) 0x10) /* Reprograming cycle initiated. */ 517 #define DIFF_P_STATUS_I2C_RPG_STATUS_RPG_CPLT ((uint8_t) 0x00) /* Reprograming cycle completed. */ 518 #define DIFF_P_STATUS_I2C_RPG_RPG_SUCCESS ((uint8_t) 0x20) /* I2C Reprograming successful. */ 519 #define DIFF_P_STATUS_I2C_RPG_NO_RPG ((uint8_t) 0x00) /* No Reprograming has taken place. */ 520 #define DIFF_P_STATUS_I2C_RPG_CNT_CANT_RPG ((uint8_t) 0x40) /* I2C address cannot be reprogrammed. */ 521 #define DIFF_P_STATUS_I2C_RPG_CNT_CAN_RPG ((uint8_t) 0x00) /* I2C address can be reprogrammed. */ 522 #define DIFF_P_STATUS_ACTIVE_MODE_ACTIVE ((uint8_t) 0x80) /* Sensor is in active mode. */ 523 #define DIFF_P_STATUS_ACTIVE_MODE_STANDBY ((uint8_t) 0x00) /* Sensor is in standby mode. */ 524 /*------------------------------*/ 525 526 527 528 /*-------------------------------- 529 ** Register: WHO_AM_I 530 ** Enum: DIFF_P_WHO_AM_I 531 ** -- 532 ** Offset : 0x13 - This register contains the device identifier. 533 ** ------------------------------*/ 534 typedef uint8_t DIFF_P_WHO_AM_I_t; 535 536 537 538 /*-------------------------------- 539 ** Register: OFF_P_LSB 540 ** Enum: DIFF_P_OFF_P_LSB 541 ** -- 542 ** Offset : 0x14 - 8 LSBs of 16 bit Pressure Data Offset LSB. 543 ** ------------------------------*/ 544 typedef uint8_t DIFF_P_OFF_P_LSB_t; 545 546 547 /*-------------------------------- 548 ** Register: OFF_P_MSB 549 ** Enum: DIFF_P_OFF_P_MSB 550 ** -- 551 ** Offset : 0x15 - 8 MSBs of 16 bit Pressure Data Offset MSB. 552 ** ------------------------------*/ 553 typedef uint8_t DIFF_P_OFF_P_MSB_t; 554 555 556 /*-------------------------------- 557 ** Register: OFF_CAL_P_LSB 558 ** Enum: DIFF_P_OFF_CAL_P_LSB 559 ** -- 560 ** Offset : 0x16 - 8 LSBs of 16 bit Existing Pressure Offset LSB. 561 ** ------------------------------*/ 562 typedef uint8_t DIFF_P_OFF_CAL_P_LSB_t; 563 564 565 /*-------------------------------- 566 ** Register: OFF_CAL_P_MSB 567 ** Enum: DIFF_P_OFF_CAL_P_MSB 568 ** -- 569 ** Offset : 0x17 - 8 MSBs of 16 bit Existing Pressure Offset MSB. 570 ** ------------------------------*/ 571 typedef uint8_t DIFF_P_OFF_CAL_P_MSB_t; 572 573 574 /*-------------------------------- 575 ** Register: OFF_T 576 ** Enum: DIFF_P_OFF_T 577 ** -- 578 ** Offset : 0x18 - Temperature Data Offset. 579 ** ------------------------------*/ 580 typedef uint8_t DIFF_P_OFF_T_t; 581 582 583 584 /*-------------------------------- 585 ** Register: P_TGT0_LSB 586 ** Enum: DIFF_P_P_TGT0_LSB 587 ** -- 588 ** Offset : 0x19 - 8 LSBs of 16 bit Pressure Data Offset LSB. 589 ** ------------------------------*/ 590 typedef uint8_t DIFF_P_P_TGT0_LSB_t; 591 592 593 /*-------------------------------- 594 ** Register: P_TGT0_MSB 595 ** Enum: DIFF_P_P_TGT0_MSB 596 ** -- 597 ** Offset : 0x1A - 8 MSBs of 16 bit Pressure Data Offset MSB. 598 ** ------------------------------*/ 599 typedef uint8_t DIFF_P_P_TGT0_MSB_t; 600 601 602 /*-------------------------------- 603 ** Register: P_TGT1_LSB 604 ** Enum: DIFF_P_P_TGT1_LSB 605 ** -- 606 ** Offset : 0x1B - 8 LSBs of 16 bit Pressure Data Offset LSB. 607 ** ------------------------------*/ 608 typedef uint8_t DIFF_P_P_TGT1_LSB_t; 609 610 611 /*-------------------------------- 612 ** Register: P_TGT1_MSB 613 ** Enum: DIFF_P_P_TGT1_MSB 614 ** -- 615 ** Offset : 0x1C - 8 MSBs of 16 bit Pressure Data Offset MSB. 616 ** ------------------------------*/ 617 typedef uint8_t DIFF_P_P_TGT1_MSB_t; 618 619 620 /*-------------------------------- 621 ** Register: P_TGT2_LSB 622 ** Enum: DIFF_P_P_TGT2_LSB 623 ** -- 624 ** Offset : 0x1D - 8 LSBs of 16 bit Pressure Data Offset LSB. 625 ** ------------------------------*/ 626 typedef uint8_t DIFF_P_P_TGT2_LSB_t; 627 628 629 /*-------------------------------- 630 ** Register: P_TGT2_MSB 631 ** Enum: DIFF_P_P_TGT2_MSB 632 ** -- 633 ** Offset : 0x1E - 8 MSBs of 16 bit Pressure Data Offset MSB. 634 ** ------------------------------*/ 635 typedef uint8_t DIFF_P_P_TGT2_MSB_t; 636 637 638 /*-------------------------------- 639 ** Register: T_TGT 640 ** Enum: DIFF_P_T_TGT 641 ** -- 642 ** Offset : 0x1F - Temperature Target Value. 643 ** ------------------------------*/ 644 typedef uint8_t DIFF_P_T_TGT_t; 645 646 647 648 /*-------------------------------- 649 ** Register: CTRL_REG1 650 ** Enum: DIFF_P_CTRL_REG1 651 ** -- 652 ** Offset : 0x20 - Control Register 1. 653 ** ------------------------------*/ 654 typedef union { 655 struct { 656 /* osr >= 21 will select OSR8192 */ 657 uint8_t sbyb : 1; /* This bit sets the mode to ACTIVE. */ 658 659 uint8_t ost : 1; /* One Shot Mode. The OST bit, when set, will initiate a measurement */ 660 /* immediately and take the samples indicated by the OSR[4:0] bits. */ 661 662 uint8_t rst : 1; /* Software Reset. This bit is used to activate the software reset. */ 663 664 uint8_t osr : 5; /* Interrupt Mask for P_TGT1 interrupt. */ 665 666 } b; 667 uint8_t w; 668 } DIFF_P_CTRL_REG1_t; 669 670 671 /* 672 ** CTRL_REG1 - Bit field mask definitions 673 */ 674 #define DIFF_P_CTRL_REG1_SBYB_MASK ((uint8_t) 0x01) 675 #define DIFF_P_CTRL_REG1_SBYB_SHIFT ((uint8_t) 0) 676 677 #define DIFF_P_CTRL_REG1_OST_MASK ((uint8_t) 0x02) 678 #define DIFF_P_CTRL_REG1_OST_SHIFT ((uint8_t) 1) 679 680 #define DIFF_P_CTRL_REG1_RST_MASK ((uint8_t) 0x04) 681 #define DIFF_P_CTRL_REG1_RST_SHIFT ((uint8_t) 2) 682 683 #define DIFF_P_CTRL_REG1_OSR_MASK ((uint8_t) 0xF8) 684 #define DIFF_P_CTRL_REG1_OSR_SHIFT ((uint8_t) 3) 685 686 687 /* 688 ** CTRL_REG1 - Bit field value definitions 689 */ 690 #define DIFF_P_CTRL_REG1_SBYB_ACTIVE ((uint8_t) 0x01) /* Part is ACTIVE. */ 691 #define DIFF_P_CTRL_REG1_SBYB_STANDBY ((uint8_t) 0x00) /* Part is in STANDBY mode. */ 692 #define DIFF_P_CTRL_REG1_OST_ONESHOT ((uint8_t) 0x02) /* One Shot Mode. */ 693 #define DIFF_P_CTRL_REG1_OST_NORMAL ((uint8_t) 0x00) /* Normal operating mode. */ 694 #define DIFF_P_CTRL_REG1_RST_RESET ((uint8_t) 0x04) /* Device will be reset. */ 695 #define DIFF_P_CTRL_REG1_RST_NORMAL ((uint8_t) 0x00) /* Normal operating mode. */ 696 #define DIFF_P_CTRL_REG1_OSR_OSR1 ((uint8_t) 0x00) /* Oversampling Rate#1. */ 697 #define DIFF_P_CTRL_REG1_OSR_OSR2 ((uint8_t) 0x08) /* Oversampling Rate#2. */ 698 #define DIFF_P_CTRL_REG1_OSR_OSR4 ((uint8_t) 0x10) /* Oversampling Rate#4. */ 699 #define DIFF_P_CTRL_REG1_OSR_OSR8 ((uint8_t) 0x18) /* Oversampling Rate#8. */ 700 #define DIFF_P_CTRL_REG1_OSR_OSR16 ((uint8_t) 0x20) /* Oversampling Rate#16. */ 701 #define DIFF_P_CTRL_REG1_OSR_OSR32 ((uint8_t) 0x28) /* Oversampling Rate#32. */ 702 #define DIFF_P_CTRL_REG1_OSR_OSR64 ((uint8_t) 0x30) /* Oversampling Rate#64. */ 703 #define DIFF_P_CTRL_REG1_OSR_OSR128 ((uint8_t) 0x38) /* Oversampling Rate#128. */ 704 #define DIFF_P_CTRL_REG1_OSR_OSR256 ((uint8_t) 0x40) /* Oversampling Rate#256. */ 705 #define DIFF_P_CTRL_REG1_OSR_OSR512 ((uint8_t) 0x48) /* Oversampling Rate#512. */ 706 #define DIFF_P_CTRL_REG1_OSR_OSR768 ((uint8_t) 0x50) /* Oversampling Rate#768. */ 707 #define DIFF_P_CTRL_REG1_OSR_OSR1024 ((uint8_t) 0x58) /* Oversampling Rate#1024. */ 708 #define DIFF_P_CTRL_REG1_OSR_OSR1280 ((uint8_t) 0x60) /* Oversampling Rate#1280. */ 709 #define DIFF_P_CTRL_REG1_OSR_OSR1536 ((uint8_t) 0x68) /* Oversampling Rate#1536. */ 710 #define DIFF_P_CTRL_REG1_OSR_OSR2048 ((uint8_t) 0x70) /* Oversampling Rate#2048. */ 711 #define DIFF_P_CTRL_REG1_OSR_OSR2560 ((uint8_t) 0x78) /* Oversampling Rate#2560. */ 712 #define DIFF_P_CTRL_REG1_OSR_OSR3072 ((uint8_t) 0x80) /* Oversampling Rate#3072. */ 713 #define DIFF_P_CTRL_REG1_OSR_OSR4096 ((uint8_t) 0x88) /* Oversampling Rate#4096. */ 714 #define DIFF_P_CTRL_REG1_OSR_OSR5120 ((uint8_t) 0x90) /* Oversampling Rate#5120. */ 715 #define DIFF_P_CTRL_REG1_OSR_OSR6144 ((uint8_t) 0x98) /* Oversampling Rate#6144. */ 716 #define DIFF_P_CTRL_REG1_OSR_OSR7168 ((uint8_t) 0xa0) /* Oversampling Rate#7168. */ 717 #define DIFF_P_CTRL_REG1_OSR_OSR8192 ((uint8_t) 0xa8) /* Oversampling Rate#8192. */ 718 /*------------------------------*/ 719 720 721 722 /*-------------------------------- 723 ** Register: CTRL_REG2 724 ** Enum: DIFF_P_CTRL_REG2 725 ** -- 726 ** Offset : 0x21 - Control Register 2. 727 ** ------------------------------*/ 728 typedef union { 729 struct { 730 /* odr >= 12 will select ODR0P781 */ 731 uint8_t odr : 4; /* Output Data Rate. Sets the output data rate. */ 732 733 uint8_t _reserved_ : 1; 734 uint8_t f_read : 1; /* Fast Read Mode. Selects the auto-increment address methodology. */ 735 736 uint8_t brwnout_en : 1; /* Enables or disables internal brown out circuit.. */ 737 738 uint8_t ctrl_ac : 1; /* This bit controls when the Calibration Algorithm is to be run.. */ 739 740 } b; 741 uint8_t w; 742 } DIFF_P_CTRL_REG2_t; 743 744 745 /* 746 ** CTRL_REG2 - Bit field mask definitions 747 */ 748 #define DIFF_P_CTRL_REG2_ODR_MASK ((uint8_t) 0x0F) 749 #define DIFF_P_CTRL_REG2_ODR_SHIFT ((uint8_t) 0) 750 751 #define DIFF_P_CTRL_REG2_F_READ_MASK ((uint8_t) 0x20) 752 #define DIFF_P_CTRL_REG2_F_READ_SHIFT ((uint8_t) 5) 753 754 #define DIFF_P_CTRL_REG2_BRWNOUT_EN_MASK ((uint8_t) 0x40) 755 #define DIFF_P_CTRL_REG2_BRWNOUT_EN_SHIFT ((uint8_t) 6) 756 757 #define DIFF_P_CTRL_REG2_CTRL_AC_MASK ((uint8_t) 0x80) 758 #define DIFF_P_CTRL_REG2_CTRL_AC_SHIFT ((uint8_t) 7) 759 760 761 /* 762 ** CTRL_REG2 - Bit field value definitions 763 */ 764 #define DIFF_P_CTRL_REG2_ODR_ODR3200 ((uint8_t) 0x00) /* Output Data Rate#3200. */ 765 #define DIFF_P_CTRL_REG2_ODR_ODR1600 ((uint8_t) 0x01) /* Output Data Rate#1600. */ 766 #define DIFF_P_CTRL_REG2_ODR_ODR800 ((uint8_t) 0x02) /* Output Data Rate#800. */ 767 #define DIFF_P_CTRL_REG2_ODR_ODR400 ((uint8_t) 0x03) /* Output Data Rate#400. */ 768 #define DIFF_P_CTRL_REG2_ODR_ODR200 ((uint8_t) 0x04) /* Output Data Rate#200. */ 769 #define DIFF_P_CTRL_REG2_ODR_ODR100 ((uint8_t) 0x05) /* Output Data Rate#100. */ 770 #define DIFF_P_CTRL_REG2_ODR_ODR50 ((uint8_t) 0x06) /* Output Data Rate#50. */ 771 #define DIFF_P_CTRL_REG2_ODR_ODR25 ((uint8_t) 0x07) /* Output Data Rate#25. */ 772 #define DIFF_P_CTRL_REG2_ODR_ODR12P5 ((uint8_t) 0x08) /* Output Data Rate#12.5. */ 773 #define DIFF_P_CTRL_REG2_ODR_ODR6P25 ((uint8_t) 0x09) /* Output Data Rate#6.25. */ 774 #define DIFF_P_CTRL_REG2_ODR_ODR3P125 ((uint8_t) 0x0a) /* Output Data Rate#3.125. */ 775 #define DIFF_P_CTRL_REG2_ODR_ODR1P563 ((uint8_t) 0x0b) /* Output Data Rate#1.563. */ 776 #define DIFF_P_CTRL_REG2_ODR_ODR0P781 ((uint8_t) 0x0c) /* Output Data Rate#0.781. */ 777 #define DIFF_P_CTRL_REG2_F_READ_NORMAL ((uint8_t) 0x20) /* Loops between all register addresses. */ 778 #define DIFF_P_CTRL_REG2_F_READ_FASTREAD ((uint8_t) 0x00) /* Loops between register address 0x00 and 0x04. */ 779 #define DIFF_P_CTRL_REG2_BRWNOUT_EN_ENABLED ((uint8_t) 0x40) /* Internal brown out circuit is enabled. */ 780 #define DIFF_P_CTRL_REG2_BRWNOUT_EN_DISABLED ((uint8_t) 0x00) /* Internal brown out circuit is disabled. */ 781 #define DIFF_P_CTRL_REG2_CTRL_AC_CALRUN ((uint8_t) 0x80) /* Run Calibration Algorithm. */ 782 #define DIFF_P_CTRL_REG2_CTRL_AC_NOCALRUN ((uint8_t) 0x00) /* Calibration Algorithm not run. */ 783 /*------------------------------*/ 784 785 786 787 /*-------------------------------- 788 ** Register: CTRL_REG3 789 ** Enum: DIFF_P_CTRL_REG3 790 ** -- 791 ** Offset : 0x22 - Control Register 3. 792 ** ------------------------------*/ 793 typedef union { 794 struct { 795 uint8_t pp_od2 : 1; /* This bit configures the interrupt pin to Push-Pull or in Open Drain */ 796 /* mode.Push-Pull/Open Drain selection on interrupt pad INT2. */ 797 798 uint8_t ipol2 : 1; /* The IPOL bit selects the polarity of the interrupt signal on pin INT2. */ 799 800 uint8_t _reserved_ : 2; 801 uint8_t pp_od1 : 1; /* This bit configures the interrupt pin to Push-Pull or in Open Drain */ 802 /* mode.Push-Pull/Open Drain selection on interrupt pad INT1. */ 803 804 uint8_t ipol1 : 1; /* The IPOL bit selects the polarity of the interrupt signal on pin INT1. */ 805 806 } b; 807 uint8_t w; 808 } DIFF_P_CTRL_REG3_t; 809 810 811 /* 812 ** CTRL_REG3 - Bit field mask definitions 813 */ 814 #define DIFF_P_CTRL_REG3_PP_OD2_MASK ((uint8_t) 0x01) 815 #define DIFF_P_CTRL_REG3_PP_OD2_SHIFT ((uint8_t) 0) 816 817 #define DIFF_P_CTRL_REG3_IPOL2_MASK ((uint8_t) 0x02) 818 #define DIFF_P_CTRL_REG3_IPOL2_SHIFT ((uint8_t) 1) 819 820 #define DIFF_P_CTRL_REG3_PP_OD1_MASK ((uint8_t) 0x10) 821 #define DIFF_P_CTRL_REG3_PP_OD1_SHIFT ((uint8_t) 4) 822 823 #define DIFF_P_CTRL_REG3_IPOL1_MASK ((uint8_t) 0x20) 824 #define DIFF_P_CTRL_REG3_IPOL1_SHIFT ((uint8_t) 5) 825 826 827 /* 828 ** CTRL_REG3 - Bit field value definitions 829 */ 830 #define DIFF_P_CTRL_REG3_PP_OD2_OPENDRAIN ((uint8_t) 0x01) /* Open drain. */ 831 #define DIFF_P_CTRL_REG3_PP_OD2_PUSHPULL ((uint8_t) 0x00) /* Push-pull. */ 832 #define DIFF_P_CTRL_REG3_IPOL2_ACTIVE_HIGH ((uint8_t) 0x02) /* Active High. */ 833 #define DIFF_P_CTRL_REG3_IPOL2_ACTIVE_LOW ((uint8_t) 0x00) /* Active Low. */ 834 #define DIFF_P_CTRL_REG3_PP_OD1_OPENDRAIN ((uint8_t) 0x10) /* Open drain. */ 835 #define DIFF_P_CTRL_REG3_PP_OD1_PUSHPULL ((uint8_t) 0x00) /* Push-pull. */ 836 #define DIFF_P_CTRL_REG3_IPOL1_ACTIVE_HIGH ((uint8_t) 0x20) /* Active High. */ 837 #define DIFF_P_CTRL_REG3_IPOL1_ACTIVE_LOW ((uint8_t) 0x00) /* Active Low. */ 838 /*------------------------------*/ 839 840 841 842 /*-------------------------------- 843 ** Register: INT_ROUTE0 844 ** Enum: DIFF_P_INT_ROUTE0 845 ** -- 846 ** Offset : 0x23 - Interrupt Route Register 0. 847 ** ------------------------------*/ 848 typedef union { 849 struct { 850 uint8_t pdu : 1; /* Pressure data underflow. */ 851 852 uint8_t pdo : 1; /* Pressure data overflow. */ 853 854 uint8_t _reserved_ : 1; 855 uint8_t verra : 1; /* Analog voltage brown-out error status bit. */ 856 857 uint8_t tdr : 1; /* Temperature new Data Ready. */ 858 859 uint8_t pdr : 1; /* Pressure new Data Ready. */ 860 861 uint8_t tow : 1; /* Temperature Data Overwrite. */ 862 863 uint8_t pow : 1; /* Pressure Data Overwrite. */ 864 865 } b; 866 uint8_t w; 867 } DIFF_P_INT_ROUTE0_t; 868 869 870 /* 871 ** INT_ROUTE0 - Bit field mask definitions 872 */ 873 #define DIFF_P_INT_ROUTE0_PDU_MASK ((uint8_t) 0x01) 874 #define DIFF_P_INT_ROUTE0_PDU_SHIFT ((uint8_t) 0) 875 876 #define DIFF_P_INT_ROUTE0_PDO_MASK ((uint8_t) 0x02) 877 #define DIFF_P_INT_ROUTE0_PDO_SHIFT ((uint8_t) 1) 878 879 #define DIFF_P_INT_ROUTE0_VERRA_MASK ((uint8_t) 0x08) 880 #define DIFF_P_INT_ROUTE0_VERRA_SHIFT ((uint8_t) 3) 881 882 #define DIFF_P_INT_ROUTE0_TDR_MASK ((uint8_t) 0x10) 883 #define DIFF_P_INT_ROUTE0_TDR_SHIFT ((uint8_t) 4) 884 885 #define DIFF_P_INT_ROUTE0_PDR_MASK ((uint8_t) 0x20) 886 #define DIFF_P_INT_ROUTE0_PDR_SHIFT ((uint8_t) 5) 887 888 #define DIFF_P_INT_ROUTE0_TOW_MASK ((uint8_t) 0x40) 889 #define DIFF_P_INT_ROUTE0_TOW_SHIFT ((uint8_t) 6) 890 891 #define DIFF_P_INT_ROUTE0_POW_MASK ((uint8_t) 0x80) 892 #define DIFF_P_INT_ROUTE0_POW_SHIFT ((uint8_t) 7) 893 894 895 /* 896 ** INT_ROUTE0 - Bit field value definitions 897 */ 898 #define DIFF_P_INT_ROUTE0_PDU_INT2 ((uint8_t) 0x01) /* Interrupt routed to INT2 pin. */ 899 #define DIFF_P_INT_ROUTE0_PDU_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 900 #define DIFF_P_INT_ROUTE0_PDO_INT2 ((uint8_t) 0x02) /* Interrupt routed to INT2 pin. */ 901 #define DIFF_P_INT_ROUTE0_PDO_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 902 #define DIFF_P_INT_ROUTE0_VERRA_INT2 ((uint8_t) 0x08) /* Interrupt routed to INT2 pin. */ 903 #define DIFF_P_INT_ROUTE0_VERRA_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 904 #define DIFF_P_INT_ROUTE0_TDR_INT2 ((uint8_t) 0x10) /* Interrupt routed to INT2 pin. */ 905 #define DIFF_P_INT_ROUTE0_TDR_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 906 #define DIFF_P_INT_ROUTE0_PDR_INT2 ((uint8_t) 0x20) /* Interrupt routed to INT2 pin. */ 907 #define DIFF_P_INT_ROUTE0_PDR_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 908 #define DIFF_P_INT_ROUTE0_TOW_INT2 ((uint8_t) 0x40) /* Interrupt routed to INT2 pin. */ 909 #define DIFF_P_INT_ROUTE0_TOW_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 910 #define DIFF_P_INT_ROUTE0_POW_INT2 ((uint8_t) 0x80) /* Interrupt routed to INT2 pin. */ 911 #define DIFF_P_INT_ROUTE0_POW_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 912 /*------------------------------*/ 913 914 915 916 /*-------------------------------- 917 ** Register: INT_ROUTE1 918 ** Enum: DIFF_P_INT_ROUTE1 919 ** -- 920 ** Offset : 0x24 - Interrupt Route Register 1. 921 ** ------------------------------*/ 922 typedef union { 923 struct { 924 uint8_t _reserved_ : 1; 925 uint8_t p_wchg : 1; /* Window threshold interrupt. */ 926 927 uint8_t p_tgt2 : 1; /* Pressure target value 2. */ 928 929 uint8_t p_tgt1 : 1; /* Pressure target value 1. */ 930 931 uint8_t p_tgt0 : 1; /* Pressure target value 0. */ 932 933 uint8_t t_tgt : 1; /* Temperature target value. */ 934 935 uint8_t tdu : 1; /* Temperature data underflow. */ 936 937 uint8_t tdo : 1; /* Temperature data overflow. */ 938 939 } b; 940 uint8_t w; 941 } DIFF_P_INT_ROUTE1_t; 942 943 944 /* 945 ** INT_ROUTE1 - Bit field mask definitions 946 */ 947 #define DIFF_P_INT_ROUTE1_P_WCHG_MASK ((uint8_t) 0x02) 948 #define DIFF_P_INT_ROUTE1_P_WCHG_SHIFT ((uint8_t) 1) 949 950 #define DIFF_P_INT_ROUTE1_P_TGT2_MASK ((uint8_t) 0x04) 951 #define DIFF_P_INT_ROUTE1_P_TGT2_SHIFT ((uint8_t) 2) 952 953 #define DIFF_P_INT_ROUTE1_P_TGT1_MASK ((uint8_t) 0x08) 954 #define DIFF_P_INT_ROUTE1_P_TGT1_SHIFT ((uint8_t) 3) 955 956 #define DIFF_P_INT_ROUTE1_P_TGT0_MASK ((uint8_t) 0x10) 957 #define DIFF_P_INT_ROUTE1_P_TGT0_SHIFT ((uint8_t) 4) 958 959 #define DIFF_P_INT_ROUTE1_T_TGT_MASK ((uint8_t) 0x20) 960 #define DIFF_P_INT_ROUTE1_T_TGT_SHIFT ((uint8_t) 5) 961 962 #define DIFF_P_INT_ROUTE1_TDU_MASK ((uint8_t) 0x40) 963 #define DIFF_P_INT_ROUTE1_TDU_SHIFT ((uint8_t) 6) 964 965 #define DIFF_P_INT_ROUTE1_TDO_MASK ((uint8_t) 0x80) 966 #define DIFF_P_INT_ROUTE1_TDO_SHIFT ((uint8_t) 7) 967 968 969 /* 970 ** INT_ROUTE1 - Bit field value definitions 971 */ 972 #define DIFF_P_INT_ROUTE1_P_WCHG_INT2 ((uint8_t) 0x02) /* Interrupt routed to INT2 pin. */ 973 #define DIFF_P_INT_ROUTE1_P_WCHG_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 974 #define DIFF_P_INT_ROUTE1_P_TGT2_INT2 ((uint8_t) 0x04) /* Interrupt routed to INT2 pin. */ 975 #define DIFF_P_INT_ROUTE1_P_TGT2_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 976 #define DIFF_P_INT_ROUTE1_P_TGT1_INT2 ((uint8_t) 0x08) /* Interrupt routed to INT2 pin. */ 977 #define DIFF_P_INT_ROUTE1_P_TGT1_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 978 #define DIFF_P_INT_ROUTE1_P_TGT0_INT2 ((uint8_t) 0x10) /* Interrupt routed to INT2 pin. */ 979 #define DIFF_P_INT_ROUTE1_P_TGT0_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 980 #define DIFF_P_INT_ROUTE1_T_TGT_INT2 ((uint8_t) 0x20) /* Interrupt routed to INT2 pin. */ 981 #define DIFF_P_INT_ROUTE1_T_TGT_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 982 #define DIFF_P_INT_ROUTE1_TDU_INT2 ((uint8_t) 0x40) /* Interrupt routed to INT2 pin. */ 983 #define DIFF_P_INT_ROUTE1_TDU_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 984 #define DIFF_P_INT_ROUTE1_TDO_INT2 ((uint8_t) 0x80) /* Interrupt routed to INT2 pin. */ 985 #define DIFF_P_INT_ROUTE1_TDO_INT1 ((uint8_t) 0x00) /* Interrupt routed to INT1 pin. */ 986 /*------------------------------*/ 987 988 989 990 /*-------------------------------- 991 ** Register: I2C_ADDRESS 992 ** Enum: DIFF_P_I2C_ADDRESS 993 ** -- 994 ** Offset : 0x61 - This register configures the I2C address of the device. 995 ** ------------------------------*/ 996 typedef uint8_t DIFF_P_I2C_ADDRESS_t; 997 998 999 /*-------------------------------- 1000 ** Register: PROD_REV 1001 ** Enum: DIFF_P_PROD_REV 1002 ** -- 1003 ** Offset : 0x63 - This register keeps track of ASIC and MEMS die revisions. 1004 ** ------------------------------*/ 1005 typedef uint8_t DIFF_P_PROD_REV_t; 1006 1007 1008 1009 /*-------------------------------- 1010 ** Register: OFF_MOP_LSB 1011 ** Enum: DIFF_P_OFF_MOP_LSB 1012 ** -- 1013 ** Offset : 0x64 - 8 LSBs of 16 bit Maximum Offset Pressure LSB. 1014 ** ------------------------------*/ 1015 typedef uint8_t DIFF_P_OFF_MOP_LSB_t; 1016 1017 1018 /*-------------------------------- 1019 ** Register: OFF_MOP_MSB 1020 ** Enum: DIFF_P_OFF_MOP_MSB 1021 ** -- 1022 ** Offset : 0x65 - 8 MSBs of 16 bit Maximum Offset Pressure MSB. 1023 ** ------------------------------*/ 1024 typedef uint8_t DIFF_P_OFF_MOP_MSB_t; 1025 1026 1027 1028 /*-------------------------------- 1029 ** Register: SERIALNUMBER_BYTE7 1030 ** Enum: DIFF_P_SERIALNUMBER_BYTE7 1031 ** -- 1032 ** Offset :0x66 - SerialNumber byte 7 stored in NVM memory and will be programmed at final test. 1033 ** ------------------------------*/ 1034 typedef uint8_t DIFF_P_SERIALNUMBER_BYTE7_t; 1035 1036 1037 /*-------------------------------- 1038 ** Register: SERIALNUMBER_BYTE6 1039 ** Enum: DIFF_P_SERIALNUMBER_BYTE6 1040 ** -- 1041 ** Offset :0x67 - SerialNumber byte 6 stored in NVM memory and will be programmed at final test. 1042 ** ------------------------------*/ 1043 typedef uint8_t DIFF_P_SERIALNUMBER_BYTE6_t; 1044 1045 1046 /*-------------------------------- 1047 ** Register: SERIALNUMBER_BYTE5 1048 ** Enum: DIFF_P_SERIALNUMBER_BYTE5 1049 ** -- 1050 ** Offset :0x68 - SerialNumber byte 5 stored in NVM memory and will be programmed at final test. 1051 ** ------------------------------*/ 1052 typedef uint8_t DIFF_P_SERIALNUMBER_BYTE5_t; 1053 1054 1055 /*-------------------------------- 1056 ** Register: SERIALNUMBER_BYTE4 1057 ** Enum: DIFF_P_SERIALNUMBER_BYTE4 1058 ** -- 1059 ** Offset :0x69 - SerialNumber byte 4 stored in NVM memory and will be programmed at final test. 1060 ** ------------------------------*/ 1061 typedef uint8_t DIFF_P_SERIALNUMBER_BYTE4_t; 1062 1063 1064 /*-------------------------------- 1065 ** Register: SERIALNUMBER_BYTE3 1066 ** Enum: DIFF_P_SERIALNUMBER_BYTE3 1067 ** -- 1068 ** Offset :0x6A - SerialNumber byte 3 stored in NVM memory and will be programmed at final test. 1069 ** ------------------------------*/ 1070 typedef uint8_t DIFF_P_SERIALNUMBER_BYTE3_t; 1071 1072 1073 /*-------------------------------- 1074 ** Register: SERIALNUMBER_BYTE2 1075 ** Enum: DIFF_P_SERIALNUMBER_BYTE2 1076 ** -- 1077 ** Offset :0x6B - SerialNumber byte 2 stored in NVM memory and will be programmed at final test. 1078 ** ------------------------------*/ 1079 typedef uint8_t DIFF_P_SERIALNUMBER_BYTE2_t; 1080 1081 1082 /*-------------------------------- 1083 ** Register: SERIALNUMBER_BYTE1 1084 ** Enum: DIFF_P_SERIALNUMBER_BYTE1 1085 ** -- 1086 ** Offset :0x6C - SerialNumber byte 1 stored in NVM memory and will be programmed at final test. 1087 ** ------------------------------*/ 1088 typedef uint8_t DIFF_P_SERIALNUMBER_BYTE1_t; 1089 1090 1091 /*-------------------------------- 1092 ** Register: SERIALNUMBER_BYTE0 1093 ** Enum: DIFF_P_SERIALNUMBER_BYTE0 1094 ** -- 1095 ** Offset :0x6D - SerialNumber byte 0 stored in NVM memory and will be programmed at final test. 1096 ** ------------------------------*/ 1097 typedef uint8_t DIFF_P_SERIALNUMBER_BYTE0_t; 1098 1099 1100 #endif /* DIFF_P_H_ */ 1101
