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Searched refs:Clock_Ip_apxCgm (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Selector.c160 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswSwip()
161 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssClkswSwip()
198 …if (SelectorValue != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & SelectorMask) >> SelectorSh… in Clock_Ip_SetCgmXCscCssClkswSwip()
205 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
209 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()
213 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()
221 …while((CLOCK_IP_MC_CGM_MUX_CSS_CLK_SW_NOT_REQUESTED == (Clock_Ip_apxCgm[Instance][SelectorIndex]->… in Clock_Ip_SetCgmXCscCssClkswSwip()
231 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
236 …if (CLOCK_IP_MC_CGM_MUX_CSS_SWTRG_SUCCEEDED != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & M… in Clock_Ip_SetCgmXCscCssClkswSwip()
292 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswRampupRampdownSwip()
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DClock_Ip_Divider.c163 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
166 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
188 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
199Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] |= MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
203Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] &= ~MC_CGM_MUX_DC_DE_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
DClock_Ip_DividerTrigger.c138Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
142Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
172Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG = MC_CGM_MUX_DIV_TRIG_TRIGGER(CLOCK_IP_TRIG… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
178 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
DClock_Ip_Data.c3312 Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_MUXS_CO… variable
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Selector.c162 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= MC_CGM_MUX_CSC_SAFE_SW_MASK; in Clock_Ip_ResetCgmXCscCssClkswSwip()
163 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC &= ~SelectorMask; in Clock_Ip_ResetCgmXCscCssClkswSwip()
200 …if (SelectorValue != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & SelectorMask) >> SelectorSh… in Clock_Ip_SetCgmXCscCssClkswSwip()
207 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
211 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC; in Clock_Ip_SetCgmXCscCssClkswSwip()
215 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC = RegValue; in Clock_Ip_SetCgmXCscCssClkswSwip()
223 …while((CLOCK_IP_MC_CGM_MUX_CSS_CLK_SW_NOT_REQUESTED == (Clock_Ip_apxCgm[Instance][SelectorIndex]->… in Clock_Ip_SetCgmXCscCssClkswSwip()
233 …while((MC_CGM_MUX_CSS_SWIP_IN_PROGRESS == (Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & MC_CGM_… in Clock_Ip_SetCgmXCscCssClkswSwip()
238 …if (CLOCK_IP_MC_CGM_MUX_CSS_SWTRG_SUCCEEDED != ((Clock_Ip_apxCgm[Instance][SelectorIndex]->CSS & M… in Clock_Ip_SetCgmXCscCssClkswSwip()
303 Clock_Ip_apxCgm[Instance][SelectorIndex]->CSC |= (MC_CGM_MUX_CSC_CG_MASK); in Clock_Ip_ResetCgmXCscCssCsGrip()
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DClock_Ip_Divider.c160 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
191 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
197 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
249 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
266 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
269 …if ((Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL & MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_M… in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
275 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivStatWithoutPhaseWithTrigger()
367 RegValue = Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex]; in Clock_Ip_SetCgmXDeDivFmtStatWithoutPhase()
386 Clock_Ip_apxCgm[Instance][SelectorIndex]->Divider[DividerIndex] = RegValue; in Clock_Ip_SetCgmXDeDivFmtStatWithoutPhase()
392 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_SetCgmXDeDivFmtStatWithoutPhase()
DClock_Ip_DividerTrigger.c138Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL = (MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK); in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
142Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG_CTRL &= ~(MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MAS… in Clock_Ip_ConfigureCgmXDivTrigCtrlTctlHhenUpdStat()
172Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_TRIG = MC_CGM_MUX_DIV_TRIG_TRIGGER(CLOCK_IP_TRIG… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
178 …DividerStatus = (Clock_Ip_apxCgm[Instance][SelectorIndex]->MUX_DIV_UPD_STAT & MC_CGM_MUX_DIV_UPD_S… in Clock_Ip_TriggerUpdateCgmXDivTrigCtrlTctlHhenUpdStat()
DClock_Ip_Data.c2634 Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_MUXS_CO… variable
/hal_nxp-3.6.0/s32/drivers/s32ze/Mcu/include/
DClock_Ip_Specific.h305 extern Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_…
/hal_nxp-3.6.0/s32/drivers/s32k3/Mcu/include/
DClock_Ip_Specific.h455 extern Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM…